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dt-bindings: Add devicetree bindings

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Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").

Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
This commit is contained in:
Melody Olvera
2023-04-03 14:38:11 -07:00
parent c334acf377
commit 6f18ce8026
4878 changed files with 424312 additions and 0 deletions
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259
bindings/serial/8250.yaml Normal file
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# Copyright 2020 Lubomir Rintel <lkundrak@v3.sk>
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/8250.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: UART (Universal Asynchronous Receiver/Transmitter) bindings
maintainers:
- devicetree@vger.kernel.org
allOf:
- $ref: serial.yaml#
- if:
anyOf:
- required:
- aspeed,lpc-io-reg
- required:
- aspeed,lpc-interrupts
- required:
- aspeed,sirq-polarity-sense
then:
properties:
compatible:
const: aspeed,ast2500-vuart
- if:
properties:
compatible:
const: mrvl,mmp-uart
then:
properties:
reg-shift:
const: 2
required:
- reg-shift
- if:
not:
properties:
compatible:
items:
- enum:
- ns8250
- ns16450
- ns16550
- ns16550a
then:
anyOf:
- required: [ clock-frequency ]
- required: [ clocks ]
properties:
compatible:
oneOf:
- const: ns8250
- const: ns16450
- const: ns16550
- const: ns16550a
- const: ns16850
- const: aspeed,ast2400-vuart
- const: aspeed,ast2500-vuart
- const: intel,xscale-uart
- const: mrvl,pxa-uart
- const: nuvoton,wpcm450-uart
- const: nuvoton,npcm750-uart
- const: nuvoton,npcm845-uart
- const: nvidia,tegra20-uart
- const: nxp,lpc3220-uart
- items:
- enum:
- exar,xr16l2552
- exar,xr16l2551
- exar,xr16l2550
- const: ns8250
- items:
- enum:
- altr,16550-FIFO32
- altr,16550-FIFO64
- altr,16550-FIFO128
- fsl,16550-FIFO64
- fsl,ns16550
- andestech,uart16550
- nxp,lpc1850-uart
- opencores,uart16550-rtlsvn105
- ti,da830-uart
- const: ns16550a
- items:
- enum:
- ns16750
- cavium,octeon-3860-uart
- xlnx,xps-uart16550-2.00.b
- ralink,rt2880-uart
- enum:
- ns16550 # Deprecated, unless the FIFO really is broken
- ns16550a
- items:
- enum:
- ralink,mt7620a-uart
- ralink,rt3052-uart
- ralink,rt3883-uart
- const: ralink,rt2880-uart
- enum:
- ns16550 # Deprecated, unless the FIFO really is broken
- ns16550a
- items:
- enum:
- mediatek,mt7622-btif
- mediatek,mt7623-btif
- const: mediatek,mtk-btif
- items:
- const: mrvl,mmp-uart
- const: intel,xscale-uart
- items:
- enum:
- nvidia,tegra30-uart
- nvidia,tegra114-uart
- nvidia,tegra124-uart
- nvidia,tegra210-uart
- nvidia,tegra186-uart
- nvidia,tegra194-uart
- nvidia,tegra234-uart
- const: nvidia,tegra20-uart
reg:
maxItems: 1
interrupts:
maxItems: 1
clock-frequency: true
clocks:
maxItems: 1
resets:
maxItems: 1
current-speed:
$ref: /schemas/types.yaml#/definitions/uint32
description: The current active speed of the UART.
reg-offset:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Offset to apply to the mapbase from the start of the registers.
reg-shift:
description: Quantity to shift the register offsets by.
reg-io-width:
description: |
The size (in bytes) of the IO accesses that should be performed on the
device. There are some systems that require 32-bit accesses to the
UART (e.g. TI davinci).
used-by-rtas:
type: boolean
description: |
Set to indicate that the port is in use by the OpenFirmware RTAS and
should not be registered.
no-loopback-test:
type: boolean
description: |
Set to indicate that the port does not implement loopback test mode.
fifo-size:
$ref: /schemas/types.yaml#/definitions/uint32
description: The fifo size of the UART.
auto-flow-control:
type: boolean
description: |
One way to enable automatic flow control support. The driver is
allowed to detect support for the capability even without this
property.
tx-threshold:
description: |
Specify the TX FIFO low water indication for parts with programmable
TX FIFO thresholds.
overrun-throttle-ms:
description: |
How long to pause uart rx when input overrun is encountered.
rts-gpios: true
cts-gpios: true
dtr-gpios: true
dsr-gpios: true
rng-gpios: true
dcd-gpios: true
aspeed,sirq-polarity-sense:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: |
Phandle to aspeed,ast2500-scu compatible syscon alongside register
offset and bit number to identify how the SIRQ polarity should be
configured. One possible data source is the LPC/eSPI mode bit. Only
applicable to aspeed,ast2500-vuart.
deprecated: true
aspeed,lpc-io-reg:
$ref: '/schemas/types.yaml#/definitions/uint32'
description: |
The VUART LPC address. Only applicable to aspeed,ast2500-vuart.
aspeed,lpc-interrupts:
$ref: "/schemas/types.yaml#/definitions/uint32-array"
minItems: 2
maxItems: 2
description: |
A 2-cell property describing the VUART SIRQ number and SIRQ
polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_LEVEL_HIGH). Only
applicable to aspeed,ast2500-vuart.
required:
- reg
- interrupts
unevaluatedProperties: false
examples:
- |
serial@80230000 {
compatible = "ns8250";
reg = <0x80230000 0x100>;
interrupts = <10>;
reg-shift = <2>;
clock-frequency = <48000000>;
};
- |
#include <dt-bindings/gpio/gpio.h>
serial@49042000 {
compatible = "andestech,uart16550", "ns16550a";
reg = <0x49042000 0x400>;
interrupts = <80>;
clock-frequency = <48000000>;
cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
};
- |
#include <dt-bindings/clock/aspeed-clock.h>
#include <dt-bindings/interrupt-controller/irq.h>
serial@1e787000 {
compatible = "aspeed,ast2500-vuart";
reg = <0x1e787000 0x40>;
reg-shift = <2>;
interrupts = <8>;
clocks = <&syscon ASPEED_CLK_APB>;
no-loopback-test;
aspeed,lpc-io-reg = <0x3f8>;
aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
};
...

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bindings/serial/8250_omap.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/8250_omap.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Bindings for 8250 compliant UARTs on TI's OMAP2+ and K3 SoCs
maintainers:
- Vignesh Raghavendra <vigneshr@ti.com>
allOf:
- $ref: /schemas/serial/serial.yaml#
- $ref: /schemas/serial/rs485.yaml#
properties:
compatible:
oneOf:
- enum:
- ti,am3352-uart
- ti,am4372-uart
- ti,am654-uart
- ti,dra742-uart
- ti,omap2-uart
- ti,omap3-uart
- ti,omap4-uart
- items:
- enum:
- ti,am64-uart
- ti,j721e-uart
- const: ti,am654-uart
ti,hwmods:
description:
Must be "uart<n>", n being the instance number (1-based)
This property is applicable only on legacy platforms mainly omap2/3
and ti81xx and should not be used on other platforms.
$ref: /schemas/types.yaml#/definitions/string
deprecated: true
dmas:
minItems: 1
maxItems: 2
dma-names:
items:
- const: tx
- const: rx
reg:
maxItems: 1
interrupts:
minItems: 1
maxItems: 2
description:
First entry is module IRQ required for normal IO operation.
Second entry is optional and corresponds to system wakeup IRQ
where supported.
clocks:
maxItems: 1
clock-names:
const: fclk
rts-gpios: true
cts-gpios: true
dtr-gpios: true
dsr-gpios: true
rng-gpios: true
dcd-gpios: true
rs485-rts-delay: true
rs485-rts-active-low: true
rs485-rx-during-tx: true
rs485-rts-active-high: true
linux,rs485-enabled-at-boot-time: true
rts-gpio: true
power-domains: true
clock-frequency: true
current-speed: true
overrun-throttle-ms: true
required:
- compatible
- reg
- interrupts
unevaluatedProperties: false
if:
properties:
compatible:
contains:
enum:
- ti,omap2-uart
- ti,omap3-uart
- ti,omap4-uart
then:
properties:
ti,hwmods:
items:
- pattern: "^uart([1-9])$"
else:
properties:
ti,hwmods: false
examples:
- |
serial@49042000 {
compatible = "ti,omap3-uart";
reg = <0x49042000 0x400>;
interrupts = <80>;
dmas = <&sdma 81 &sdma 82>;
dma-names = "tx", "rx";
ti,hwmods = "uart4";
clock-frequency = <48000000>;
};

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bindings/serial/actions,owl-uart.txt Normal file
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Actions Semi Owl UART
Required properties:
- compatible : "actions,s500-uart", "actions,owl-uart" for S500
"actions,s900-uart", "actions,owl-uart" for S900
- reg : Offset and length of the register set for the device.
- interrupts : Should contain UART interrupt.
Example:
uart3: serial@b0126000 {
compatible = "actions,s500-uart", "actions,owl-uart";
reg = <0xb0126000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};

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bindings/serial/altera_jtaguart.txt Normal file
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Altera JTAG UART
Required properties:
- compatible : should be "ALTR,juart-1.0" <DEPRECATED>
- compatible : should be "altr,juart-1.0"

8
bindings/serial/altera_uart.txt Normal file
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Altera UART
Required properties:
- compatible : should be "ALTR,uart-1.0" <DEPRECATED>
- compatible : should be "altr,uart-1.0"
Optional properties:
- clock-frequency : frequency of the clock input to the UART

82
bindings/serial/amlogic,meson-uart.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/serial/amlogic,meson-uart.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Amlogic Meson SoC UART Serial Interface
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
description: |
The Amlogic Meson SoC UART Serial Interface is present on a large range
of SoCs, and can be present either in the "Always-On" power domain or the
"Everything-Else" power domain.
The particularity of the "Always-On" Serial Interface is that the hardware
is active since power-on and does not need any clock gating and is usable
as very early serial console.
properties:
compatible:
oneOf:
- description: Always-on power domain UART controller
items:
- enum:
- amlogic,meson6-uart
- amlogic,meson8-uart
- amlogic,meson8b-uart
- amlogic,meson-gx-uart
- amlogic,meson-s4-uart
- const: amlogic,meson-ao-uart
- description: Everything-Else power domain UART controller
enum:
- amlogic,meson6-uart
- amlogic,meson8-uart
- amlogic,meson8b-uart
- amlogic,meson-gx-uart
- amlogic,meson-s4-uart
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: external xtal clock identifier
- description: the bus core clock, either the clk81 clock or the gate clock
- description: the source of the baudrate generator, can be either the xtal or the pclk
clock-names:
items:
- const: xtal
- const: pclk
- const: baud
fifo-size:
description: The fifo size supported by the UART channel.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [64, 128]
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
additionalProperties: false
examples:
- |
serial@84c0 {
compatible = "amlogic,meson-gx-uart";
reg = <0x84c0 0x14>;
interrupts = <26>;
clocks = <&xtal>, <&pclk>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
};

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* Synopsys ARC UART : Non standard UART used in some of the ARC FPGA boards
Required properties:
- compatible : "snps,arc-uart"
- reg : offset and length of the register set for the device.
- interrupts : device interrupt
- clock-frequency : the input clock frequency for the UART
- current-speed : baud rate for UART
e.g.
arcuart0: serial@c0fc1000 {
compatible = "snps,arc-uart";
reg = <0xc0fc1000 0x100>;
interrupts = <5>;
clock-frequency = <80000000>;
current-speed = <115200>;
};
Note: Each port should have an alias correctly numbered in "aliases" node.
e.g.
aliases {
serial0 = &arcuart0;
};

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bindings/serial/arm,mps2-uart.txt Normal file
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ARM MPS2 UART
Required properties:
- compatible : Should be "arm,mps2-uart"
- reg : Address and length of the register set
- interrupts : Reference to the UART RX, TX and overrun interrupts
Required clocking property:
- clocks : The input clock of the UART
Examples:
uart0: serial@40004000 {
compatible = "arm,mps2-uart";
reg = <0x40004000 0x1000>;
interrupts = <0 1 12>;
clocks = <&sysclk>;
};

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bindings/serial/arm_sbsa_uart.txt Normal file
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* ARM SBSA defined generic UART
This UART uses a subset of the PL011 registers and consequently lives
in the PL011 driver. It's baudrate and other communication parameters
cannot be adjusted at runtime, so it lacks a clock specifier here.
Required properties:
- compatible: must be "arm,sbsa-uart"
- reg: exactly one register range
- interrupts: exactly one interrupt specifier
- current-speed: the (fixed) baud rate set by the firmware

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bindings/serial/atmel,at91-usart.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/atmel,at91-usart.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART)
maintainers:
- Richard Genoud <richard.genoud@gmail.com>
properties:
compatible:
oneOf:
- enum:
- atmel,at91rm9200-usart
- atmel,at91sam9260-usart
- microchip,sam9x60-usart
- items:
- const: atmel,at91rm9200-dbgu
- const: atmel,at91rm9200-usart
- items:
- const: atmel,at91sam9260-dbgu
- const: atmel,at91sam9260-usart
- items:
- const: microchip,sam9x60-dbgu
- const: microchip,sam9x60-usart
- const: atmel,at91sam9260-dbgu
- const: atmel,at91sam9260-usart
reg:
maxItems: 1
interrupts:
maxItems: 1
clock-names:
minItems: 1
items:
- const: usart
- const: gclk
clocks:
minItems: 1
items:
- description: USART Peripheral Clock
- description: USART Generic Clock
dmas:
items:
- description: TX DMA Channel
- description: RX DMA Channel
dma-names:
items:
- const: tx
- const: rx
atmel,usart-mode:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Must be either <AT91_USART_MODE_SPI> for SPI or
<AT91_USART_MODE_SERIAL> for USART (found in dt-bindings/mfd/at91-usart.h).
enum: [ 0, 1 ]
atmel,use-dma-rx:
type: boolean
description: use of PDC or DMA for receiving data
atmel,use-dma-tx:
type: boolean
description: use of PDC or DMA for transmitting data
atmel,fifo-size:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Maximum number of data the RX and TX FIFOs can store for FIFO
capable USARTS.
enum: [ 16, 32 ]
required:
- compatible
- reg
- interrupts
- clock-names
- clocks
- atmel,usart-mode
allOf:
- if:
properties:
atmel,usart-mode:
const: 1
then:
allOf:
- $ref: /schemas/spi/spi-controller.yaml#
properties:
atmel,use-dma-rx: false
atmel,use-dma-tx: false
atmel,fifo-size: false
"#size-cells":
const: 0
"#address-cells":
const: 1
required:
- "#size-cells"
- "#address-cells"
else:
allOf:
- $ref: /schemas/serial/serial.yaml#
- $ref: /schemas/serial/rs485.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/mfd/at91-usart.h>
#include <dt-bindings/dma/at91.h>
/* use PDC */
usart0: serial@fff8c000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfff8c000 0x4000>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <7>;
clocks = <&usart0_clk>;
clock-names = "usart";
atmel,use-dma-rx;
atmel,use-dma-tx;
rts-gpios = <&pioD 15 GPIO_ACTIVE_LOW>;
cts-gpios = <&pioD 16 GPIO_ACTIVE_LOW>;
dtr-gpios = <&pioD 17 GPIO_ACTIVE_LOW>;
dsr-gpios = <&pioD 18 GPIO_ACTIVE_LOW>;
dcd-gpios = <&pioD 20 GPIO_ACTIVE_LOW>;
rng-gpios = <&pioD 19 GPIO_ACTIVE_LOW>;
};
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/mfd/at91-usart.h>
#include <dt-bindings/dma/at91.h>
/* use DMA */
usart1: serial@f001c000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf001c000 0x100>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
clocks = <&usart0_clk>;
clock-names = "usart";
atmel,use-dma-rx;
atmel,use-dma-tx;
dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>,
<&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
dma-names = "tx", "rx";
atmel,fifo-size = <32>;
};
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/mfd/at91-usart.h>
#include <dt-bindings/dma/at91.h>
/* SPI mode */
spi0: spi@f001c000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf001c000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
atmel,usart-mode = <AT91_USART_MODE_SPI>;
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
clocks = <&usart0_clk>;
clock-names = "usart";
dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>,
<&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
dma-names = "tx", "rx";
cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>;
};

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bindings/serial/brcm,bcm2835-aux-uart.txt Normal file
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* BCM2835 AUXILIAR UART
Required properties:
- compatible: "brcm,bcm2835-aux-uart"
- reg: The base address of the UART register bank.
- interrupts: A single interrupt specifier.
- clocks: Clock driving the hardware; used to figure out the baud rate
divisor.
Example:
uart1: serial@7e215040 {
compatible = "brcm,bcm2835-aux-uart";
reg = <0x7e215040 0x40>;
interrupts = <1 29>;
clocks = <&aux BCM2835_AUX_CLOCK_UART>;
};

47
bindings/serial/brcm,bcm6345-uart.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/brcm,bcm6345-uart.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: BCM63xx UART
maintainers:
- Rafał Miłecki <rafal@milecki.pl>
allOf:
- $ref: serial.yaml#
properties:
compatible:
const: brcm,bcm6345-uart
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
clock-names:
const: refclk
unevaluatedProperties: false
required:
- reg
- interrupts
- clocks
examples:
- |
serial@14e00520 {
compatible = "brcm,bcm6345-uart";
reg = <0x14e00520 0x18>;
interrupt-parent = <&periph_intc>;
interrupts = <2>;
clocks = <&periph_clk>;
clock-names = "refclk";
};

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bindings/serial/brcm,bcm7271-uart.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/brcm,bcm7271-uart.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom 8250 based serial port devicetree bindings
maintainers:
- Al Cooper <alcooperx@gmail.com>
allOf:
- $ref: serial.yaml#
description: |+
The Broadcom UART is based on the basic 8250 UART but with
enhancements for more accurate high speed baud rates and support
for DMA.
properties:
compatible:
items:
- enum:
- brcm,bcm7271-uart
- brcm,bcm7278-uart
reg:
minItems: 1
maxItems: 5
reg-names:
description: The UART register block and optionally the DMA register blocks.
oneOf:
- items:
- const: uart
- items:
- const: uart
- const: dma_arb
- const: dma_rx
- const: dma_tx
- const: dma_intr2
clocks:
minItems: 1
clock-names:
const: sw_baud
interrupts:
minItems: 1
maxItems: 2
interrupt-names:
description: The UART interrupt and optionally the DMA interrupt.
minItems: 1
items:
- const: uart
- const: dma
required:
- compatible
- reg
- reg-names
- clocks
- clock-names
- interrupts
- interrupt-names
unevaluatedProperties: false
examples:
- |
serial@840d000 {
compatible = "brcm,bcm7271-uart";
reg = <0x840d000 0x20>;
reg-names = "uart";
interrupts = <0x0 0x62 0x4>;
interrupt-names = "uart";
clocks = <&scmi_clk 190>;
clock-names = "sw_baud";
};
serial@840e000 {
compatible = "brcm,bcm7271-uart";
reg = <0x840e000 0x20>,
<0x840e080 0x8>,
<0x840e100 0xa8>,
<0x840e200 0x4c>,
<0x840e300 0x30>;
reg-names = "uart", "dma_arb", "dma_rx", "dma_tx", "dma_intr2";
interrupts = <0x0 0x62 0x4>, <0x0 0x75 0x4>;
interrupt-names = "uart", "dma";
clocks = <&scmi_clk 190>;
clock-names = "sw_baud";
};

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* Universal Asynchronous Receiver/Transmitter (UART)
- compatible: "cavium,octeon-3860-uart"
Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
- reg: The base address of the UART register bank.
- interrupts: A single interrupt specifier.
- current-speed: Optional, the current bit rate in bits per second.
Example:
uart1: serial@1180000000c00 {
compatible = "cavium,octeon-3860-uart","ns16550";
reg = <0x11800 0x00000c00 0x0 0x400>;
current-speed = <115200>;
interrupts = <0 35>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/cdns,uart.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cadence UART Controller
maintainers:
- Michal Simek <michal.simek@xilinx.com>
allOf:
- $ref: /schemas/serial.yaml#
properties:
compatible:
oneOf:
- description: UART controller for Zynq-7xxx SoC
items:
- const: xlnx,xuartps
- const: cdns,uart-r1p8
- description: UART controller for Zynq Ultrascale+ MPSoC
items:
- const: xlnx,zynqmp-uart
- const: cdns,uart-r1p12
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 2
clock-names:
items:
- const: uart_clk
- const: pclk
cts-override:
description: |
Override the CTS modem status signal. This signal will
always be reported as active instead of being obtained
from the modem status register. Define this if your serial
port does not use this pin.
type: boolean
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
uart0: serial@e0000000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
clocks = <&clkc 23>, <&clkc 40>;
clock-names = "uart_clk", "pclk";
reg = <0xE0000000 0x1000>;
interrupts = <0 27 4>;
};

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* Cirrus Logic CLPS711X Universal Asynchronous Receiver/Transmitter (UART)
Required properties:
- compatible: Should be "cirrus,ep7209-uart".
- reg: Address and length of the register set for the device.
- interrupts: Should contain UART TX and RX interrupt.
- clocks: Should contain UART core clock number.
- syscon: Phandle to SYSCON node, which contain UART control bits.
Optional properties:
- {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD
line respectively.
Note: Each UART port should have an alias correctly numbered
in "aliases" node.
Example:
aliases {
serial0 = &uart1;
};
uart1: uart@80000480 {
compatible = "cirrus,ep7312-uart","cirrus,ep7209-uart";
reg = <0x80000480 0x80>;
interrupts = <12 13>;
clocks = <&clks 11>;
syscon = <&syscon1>;
cts-gpios = <&sysgpio 0 GPIO_ACTIVE_LOW>;
dsr-gpios = <&sysgpio 1 GPIO_ACTIVE_LOW>;
dcd-gpios = <&sysgpio 2 GPIO_ACTIVE_LOW>;
};

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Binding for Conexant Digicolor USART
Note: this binding is only applicable for using the USART peripheral as
UART. USART also support synchronous serial protocols like SPI and I2S. Use
the binding that matches the wiring of your system.
Required properties:
- compatible : should be "cnxt,cx92755-usart".
- reg: Should contain USART controller registers location and length.
- interrupts: Should contain a single USART controller interrupt.
- clocks: Must contain phandles to the USART clock
See ../clocks/clock-bindings.txt for details.
Note: Each UART port should have an alias correctly numbered
in "aliases" node.
Example:
aliases {
serial0 = &uart0;
};
uart0: uart@f0000740 {
compatible = "cnxt,cx92755-usart";
reg = <0xf0000740 0x20>;
clocks = <&main_clk>;
interrupts = <44>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/fsl,s32-linflexuart.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale LINFlexD UART
description: |
The LINFlexD controller implements several LIN protocol versions, as well
as support for full-duplex UART communication through 8-bit and 9-bit
frames. See chapter 47 ("LINFlexD") in the reference manual
https://www.nxp.com/webapp/Download?colCode=S32V234RM.
maintainers:
- Chester Lin <clin@suse.com>
allOf:
- $ref: "serial.yaml"
properties:
compatible:
oneOf:
- const: fsl,s32v234-linflexuart
- items:
- const: nxp,s32g2-linflexuart
- const: fsl,s32v234-linflexuart
reg:
maxItems: 1
interrupts:
maxItems: 1
required:
- compatible
- reg
- interrupts
unevaluatedProperties: false
examples:
- |
serial@40053000 {
compatible = "fsl,s32v234-linflexuart";
reg = <0x40053000 0x1000>;
interrupts = <0 59 4>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART)
maintainers:
- Fabio Estevam <festevam@gmail.com>
allOf:
- $ref: "serial.yaml"
- $ref: "rs485.yaml"
properties:
compatible:
oneOf:
- const: fsl,imx1-uart
- const: fsl,imx21-uart
- items:
- enum:
- fsl,imx25-uart
- fsl,imx27-uart
- fsl,imx31-uart
- fsl,imx35-uart
- fsl,imx50-uart
- fsl,imx51-uart
- fsl,imx53-uart
- fsl,imx6q-uart
- const: fsl,imx21-uart
- items:
- enum:
- fsl,imx6sl-uart
- fsl,imx6sll-uart
- fsl,imx6sx-uart
- const: fsl,imx6q-uart
- const: fsl,imx21-uart
- items:
- enum:
- fsl,imx6ul-uart
- fsl,imx7d-uart
- fsl,imx8mm-uart
- fsl,imx8mn-uart
- fsl,imx8mp-uart
- fsl,imx8mq-uart
- const: fsl,imx6q-uart
reg:
maxItems: 1
interrupts:
maxItems: 1
fsl,dte-mode:
$ref: /schemas/types.yaml#/definitions/flag
description: |
Indicate the uart works in DTE mode. The uart works in DCE mode by default.
fsl,inverted-tx:
$ref: /schemas/types.yaml#/definitions/flag
description: |
Indicate that the hardware attached to the peripheral inverts the signal
transmitted, and that the peripheral should invert its output using the
INVT registers.
fsl,inverted-rx:
$ref: /schemas/types.yaml#/definitions/flag
description: |
Indicate that the hardware attached to the peripheral inverts the signal
received, and that the peripheral should invert its input using the
INVR registers.
fsl,dma-info:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 2
maxItems: 2
description: |
First cell contains the size of DMA buffer chunks, second cell contains
the amount of chunks used for the device. Multiplying both numbers is
the total size of memory used for receiving data.
When not being configured the system will use default settings, which
are sensible for most use cases. If you need low latency processing on
slow connections this needs to be configured appropriately.
uart-has-rtscts: true
rs485-rts-delay: true
rs485-rts-active-low: true
rs485-rx-during-tx: true
linux,rs485-enabled-at-boot-time: true
required:
- compatible
- reg
- interrupts
unevaluatedProperties: false
examples:
- |
aliases {
serial0 = &uart1;
};
uart1: serial@73fbc000 {
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x73fbc000 0x4000>;
interrupts = <31>;
uart-has-rtscts;
fsl,dte-mode;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/fsl-lpuart.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale low power universal asynchronous receiver/transmitter (lpuart)
maintainers:
- Fugang Duan <fugang.duan@nxp.com>
allOf:
- $ref: "rs485.yaml"
properties:
compatible:
oneOf:
- enum:
- fsl,vf610-lpuart
- fsl,ls1021a-lpuart
- fsl,ls1028a-lpuart
- fsl,imx7ulp-lpuart
- fsl,imx8qxp-lpuart
- fsl,imxrt1050-lpuart
- items:
- enum:
- fsl,imx93-lpuart
- fsl,imx8ulp-lpuart
- const: fsl,imx7ulp-lpuart
- items:
- enum:
- fsl,imx8qm-lpuart
- fsl,imx8dxl-lpuart
- const: fsl,imx8qxp-lpuart
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: ipg clock
- description: baud clock
minItems: 1
clock-names:
items:
- const: ipg
- const: baud
minItems: 1
dmas:
items:
- description: DMA controller phandle and request line for RX
- description: DMA controller phandle and request line for TX
dma-names:
items:
- const: rx
- const: tx
rs485-rts-active-low: true
linux,rs485-enabled-at-boot-time: true
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/vf610-clock.h>
serial@40027000 {
compatible = "fsl,vf610-lpuart";
reg = <0x40027000 0x1000>;
interrupts = <0 61 0x00>;
clocks = <&clks VF610_CLK_UART0>;
clock-names = "ipg";
dmas = <&edma0 0 2>, <&edma0 0 3>;
dma-names = "rx","tx";
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/fsl-mxs-auart.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale MXS Application UART (AUART)
maintainers:
- Fabio Estevam <festevam@gmail.com>
allOf:
- $ref: "serial.yaml"
properties:
compatible:
enum:
- fsl,imx23-auart
- fsl,imx28-auart
- alphascale,asm9260-auart
reg:
maxItems: 1
interrupts:
maxItems: 1
dmas:
items:
- description: DMA controller phandle and request line for RX
- description: DMA controller phandle and request line for TX
dma-names:
items:
- const: rx
- const: tx
clocks:
items:
- description: mod clock
- description: ahb clock
minItems: 1
clock-names:
items:
- const: mod
- const: ahb
minItems: 1
uart-has-rtscts: true
rts-gpios: true
cts-gpios: true
dtr-gpios: true
dsr-gpios: true
rng-gpios: true
dcd-gpios: true
if:
properties:
compatible:
contains:
enum:
- alphascale,asm9260-auart
then:
required:
- clocks
- clock-names
required:
- compatible
- reg
- interrupts
- dmas
- dma-names
unevaluatedProperties: false
examples:
- |
aliases {
serial0 = &auart0;
};
auart0: serial@8006a000 {
compatible = "fsl,imx28-auart";
reg = <0x8006a000 0x2000>;
interrupts = <112>;
dmas = <&dma_apbx 8>, <&dma_apbx 9>;
dma-names = "rx", "tx";
clocks = <&clks 45>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/ingenic,uart.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ingenic SoCs UART controller devicetree bindings
maintainers:
- Paul Cercueil <paul@crapouillou.net>
allOf:
- $ref: serial.yaml#
properties:
$nodename:
pattern: "^serial@[0-9a-f]+$"
compatible:
oneOf:
- enum:
- ingenic,jz4740-uart
- ingenic,jz4760-uart
- ingenic,jz4780-uart
- ingenic,x1000-uart
- items:
- enum:
- ingenic,jz4770-uart
- ingenic,jz4775-uart
- const: ingenic,jz4760-uart
- items:
- const: ingenic,jz4725b-uart
- const: ingenic,jz4740-uart
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: Baud clock
- description: UART module clock
clock-names:
items:
- const: baud
- const: module
dmas:
items:
- description: DMA controller phandle and request line for RX
- description: DMA controller phandle and request line for TX
dma-names:
items:
- const: rx
- const: tx
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- dmas
- dma-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/ingenic,jz4780-cgu.h>
#include <dt-bindings/dma/jz4780-dma.h>
#include <dt-bindings/gpio/gpio.h>
serial@10032000 {
compatible = "ingenic,jz4780-uart";
reg = <0x10032000 0x100>;
interrupt-parent = <&intc>;
interrupts = <49>;
clocks = <&ext>, <&cgu JZ4780_CLK_UART2>;
clock-names = "baud", "module";
dmas = <&dma JZ4780_DMA_UART2_RX 0xffffffff>,
<&dma JZ4780_DMA_UART2_TX 0xffffffff>;
dma-names = "rx", "tx";
bluetooth {
compatible = "brcm,bcm4330-bt";
reset-gpios = <&gpf 8 GPIO_ACTIVE_HIGH>;
vbat-supply = <&wlan0_power>;
device-wakeup-gpios = <&gpf 5 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpf 6 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpf 4 GPIO_ACTIVE_LOW>;
};
};

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Lantiq SoC ASC serial controller
Required properties:
- compatible : Should be "lantiq,asc"
- reg : Address and length of the register set for the device
- interrupts: the 3 (tx rx err) interrupt numbers. The interrupt specifier
depends on the interrupt-parent interrupt controller.
Optional properties:
- clocks: Should contain frequency clock and gate clock
- clock-names: Should be "freq" and "asc"
Example:
asc0: serial@16600000 {
compatible = "lantiq,asc";
reg = <0x16600000 0x100000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cgu CLK_SSX4>, <&cgu GCLK_UART>;
clock-names = "freq", "asc";
};
asc1: serial@e100c00 {
compatible = "lantiq,asc";
reg = <0xE100C00 0x400>;
interrupt-parent = <&icu0>;
interrupts = <112 113 114>;
};

40
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/litex,liteuart.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: LiteUART serial controller
maintainers:
- Karol Gugala <kgugala@antmicro.com>
- Mateusz Holenko <mholenko@antmicro.com>
description: |
LiteUART serial controller is a part of the LiteX FPGA SoC builder. It supports
multiple CPU architectures, currently including e.g. OpenRISC and RISC-V.
properties:
compatible:
const: litex,liteuart
reg:
maxItems: 1
interrupts:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
uart0: serial@e0001800 {
compatible = "litex,liteuart";
reg = <0xe0001800 0x100>;
interrupts = <2>;
};

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* Maxim MAX310X advanced Universal Asynchronous Receiver-Transmitter (UART)
Required properties:
- compatible: Should be one of the following:
- "maxim,max3107" for Maxim MAX3107,
- "maxim,max3108" for Maxim MAX3108,
- "maxim,max3109" for Maxim MAX3109,
- "maxim,max14830" for Maxim MAX14830.
- reg: SPI chip select number.
- interrupts: Specifies the interrupt source of the parent interrupt
controller. The format of the interrupt specifier depends on the
parent interrupt controller.
- clocks: phandle to the IC source clock.
- clock-names: Should be "xtal" if clock is an external crystal or
"osc" if an external clock source is used.
Optional properties:
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Should be two. The first cell is the GPIO number and
the second cell is used to specify the GPIO polarity:
0 = active high,
1 = active low.
Example:
/ {
clocks {
spi_uart_clk: osc_max14830 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <3686400>;
};
};
};
&spi0 {
max14830: max14830@0 {
compatible = "maxim,max14830";
reg = <0>;
clocks = <&spi_uart_clk>;
clock-names = "osc";
interrupt-parent = <&gpio3>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
gpio-controller;
#gpio-cells = <2>;
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/mediatek,uart.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Universal Asynchronous Receiver/Transmitter (UART)
maintainers:
- Matthias Brugger <matthias.bgg@gmail.com>
allOf:
- $ref: serial.yaml#
description: |
The MediaTek UART is based on the basic 8250 UART and compatible
with 16550A, with enhancements for high speed baud rates and
support for DMA.
properties:
compatible:
oneOf:
- const: mediatek,mt6577-uart
- items:
- enum:
- mediatek,mt2701-uart
- mediatek,mt2712-uart
- mediatek,mt6580-uart
- mediatek,mt6582-uart
- mediatek,mt6589-uart
- mediatek,mt6755-uart
- mediatek,mt6765-uart
- mediatek,mt6779-uart
- mediatek,mt6795-uart
- mediatek,mt6797-uart
- mediatek,mt7622-uart
- mediatek,mt7623-uart
- mediatek,mt7629-uart
- mediatek,mt7986-uart
- mediatek,mt8127-uart
- mediatek,mt8135-uart
- mediatek,mt8173-uart
- mediatek,mt8183-uart
- mediatek,mt8186-uart
- mediatek,mt8188-uart
- mediatek,mt8192-uart
- mediatek,mt8195-uart
- mediatek,mt8516-uart
- const: mediatek,mt6577-uart
reg:
description: The base address of the UART register bank
maxItems: 1
clocks:
minItems: 1
items:
- description: The clock the baudrate is derived from
- description: The bus clock for register accesses
clock-names:
minItems: 1
items:
- const: baud
- const: bus
dmas:
items:
- description: phandle to TX DMA
- description: phandle to RX DMA
dma-names:
items:
- const: tx
- const: rx
interrupts:
minItems: 1
maxItems: 2
interrupt-names:
description:
The UART interrupt and optionally the RX in-band wakeup interrupt.
minItems: 1
items:
- const: uart
- const: wakeup
pinctrl-0: true
pinctrl-1: true
pinctrl-names:
minItems: 1
items:
- const: default
- const: sleep
required:
- compatible
- reg
- clocks
- interrupts
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
serial@11006000 {
compatible = "mediatek,mt6589-uart", "mediatek,mt6577-uart";
reg = <0x11006000 0x400>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 52 IRQ_TYPE_EDGE_FALLING>;
interrupt-names = "uart", "wakeup";
clocks = <&uart_clk>, <&bus_clk>;
clock-names = "baud", "bus";
pinctrl-0 = <&uart_pin>;
pinctrl-1 = <&uart_pin_sleep>;
pinctrl-names = "default", "sleep";
};

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* Microchip Universal Asynchronous Receiver Transmitter (UART)
Required properties:
- compatible: Should be "microchip,pic32mzda-uart"
- reg: Should contain registers location and length
- interrupts: Should contain interrupt
- clocks: Phandle to the clock.
See: Documentation/devicetree/bindings/clock/clock-bindings.txt
- pinctrl-names: A pinctrl state names "default" must be defined.
- pinctrl-0: Phandle referencing pin configuration of the UART peripheral.
See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
Optional properties:
- cts-gpios: CTS pin for UART
Example:
uart1: serial@1f822000 {
compatible = "microchip,pic32mzda-uart";
reg = <0x1f822000 0x50>;
interrupts = <112 IRQ_TYPE_LEVEL_HIGH>,
<113 IRQ_TYPE_LEVEL_HIGH>,
<114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rootclk PB2CLK>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1
&pinctrl_uart1_cts
&pinctrl_uart1_rts>;
cts-gpios = <&gpio1 15 0>;
};

21
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Socionext Milbeaut UART controller
Required properties:
- compatible: should be "socionext,milbeaut-usio-uart".
- reg: offset and length of the register set for the device.
- interrupts: two interrupts specifier.
- interrupt-names: should be "rx", "tx".
- clocks: phandle to the input clock.
Optional properties:
- auto-flow-control: flow control enable.
Example:
usio1: usio_uart@1e700010 {
compatible = "socionext,milbeaut-usio-uart";
reg = <0x1e700010 0x10>;
interrupts = <0 141 0x4>, <0 149 0x4>;
interrupt-names = "rx", "tx";
clocks = <&clk 2>;
auto-flow-control;
};

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Device tree bindings for Marvell PXA SSP ports
Required properties:
- compatible: Must be one of
mrvl,pxa25x-ssp
mvrl,pxa25x-nssp
mrvl,pxa27x-ssp
mrvl,pxa3xx-ssp
mvrl,pxa168-ssp
mrvl,pxa910-ssp
mrvl,ce4100-ssp
- reg: The memory base
- dmas: Two dma phandles, one for rx, one for tx
- dma-names: Must be "rx", "tx"
Example for PXA3xx:
ssp0: ssp@41000000 {
compatible = "mrvl,pxa3xx-ssp";
reg = <0x41000000 0x40>;
ssp-id = <1>;
interrupts = <24>;
clock-names = "pxa27x-ssp.0";
dmas = <&dma 13
&dma 14>;
dma-names = "rx", "tx";
};
ssp1: ssp@41700000 {
compatible = "mrvl,pxa3xx-ssp";
reg = <0x41700000 0x40>;
ssp-id = <2>;
interrupts = <16>;
clock-names = "pxa27x-ssp.1";
dmas = <&dma 15
&dma 16>;
dma-names = "rx", "tx";
};
ssp2: ssp@41900000 {
compatibl3 = "mrvl,pxa3xx-ssp";
reg = <0x41900000 0x40>;
ssp-id = <3>;
interrupts = <0>;
clock-names = "pxa27x-ssp.2";
dmas = <&dma 66
&dma 67>;
dma-names = "rx", "tx";
};
ssp3: ssp@41a00000 {
compatible = "mrvl,pxa3xx-ssp";
reg = <0x41a00000 0x40>;
ssp-id = <4>;
interrupts = <13>;
clock-names = "pxa27x-ssp.3";
dmas = <&dma 2
&dma 3>;
dma-names = "rx", "tx";
};

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* Marvell UART : Non standard UART used in some of Marvell EBU SoCs
e.g., Armada-3700.
Required properties:
- compatible:
- "marvell,armada-3700-uart" for the standard variant of the UART
(32 bytes FIFO, no DMA, level interrupts, 8-bit access to the
FIFO), called also UART1.
- "marvell,armada-3700-uart-ext" for the extended variant of the
UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
accesses to the FIFO), called also UART2.
- reg: offset and length of the register set for the device.
- clocks: UART reference clock used to derive the baudrate. If no clock
is provided (possible only with the "marvell,armada-3700-uart"
compatible string for backward compatibility), it will only work
if the baudrate was initialized by the bootloader and no baudrate
change will then be possible. When provided it should be UART1-clk
for standard variant of UART and UART2-clk for extended variant
of UART. TBG clock (with UART TBG divisors d1=d2=1) or xtal clock
should not be used and are supported only for backward compatibility.
- interrupts:
- Must contain three elements for the standard variant of the IP
(marvell,armada-3700-uart): "uart-sum", "uart-tx" and "uart-rx",
respectively the UART sum interrupt, the UART TX interrupt and
UART RX interrupt. A corresponding interrupt-names property must
be defined.
- Must contain two elements for the extended variant of the IP
(marvell,armada-3700-uart-ext): "uart-tx" and "uart-rx",
respectively the UART TX interrupt and the UART RX interrupt. A
corresponding interrupt-names property must be defined.
- For backward compatibility reasons, a single element interrupts
property is also supported for the standard variant of the IP,
containing only the UART sum interrupt. This form is deprecated
and should no longer be used.
Example:
uart0: serial@12000 {
compatible = "marvell,armada-3700-uart";
reg = <0x12000 0x18>;
clocks = <&uartclk 0>;
interrupts =
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uart-sum", "uart-tx", "uart-rx";
};
uart1: serial@12200 {
compatible = "marvell,armada-3700-uart-ext";
reg = <0x12200 0x30>;
clocks = <&uartclk 1>;
interrupts =
<GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "uart-tx", "uart-rx";
};

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/nvidia,tegra194-tcu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra Combined UART (TCU)
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jonathan Hunter <jonathanh@nvidia.com>
description:
The TCU is a system for sharing a hardware UART instance among multiple
systems within the Tegra SoC. It is implemented through a mailbox-
based protocol where each "virtual UART" has a pair of mailboxes, one
for transmitting and one for receiving, that is used to communicate
with the hardware implementing the TCU.
properties:
$nodename:
pattern: "^serial(@.*)?$"
compatible:
oneOf:
- const: nvidia,tegra194-tcu
- items:
- enum:
- nvidia,tegra234-tcu
- const: nvidia,tegra194-tcu
mbox-names:
items:
- const: rx
- const: tx
mboxes:
description: |
List of phandles to mailbox channels used for receiving and
transmitting data from and to the hardware UART.
items:
- description: mailbox for receiving data from hardware UART
- description: mailbox for transmitting data to hardware UART
required:
- compatible
- mbox-names
- mboxes
additionalProperties: false
examples:
- |
#include <dt-bindings/mailbox/tegra186-hsp.h>
tcu: serial {
compatible = "nvidia,tegra194-tcu";
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>,
<&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>;
mbox-names = "rx", "tx";
};

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NVIDIA Tegra20/Tegra30 high speed (DMA based) UART controller driver.
Required properties:
- compatible : should be,
"nvidia,tegra20-hsuart" for Tegra20,
"nvidia,tegra30-hsuart" for Tegra30,
"nvidia,tegra186-hsuart" for Tegra186,
"nvidia,tegra194-hsuart" for Tegra194.
- reg: Should contain UART controller registers location and length.
- interrupts: Should contain UART controller interrupts.
- clocks: Must contain one entry, for the module clock.
See ../clocks/clock-bindings.txt for details.
- resets : Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names : Must include the following entries:
- serial
- dmas : Must contain an entry for each entry in dma-names.
See ../dma/dma.txt for details.
- dma-names : Must include the following entries:
- rx
- tx
Optional properties:
- nvidia,enable-modem-interrupt: Enable modem interrupts. Should be enable
only if all 8 lines of UART controller are pinmuxed.
- nvidia,adjust-baud-rates: List of entries providing percentage of baud rate
adjustment within a range.
Each entry contains sets of 3 values. Range low/high and adjusted rate.
<range_low range_high adjusted_rate>
When baud rate set on controller falls within the range mentioned in this
field, baud rate will be adjusted by percentage mentioned here.
Ex: <9600 115200 200>
Increase baud rate by 2% when set baud rate falls within range 9600 to 115200
Baud Rate tolerance:
Standard UART devices are expected to have tolerance for baud rate error by
-4 to +4 %. All Tegra devices till Tegra210 had this support. However,
Tegra186 chip has a known hardware issue. UART Rx baud rate tolerance level
is 0% to +4% in 1-stop config. Otherwise, the received data will have
corruption/invalid framing errors. Parker errata suggests adjusting baud
rate to be higher than the deviations observed in Tx.
Tx deviation of connected device can be captured over scope (or noted from
its spec) for valid range and Tegra baud rate has to be set above actual
Tx baud rate observed. To do this we use nvidia,adjust-baud-rates
As an example, consider there is deviation observed in Tx for baud rates as
listed below.
0 to 9600 has 1% deviation
9600 to 115200 2% deviation
This slight deviation is expcted and Tegra UART is expected to handle it. Due
to the issue stated above, baud rate on Tegra UART should be set equal to or
above deviation observed for avoiding frame errors.
Property should be set like this
nvidia,adjust-baud-rates = <0 9600 100>,
<9600 115200 200>;
Example:
serial@70006000 {
compatible = "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart";
reg = <0x70006000 0x40>;
reg-shift = <2>;
interrupts = <0 36 0x04>;
nvidia,enable-modem-interrupt;
clocks = <&tegra_car 6>;
resets = <&tegra_car 6>;
reset-names = "serial";
dmas = <&apbdma 8>, <&apbdma 8>;
dma-names = "rx", "tx";
nvidia,adjust-baud-rates = <1000000 4000000 136>; /* 1.36% shift */
};

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* NXP LPC1850 UART
Required properties:
- compatible : "nxp,lpc1850-uart", "ns16550a".
- reg : offset and length of the register set for the device.
- interrupts : should contain uart interrupt.
- clocks : phandle to the input clocks.
- clock-names : required elements: "uartclk", "reg".
Optional properties:
- dmas : Two or more DMA channel specifiers following the
convention outlined in bindings/dma/dma.txt
- dma-names : Names for the dma channels, if present. There must
be at least one channel named "tx" for transmit
and named "rx" for receive.
Since it's also possible to also use the of_serial.c driver all
parameters from 8250.txt also apply but are optional.
Example:
uart0: serial@40081000 {
compatible = "nxp,lpc1850-uart", "ns16550a";
reg = <0x40081000 0x1000>;
reg-shift = <2>;
interrupts = <24>;
clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;
clock-names = "uartclk", "reg";
};

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* NXP SC16IS7xx advanced Universal Asynchronous Receiver-Transmitter (UART)
* i2c as bus
Required properties:
- compatible: Should be one of the following:
- "nxp,sc16is740" for NXP SC16IS740,
- "nxp,sc16is741" for NXP SC16IS741,
- "nxp,sc16is750" for NXP SC16IS750,
- "nxp,sc16is752" for NXP SC16IS752,
- "nxp,sc16is760" for NXP SC16IS760,
- "nxp,sc16is762" for NXP SC16IS762.
- reg: I2C address of the SC16IS7xx device.
- interrupts: Should contain the UART interrupt
- clocks: Reference to the IC source clock.
OR (when there is no clock provider visible to the platform)
- clock-frequency: The source clock frequency for the IC.
Optional properties:
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Should be two. The first cell is the GPIO number and
the second cell is used to specify the GPIO polarity:
0 = active high,
1 = active low.
- irda-mode-ports: An array that lists the indices of the port that
should operate in IrDA mode.
Example:
sc16is750: sc16is750@51 {
compatible = "nxp,sc16is750";
reg = <0x51>;
clocks = <&clk20m>;
interrupt-parent = <&gpio3>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
};
* spi as bus
Required properties:
- compatible: Should be one of the following:
- "nxp,sc16is740" for NXP SC16IS740,
- "nxp,sc16is741" for NXP SC16IS741,
- "nxp,sc16is750" for NXP SC16IS750,
- "nxp,sc16is752" for NXP SC16IS752,
- "nxp,sc16is760" for NXP SC16IS760,
- "nxp,sc16is762" for NXP SC16IS762.
- reg: SPI chip select number.
- interrupts: Specifies the interrupt source of the parent interrupt
controller. The format of the interrupt specifier depends on the
parent interrupt controller.
- clocks: phandle to the IC source clock.
Optional properties:
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Should be two. The first cell is the GPIO number and
the second cell is used to specify the GPIO polarity:
0 = active high,
1 = active low.
- irda-mode-ports: An array that lists the indices of the port that
should operate in IrDA mode.
Example:
sc16is750: sc16is750@0 {
compatible = "nxp,sc16is750";
reg = <0>;
clocks = <&clk20m>;
interrupt-parent = <&gpio3>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
};

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* NXP LPC32xx SoC High Speed UART
Required properties:
- compatible: Should be "nxp,lpc3220-hsuart"
- reg: Should contain registers location and length
- interrupts: Should contain interrupt
Example:
uart1: serial@40014000 {
compatible = "nxp,lpc3220-hsuart";
reg = <0x40014000 0x1000>;
interrupts = <26 0>;
};

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/pl011.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM AMBA Primecell PL011 serial UART
maintainers:
- Rob Herring <robh@kernel.org>
allOf:
- $ref: serial.yaml#
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
properties:
compatible:
contains:
enum:
- arm,pl011
required:
- compatible
properties:
compatible:
items:
- const: arm,pl011
- const: arm,primecell
reg:
maxItems: 1
interrupts:
maxItems: 1
pinctrl-0: true
pinctrl-1: true
pinctrl-names:
description:
When present, must have one state named "default",
and may contain a second name named "sleep". The former
state sets up pins for ordinary operation whereas
the latter state will put the associated pins to sleep
when the UART is unused
minItems: 1
items:
- const: default
- const: sleep
clocks:
description:
When present, the first clock listed must correspond to
the clock named UARTCLK on the IP block, i.e. the clock
to the external serial line, whereas the second clock
must correspond to the PCLK clocking the internal logic
of the block. Just listing one clock (the first one) is
deprecated.
maxItems: 2
clock-names:
items:
- const: uartclk
- const: apb_pclk
dmas:
minItems: 1
maxItems: 2
dma-names:
minItems: 1
items:
- const: rx
- const: tx
auto-poll:
description:
Enables polling when using RX DMA.
type: boolean
poll-rate-ms:
description:
Rate at which poll occurs when auto-poll is set.
default 100ms.
default: 100
poll-timeout-ms:
description:
Poll timeout when auto-poll is set, default
3000ms.
default: 3000
resets:
maxItems: 1
reg-io-width:
description:
The size (in bytes) of the IO accesses that should be performed
on the device.
enum: [1, 4]
required:
- compatible
- reg
- interrupts
dependencies:
poll-rate-ms: [ auto-poll ]
poll-timeout-ms: [ auto-poll ]
unevaluatedProperties: false
examples:
- |
serial@80120000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x80120000 0x1000>;
interrupts = <0 11 4>;
dmas = <&dma 13 0 0x2>, <&dma 13 0 0x0>;
dma-names = "rx", "tx";
clocks = <&foo_clk>, <&bar_clk>;
clock-names = "uartclk", "apb_pclk";
};
...

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/qca,ar9330-uart.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Atheros AR9330 High-Speed UART
maintainers:
- Oleksij Rempel <o.rempel@pengutronix.de>
allOf:
- $ref: serial.yaml#
properties:
compatible:
const: qca,ar9330-uart
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
clock-names:
const: uart
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
serial@18020000 {
compatible = "qca,ar9330-uart";
reg = <0x18020000 0x14>;
clocks = <&ref>;
clock-names = "uart";
interrupt-parent = <&intc>;
interrupts = <3>;
};
...

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* MSM Serial UART
The MSM serial UART hardware is designed for low-speed use cases where a
dma-engine isn't needed. From a software perspective it's mostly compatible
with the MSM serial UARTDM except that it only supports reading and writing one
character at a time.
Required properties:
- compatible: Should contain "qcom,msm-uart"
- reg: Should contain UART register location and length.
- interrupts: Should contain UART interrupt.
- clocks: Should contain the core clock.
- clock-names: Should be "core".
Example:
A uart device at 0xa9c00000 with interrupt 11.
serial@a9c00000 {
compatible = "qcom,msm-uart";
reg = <0xa9c00000 0x1000>;
interrupts = <11>;
clocks = <&uart_cxc>;
clock-names = "core";
};

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# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/qcom,msm-uartdm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm MSM Serial UARTDM
maintainers:
- Andy Gross <agross@kernel.org>
- Bjorn Andersson <bjorn.andersson@linaro.org>
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
description: |
The MSM serial UARTDM hardware is designed for high-speed use cases where the
transmit and/or receive channels can be offloaded to a dma-engine. From a
software perspective it's mostly compatible with the MSM serial UART except
that it supports reading and writing multiple characters at a time.
Note:: Aliases may be defined to ensure the correct ordering of the UARTs.
The alias serialN will result in the UART being assigned port N. If any
serialN alias exists, then an alias must exist for each enabled UART. The
serialN aliases should be in a .dts file instead of in a .dtsi file.
properties:
compatible:
items:
- enum:
- qcom,msm-uartdm-v1.1
- qcom,msm-uartdm-v1.2
- qcom,msm-uartdm-v1.3
- qcom,msm-uartdm-v1.4
- const: qcom,msm-uartdm
clocks:
maxItems: 2
clock-names:
items:
- const: core
- const: iface
dmas:
maxItems: 2
dma-names:
items:
- const: tx
- const: rx
interrupts:
maxItems: 1
qcom,rx-crci:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Identificator for Client Rate Control Interface to be used with RX DMA
channel. Required when using DMA for reception with UARTDM v1.3 and
below.
qcom,tx-crci:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Identificator for Client Rate Control Interface to be used with TX DMA
channel. Required when using DMA for transmission with UARTDM v1.3 and
below.
reg:
minItems: 1
items:
- description: Main control registers
- description: An optional second register location shall specify the GSBI control region.
required:
- compatible
- clock-names
- clocks
- interrupts
- reg
unevaluatedProperties: false
allOf:
- $ref: /schemas/serial/serial.yaml#
- if:
properties:
compatible:
contains:
const: qcom,msm-uartdm-v1.3
then:
properties:
reg:
minItems: 2
else:
properties:
reg:
maxItems: 1
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
serial@f991e000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf991e000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&blsp1_uart2_apps_cxc>, <&blsp1_ahb_cxc>;
clock-names = "core", "iface";
dmas = <&dma0 0>, <&dma0 1>;
dma-names = "tx", "rx";
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/serial/qcom,serial-geni-qcom.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Qualcomm Geni based QUP UART interface
maintainers:
- Andy Gross <agross@kernel.org>
- Bjorn Andersson <bjorn.andersson@linaro.org>
allOf:
- $ref: /schemas/serial/serial.yaml#
properties:
compatible:
enum:
- qcom,geni-uart
- qcom,geni-debug-uart
clocks:
maxItems: 1
clock-names:
const: se
interconnects:
maxItems: 2
interconnect-names:
items:
- const: qup-core
- const: qup-config
interrupts:
minItems: 1
items:
- description: UART core irq
- description: Wakeup irq (RX GPIO)
operating-points-v2: true
pinctrl-0: true
pinctrl-1: true
pinctrl-names:
minItems: 1
items:
- const: default
- const: sleep
power-domains:
maxItems: 1
reg:
maxItems: 1
required:
- compatible
- clocks
- clock-names
- interrupts
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
#include <dt-bindings/interconnect/qcom,sc7180.h>
serial@a88000 {
compatible = "qcom,geni-uart";
reg = <0xa88000 0x7000>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-0 = <&qup_uart0_default>;
pinctrl-names = "default";
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
};
...

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/rda,8810pl-uart.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: RDA Micro UART Interface
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
allOf:
- $ref: serial.yaml#
properties:
compatible:
const: rda,8810pl-uart
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
- interrupts
- clocks
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
uart3: serial@20a90000 {
compatible = "rda,8810pl-uart";
reg = <0x20a90000 0x1000>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>;
};
...

74
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/serial/renesas,em-uart.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Renesas EMMA Mobile UART Interface
maintainers:
- Magnus Damm <magnus.damm@gmail.com>
properties:
compatible:
oneOf:
- items:
- enum:
- renesas,r9a09g011-uart # RZ/V2M
- const: renesas,em-uart # generic EMMA Mobile compatible UART
- items:
- const: renesas,em-uart # generic EMMA Mobile compatible UART
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 1
items:
- description: UART functional clock
- description: Internal clock to access the registers
clock-names:
minItems: 1
items:
- const: sclk
- const: pclk
allOf:
- $ref: serial.yaml#
- if:
properties:
compatible:
contains:
const: renesas,r9a09g011-uart
then:
properties:
clocks:
minItems: 2
clock-names:
minItems: 2
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
uart0: serial@e1020000 {
compatible = "renesas,em-uart";
reg = <0xe1020000 0x38>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&usia_u0_sclk>;
clock-names = "sclk";
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/serial/renesas,hscif.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Renesas High Speed Serial Communication Interface with FIFO (HSCIF)
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
allOf:
- $ref: serial.yaml#
properties:
compatible:
oneOf:
- items:
- enum:
- renesas,hscif-r8a7778 # R-Car M1
- renesas,hscif-r8a7779 # R-Car H1
- const: renesas,rcar-gen1-hscif # R-Car Gen1
- const: renesas,hscif # generic HSCIF compatible UART
- items:
- enum:
- renesas,hscif-r8a7742 # RZ/G1H
- renesas,hscif-r8a7743 # RZ/G1M
- renesas,hscif-r8a7744 # RZ/G1N
- renesas,hscif-r8a7745 # RZ/G1E
- renesas,hscif-r8a77470 # RZ/G1C
- renesas,hscif-r8a7790 # R-Car H2
- renesas,hscif-r8a7791 # R-Car M2-W
- renesas,hscif-r8a7792 # R-Car V2H
- renesas,hscif-r8a7793 # R-Car M2-N
- renesas,hscif-r8a7794 # R-Car E2
- const: renesas,rcar-gen2-hscif # R-Car Gen2 and RZ/G1
- const: renesas,hscif # generic HSCIF compatible UART
- items:
- enum:
- renesas,hscif-r8a774a1 # RZ/G2M
- renesas,hscif-r8a774b1 # RZ/G2N
- renesas,hscif-r8a774c0 # RZ/G2E
- renesas,hscif-r8a774e1 # RZ/G2H
- renesas,hscif-r8a7795 # R-Car H3
- renesas,hscif-r8a7796 # R-Car M3-W
- renesas,hscif-r8a77961 # R-Car M3-W+
- renesas,hscif-r8a77965 # R-Car M3-N
- renesas,hscif-r8a77970 # R-Car V3M
- renesas,hscif-r8a77980 # R-Car V3H
- renesas,hscif-r8a77990 # R-Car E3
- renesas,hscif-r8a77995 # R-Car D3
- const: renesas,rcar-gen3-hscif # R-Car Gen3 and RZ/G2
- const: renesas,hscif # generic HSCIF compatible UART
- items:
- enum:
- renesas,hscif-r8a779a0 # R-Car V3U
- renesas,hscif-r8a779f0 # R-Car S4-8
- renesas,hscif-r8a779g0 # R-Car V4H
- const: renesas,rcar-gen4-hscif # R-Car Gen4
- const: renesas,hscif # generic HSCIF compatible UART
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 1
maxItems: 4
clock-names:
minItems: 1
maxItems: 4
items:
enum:
- fck # UART functional clock
- hsck # optional external clock input
- brg_int # optional internal clock source for BRG frequency divider
- scif_clk # optional external clock source for BRG frequency divider
power-domains:
maxItems: 1
resets:
maxItems: 1
dmas:
minItems: 2
maxItems: 4
description:
Must contain a list of pairs of references to DMA specifiers, one for
transmission, and one for reception.
dma-names:
minItems: 2
maxItems: 4
items:
enum:
- tx
- rx
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- power-domains
unevaluatedProperties: false
if:
properties:
compatible:
contains:
enum:
- renesas,rcar-gen2-hscif
- renesas,rcar-gen3-hscif
- renesas,rcar-gen4-hscif
then:
required:
- resets
examples:
- |
#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a7795-sysc.h>
aliases {
serial1 = &hscif1;
};
hscif1: serial@e6550000 {
compatible = "renesas,hscif-r8a7795", "renesas,rcar-gen3-hscif",
"renesas,hscif";
reg = <0xe6550000 96>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 519>, <&cpg CPG_CORE R8A7795_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x33>, <&dmac1 0x32>, <&dmac2 0x33>, <&dmac2 0x32>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 519>;
uart-has-rtscts;
};

109
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/serial/renesas,sci.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Renesas Serial Communication Interface
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
allOf:
- $ref: serial.yaml#
properties:
compatible:
oneOf:
- items:
- enum:
- renesas,r9a07g043-sci # RZ/G2UL
- renesas,r9a07g044-sci # RZ/G2{L,LC}
- renesas,r9a07g054-sci # RZ/V2L
- const: renesas,sci # generic SCI compatible UART
- items:
- const: renesas,sci # generic SCI compatible UART
reg:
maxItems: 1
interrupts:
items:
- description: Error interrupt
- description: Receive buffer full interrupt
- description: Transmit buffer empty interrupt
- description: Transmit end interrupt
interrupt-names:
items:
- const: eri
- const: rxi
- const: txi
- const: tei
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
maxItems: 2
items:
enum:
- fck # UART functional clock
- sck # optional external clock input
uart-has-rtscts: false
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
if:
properties:
compatible:
contains:
enum:
- renesas,r9a07g043-sci
- renesas,r9a07g044-sci
- renesas,r9a07g054-sci
then:
properties:
resets:
maxItems: 1
power-domains:
maxItems: 1
required:
- resets
- power-domains
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/r9a07g044-cpg.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
aliases {
serial0 = &sci0;
};
sci0: serial@1004d000 {
compatible = "renesas,r9a07g044-sci", "renesas,sci";
reg = <0x1004d000 0x400>;
interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>;
clock-names = "fck";
power-domains = <&cpg>;
resets = <&cpg R9A07G044_SCI0_RST>;
};

197
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/serial/renesas,scif.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Renesas Serial Communication Interface with FIFO (SCIF)
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
allOf:
- $ref: serial.yaml#
properties:
compatible:
oneOf:
- items:
- enum:
- renesas,scif-r7s72100 # RZ/A1H
- const: renesas,scif # generic SCIF compatible UART
- items:
- enum:
- renesas,scif-r7s9210 # RZ/A2
- items:
- enum:
- renesas,scif-r8a7778 # R-Car M1
- renesas,scif-r8a7779 # R-Car H1
- const: renesas,rcar-gen1-scif # R-Car Gen1
- const: renesas,scif # generic SCIF compatible UART
- items:
- enum:
- renesas,scif-r8a7742 # RZ/G1H
- renesas,scif-r8a7743 # RZ/G1M
- renesas,scif-r8a7744 # RZ/G1N
- renesas,scif-r8a7745 # RZ/G1E
- renesas,scif-r8a77470 # RZ/G1C
- renesas,scif-r8a7790 # R-Car H2
- renesas,scif-r8a7791 # R-Car M2-W
- renesas,scif-r8a7792 # R-Car V2H
- renesas,scif-r8a7793 # R-Car M2-N
- renesas,scif-r8a7794 # R-Car E2
- const: renesas,rcar-gen2-scif # R-Car Gen2 and RZ/G1
- const: renesas,scif # generic SCIF compatible UART
- items:
- enum:
- renesas,scif-r8a774a1 # RZ/G2M
- renesas,scif-r8a774b1 # RZ/G2N
- renesas,scif-r8a774c0 # RZ/G2E
- renesas,scif-r8a774e1 # RZ/G2H
- renesas,scif-r8a7795 # R-Car H3
- renesas,scif-r8a7796 # R-Car M3-W
- renesas,scif-r8a77961 # R-Car M3-W+
- renesas,scif-r8a77965 # R-Car M3-N
- renesas,scif-r8a77970 # R-Car V3M
- renesas,scif-r8a77980 # R-Car V3H
- renesas,scif-r8a77990 # R-Car E3
- renesas,scif-r8a77995 # R-Car D3
- const: renesas,rcar-gen3-scif # R-Car Gen3 and RZ/G2
- const: renesas,scif # generic SCIF compatible UART
- items:
- enum:
- renesas,scif-r8a779a0 # R-Car V3U
- renesas,scif-r8a779f0 # R-Car S4-8
- const: renesas,rcar-gen4-scif # R-Car Gen4
- const: renesas,scif # generic SCIF compatible UART
- items:
- enum:
- renesas,scif-r9a07g044 # RZ/G2{L,LC}
- items:
- enum:
- renesas,scif-r9a07g043 # RZ/G2UL and RZ/Five
- renesas,scif-r9a07g054 # RZ/V2L
- const: renesas,scif-r9a07g044 # RZ/G2{L,LC} fallback
reg:
maxItems: 1
interrupts:
oneOf:
- items:
- description: A combined interrupt
- items:
- description: Error interrupt
- description: Receive buffer full interrupt
- description: Transmit buffer empty interrupt
- description: Transmit End interrupt
- items:
- description: Error interrupt
- description: Receive buffer full interrupt
- description: Transmit buffer empty interrupt
- description: Break interrupt
- description: Data Ready interrupt
- description: Transmit End interrupt
interrupt-names:
oneOf:
- items:
- const: eri
- const: rxi
- const: txi
- const: tei
- items:
- const: eri
- const: rxi
- const: txi
- const: bri
- const: dri
- const: tei
clocks:
minItems: 1
maxItems: 4
clock-names:
minItems: 1
maxItems: 4
items:
enum:
- fck # UART functional clock
- sck # optional external clock input
- brg_int # optional internal clock source for BRG frequency divider
- scif_clk # optional external clock source for BRG frequency divider
power-domains:
maxItems: 1
resets:
maxItems: 1
dmas:
minItems: 2
maxItems: 4
description:
Must contain a list of pairs of references to DMA specifiers, one for
transmission, and one for reception.
dma-names:
minItems: 2
maxItems: 4
items:
enum:
- tx
- rx
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- power-domains
if:
properties:
compatible:
contains:
enum:
- renesas,rcar-gen2-scif
- renesas,rcar-gen3-scif
- renesas,rcar-gen4-scif
- renesas,scif-r9a07g044
then:
required:
- resets
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/r8a7791-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a7791-sysc.h>
aliases {
serial0 = &scif0;
};
scif0: serial@e6e60000 {
compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
"renesas,scif";
reg = <0xe6e60000 64>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x29>, <&dmac0 0x2a>, <&dmac1 0x29>, <&dmac1 0x2a>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 721>;
};

112
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/serial/renesas,scifa.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Renesas Serial Communications Interface with FIFO A (SCIFA)
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
allOf:
- $ref: serial.yaml#
properties:
compatible:
oneOf:
- items:
- enum:
- renesas,scifa-r8a73a4 # R-Mobile APE6
- renesas,scifa-r8a7740 # R-Mobile A1
- renesas,scifa-sh73a0 # SH-Mobile AG5
- const: renesas,scifa # generic SCIFA compatible UART
- items:
- enum:
- renesas,scifa-r8a7742 # RZ/G1H
- renesas,scifa-r8a7743 # RZ/G1M
- renesas,scifa-r8a7744 # RZ/G1N
- renesas,scifa-r8a7745 # RZ/G1E
- renesas,scifa-r8a7790 # R-Car H2
- renesas,scifa-r8a7791 # R-Car M2-W
- renesas,scifa-r8a7793 # R-Car M2-N
- renesas,scifa-r8a7794 # R-Car E2
- const: renesas,rcar-gen2-scifa # R-Car Gen2 and RZ/G1
- const: renesas,scifa # generic SCIFA compatible UART
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
clock-names:
enum:
- fck # UART functional clock
power-domains:
maxItems: 1
resets:
maxItems: 1
dmas:
minItems: 2
maxItems: 4
description:
Must contain a list of pairs of references to DMA specifiers, one for
transmission, and one for reception.
dma-names:
minItems: 2
maxItems: 4
items:
enum:
- tx
- rx
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- power-domains
unevaluatedProperties: false
if:
properties:
compatible:
contains:
enum:
- renesas,rcar-gen2-scifa
then:
required:
- resets
examples:
- |
#include <dt-bindings/clock/r8a7790-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a7790-sysc.h>
aliases {
serial0 = &scifa0;
};
scifa0: serial@e6c40000 {
compatible = "renesas,scifa-r8a7790", "renesas,rcar-gen2-scifa",
"renesas,scifa";
reg = <0xe6c40000 64>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 204>;
clock-names = "fck";
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 204>;
dmas = <&dmac0 0x21>, <&dmac0 0x22>, <&dmac1 0x21>, <&dmac1 0x22>;
dma-names = "tx", "rx", "tx", "rx";
};

103
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/serial/renesas,scifb.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Renesas Serial Communications Interface with FIFO B (SCIFB)
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
allOf:
- $ref: serial.yaml#
properties:
compatible:
oneOf:
- items:
- enum:
- renesas,scifb-r8a73a4 # R-Mobile APE6
- renesas,scifb-r8a7740 # R-Mobile A1
- renesas,scifb-sh73a0 # SH-Mobile AG5
- const: renesas,scifb # generic SCIFB compatible UART
- items:
- enum:
- renesas,scifb-r8a7742 # RZ/G1H
- renesas,scifb-r8a7743 # RZ/G1M
- renesas,scifb-r8a7744 # RZ/G1N
- renesas,scifb-r8a7745 # RZ/G1E
- renesas,scifb-r8a7790 # R-Car H2
- renesas,scifb-r8a7791 # R-Car M2-W
- renesas,scifb-r8a7793 # R-Car M2-N
- renesas,scifb-r8a7794 # R-Car E2
- const: renesas,rcar-gen2-scifb # R-Car Gen2 and RZ/G1
- const: renesas,scifb # generic SCIFB compatible UART
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
clock-names:
enum:
- fck # UART functional clock
power-domains:
maxItems: 1
resets:
maxItems: 1
dmas:
minItems: 2
maxItems: 4
description:
Must contain a list of pairs of references to DMA specifiers, one for
transmission, and one for reception.
dma-names:
minItems: 2
maxItems: 4
items:
enum:
- tx
- rx
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- power-domains
unevaluatedProperties: false
if:
properties:
compatible:
contains:
enum:
- renesas,rcar-gen2-scifb
then:
required:
- resets
examples:
- |
#include <dt-bindings/clock/r8a7740-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
scifb: serial@e6c30000 {
compatible = "renesas,scifb-r8a7740", "renesas,scifb";
reg = <0xe6c30000 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
clock-names = "fck";
power-domains = <&pd_a3sp>;
};

1
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See rs485.yaml

56
bindings/serial/rs485.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/rs485.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: RS485 serial communications Bindings
description: The RTS signal is capable of automatically controlling line
direction for the built-in half-duplex mode. The properties described
hereafter shall be given to a half-duplex capable UART node.
maintainers:
- Rob Herring <robh@kernel.org>
properties:
rs485-rts-delay:
description: prop-encoded-array <a b>
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
items:
- description: Delay between rts signal and beginning of data sent in
milliseconds. It corresponds to the delay before sending data.
default: 0
maximum: 100
- description: Delay between end of data sent and rts signal in milliseconds.
It corresponds to the delay after sending data and actual release
of the line.
default: 0
maximum: 100
rs485-rts-active-low:
description: drive RTS low when sending (default is high).
$ref: /schemas/types.yaml#/definitions/flag
rs485-rx-active-high:
description: Polarity of receiver enable signal (when separate from RTS).
True indicates active high (default is low).
$ref: /schemas/types.yaml#/definitions/flag
linux,rs485-enabled-at-boot-time:
description: enables the rs485 feature at boot time. It can be disabled
later with proper ioctl.
$ref: /schemas/types.yaml#/definitions/flag
rs485-rx-during-tx:
description: enables the receiving of data even while sending data.
$ref: /schemas/types.yaml#/definitions/flag
rs485-term-gpios:
description: GPIO pin to enable RS485 bus termination.
maxItems: 1
additionalProperties: true
...

145
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/samsung_uart.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung S3C, S5P, Exynos, and S5L (Apple SoC) SoC UART Controller
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
- Greg Kroah-Hartman <gregkh@linuxfoundation.org>
description: |+
Each Samsung UART should have an alias correctly numbered in the "aliases"
node, according to serialN format, where N is the port number (non-negative
decimal integer) as specified by User's Manual of respective SoC.
properties:
compatible:
oneOf:
- items:
- const: samsung,exynosautov9-uart
- const: samsung,exynos850-uart
- enum:
- apple,s5l-uart
- axis,artpec8-uart
- samsung,s3c2410-uart
- samsung,s3c2412-uart
- samsung,s3c2440-uart
- samsung,s3c6400-uart
- samsung,s5pv210-uart
- samsung,exynos4210-uart
- samsung,exynos5433-uart
- samsung,exynos850-uart
reg:
maxItems: 1
reg-io-width:
description: |
The size (in bytes) of the IO accesses that should be performed
on the device.
enum: [ 1, 4 ]
clocks:
minItems: 2
maxItems: 5
clock-names:
description: N = 0 is allowed for SoCs without internal baud clock mux.
minItems: 2
items:
- const: uart
- pattern: '^clk_uart_baud[0-3]$'
- pattern: '^clk_uart_baud[0-3]$'
- pattern: '^clk_uart_baud[0-3]$'
- pattern: '^clk_uart_baud[0-3]$'
dmas:
items:
- description: DMA controller phandle and request line for RX
- description: DMA controller phandle and request line for TX
dma-names:
items:
- const: rx
- const: tx
interrupts:
description: RX interrupt and optionally TX interrupt.
minItems: 1
maxItems: 2
power-domains:
maxItems: 1
samsung,uart-fifosize:
description: The fifo size supported by the UART channel.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [16, 64, 256]
required:
- compatible
- clocks
- clock-names
- interrupts
- reg
unevaluatedProperties: false
allOf:
- $ref: serial.yaml#
- if:
properties:
compatible:
contains:
enum:
- samsung,s3c2410-uart
- samsung,s5pv210-uart
then:
properties:
clocks:
minItems: 2
maxItems: 3
clock-names:
minItems: 2
items:
- const: uart
- pattern: '^clk_uart_baud[0-1]$'
- pattern: '^clk_uart_baud[0-1]$'
- if:
properties:
compatible:
contains:
enum:
- apple,s5l-uart
- axis,artpec8-uart
- samsung,exynos4210-uart
- samsung,exynos5433-uart
then:
properties:
clocks:
maxItems: 2
clock-names:
items:
- const: uart
- const: clk_uart_baud0
examples:
- |
#include <dt-bindings/clock/samsung,s3c64xx-clock.h>
uart0: serial@7f005000 {
compatible = "samsung,s3c6400-uart";
reg = <0x7f005000 0x100>;
interrupt-parent = <&vic1>;
interrupts = <5>;
clock-names = "uart", "clk_uart_baud2",
"clk_uart_baud3";
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
<&clocks SCLK_UART>;
samsung,uart-fifosize = <16>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/serial/serial.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Serial Interface Generic DT Bindings
maintainers:
- Rob Herring <robh@kernel.org>
- Greg Kroah-Hartman <gregkh@linuxfoundation.org>
description:
This document lists a set of generic properties for describing UARTs in a
device tree. Whether these properties apply to a particular device depends
on the DT bindings for the actual device.
Each enabled UART may have an optional "serialN" alias in the "aliases" node,
where N is the port number (non-negative decimal integer) as printed on the
label next to the physical port.
properties:
$nodename:
pattern: "^serial(@.*)?$"
label: true
cts-gpios:
maxItems: 1
description:
Must contain a GPIO specifier, referring to the GPIO pin to be used as
the UART's CTS line.
dcd-gpios:
maxItems: 1
description:
Must contain a GPIO specifier, referring to the GPIO pin to be used as
the UART's DCD line.
dsr-gpios:
maxItems: 1
description:
Must contain a GPIO specifier, referring to the GPIO pin to be used as
the UART's DSR line.
dtr-gpios:
maxItems: 1
description:
Must contain a GPIO specifier, referring to the GPIO pin to be used as
the UART's DTR line.
rng-gpios:
maxItems: 1
description:
Must contain a GPIO specifier, referring to the GPIO pin to be used as
the UART's RNG line.
rts-gpios:
maxItems: 1
description:
Must contain a GPIO specifier, referring to the GPIO pin to be used as
the UART's RTS line.
uart-has-rtscts:
$ref: /schemas/types.yaml#/definitions/flag
description:
The presence of this property indicates that the UART has dedicated lines
for RTS/CTS hardware flow control, and that they are available for use
(wired and enabled by pinmux configuration). This depends on both the
UART hardware and the board wiring.
rx-tx-swap:
type: boolean
description: RX and TX pins are swapped.
cts-rts-swap:
type: boolean
description: CTS and RTS pins are swapped.
rx-threshold:
$ref: /schemas/types.yaml#/definitions/uint32
description:
RX FIFO threshold configuration (in bytes).
tx-threshold:
$ref: /schemas/types.yaml#/definitions/uint32
description:
TX FIFO threshold configuration (in bytes).
if:
required:
- uart-has-rtscts
then:
properties:
cts-gpios: false
rts-gpios: false
patternProperties:
".*":
if:
type: object
then:
description:
Serial attached devices shall be a child node of the host UART device
the slave device is attached to. It is expected that the attached
device is the only child node of the UART device. The slave device node
name shall reflect the generic type of device for the node.
properties:
compatible:
description:
Compatible of the device connected to the serial port.
max-speed:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The maximum baud rate the device operates at.
This should only be present if the maximum is less than the slave
device can support. For example, a particular board has some
signal quality issue or the host processor can't support higher
baud rates.
current-speed:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
The current baud rate the device operates at.
This should only be present in case a driver has no chance to know
the baud rate of the slave device.
Examples:
* device supports auto-baud
* the rate is setup by a bootloader and there is no way to reset
the device
* device baud rate is configured by its firmware but there is no
way to request the actual settings
required:
- compatible
additionalProperties: true
examples:
- |
serial@1234 {
compatible = "ns16550a";
reg = <0x1234 0x20>;
interrupts = <1>;
bluetooth {
compatible = "brcm,bcm4330-bt";
interrupt-parent = <&gpio>;
interrupts = <10>;
};
};

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/sifive-serial.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SiFive asynchronous serial interface (UART)
maintainers:
- Pragnesh Patel <pragnesh.patel@sifive.com>
- Paul Walmsley <paul.walmsley@sifive.com>
- Palmer Dabbelt <palmer@sifive.com>
allOf:
- $ref: serial.yaml#
properties:
compatible:
items:
- enum:
- sifive,fu540-c000-uart
- sifive,fu740-c000-uart
- canaan,k210-uarths
- const: sifive,uart0
description:
Should be something similar to "sifive,<chip>-uart"
for the UART as integrated on a particular chip,
and "sifive,uart<version>" for the general UART IP
block programming model.
UART HDL that corresponds to the IP block version
numbers can be found here -
https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/uart
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
- interrupts
- clocks
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/sifive-fu540-prci.h>
serial@10010000 {
compatible = "sifive,fu540-c000-uart", "sifive,uart0";
interrupt-parent = <&plic0>;
interrupts = <80>;
reg = <0x10010000 0x1000>;
clocks = <&prci FU540_PRCI_CLK_TLCLK>;
};
...

153
bindings/serial/snps-dw-apb-uart.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Synopsys DesignWare ABP UART
maintainers:
- Rob Herring <robh@kernel.org>
allOf:
- $ref: serial.yaml#
properties:
compatible:
oneOf:
- items:
- enum:
- renesas,r9a06g032-uart
- renesas,r9a06g033-uart
- const: renesas,rzn1-uart
- items:
- enum:
- rockchip,px30-uart
- rockchip,rk1808-uart
- rockchip,rk3036-uart
- rockchip,rk3066-uart
- rockchip,rk3128-uart
- rockchip,rk3188-uart
- rockchip,rk3288-uart
- rockchip,rk3308-uart
- rockchip,rk3328-uart
- rockchip,rk3368-uart
- rockchip,rk3399-uart
- rockchip,rk3568-uart
- rockchip,rk3588-uart
- rockchip,rv1108-uart
- rockchip,rv1126-uart
- const: snps,dw-apb-uart
- items:
- enum:
- brcm,bcm11351-dw-apb-uart
- brcm,bcm21664-dw-apb-uart
- const: snps,dw-apb-uart
- items:
- enum:
- starfive,jh7100-hsuart
- starfive,jh7100-uart
- const: snps,dw-apb-uart
- const: snps,dw-apb-uart
reg:
maxItems: 1
interrupts:
maxItems: 1
clock-frequency: true
clocks:
minItems: 1
maxItems: 2
clock-names:
items:
- const: baudclk
- const: apb_pclk
snps,uart-16550-compatible:
description: reflects the value of UART_16550_COMPATIBLE configuration
parameter. Define this if your UART does not implement the busy functionality.
type: boolean
resets:
maxItems: 1
reg-shift: true
reg-io-width: true
dcd-override:
description: Override the DCD modem status signal. This signal will
always be reported as active instead of being obtained from the modem
status register. Define this if your serial port does not use this
pin.
type: boolean
dsr-override:
description: Override the DTS modem status signal. This signal will
always be reported as active instead of being obtained from the modem
status register. Define this if your serial port does not use this
pin.
type: boolean
cts-override:
description: Override the CTS modem status signal. This signal will
always be reported as active instead of being obtained from the modem
status register. Define this if your serial port does not use this
pin.
type: boolean
ri-override:
description: Override the RI modem status signal. This signal will always
be reported as inactive instead of being obtained from the modem status
register. Define this if your serial port does not use this pin.
type: boolean
required:
- compatible
- reg
- interrupts
unevaluatedProperties: false
examples:
- |
serial@80230000 {
compatible = "snps,dw-apb-uart";
reg = <0x80230000 0x100>;
clock-frequency = <3686400>;
interrupts = <10>;
reg-shift = <2>;
reg-io-width = <4>;
dcd-override;
dsr-override;
cts-override;
ri-override;
};
- |
// Example with one clock:
serial@80230000 {
compatible = "snps,dw-apb-uart";
reg = <0x80230000 0x100>;
clocks = <&baudclk>;
interrupts = <10>;
reg-shift = <2>;
reg-io-width = <4>;
};
- |
// Example with two clocks:
serial@80230000 {
compatible = "snps,dw-apb-uart";
reg = <0x80230000 0x100>;
clocks = <&baudclk>, <&apb_pclk>;
clock-names = "baudclk", "apb_pclk";
interrupts = <10>;
reg-shift = <2>;
reg-io-width = <4>;
};
...

51
bindings/serial/socionext,uniphier-uart.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/socionext,uniphier-uart.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: UniPhier UART controller
maintainers:
- Masahiro Yamada <yamada.masahiro@socionext.com>
properties:
compatible:
const: socionext,uniphier-uart
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
auto-flow-control:
description: enable automatic flow control support.
$ref: /schemas/types.yaml#/definitions/flag
required:
- compatible
- reg
- interrupts
- clocks
additionalProperties: false
examples:
- |
aliases {
serial0 = &serial0;
};
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
reg = <0x54006800 0x40>;
interrupts = <0 33 4>;
clocks = <&uart_clk>;
};

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bindings/serial/sprd-uart.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2019 Unisoc Inc.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/serial/sprd-uart.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Spreadtrum serial UART
maintainers:
- Orson Zhai <orsonzhai@gmail.com>
- Baolin Wang <baolin.wang7@gmail.com>
- Chunyan Zhang <zhang.lyra@gmail.com>
properties:
compatible:
oneOf:
- items:
- enum:
- sprd,sc9860-uart
- sprd,sc9863a-uart
- sprd,ums512-uart
- const: sprd,sc9836-uart
- const: sprd,sc9836-uart
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 1
maxItems: 3
clock-names:
description: |
"enable" for UART module enable clock, "uart" for UART clock, "source"
for UART source (parent) clock.
items:
- const: enable
- const: uart
- const: source
dmas:
minItems: 1
maxItems: 2
dma-names:
minItems: 1
items:
- const: rx
- const: tx
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
serial@0 {
compatible = "sprd,sc9860-uart", "sprd,sc9836-uart";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
dma-names = "rx", "tx";
dmas = <&ap_dma 19>, <&ap_dma 20>;
clock-names = "enable", "uart", "source";
clocks = <&clk_ap_apb_gates 9>, <&clk_uart0>, <&ext_26m>;
};
...

133
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/st,stm32-uart.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
maintainers:
- Erwan Le Ray <erwan.leray@foss.st.com>
title: STMicroelectronics STM32 USART bindings
properties:
compatible:
enum:
- st,stm32-uart
- st,stm32f7-uart
- st,stm32h7-uart
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
label:
description: label associated with this uart
st,hw-flow-ctrl:
description: enable hardware flow control (deprecated)
$ref: /schemas/types.yaml#/definitions/flag
uart-has-rtscts: true
rx-tx-swap: true
dmas:
minItems: 1
maxItems: 2
dma-names:
items:
enum: [ rx, tx ]
minItems: 1
maxItems: 2
# cts-gpios and rts-gpios properties can be used instead of 'uart-has-rtscts'
# or 'st,hw-flow-ctrl' (deprecated) for making use of any gpio pins for flow
# control instead of dedicated pins.
#
# It should be noted that both cts-gpios/rts-gpios and 'uart-has-rtscts' or
# 'st,hw-flow-ctrl' (deprecated) properties cannot co-exist in a design.
cts-gpios: true
rts-gpios: true
wakeup-source: true
rs485-rts-delay: true
rs485-rts-active-low: true
linux,rs485-enabled-at-boot-time: true
rs485-rx-during-tx: true
rx-threshold:
description:
If value is set to 1, RX FIFO threshold is disabled.
enum: [1, 2, 4, 8, 12, 14, 16]
default: 8
tx-threshold:
description:
If value is set to 1, TX FIFO threshold is disabled.
enum: [1, 2, 4, 8, 12, 14, 16]
default: 8
allOf:
- $ref: rs485.yaml#
- $ref: serial.yaml#
- if:
required:
- st,hw-flow-ctrl
then:
properties:
cts-gpios: false
rts-gpios: false
- if:
properties:
compatible:
const: st,stm32-uart
then:
properties:
rx-tx-swap: false
- if:
properties:
compatible:
contains:
enum:
- st,stm32-uart
- st,stm32f7-uart
then:
properties:
rx-threshold: false
tx-threshold: false
required:
- compatible
- reg
- interrupts
- clocks
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/stm32mp1-clks.h>
usart1: serial@40011000 {
compatible = "st,stm32h7-uart";
reg = <0x40011000 0x400>;
interrupts = <37>;
clocks = <&rcc 0 164>;
dmas = <&dma2 2 4 0x414 0x0>,
<&dma2 7 4 0x414 0x0>;
dma-names = "rx", "tx";
rx-threshold = <4>;
tx-threshold = <4>;
rs485-rts-active-low;
};
...

18
bindings/serial/st-asc.txt Normal file
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*st-asc(Serial Port)
Required properties:
- compatible : Should be "st,asc".
- reg, reg-names, interrupts, interrupt-names : Standard way to define device
resources with names. look in
Documentation/devicetree/bindings/resource-names.txt
Optional properties:
- st,hw-flow-ctrl bool flag to enable hardware flow control.
- st,force-m1 bool flat to force asc to be in Mode-1 recommeded
for high bit rates (above 19.2K)
Example:
serial@fe440000{
compatible = "st,asc";
reg = <0xfe440000 0x2c>;
interrupts = <0 209 0>;
};

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bindings/serial/sunplus,sp7021-uart.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) Sunplus Co., Ltd. 2021
%YAML 1.2
---
$id: "http://devicetree.org/schemas/serial/sunplus,sp7021-uart.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Sunplus SoC SP7021 UART Controller
maintainers:
- Hammer Hsieh <hammerh0314@gmail.com>
allOf:
- $ref: serial.yaml#
properties:
compatible:
const: sunplus,sp7021-uart
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
required:
- compatible
- reg
- interrupts
- clocks
- resets
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
aliases {
serial0 = &uart0;
};
uart0: serial@9c000900 {
compatible = "sunplus,sp7021-uart";
reg = <0x9c000900 0x80>;
interrupt-parent = <&intc>;
interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc 0x28>;
resets = <&rstc 0x18>;
};
...

27
bindings/serial/vt8500-uart.txt Normal file
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* VIA VT8500 and WonderMedia WM8xxx UART Controller
Required properties:
- compatible: should be "via,vt8500-uart" (for VIA/WonderMedia chips up to and
including WM8850/WM8950), or "wm,wm8880-uart" (for WM8880 and later)
- reg: base physical address of the controller and length of memory mapped
region.
- interrupts: hardware interrupt number
- clocks: shall be the input parent clock phandle for the clock. This should
be the 24Mhz reference clock.
Aliases may be defined to ensure the correct ordering of the uarts.
Example:
aliases {
serial0 = &uart0;
};
uart0: serial@d8200000 {
compatible = "via,vt8500-uart";
reg = <0xd8200000 0x1040>;
interrupts = <32>;
clocks = <&clkuart0>;
};

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bindings/serial/xlnx,opb-uartlite.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/xlnx,opb-uartlite.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Axi Uartlite
maintainers:
- Peter Korsgaard <jacmet@sunsite.dk>
properties:
compatible:
contains:
enum:
- xlnx,xps-uartlite-1.00.a
- xlnx,opb-uartlite-1.00.b
reg:
maxItems: 1
interrupts:
maxItems: 1
port-number:
$ref: /schemas/types.yaml#/definitions/uint32
description: Set Uart port number
clocks:
maxItems: 1
clock-names:
const: s_axi_aclk
current-speed:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The fixed baud rate that the device was configured for.
xlnx,data-bits:
enum: [5, 6, 7, 8]
description:
The fixed number of data bits that the device was configured for.
xlnx,use-parity:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
description:
Whether parity checking was enabled when the device was configured.
xlnx,odd-parity:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
description:
Whether odd parity was configured.
required:
- compatible
- reg
- interrupts
- current-speed
- xlnx,data-bits
- xlnx,use-parity
allOf:
- $ref: /schemas/serial.yaml#
- if:
properties:
xlnx,use-parity:
contains:
const: 1
then:
required:
- xlnx,odd-parity
unevaluatedProperties: false
examples:
- |
serial@800c0000 {
compatible = "xlnx,xps-uartlite-1.00.a";
reg = <0x800c0000 0x10000>;
interrupts = <0x0 0x6e 0x1>;
port-number = <0>;
current-speed = <115200>;
xlnx,data-bits = <8>;
xlnx,use-parity = <0>;
};
...