dt-bindings: Add devicetree bindings
Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").
Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
This commit is contained in:
Melody Olvera
115
bindings/pwm/allwinner,sun4i-a10-pwm.yaml
Normal file
115
bindings/pwm/allwinner,sun4i-a10-pwm.yaml
Normal file
@@ -0,0 +1,115 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pwm/allwinner,sun4i-a10-pwm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A10 PWM
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
properties:
|
||||
"#pwm-cells":
|
||||
const: 3
|
||||
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: allwinner,sun4i-a10-pwm
|
||||
- const: allwinner,sun5i-a10s-pwm
|
||||
- const: allwinner,sun5i-a13-pwm
|
||||
- const: allwinner,sun7i-a20-pwm
|
||||
- const: allwinner,sun8i-h3-pwm
|
||||
- items:
|
||||
- const: allwinner,sun8i-a83t-pwm
|
||||
- const: allwinner,sun8i-h3-pwm
|
||||
- items:
|
||||
- enum:
|
||||
- allwinner,suniv-f1c100s-pwm
|
||||
- allwinner,sun8i-v3s-pwm
|
||||
- const: allwinner,sun7i-a20-pwm
|
||||
- items:
|
||||
- const: allwinner,sun50i-a64-pwm
|
||||
- const: allwinner,sun5i-a13-pwm
|
||||
- items:
|
||||
- const: allwinner,sun50i-h5-pwm
|
||||
- const: allwinner,sun5i-a13-pwm
|
||||
- const: allwinner,sun50i-h6-pwm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: Module Clock
|
||||
- description: Bus Clock
|
||||
|
||||
# Even though it only applies to subschemas under the conditionals,
|
||||
# not listing them here will trigger a warning because of the
|
||||
# additionalsProperties set to false.
|
||||
clock-names: true
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
|
||||
allOf:
|
||||
- $ref: pwm.yaml#
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: allwinner,sun50i-h6-pwm
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: mod
|
||||
- const: bus
|
||||
|
||||
required:
|
||||
- clock-names
|
||||
- resets
|
||||
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
pwm: pwm@1c20e00 {
|
||||
compatible = "allwinner,sun7i-a20-pwm";
|
||||
reg = <0x01c20e00 0xc>;
|
||||
clocks = <&osc24M>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/clock/sun50i-h6-ccu.h>
|
||||
#include <dt-bindings/reset/sun50i-h6-ccu.h>
|
||||
|
||||
pwm@300a000 {
|
||||
compatible = "allwinner,sun50i-h6-pwm";
|
||||
reg = <0x0300a000 0x400>;
|
||||
clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
|
||||
clock-names = "mod", "bus";
|
||||
resets = <&ccu RST_BUS_PWM>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
...
|
||||
47
bindings/pwm/atmel,at91sam-pwm.yaml
Normal file
47
bindings/pwm/atmel,at91sam-pwm.yaml
Normal file
@@ -0,0 +1,47 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pwm/atmel,at91sam-pwm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Atmel/Microchip PWM controller
|
||||
|
||||
maintainers:
|
||||
- Claudiu Beznea <claudiu.beznea@microchip.com>
|
||||
|
||||
allOf:
|
||||
- $ref: "pwm.yaml#"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- atmel,at91sam9rl-pwm
|
||||
- atmel,sama5d3-pwm
|
||||
- atmel,sama5d2-pwm
|
||||
- microchip,sam9x60-pwm
|
||||
- items:
|
||||
- const: microchip,sama7g5-pwm
|
||||
- const: atmel,sama5d2-pwm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#pwm-cells":
|
||||
const: 3
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
pwm0: pwm@f8034000 {
|
||||
compatible = "atmel,at91sam9rl-pwm";
|
||||
reg = <0xf8034000 0x400>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
29
bindings/pwm/atmel-hlcdc-pwm.txt
Normal file
29
bindings/pwm/atmel-hlcdc-pwm.txt
Normal file
@@ -0,0 +1,29 @@
|
||||
Device-Tree bindings for Atmel's HLCDC (High-end LCD Controller) PWM driver
|
||||
|
||||
The Atmel HLCDC PWM is subdevice of the HLCDC MFD device.
|
||||
See ../mfd/atmel-hlcdc.txt for more details.
|
||||
|
||||
Required properties:
|
||||
- compatible: value should be one of the following:
|
||||
"atmel,hlcdc-pwm"
|
||||
- pinctr-names: the pin control state names. Should contain "default".
|
||||
- pinctrl-0: should contain the pinctrl states described by pinctrl
|
||||
default.
|
||||
- #pwm-cells: should be set to 3. This PWM chip use the default 3 cells
|
||||
bindings defined in pwm.yaml in this directory.
|
||||
|
||||
Example:
|
||||
|
||||
hlcdc: hlcdc@f0030000 {
|
||||
compatible = "atmel,sama5d3-hlcdc";
|
||||
reg = <0xf0030000 0x2000>;
|
||||
clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
|
||||
clock-names = "periph_clk","sys_clk", "slow_clk";
|
||||
|
||||
hlcdc_pwm: hlcdc-pwm {
|
||||
compatible = "atmel,hlcdc-pwm";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lcd_pwm>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
42
bindings/pwm/brcm,bcm7038-pwm.yaml
Normal file
42
bindings/pwm/brcm,bcm7038-pwm.yaml
Normal file
@@ -0,0 +1,42 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pwm/brcm,bcm7038-pwm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom BCM7038 PWM controller (BCM7xxx Set Top Box PWM controller)
|
||||
|
||||
maintainers:
|
||||
- Florian Fainelli <f.fainelli@gmail.com>
|
||||
|
||||
allOf:
|
||||
- $ref: pwm.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: brcm,bcm7038-pwm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#pwm-cells":
|
||||
const: 2
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
pwm: pwm@f0408000 {
|
||||
compatible = "brcm,bcm7038-pwm";
|
||||
reg = <0xf0408000 0x28>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&upg_fixed>;
|
||||
};
|
||||
45
bindings/pwm/brcm,iproc-pwm.yaml
Normal file
45
bindings/pwm/brcm,iproc-pwm.yaml
Normal file
@@ -0,0 +1,45 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pwm/brcm,iproc-pwm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom iProc PWM controller
|
||||
|
||||
maintainers:
|
||||
- Rafał Miłecki <rafal@milecki.pl>
|
||||
|
||||
description:
|
||||
This controller has 4 channels.
|
||||
|
||||
allOf:
|
||||
- $ref: pwm.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: brcm,iproc-pwm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
description: external clock
|
||||
maxItems: 1
|
||||
|
||||
"#pwm-cells":
|
||||
const: 3
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- reg
|
||||
- clocks
|
||||
|
||||
examples:
|
||||
- |
|
||||
pwm@18031000 {
|
||||
compatible = "brcm,iproc-pwm";
|
||||
reg = <0x18031000 0x28>;
|
||||
clocks = <&osc>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
21
bindings/pwm/brcm,kona-pwm.txt
Normal file
21
bindings/pwm/brcm,kona-pwm.txt
Normal file
@@ -0,0 +1,21 @@
|
||||
Broadcom Kona PWM controller device tree bindings
|
||||
|
||||
This controller has 6 channels.
|
||||
|
||||
Required Properties :
|
||||
- compatible: should contain "brcm,kona-pwm"
|
||||
- reg: physical base address and length of the controller's registers
|
||||
- clocks: phandle + clock specifier pair for the external clock
|
||||
- #pwm-cells: Should be 3. See pwm.yaml in this directory for a
|
||||
description of the cells format.
|
||||
|
||||
Refer to clocks/clock-bindings.txt for generic clock consumer properties.
|
||||
|
||||
Example:
|
||||
|
||||
pwm: pwm@3e01a000 {
|
||||
compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm";
|
||||
reg = <0x3e01a000 0xc4>;
|
||||
clocks = <&pwm_clk>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
15
bindings/pwm/cirrus,clps711x-pwm.txt
Normal file
15
bindings/pwm/cirrus,clps711x-pwm.txt
Normal file
@@ -0,0 +1,15 @@
|
||||
* Cirris Logic CLPS711X PWM controller
|
||||
|
||||
Required properties:
|
||||
- compatible: Shall contain "cirrus,ep7209-pwm".
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- clocks: phandle + clock specifier pair of the PWM reference clock.
|
||||
- #pwm-cells: Should be 1. The cell specifies the index of the channel.
|
||||
|
||||
Example:
|
||||
pwm: pwm@80000400 {
|
||||
compatible = "cirrus,ep7312-pwm", "cirrus,ep7209-pwm";
|
||||
reg = <0x80000400 0x4>;
|
||||
clocks = <&clks 8>;
|
||||
#pwm-cells = <1>;
|
||||
};
|
||||
46
bindings/pwm/clk-pwm.yaml
Normal file
46
bindings/pwm/clk-pwm.yaml
Normal file
@@ -0,0 +1,46 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pwm/clk-pwm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock based PWM controller
|
||||
|
||||
maintainers:
|
||||
- Nikita Travkin <nikita@trvn.ru>
|
||||
|
||||
description: |
|
||||
Some systems have clocks that can be exposed to external devices.
|
||||
(e.g. by muxing them to GPIO pins)
|
||||
It's often possible to control duty-cycle of such clocks which makes them
|
||||
suitable for generating PWM signal.
|
||||
|
||||
allOf:
|
||||
- $ref: pwm.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: clk-pwm
|
||||
|
||||
clocks:
|
||||
description: Clock used to generate the signal.
|
||||
maxItems: 1
|
||||
|
||||
"#pwm-cells":
|
||||
const: 2
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
|
||||
examples:
|
||||
- |
|
||||
pwm {
|
||||
compatible = "clk-pwm";
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&gcc 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm_clk_flash_default>;
|
||||
};
|
||||
58
bindings/pwm/google,cros-ec-pwm.yaml
Normal file
58
bindings/pwm/google,cros-ec-pwm.yaml
Normal file
@@ -0,0 +1,58 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pwm/google,cros-ec-pwm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: PWM controlled by ChromeOS EC
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- '"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>'
|
||||
|
||||
description: |
|
||||
Google's ChromeOS EC PWM is a simple PWM attached to the Embedded Controller
|
||||
(EC) and controlled via a host-command interface.
|
||||
An EC PWM node should be only found as a sub-node of the EC node (see
|
||||
Documentation/devicetree/bindings/mfd/google,cros-ec.yaml).
|
||||
|
||||
allOf:
|
||||
- $ref: pwm.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: PWM controlled using EC_PWM_TYPE_GENERIC channels.
|
||||
items:
|
||||
- const: google,cros-ec-pwm
|
||||
- description: PWM controlled using CROS_EC_PWM_DT_<...> types.
|
||||
items:
|
||||
- const: google,cros-ec-pwm-type
|
||||
|
||||
"#pwm-cells":
|
||||
description: The cell specifies the PWM index.
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#pwm-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cros-ec@0 {
|
||||
compatible = "google,cros-ec-spi";
|
||||
reg = <0>;
|
||||
interrupts = <101 0>;
|
||||
|
||||
cros_ec_pwm: pwm {
|
||||
compatible = "google,cros-ec-pwm";
|
||||
#pwm-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
24
bindings/pwm/img-pwm.txt
Normal file
24
bindings/pwm/img-pwm.txt
Normal file
@@ -0,0 +1,24 @@
|
||||
*Imagination Technologies PWM DAC driver
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "img,pistachio-pwm"
|
||||
- reg: Should contain physical base address and length of pwm registers.
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
See ../clock/clock-bindings.txt for details.
|
||||
- clock-names: Must include the following entries.
|
||||
- pwm: PWM operating clock.
|
||||
- sys: PWM system interface clock.
|
||||
- #pwm-cells: Should be 2. See pwm.yaml in this directory for the
|
||||
description of the cells format.
|
||||
- img,cr-periph: Must contain a phandle to the peripheral control
|
||||
syscon node which contains PWM control registers.
|
||||
|
||||
Example:
|
||||
pwm: pwm@18101300 {
|
||||
compatible = "img,pistachio-pwm";
|
||||
reg = <0x18101300 0x100>;
|
||||
clocks = <&pwm_clk>, <&system_clk>;
|
||||
clock-names = "pwm", "sys";
|
||||
#pwm-cells = <2>;
|
||||
img,cr-periph = <&cr_periph>;
|
||||
};
|
||||
85
bindings/pwm/imx-pwm.yaml
Normal file
85
bindings/pwm/imx-pwm.yaml
Normal file
@@ -0,0 +1,85 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pwm/imx-pwm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale i.MX PWM controller
|
||||
|
||||
maintainers:
|
||||
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||
|
||||
allOf:
|
||||
- $ref: pwm.yaml#
|
||||
|
||||
properties:
|
||||
"#pwm-cells":
|
||||
description: |
|
||||
Should be 2 for i.MX1 and 3 for i.MX27 and newer SoCs. See pwm.yaml
|
||||
in this directory for a description of the cells format.
|
||||
enum:
|
||||
- 2
|
||||
- 3
|
||||
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- fsl,imx1-pwm
|
||||
- fsl,imx27-pwm
|
||||
- items:
|
||||
- enum:
|
||||
- fsl,imx25-pwm
|
||||
- fsl,imx31-pwm
|
||||
- fsl,imx50-pwm
|
||||
- fsl,imx51-pwm
|
||||
- fsl,imx53-pwm
|
||||
- fsl,imx6q-pwm
|
||||
- fsl,imx6sl-pwm
|
||||
- fsl,imx6sll-pwm
|
||||
- fsl,imx6sx-pwm
|
||||
- fsl,imx6ul-pwm
|
||||
- fsl,imx7d-pwm
|
||||
- fsl,imx8mm-pwm
|
||||
- fsl,imx8mn-pwm
|
||||
- fsl,imx8mp-pwm
|
||||
- fsl,imx8mq-pwm
|
||||
- const: fsl,imx27-pwm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: SoC PWM ipg clock
|
||||
- description: SoC PWM per clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ipg
|
||||
- const: per
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/imx5-clock.h>
|
||||
|
||||
pwm@53fb4000 {
|
||||
#pwm-cells = <3>;
|
||||
compatible = "fsl,imx27-pwm";
|
||||
reg = <0x53fb4000 0x4000>;
|
||||
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
|
||||
<&clks IMX5_CLK_PWM1_HF_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
interrupts = <61>;
|
||||
};
|
||||
57
bindings/pwm/imx-tpm-pwm.yaml
Normal file
57
bindings/pwm/imx-tpm-pwm.yaml
Normal file
@@ -0,0 +1,57 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pwm/imx-tpm-pwm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale i.MX TPM PWM controller
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <anson.huang@nxp.com>
|
||||
|
||||
description: |
|
||||
The TPM counter and period counter are shared between multiple
|
||||
channels, so all channels should use same period setting.
|
||||
|
||||
allOf:
|
||||
- $ref: pwm.yaml#
|
||||
|
||||
properties:
|
||||
"#pwm-cells":
|
||||
const: 3
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- fsl,imx7ulp-pwm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
assigned-clocks:
|
||||
maxItems: 1
|
||||
|
||||
assigned-clock-parents:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/imx7ulp-clock.h>
|
||||
|
||||
pwm@40250000 {
|
||||
compatible = "fsl,imx7ulp-pwm";
|
||||
reg = <0x40250000 0x1000>;
|
||||
assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
|
||||
assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
|
||||
clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
46
bindings/pwm/intel,keembay-pwm.yaml
Normal file
46
bindings/pwm/intel,keembay-pwm.yaml
Normal file
@@ -0,0 +1,46 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2020 Intel Corporation
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pwm/intel,keembay-pwm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Intel Keem Bay PWM
|
||||
|
||||
maintainers:
|
||||
- Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
|
||||
|
||||
allOf:
|
||||
- $ref: pwm.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- intel,keembay-pwm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
"#pwm-cells":
|
||||
const: 2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#define KEEM_BAY_A53_GPIO
|
||||
|
||||
pwm@203200a0 {
|
||||
compatible = "intel,keembay-pwm";
|
||||
reg = <0x203200a0 0xe8>;
|
||||
clocks = <&scmi_clk KEEM_BAY_A53_GPIO>;
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
47
bindings/pwm/intel,lgm-pwm.yaml
Normal file
47
bindings/pwm/intel,lgm-pwm.yaml
Normal file
@@ -0,0 +1,47 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pwm/intel,lgm-pwm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: LGM SoC PWM fan controller
|
||||
|
||||
maintainers:
|
||||
- Rahul Tanwar <rtanwar@maxlinear.com>
|
||||
|
||||
allOf:
|
||||
- $ref: pwm.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: intel,lgm-pwm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#pwm-cells":
|
||||
const: 2
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- resets
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
pwm: pwm@e0d00000 {
|
||||
compatible = "intel,lgm-pwm";
|
||||
reg = <0xe0d00000 0x30>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&cgu0 126>;
|
||||
resets = <&rcu0 0x30 21>;
|
||||
};
|
||||
34
bindings/pwm/iqs620a-pwm.yaml
Normal file
34
bindings/pwm/iqs620a-pwm.yaml
Normal file
@@ -0,0 +1,34 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pwm/iqs620a-pwm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Azoteq IQS620A PWM Generator
|
||||
|
||||
maintainers:
|
||||
- Jeff LaBundy <jeff@labundy.com>
|
||||
|
||||
description: |
|
||||
The Azoteq IQS620A multi-function sensor generates a fixed-frequency PWM
|
||||
output represented by a "pwm" child node from the parent MFD driver. See
|
||||
Documentation/devicetree/bindings/mfd/iqs62x.yaml for further details as
|
||||
well as an example.
|
||||
|
||||
allOf:
|
||||
- $ref: pwm.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- azoteq,iqs620a-pwm
|
||||
|
||||
"#pwm-cells":
|
||||
const: 2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
...
|
||||
35
bindings/pwm/kontron,sl28cpld-pwm.yaml
Normal file
35
bindings/pwm/kontron,sl28cpld-pwm.yaml
Normal file
@@ -0,0 +1,35 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pwm/kontron,sl28cpld-pwm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: PWM driver for the sl28cpld board management controller
|
||||
|
||||
maintainers:
|
||||
- Michael Walle <michael@walle.cc>
|
||||
|
||||
description: |
|
||||
This module is part of the sl28cpld multi-function device. For more
|
||||
details see ../mfd/kontron,sl28cpld.yaml.
|
||||
|
||||
The controller supports one PWM channel and supports only four distinct
|
||||
frequencies (250Hz, 500Hz, 1kHz, 2kHz).
|
||||
|
||||
allOf:
|
||||
- $ref: pwm.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: kontron,sl28cpld-pwm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#pwm-cells":
|
||||
const: 2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
additionalProperties: false
|
||||
20
bindings/pwm/lpc1850-sct-pwm.txt
Normal file
20
bindings/pwm/lpc1850-sct-pwm.txt
Normal file
@@ -0,0 +1,20 @@
|
||||
* NXP LPC18xx State Configurable Timer - Pulse Width Modulator driver
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "nxp,lpc1850-sct-pwm"
|
||||
- reg: Should contain physical base address and length of pwm registers.
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
See ../clock/clock-bindings.txt for details.
|
||||
- clock-names: Must include the following entries.
|
||||
- pwm: PWM operating clock.
|
||||
- #pwm-cells: Should be 3. See pwm.yaml in this directory for the description
|
||||
of the cells format.
|
||||
|
||||
Example:
|
||||
pwm: pwm@40000000 {
|
||||
compatible = "nxp,lpc1850-sct-pwm";
|
||||
reg = <0x40000000 0x1000>;
|
||||
clocks =<&ccu1 CLK_CPU_SCT>;
|
||||
clock-names = "pwm";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
17
bindings/pwm/lpc32xx-pwm.txt
Normal file
17
bindings/pwm/lpc32xx-pwm.txt
Normal file
@@ -0,0 +1,17 @@
|
||||
LPC32XX PWM controller
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "nxp,lpc3220-pwm"
|
||||
- reg: physical base address and length of the controller's registers
|
||||
|
||||
Examples:
|
||||
|
||||
pwm@4005c000 {
|
||||
compatible = "nxp,lpc3220-pwm";
|
||||
reg = <0x4005c000 0x4>;
|
||||
};
|
||||
|
||||
pwm@4005c004 {
|
||||
compatible = "nxp,lpc3220-pwm";
|
||||
reg = <0x4005c004 0x4>;
|
||||
};
|
||||
76
bindings/pwm/mediatek,pwm-disp.yaml
Normal file
76
bindings/pwm/mediatek,pwm-disp.yaml
Normal file
@@ -0,0 +1,76 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pwm/mediatek,pwm-disp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek DISP_PWM Controller
|
||||
|
||||
maintainers:
|
||||
- Jitao Shi <jitao.shi@mediatek.com>
|
||||
- Xinlei Lee <xinlei.lee@mediatek.com>
|
||||
|
||||
allOf:
|
||||
- $ref: pwm.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- mediatek,mt2701-disp-pwm
|
||||
- mediatek,mt6595-disp-pwm
|
||||
- mediatek,mt8173-disp-pwm
|
||||
- mediatek,mt8183-disp-pwm
|
||||
- items:
|
||||
- const: mediatek,mt8167-disp-pwm
|
||||
- const: mediatek,mt8173-disp-pwm
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8186-disp-pwm
|
||||
- mediatek,mt8188-disp-pwm
|
||||
- mediatek,mt8192-disp-pwm
|
||||
- mediatek,mt8195-disp-pwm
|
||||
- const: mediatek,mt8183-disp-pwm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#pwm-cells":
|
||||
const: 2
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Main Clock
|
||||
- description: Mm Clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: main
|
||||
- const: mm
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#pwm-cells"
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/mt8173-clk.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
pwm0: pwm@1401e000 {
|
||||
compatible = "mediatek,mt8173-disp-pwm";
|
||||
reg = <0x1401e000 0x1000>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&mmsys CLK_MM_DISP_PWM026M>,
|
||||
<&mmsys CLK_MM_DISP_PWM0MM>;
|
||||
clock-names = "main", "mm";
|
||||
};
|
||||
83
bindings/pwm/microchip,corepwm.yaml
Normal file
83
bindings/pwm/microchip,corepwm.yaml
Normal file
@@ -0,0 +1,83 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pwm/microchip,corepwm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Microchip IP corePWM controller bindings
|
||||
|
||||
maintainers:
|
||||
- Conor Dooley <conor.dooley@microchip.com>
|
||||
|
||||
description: |
|
||||
corePWM is an 16 channel pulse width modulator FPGA IP
|
||||
|
||||
https://www.microsemi.com/existing-parts/parts/152118
|
||||
|
||||
allOf:
|
||||
- $ref: pwm.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: microchip,corepwm-rtl-v4
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
"#pwm-cells":
|
||||
enum: [2, 3]
|
||||
description:
|
||||
The only flag supported by the controller is PWM_POLARITY_INVERTED.
|
||||
|
||||
microchip,sync-update-mask:
|
||||
description: |
|
||||
Depending on how the IP is instantiated, there are two modes of operation.
|
||||
In synchronous mode, all channels are updated at the beginning of the PWM period,
|
||||
and in asynchronous mode updates happen as the control registers are written.
|
||||
A 16 bit wide "SHADOW_REG_EN" parameter of the IP core controls whether synchronous
|
||||
mode is possible for each channel, and is set by the bitstream programmed to the
|
||||
FPGA. If the IP core is instantiated with SHADOW_REG_ENx=1, both registers that
|
||||
control the duty cycle for channel x have a second "shadow"/buffer reg synthesised.
|
||||
At runtime a bit wide register exposed to APB can be used to toggle on/off
|
||||
synchronised mode for all channels it has been synthesised for.
|
||||
Each bit of "microchip,sync-update-mask" corresponds to a PWM channel & represents
|
||||
whether synchronous mode is possible for the PWM channel.
|
||||
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
default: 0
|
||||
|
||||
microchip,dac-mode-mask:
|
||||
description: |
|
||||
Optional, per-channel Low Ripple DAC mode is possible on this IP core. It creates
|
||||
a minimum period pulse train whose High/Low average is that of the chosen duty
|
||||
cycle. This "DAC" will have far better bandwidth and ripple performance than the
|
||||
standard PWM algorithm can achieve. A 16 bit DAC_MODE module parameter of the IP
|
||||
core, set at instantiation and by the bitstream programmed to the FPGA, determines
|
||||
whether a given channel operates in regular PWM or DAC mode.
|
||||
Each bit corresponds to a PWM channel & represents whether DAC mode is enabled
|
||||
for that channel.
|
||||
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
default: 0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
pwm@41000000 {
|
||||
compatible = "microchip,corepwm-rtl-v4";
|
||||
microchip,sync-update-mask = /bits/ 32 <0>;
|
||||
clocks = <&clkcfg 30>;
|
||||
reg = <0x41000000 0xF0>;
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
45
bindings/pwm/mxs-pwm.yaml
Normal file
45
bindings/pwm/mxs-pwm.yaml
Normal file
@@ -0,0 +1,45 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pwm/mxs-pwm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale MXS PWM controller
|
||||
|
||||
maintainers:
|
||||
- Shawn Guo <shawnguo@kernel.org>
|
||||
- Anson Huang <anson.huang@nxp.com>
|
||||
|
||||
allOf:
|
||||
- $ref: pwm.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- fsl,imx23-pwm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#pwm-cells":
|
||||
const: 3
|
||||
|
||||
fsl,pwm-number:
|
||||
$ref: '/schemas/types.yaml#/definitions/uint32'
|
||||
description: u32 value representing the number of PWM devices
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- fsl,pwm-number
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
pwm@80064000 {
|
||||
compatible = "fsl,imx23-pwm";
|
||||
reg = <0x80064000 0x2000>;
|
||||
#pwm-cells = <3>;
|
||||
fsl,pwm-number = <8>;
|
||||
};
|
||||
96
bindings/pwm/nvidia,tegra20-pwm.yaml
Normal file
96
bindings/pwm/nvidia,tegra20-pwm.yaml
Normal file
@@ -0,0 +1,96 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pwm/nvidia,tegra20-pwm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra PWFM controller
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- nvidia,tegra20-pwm
|
||||
- nvidia,tegra186-pwm
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,tegra30-pwm
|
||||
- nvidia,tegra114-pwm
|
||||
- nvidia,tegra124-pwm
|
||||
- nvidia,tegra132-pwm
|
||||
- nvidia,tegra210-pwm
|
||||
- enum:
|
||||
- nvidia,tegra20-pwm
|
||||
|
||||
- items:
|
||||
- const: nvidia,tegra194-pwm
|
||||
- const: nvidia,tegra186-pwm
|
||||
|
||||
- items:
|
||||
- const: nvidia,tegra234-pwm
|
||||
- const: nvidia,tegra194-pwm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: module reset
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: pwm
|
||||
|
||||
"#pwm-cells":
|
||||
const: 2
|
||||
|
||||
pinctrl-names:
|
||||
items:
|
||||
- const: default
|
||||
- const: sleep
|
||||
|
||||
pinctrl-0:
|
||||
description: configuration for the default/active state
|
||||
|
||||
pinctrl-1:
|
||||
description: configuration for the sleep state
|
||||
|
||||
operating-points-v2:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
power-domains:
|
||||
items:
|
||||
- description: phandle to the core power domain
|
||||
|
||||
allOf:
|
||||
- $ref: pwm.yaml
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra20-car.h>
|
||||
|
||||
pwm: pwm@7000a000 {
|
||||
compatible = "nvidia,tegra20-pwm";
|
||||
reg = <0x7000a000 0x100>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_PWM>;
|
||||
resets = <&tegra_car 17>;
|
||||
reset-names = "pwm";
|
||||
};
|
||||
27
bindings/pwm/nxp,pca9685-pwm.txt
Normal file
27
bindings/pwm/nxp,pca9685-pwm.txt
Normal file
@@ -0,0 +1,27 @@
|
||||
NXP PCA9685 16-channel 12-bit PWM LED controller
|
||||
================================================
|
||||
|
||||
Required properties:
|
||||
- compatible: "nxp,pca9685-pwm"
|
||||
- #pwm-cells: Should be 2. See pwm.yaml in this directory for a description of
|
||||
the cells format.
|
||||
The index 16 is the ALLCALL channel, that sets all PWM channels at the same
|
||||
time.
|
||||
|
||||
Optional properties:
|
||||
- invert (bool): boolean to enable inverted logic
|
||||
- open-drain (bool): boolean to configure outputs with open-drain structure;
|
||||
if omitted use totem-pole structure
|
||||
|
||||
Example:
|
||||
|
||||
For LEDs that are directly connected to the PCA, the following setting is
|
||||
applicable:
|
||||
|
||||
pca: pca@41 {
|
||||
compatible = "nxp,pca9685-pwm";
|
||||
#pwm-cells = <2>;
|
||||
reg = <0x41>;
|
||||
invert;
|
||||
open-drain;
|
||||
};
|
||||
30
bindings/pwm/pwm-bcm2835.txt
Normal file
30
bindings/pwm/pwm-bcm2835.txt
Normal file
@@ -0,0 +1,30 @@
|
||||
BCM2835 PWM controller (Raspberry Pi controller)
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "brcm,bcm2835-pwm"
|
||||
- reg: physical base address and length of the controller's registers
|
||||
- clocks: This clock defines the base clock frequency of the PWM hardware
|
||||
system, the period and the duty_cycle of the PWM signal is a multiple of
|
||||
the base period.
|
||||
- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
|
||||
the cells format.
|
||||
|
||||
Examples:
|
||||
|
||||
pwm@2020c000 {
|
||||
compatible = "brcm,bcm2835-pwm";
|
||||
reg = <0x2020c000 0x28>;
|
||||
clocks = <&clk_pwm>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
....
|
||||
clk_pwm: pwm {
|
||||
compatible = "fixed-clock";
|
||||
reg = <3>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <9200000>;
|
||||
};
|
||||
....
|
||||
};
|
||||
17
bindings/pwm/pwm-berlin.txt
Normal file
17
bindings/pwm/pwm-berlin.txt
Normal file
@@ -0,0 +1,17 @@
|
||||
Berlin PWM controller
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "marvell,berlin-pwm"
|
||||
- reg: physical base address and length of the controller's registers
|
||||
- clocks: phandle to the input clock
|
||||
- #pwm-cells: should be 3. See pwm.yaml in this directory for a description of
|
||||
the cells format.
|
||||
|
||||
Example:
|
||||
|
||||
pwm: pwm@f7f20000 {
|
||||
compatible = "marvell,berlin-pwm";
|
||||
reg = <0xf7f20000 0x40>;
|
||||
clocks = <&chip_clk CLKID_CFG>;
|
||||
#pwm-cells = <3>;
|
||||
}
|
||||
55
bindings/pwm/pwm-fsl-ftm.txt
Normal file
55
bindings/pwm/pwm-fsl-ftm.txt
Normal file
@@ -0,0 +1,55 @@
|
||||
Freescale FlexTimer Module (FTM) PWM controller
|
||||
|
||||
The same FTM PWM device can have a different endianness on different SoCs. The
|
||||
device tree provides a property to describing this so that an operating system
|
||||
device driver can handle all variants of the device. Refer to the table below
|
||||
for the endianness of the FTM PWM block as integrated into the existing SoCs:
|
||||
|
||||
SoC | FTM-PWM endianness
|
||||
--------+-------------------
|
||||
Vybrid | LE
|
||||
LS1 | BE
|
||||
LS2 | LE
|
||||
|
||||
Please see ../regmap/regmap.txt for more detail about how to specify endian
|
||||
modes in device tree.
|
||||
|
||||
|
||||
Required properties:
|
||||
- compatible : should be "fsl,<soc>-ftm-pwm" and one of the following
|
||||
compatible strings:
|
||||
- "fsl,vf610-ftm-pwm" for PWM compatible with the one integrated on VF610
|
||||
- "fsl,imx8qm-ftm-pwm" for PWM compatible with the one integrated on i.MX8QM
|
||||
- reg: Physical base address and length of the controller's registers
|
||||
- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
|
||||
the cells format.
|
||||
- clock-names: Should include the following module clock source entries:
|
||||
"ftm_sys" (module clock, also can be used as counter clock),
|
||||
"ftm_ext" (external counter clock),
|
||||
"ftm_fix" (fixed counter clock),
|
||||
"ftm_cnt_clk_en" (external and fixed counter clock enable/disable).
|
||||
- clocks: Must contain a phandle and clock specifier for each entry in
|
||||
clock-names, please see clock/clock-bindings.txt for details of the property
|
||||
values.
|
||||
- pinctrl-names: Must contain a "default" entry.
|
||||
- pinctrl-NNN: One property must exist for each entry in pinctrl-names.
|
||||
See pinctrl/pinctrl-bindings.txt for details of the property values.
|
||||
- big-endian: Boolean property, required if the FTM PWM registers use a big-
|
||||
endian rather than little-endian layout.
|
||||
|
||||
Example:
|
||||
|
||||
pwm0: pwm@40038000 {
|
||||
compatible = "fsl,vf610-ftm-pwm";
|
||||
reg = <0x40038000 0x1000>;
|
||||
#pwm-cells = <3>;
|
||||
clock-names = "ftm_sys", "ftm_ext",
|
||||
"ftm_fix", "ftm_cnt_clk_en";
|
||||
clocks = <&clks VF610_CLK_FTM0>,
|
||||
<&clks VF610_CLK_FTM0_EXT_SEL>,
|
||||
<&clks VF610_CLK_FTM0_FIX_SEL>,
|
||||
<&clks VF610_CLK_FTM0_EXT_FIX_EN>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm0_1>;
|
||||
big-endian;
|
||||
};
|
||||
23
bindings/pwm/pwm-hibvt.txt
Normal file
23
bindings/pwm/pwm-hibvt.txt
Normal file
@@ -0,0 +1,23 @@
|
||||
Hisilicon PWM controller
|
||||
|
||||
Required properties:
|
||||
-compatible: should contain one SoC specific compatible string
|
||||
The SoC specific strings supported including:
|
||||
"hisilicon,hi3516cv300-pwm"
|
||||
"hisilicon,hi3519v100-pwm"
|
||||
"hisilicon,hi3559v100-shub-pwm"
|
||||
"hisilicon,hi3559v100-pwm
|
||||
- reg: physical base address and length of the controller's registers.
|
||||
- clocks: phandle and clock specifier of the PWM reference clock.
|
||||
- resets: phandle and reset specifier for the PWM controller reset.
|
||||
- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
|
||||
the cells format.
|
||||
|
||||
Example:
|
||||
pwm: pwm@12130000 {
|
||||
compatible = "hisilicon,hi3516cv300-pwm";
|
||||
reg = <0x12130000 0x10000>;
|
||||
clocks = <&crg_ctrl HI3516CV300_PWM_CLK>;
|
||||
resets = <&crg_ctrl 0x38 0>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
58
bindings/pwm/pwm-lp3943.txt
Normal file
58
bindings/pwm/pwm-lp3943.txt
Normal file
@@ -0,0 +1,58 @@
|
||||
TI/National Semiconductor LP3943 PWM controller
|
||||
|
||||
Required properties:
|
||||
- compatible: "ti,lp3943-pwm"
|
||||
- #pwm-cells: Should be 2. See pwm.yaml in this directory for a
|
||||
description of the cells format.
|
||||
Note that this hardware limits the period length to the
|
||||
range 6250~1600000.
|
||||
- ti,pwm0 or ti,pwm1: Output pin number(s) for PWM channel 0 or 1.
|
||||
0 = output 0
|
||||
1 = output 1
|
||||
.
|
||||
.
|
||||
15 = output 15
|
||||
|
||||
Example:
|
||||
PWM 0 is for RGB LED brightness control
|
||||
PWM 1 is for brightness control of LP8557 backlight device
|
||||
|
||||
&i2c3 {
|
||||
lp3943@60 {
|
||||
compatible = "ti,lp3943";
|
||||
reg = <0x60>;
|
||||
|
||||
/*
|
||||
* PWM 0 : output 8, 9 and 10
|
||||
* PWM 1 : output 15
|
||||
*/
|
||||
pwm3943: pwm {
|
||||
compatible = "ti,lp3943-pwm";
|
||||
#pwm-cells = <2>;
|
||||
ti,pwm0 = <8 9 10>;
|
||||
ti,pwm1 = <15>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
/* LEDs control with PWM 0 of LP3943 */
|
||||
pwmleds {
|
||||
compatible = "pwm-leds";
|
||||
rgb {
|
||||
label = "indi::rgb";
|
||||
pwms = <&pwm3943 0 10000>;
|
||||
max-brightness = <255>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
/* Backlight control with PWM 1 of LP3943 */
|
||||
backlight@2c {
|
||||
compatible = "ti,lp8557";
|
||||
reg = <0x2c>;
|
||||
|
||||
pwms = <&pwm3943 1 10000>;
|
||||
pwm-names = "lp8557";
|
||||
};
|
||||
};
|
||||
52
bindings/pwm/pwm-mediatek.txt
Normal file
52
bindings/pwm/pwm-mediatek.txt
Normal file
@@ -0,0 +1,52 @@
|
||||
MediaTek PWM controller
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "mediatek,<name>-pwm":
|
||||
- "mediatek,mt2712-pwm": found on mt2712 SoC.
|
||||
- "mediatek,mt6795-pwm": found on mt6795 SoC.
|
||||
- "mediatek,mt7622-pwm": found on mt7622 SoC.
|
||||
- "mediatek,mt7623-pwm": found on mt7623 SoC.
|
||||
- "mediatek,mt7628-pwm": found on mt7628 SoC.
|
||||
- "mediatek,mt7629-pwm": found on mt7629 SoC.
|
||||
- "mediatek,mt8183-pwm": found on mt8183 SoC.
|
||||
- "mediatek,mt8195-pwm", "mediatek,mt8183-pwm": found on mt8195 SoC.
|
||||
- "mediatek,mt8365-pwm": found on mt8365 SoC.
|
||||
- "mediatek,mt8516-pwm": found on mt8516 SoC.
|
||||
- reg: physical base address and length of the controller's registers.
|
||||
- #pwm-cells: must be 2. See pwm.yaml in this directory for a description of
|
||||
the cell format.
|
||||
- clocks: phandle and clock specifier of the PWM reference clock.
|
||||
- clock-names: must contain the following, except for MT7628 which
|
||||
has no clocks
|
||||
- "top": the top clock generator
|
||||
- "main": clock used by the PWM core
|
||||
- "pwm1-3": the three per PWM clocks for mt8365
|
||||
- "pwm1-8": the eight per PWM clocks for mt2712
|
||||
- "pwm1-6": the six per PWM clocks for mt7622
|
||||
- "pwm1-5": the five per PWM clocks for mt7623
|
||||
- "pwm1" : the PWM1 clock for mt7629
|
||||
- pinctrl-names: Must contain a "default" entry.
|
||||
- pinctrl-0: One property must exist for each entry in pinctrl-names.
|
||||
See pinctrl/pinctrl-bindings.txt for details of the property values.
|
||||
|
||||
Optional properties:
|
||||
- assigned-clocks: Reference to the PWM clock entries.
|
||||
- assigned-clock-parents: The phandle of the parent clock of PWM clock.
|
||||
|
||||
Example:
|
||||
pwm0: pwm@11006000 {
|
||||
compatible = "mediatek,mt7623-pwm";
|
||||
reg = <0 0x11006000 0 0x1000>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&topckgen CLK_TOP_PWM_SEL>,
|
||||
<&pericfg CLK_PERI_PWM>,
|
||||
<&pericfg CLK_PERI_PWM1>,
|
||||
<&pericfg CLK_PERI_PWM2>,
|
||||
<&pericfg CLK_PERI_PWM3>,
|
||||
<&pericfg CLK_PERI_PWM4>,
|
||||
<&pericfg CLK_PERI_PWM5>;
|
||||
clock-names = "top", "main", "pwm1", "pwm2",
|
||||
"pwm3", "pwm4", "pwm5";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm0_pins>;
|
||||
};
|
||||
29
bindings/pwm/pwm-meson.txt
Normal file
29
bindings/pwm/pwm-meson.txt
Normal file
@@ -0,0 +1,29 @@
|
||||
Amlogic Meson PWM Controller
|
||||
============================
|
||||
|
||||
Required properties:
|
||||
- compatible: Shall contain "amlogic,meson8b-pwm"
|
||||
or "amlogic,meson-gxbb-pwm"
|
||||
or "amlogic,meson-gxbb-ao-pwm"
|
||||
or "amlogic,meson-axg-ee-pwm"
|
||||
or "amlogic,meson-axg-ao-pwm"
|
||||
or "amlogic,meson-g12a-ee-pwm"
|
||||
or "amlogic,meson-g12a-ao-pwm-ab"
|
||||
or "amlogic,meson-g12a-ao-pwm-cd"
|
||||
- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
|
||||
the cells format.
|
||||
|
||||
Optional properties:
|
||||
- clocks: Could contain one or two parents clocks phandle for each of the two
|
||||
PWM channels.
|
||||
- clock-names: Could contain at least the "clkin0" and/or "clkin1" names.
|
||||
|
||||
Example:
|
||||
|
||||
pwm_ab: pwm@8550 {
|
||||
compatible = "amlogic,meson-gxbb-pwm";
|
||||
reg = <0x0 0x08550 0x0 0x10>;
|
||||
#pwm-cells = <3>;
|
||||
clocks = <&xtal>, <&xtal>;
|
||||
clock-names = "clkin0", "clkin1";
|
||||
}
|
||||
22
bindings/pwm/pwm-omap-dmtimer.txt
Normal file
22
bindings/pwm/pwm-omap-dmtimer.txt
Normal file
@@ -0,0 +1,22 @@
|
||||
* OMAP PWM for dual-mode timers
|
||||
|
||||
Required properties:
|
||||
- compatible: Shall contain "ti,omap-dmtimer-pwm".
|
||||
- ti,timers: phandle to PWM capable OMAP timer. See timer/ti,timer-dm.yaml for info
|
||||
about these timers.
|
||||
- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
|
||||
the cells format.
|
||||
|
||||
Optional properties:
|
||||
- ti,prescaler: Should be a value between 0 and 7, see the timers datasheet
|
||||
- ti,clock-source: Set dmtimer parent clock, values between 0 and 2:
|
||||
- 0x00 - high-frequency system clock (timer_sys_ck)
|
||||
- 0x01 - 32-kHz always-on clock (timer_32k_ck)
|
||||
- 0x02 - external clock (timer_ext_ck, OMAP2 only)
|
||||
|
||||
Example:
|
||||
pwm9: dmtimer-pwm@9 {
|
||||
compatible = "ti,omap-dmtimer-pwm";
|
||||
ti,timers = <&timer9>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
105
bindings/pwm/pwm-rockchip.yaml
Normal file
105
bindings/pwm/pwm-rockchip.yaml
Normal file
@@ -0,0 +1,105 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pwm/pwm-rockchip.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip PWM controller
|
||||
|
||||
maintainers:
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: rockchip,rk2928-pwm
|
||||
- const: rockchip,rk3288-pwm
|
||||
- const: rockchip,rk3328-pwm
|
||||
- const: rockchip,vop-pwm
|
||||
- items:
|
||||
- const: rockchip,rk3036-pwm
|
||||
- const: rockchip,rk2928-pwm
|
||||
- items:
|
||||
- enum:
|
||||
- rockchip,rk3128-pwm
|
||||
- rockchip,rk3368-pwm
|
||||
- rockchip,rk3399-pwm
|
||||
- rockchip,rv1108-pwm
|
||||
- const: rockchip,rk3288-pwm
|
||||
- items:
|
||||
- enum:
|
||||
- rockchip,px30-pwm
|
||||
- rockchip,rk3308-pwm
|
||||
- rockchip,rk3568-pwm
|
||||
- rockchip,rk3588-pwm
|
||||
- const: rockchip,rk3328-pwm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
maxItems: 2
|
||||
|
||||
"#pwm-cells":
|
||||
enum: [2, 3]
|
||||
description:
|
||||
Must be 2 (rk2928) or 3 (rk3288 and later).
|
||||
See pwm.yaml for a description of the cell format.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
allOf:
|
||||
- $ref: pwm.yaml#
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- rockchip,rk3328-pwm
|
||||
- rockchip,rv1108-pwm
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: Used to derive the functional clock for the device.
|
||||
- description: Used as the APB bus clock.
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pwm
|
||||
- const: pclk
|
||||
|
||||
required:
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 1
|
||||
description:
|
||||
Used both to derive the functional clock
|
||||
for the device and as the bus clock.
|
||||
|
||||
required:
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/rk3188-cru-common.h>
|
||||
pwm0: pwm@20030000 {
|
||||
compatible = "rockchip,rk2928-pwm";
|
||||
reg = <0x20030000 0x10>;
|
||||
clocks = <&cru PCLK_PWM01>;
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
120
bindings/pwm/pwm-samsung.yaml
Normal file
120
bindings/pwm/pwm-samsung.yaml
Normal file
@@ -0,0 +1,120 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pwm/pwm-samsung.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung SoC PWM timers
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
description: |+
|
||||
Samsung SoCs contain PWM timer blocks which can be used for system clock source
|
||||
and clock event timers, as well as to drive SoC outputs with PWM signal. Each
|
||||
PWM timer block provides 5 PWM channels (not all of them can drive physical
|
||||
outputs - see SoC and board manual).
|
||||
|
||||
Be aware that the clocksource driver supports only uniprocessor systems.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,s3c2410-pwm # 16-bit, S3C24xx
|
||||
- samsung,s3c6400-pwm # 32-bit, S3C64xx
|
||||
- samsung,s5p6440-pwm # 32-bit, S5P64x0
|
||||
- samsung,s5pc100-pwm # 32-bit, S5PC100, S5PV210, Exynos4210 rev0 SoCs
|
||||
- samsung,exynos4210-pwm # 32-bit, Exynos
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
|
||||
clock-names:
|
||||
description: |
|
||||
Should contain all following required clock names:
|
||||
- "timers" - PWM base clock used to generate PWM signals,
|
||||
and any subset of following optional clock names:
|
||||
- "pwm-tclk0" - first external PWM clock source,
|
||||
- "pwm-tclk1" - second external PWM clock source.
|
||||
Note that not all IP variants allow using all external clock sources.
|
||||
Refer to SoC documentation to learn which clock source configurations
|
||||
are available.
|
||||
oneOf:
|
||||
- items:
|
||||
- const: timers
|
||||
- items:
|
||||
- const: timers
|
||||
- const: pwm-tclk0
|
||||
- items:
|
||||
- const: timers
|
||||
- const: pwm-tclk1
|
||||
- items:
|
||||
- const: timers
|
||||
- const: pwm-tclk0
|
||||
- const: pwm-tclk1
|
||||
|
||||
interrupts:
|
||||
description:
|
||||
One interrupt per timer, starting at timer 0. Necessary only for SoCs which
|
||||
use PWM clocksource.
|
||||
minItems: 1
|
||||
maxItems: 5
|
||||
|
||||
"#pwm-cells":
|
||||
description:
|
||||
The only third cell flag supported by this binding
|
||||
is PWM_POLARITY_INVERTED.
|
||||
const: 3
|
||||
|
||||
samsung,pwm-outputs:
|
||||
description:
|
||||
A list of PWM channels used as PWM outputs on particular platform.
|
||||
It is an array of up to 5 elements being indices of PWM channels
|
||||
(from 0 to 4), the order does not matter.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
uniqueItems: true
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 4
|
||||
|
||||
required:
|
||||
- clocks
|
||||
- clock-names
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: pwm.yaml#
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- samsung,s3c2410-pwm
|
||||
- samsung,s3c6400-pwm
|
||||
- samsung,s5p6440-pwm
|
||||
- samsung,s5pc100-pwm
|
||||
then:
|
||||
required:
|
||||
- interrupts
|
||||
|
||||
examples:
|
||||
- |
|
||||
pwm@7f006000 {
|
||||
compatible = "samsung,s3c6400-pwm";
|
||||
reg = <0x7f006000 0x1000>;
|
||||
interrupt-parent = <&vic0>;
|
||||
interrupts = <23>, <24>, <25>, <27>, <28>;
|
||||
clocks = <&clock 67>;
|
||||
clock-names = "timers";
|
||||
samsung,pwm-outputs = <0>, <1>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
73
bindings/pwm/pwm-sifive.yaml
Normal file
73
bindings/pwm/pwm-sifive.yaml
Normal file
@@ -0,0 +1,73 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2020 SiFive, Inc.
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: SiFive PWM controller
|
||||
|
||||
maintainers:
|
||||
- Sagar Kadam <sagar.kadam@sifive.com>
|
||||
- Paul Walmsley <paul.walmsley@sifive.com>
|
||||
|
||||
description:
|
||||
Unlike most other PWM controllers, the SiFive PWM controller currently
|
||||
only supports one period for all channels in the PWM. All PWMs need to
|
||||
run at the same period. The period also has significant restrictions on
|
||||
the values it can achieve, which the driver rounds to the nearest
|
||||
achievable period. PWM RTL that corresponds to the IP block version
|
||||
numbers can be found here -
|
||||
|
||||
https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
|
||||
|
||||
allOf:
|
||||
- $ref: pwm.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- sifive,fu540-c000-pwm
|
||||
- sifive,fu740-c000-pwm
|
||||
- const: sifive,pwm0
|
||||
description:
|
||||
Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". Supported
|
||||
compatible strings are "sifive,fu540-c000-pwm" and
|
||||
"sifive,fu740-c000-pwm" for the SiFive PWM v0 as integrated onto the
|
||||
SiFive FU540 and FU740 chip respectively, and "sifive,pwm0" for the
|
||||
SiFive PWM v0 IP block with no chip integration tweaks.
|
||||
Please refer to sifive-blocks-ip-versioning.txt for details.
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
"#pwm-cells":
|
||||
const: 3
|
||||
|
||||
interrupts:
|
||||
maxItems: 4
|
||||
description:
|
||||
Each PWM instance in FU540-C000 has 4 comparators. One interrupt per comparator.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
pwm: pwm@10020000 {
|
||||
compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
|
||||
reg = <0x10020000 0x1000>;
|
||||
clocks = <&tlclk>;
|
||||
interrupt-parent = <&plic>;
|
||||
interrupts = <42>, <43>, <44>, <45>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
40
bindings/pwm/pwm-sprd.txt
Normal file
40
bindings/pwm/pwm-sprd.txt
Normal file
@@ -0,0 +1,40 @@
|
||||
Spreadtrum PWM controller
|
||||
|
||||
Spreadtrum SoCs PWM controller provides 4 PWM channels.
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "sprd,ums512-pwm".
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- clocks: The phandle and specifier referencing the controller's clocks.
|
||||
- clock-names: Should contain following entries:
|
||||
"pwmn": used to derive the functional clock for PWM channel n (n range: 0 ~ 3).
|
||||
"enablen": for PWM channel n enable clock (n range: 0 ~ 3).
|
||||
- #pwm-cells: Should be 2. See pwm.yaml in this directory for a description of
|
||||
the cells format.
|
||||
|
||||
Optional properties:
|
||||
- assigned-clocks: Reference to the PWM clock entries.
|
||||
- assigned-clock-parents: The phandle of the parent clock of PWM clock.
|
||||
|
||||
Example:
|
||||
pwms: pwm@32260000 {
|
||||
compatible = "sprd,ums512-pwm";
|
||||
reg = <0 0x32260000 0 0x10000>;
|
||||
clock-names = "pwm0", "enable0",
|
||||
"pwm1", "enable1",
|
||||
"pwm2", "enable2",
|
||||
"pwm3", "enable3";
|
||||
clocks = <&aon_clk CLK_PWM0>, <&aonapb_gate CLK_PWM0_EB>,
|
||||
<&aon_clk CLK_PWM1>, <&aonapb_gate CLK_PWM1_EB>,
|
||||
<&aon_clk CLK_PWM2>, <&aonapb_gate CLK_PWM2_EB>,
|
||||
<&aon_clk CLK_PWM3>, <&aonapb_gate CLK_PWM3_EB>;
|
||||
assigned-clocks = <&aon_clk CLK_PWM0>,
|
||||
<&aon_clk CLK_PWM1>,
|
||||
<&aon_clk CLK_PWM2>,
|
||||
<&aon_clk CLK_PWM3>;
|
||||
assigned-clock-parents = <&ext_26m>,
|
||||
<&ext_26m>,
|
||||
<&ext_26m>,
|
||||
<&ext_26m>;
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
43
bindings/pwm/pwm-st.txt
Normal file
43
bindings/pwm/pwm-st.txt
Normal file
@@ -0,0 +1,43 @@
|
||||
STMicroelectronics PWM driver bindings
|
||||
--------------------------------------
|
||||
|
||||
Required parameters:
|
||||
- compatible : "st,pwm"
|
||||
- #pwm-cells : Number of cells used to specify a PWM. First cell
|
||||
specifies the per-chip index of the PWM to use and the
|
||||
second cell is the period in nanoseconds - fixed to 2
|
||||
for STiH41x.
|
||||
- reg : Physical base address and length of the controller's
|
||||
registers.
|
||||
- pinctrl-names: Set to "default".
|
||||
- pinctrl-0: List of phandles pointing to pin configuration nodes
|
||||
for PWM module.
|
||||
For Pinctrl properties, please refer to [1].
|
||||
- clock-names: Valid entries are "pwm" and/or "capture".
|
||||
- clocks: phandle of the clock used by the PWM module.
|
||||
For Clk properties, please refer to [2].
|
||||
- interrupts: IRQ for the Capture device
|
||||
|
||||
Optional properties:
|
||||
- st,pwm-num-chan: Number of available PWM channels. Default is 0.
|
||||
- st,capture-num-chan: Number of available Capture channels. Default is 0.
|
||||
|
||||
[1] Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Example:
|
||||
|
||||
pwm1: pwm@fe510000 {
|
||||
compatible = "st,pwm";
|
||||
reg = <0xfe510000 0x68>;
|
||||
#pwm-cells = <2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm1_chan0_default
|
||||
&pinctrl_pwm1_chan1_default
|
||||
&pinctrl_pwm1_chan2_default
|
||||
&pinctrl_pwm1_chan3_default>;
|
||||
clocks = <&clk_sysin>;
|
||||
clock-names = "pwm";
|
||||
st,pwm-num-chan = <4>;
|
||||
st,capture-num-chan = <2>;
|
||||
};
|
||||
63
bindings/pwm/pwm-tiecap.yaml
Normal file
63
bindings/pwm/pwm-tiecap.yaml
Normal file
@@ -0,0 +1,63 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pwm/pwm-tiecap.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: TI SOC ECAP based APWM controller
|
||||
|
||||
maintainers:
|
||||
- Vignesh R <vigneshr@ti.com>
|
||||
|
||||
allOf:
|
||||
- $ref: pwm.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: ti,am3352-ecap
|
||||
- items:
|
||||
- enum:
|
||||
- ti,da850-ecap
|
||||
- ti,am4372-ecap
|
||||
- ti,dra746-ecap
|
||||
- ti,k2g-ecap
|
||||
- ti,am654-ecap
|
||||
- ti,am64-ecap
|
||||
- const: ti,am3352-ecap
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#pwm-cells":
|
||||
const: 3
|
||||
description: |
|
||||
See pwm.yaml in this directory for a description of the cells format.
|
||||
The only third cell flag supported by this binding is PWM_POLARITY_INVERTED.
|
||||
|
||||
clock-names:
|
||||
const: fck
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
ecap0: pwm@48300100 { /* ECAP on am33xx */
|
||||
compatible = "ti,am3352-ecap";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48300100 0x80>;
|
||||
clocks = <&l4ls_gclk>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
64
bindings/pwm/pwm-tiehrpwm.yaml
Normal file
64
bindings/pwm/pwm-tiehrpwm.yaml
Normal file
@@ -0,0 +1,64 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pwm/pwm-tiehrpwm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: TI SOC EHRPWM based PWM controller
|
||||
|
||||
maintainers:
|
||||
- Vignesh R <vigneshr@ti.com>
|
||||
|
||||
allOf:
|
||||
- $ref: pwm.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: ti,am3352-ehrpwm
|
||||
- items:
|
||||
- enum:
|
||||
- ti,da850-ehrpwm
|
||||
- ti,am4372-ehrpwm
|
||||
- ti,dra746-ehrpwm
|
||||
- ti,am654-ehrpwm
|
||||
- ti,am64-epwm
|
||||
- const: ti,am3352-ehrpwm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#pwm-cells":
|
||||
const: 3
|
||||
description: |
|
||||
See pwm.yaml in this directory for a description of the cells format.
|
||||
The only third cell flag supported by this binding is PWM_POLARITY_INVERTED.
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: tbclk
|
||||
- const: fck
|
||||
|
||||
clocks:
|
||||
maxItems: 2
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
ehrpwm0: pwm@48300200 { /* EHRPWM on am33xx */
|
||||
compatible = "ti,am3352-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48300200 0x100>;
|
||||
clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
|
||||
clock-names = "tbclk", "fck";
|
||||
};
|
||||
58
bindings/pwm/pwm-tipwmss.txt
Normal file
58
bindings/pwm/pwm-tipwmss.txt
Normal file
@@ -0,0 +1,58 @@
|
||||
TI SOC based PWM Subsystem
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "ti,<soc>-pwmss".
|
||||
for am33xx - compatible = "ti,am33xx-pwmss";
|
||||
for am4372 - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
|
||||
for dra746 - compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"
|
||||
|
||||
- reg: physical base address and size of the registers map.
|
||||
- address-cells: Specify the number of u32 entries needed in child nodes.
|
||||
Should set to 1.
|
||||
- size-cells: specify number of u32 entries needed to specify child nodes size
|
||||
in reg property. Should set to 1.
|
||||
- ranges: describes the address mapping of a memory-mapped bus. Should set to
|
||||
physical address map of child's base address, physical address within
|
||||
parent's address space and length of the address map. For am33xx,
|
||||
3 set of child register maps present, ECAP register space, EQEP
|
||||
register space, EHRPWM register space.
|
||||
|
||||
Also child nodes should also populated under PWMSS DT node.
|
||||
|
||||
Example:
|
||||
epwmss0: epwmss@48300000 { /* PWMSS for am33xx */
|
||||
compatible = "ti,am33xx-pwmss";
|
||||
reg = <0x48300000 0x10>;
|
||||
ti,hwmods = "epwmss0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x48300100 0x48300100 0x80 /* ECAP */
|
||||
0x48300180 0x48300180 0x80 /* EQEP */
|
||||
0x48300200 0x48300200 0x80>; /* EHRPWM */
|
||||
|
||||
/* child nodes go here */
|
||||
};
|
||||
|
||||
epwmss0: epwmss@48300000 { /* PWMSS for am4372 */
|
||||
compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"
|
||||
reg = <0x48300000 0x10>;
|
||||
ti,hwmods = "epwmss0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x48300100 0x48300100 0x80 /* ECAP */
|
||||
0x48300180 0x48300180 0x80 /* EQEP */
|
||||
0x48300200 0x48300200 0x80>; /* EHRPWM */
|
||||
|
||||
/* child nodes go here */
|
||||
};
|
||||
|
||||
epwmss0: epwmss@4843e000 { /* PWMSS for DRA7xx */
|
||||
compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
|
||||
reg = <0x4843e000 0x30>;
|
||||
ti,hwmods = "epwmss0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
/* child nodes go here */
|
||||
};
|
||||
60
bindings/pwm/pwm.txt
Normal file
60
bindings/pwm/pwm.txt
Normal file
@@ -0,0 +1,60 @@
|
||||
Specifying PWM information for devices
|
||||
======================================
|
||||
|
||||
1) PWM user nodes
|
||||
-----------------
|
||||
|
||||
PWM users should specify a list of PWM devices that they want to use
|
||||
with a property containing a 'pwm-list':
|
||||
|
||||
pwm-list ::= <single-pwm> [pwm-list]
|
||||
single-pwm ::= <pwm-phandle> <pwm-specifier>
|
||||
pwm-phandle : phandle to PWM controller node
|
||||
pwm-specifier : array of #pwm-cells specifying the given PWM
|
||||
(controller specific)
|
||||
|
||||
PWM properties should be named "pwms". The exact meaning of each pwms
|
||||
property must be documented in the device tree binding for each device.
|
||||
An optional property "pwm-names" may contain a list of strings to label
|
||||
each of the PWM devices listed in the "pwms" property. If no "pwm-names"
|
||||
property is given, the name of the user node will be used as fallback.
|
||||
|
||||
Drivers for devices that use more than a single PWM device can use the
|
||||
"pwm-names" property to map the name of the PWM device requested by the
|
||||
pwm_get() call to an index into the list given by the "pwms" property.
|
||||
|
||||
The following example could be used to describe a PWM-based backlight
|
||||
device:
|
||||
|
||||
pwm: pwm {
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
|
||||
[...]
|
||||
|
||||
bl: backlight {
|
||||
pwms = <&pwm 0 5000000>;
|
||||
pwm-names = "backlight";
|
||||
};
|
||||
|
||||
Note that in the example above, specifying the "pwm-names" is redundant
|
||||
because the name "backlight" would be used as fallback anyway.
|
||||
|
||||
pwm-specifier typically encodes the chip-relative PWM number and the PWM
|
||||
period in nanoseconds.
|
||||
|
||||
Optionally, the pwm-specifier can encode a number of flags (defined in
|
||||
<dt-bindings/pwm/pwm.h>) in a third cell:
|
||||
- PWM_POLARITY_INVERTED: invert the PWM signal polarity
|
||||
|
||||
Example with optional PWM specifier for inverse polarity
|
||||
|
||||
bl: backlight {
|
||||
pwms = <&pwm 0 5000000 PWM_POLARITY_INVERTED>;
|
||||
pwm-names = "backlight";
|
||||
};
|
||||
|
||||
2) PWM controller nodes
|
||||
-----------------------
|
||||
|
||||
See pwm.yaml.
|
||||
34
bindings/pwm/pwm.yaml
Normal file
34
bindings/pwm/pwm.yaml
Normal file
@@ -0,0 +1,34 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pwm/pwm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: PWM controllers (providers)
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
|
||||
select: false
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^pwm(@.*|-[0-9a-f])*$"
|
||||
|
||||
"#pwm-cells":
|
||||
description:
|
||||
Number of cells in a PWM specifier.
|
||||
|
||||
required:
|
||||
- "#pwm-cells"
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
examples:
|
||||
- |
|
||||
pwm: pwm@1c20e00 {
|
||||
compatible = "allwinner,sun7i-a20-pwm";
|
||||
reg = <0x01c20e00 0xc>;
|
||||
clocks = <&osc24M>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
30
bindings/pwm/pxa-pwm.txt
Normal file
30
bindings/pwm/pxa-pwm.txt
Normal file
@@ -0,0 +1,30 @@
|
||||
Marvell PWM controller
|
||||
|
||||
Required properties:
|
||||
- compatible: should be one or more of:
|
||||
- "marvell,pxa250-pwm"
|
||||
- "marvell,pxa270-pwm"
|
||||
- "marvell,pxa168-pwm"
|
||||
- "marvell,pxa910-pwm"
|
||||
- reg: Physical base address and length of the registers used by the PWM channel
|
||||
Note that one device instance must be created for each PWM that is used, so the
|
||||
length covers only the register window for one PWM output, not that of the
|
||||
entire PWM controller. Currently length is 0x10 for all supported devices.
|
||||
- #pwm-cells: Should be 1. This cell is used to specify the period in
|
||||
nanoseconds.
|
||||
|
||||
Example PWM device node:
|
||||
|
||||
pwm0: pwm@40b00000 {
|
||||
compatible = "marvell,pxa250-pwm";
|
||||
reg = <0x40b00000 0x10>;
|
||||
#pwm-cells = <1>;
|
||||
};
|
||||
|
||||
Example PWM client node:
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm0 5000000>;
|
||||
...
|
||||
}
|
||||
96
bindings/pwm/renesas,pwm-rcar.yaml
Normal file
96
bindings/pwm/renesas,pwm-rcar.yaml
Normal file
@@ -0,0 +1,96 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pwm/renesas,pwm-rcar.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas R-Car PWM Timer Controller
|
||||
|
||||
maintainers:
|
||||
- Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- renesas,pwm-r8a7742 # RZ/G1H
|
||||
- renesas,pwm-r8a7743 # RZ/G1M
|
||||
- renesas,pwm-r8a7744 # RZ/G1N
|
||||
- renesas,pwm-r8a7745 # RZ/G1E
|
||||
- renesas,pwm-r8a77470 # RZ/G1C
|
||||
- renesas,pwm-r8a774a1 # RZ/G2M
|
||||
- renesas,pwm-r8a774b1 # RZ/G2N
|
||||
- renesas,pwm-r8a774c0 # RZ/G2E
|
||||
- renesas,pwm-r8a774e1 # RZ/G2H
|
||||
- renesas,pwm-r8a7778 # R-Car M1A
|
||||
- renesas,pwm-r8a7779 # R-Car H1
|
||||
- renesas,pwm-r8a7790 # R-Car H2
|
||||
- renesas,pwm-r8a7791 # R-Car M2-W
|
||||
- renesas,pwm-r8a7794 # R-Car E2
|
||||
- renesas,pwm-r8a7795 # R-Car H3
|
||||
- renesas,pwm-r8a7796 # R-Car M3-W
|
||||
- renesas,pwm-r8a77961 # R-Car M3-W+
|
||||
- renesas,pwm-r8a77965 # R-Car M3-N
|
||||
- renesas,pwm-r8a77970 # R-Car V3M
|
||||
- renesas,pwm-r8a77980 # R-Car V3H
|
||||
- renesas,pwm-r8a77990 # R-Car E3
|
||||
- renesas,pwm-r8a77995 # R-Car D3
|
||||
- const: renesas,pwm-rcar
|
||||
|
||||
reg:
|
||||
# base address and length of the registers block for the PWM.
|
||||
maxItems: 1
|
||||
|
||||
'#pwm-cells':
|
||||
# should be 2. See pwm.yaml in this directory for a description of
|
||||
# the cells format.
|
||||
const: 2
|
||||
|
||||
clocks:
|
||||
# clock phandle and specifier pair.
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- power-domains
|
||||
|
||||
allOf:
|
||||
- $ref: pwm.yaml#
|
||||
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- renesas,pwm-r8a7778
|
||||
- renesas,pwm-r8a7779
|
||||
then:
|
||||
required:
|
||||
- resets
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/r8a7743-cpg-mssr.h>
|
||||
#include <dt-bindings/power/r8a7743-sysc.h>
|
||||
|
||||
pwm0: pwm@e6e30000 {
|
||||
compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar";
|
||||
reg = <0xe6e30000 0x8>;
|
||||
clocks = <&cpg CPG_MOD 523>;
|
||||
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 523>;
|
||||
#pwm-cells = <2>;
|
||||
pinctrl-0 = <&pwm0_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
101
bindings/pwm/renesas,tpu-pwm.yaml
Normal file
101
bindings/pwm/renesas,tpu-pwm.yaml
Normal file
@@ -0,0 +1,101 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pwm/renesas,tpu-pwm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas R-Car Timer Pulse Unit PWM Controller
|
||||
|
||||
maintainers:
|
||||
- Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
|
||||
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: renesas,tpu
|
||||
required:
|
||||
- compatible
|
||||
- '#pwm-cells'
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- renesas,tpu-r8a73a4 # R-Mobile APE6
|
||||
- renesas,tpu-r8a7740 # R-Mobile A1
|
||||
- renesas,tpu-r8a7742 # RZ/G1H
|
||||
- renesas,tpu-r8a7743 # RZ/G1M
|
||||
- renesas,tpu-r8a7744 # RZ/G1N
|
||||
- renesas,tpu-r8a7745 # RZ/G1E
|
||||
- renesas,tpu-r8a7790 # R-Car H2
|
||||
- renesas,tpu-r8a7791 # R-Car M2-W
|
||||
- renesas,tpu-r8a7792 # R-Car V2H
|
||||
- renesas,tpu-r8a7793 # R-Car M2-N
|
||||
- renesas,tpu-r8a7794 # R-Car E2
|
||||
- renesas,tpu-r8a7795 # R-Car H3
|
||||
- renesas,tpu-r8a7796 # R-Car M3-W
|
||||
- renesas,tpu-r8a77961 # R-Car M3-W+
|
||||
- renesas,tpu-r8a77965 # R-Car M3-N
|
||||
- renesas,tpu-r8a77970 # R-Car V3M
|
||||
- renesas,tpu-r8a77980 # R-Car V3H
|
||||
- renesas,tpu-r8a779a0 # R-Car V3U
|
||||
- const: renesas,tpu
|
||||
|
||||
reg:
|
||||
# Base address and length of each memory resource used by the PWM
|
||||
# controller hardware module.
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
'#pwm-cells':
|
||||
# should be 3. See pwm.yaml in this directory for a description of
|
||||
# the cells format. The only third cell flag supported by this binding is
|
||||
# PWM_POLARITY_INVERTED.
|
||||
const: 3
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- power-domains
|
||||
|
||||
allOf:
|
||||
- $ref: pwm.yaml#
|
||||
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- renesas,tpu-r8a73a4
|
||||
- renesas,tpu-r8a7740
|
||||
then:
|
||||
required:
|
||||
- resets
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/r8a7740-clock.h>
|
||||
|
||||
tpu: pwm@e6600000 {
|
||||
compatible = "renesas,tpu-r8a7740", "renesas,tpu";
|
||||
reg = <0xe6600000 0x148>;
|
||||
clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
|
||||
power-domains = <&pd_a3sp>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
17
bindings/pwm/spear-pwm.txt
Normal file
17
bindings/pwm/spear-pwm.txt
Normal file
@@ -0,0 +1,17 @@
|
||||
== ST SPEAr SoC PWM controller ==
|
||||
|
||||
Required properties:
|
||||
- compatible: should be one of:
|
||||
- "st,spear320-pwm"
|
||||
- "st,spear1340-pwm"
|
||||
- reg: physical base address and length of the controller's registers
|
||||
- #pwm-cells: should be 2. See pwm.yaml in this directory for a description of
|
||||
the cells format.
|
||||
|
||||
Example:
|
||||
|
||||
pwm: pwm@a8000000 {
|
||||
compatible ="st,spear320-pwm";
|
||||
reg = <0xa8000000 0x1000>;
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
18
bindings/pwm/st,stmpe-pwm.txt
Normal file
18
bindings/pwm/st,stmpe-pwm.txt
Normal file
@@ -0,0 +1,18 @@
|
||||
== ST STMPE PWM controller ==
|
||||
|
||||
This is a PWM block embedded in the ST Microelectronics STMPE
|
||||
(ST Multi-Purpose Expander) chips. The PWM is registered as a
|
||||
subdevices of the STMPE MFD device.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be:
|
||||
- "st,stmpe-pwm"
|
||||
- #pwm-cells: should be 2. See pwm.yaml in this directory for a description of
|
||||
the cells format.
|
||||
|
||||
Example:
|
||||
|
||||
pwm0: pwm {
|
||||
compatible = "st,stmpe-pwm";
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
42
bindings/pwm/sunplus,sp7021-pwm.yaml
Normal file
42
bindings/pwm/sunplus,sp7021-pwm.yaml
Normal file
@@ -0,0 +1,42 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) Sunplus Co., Ltd. 2021
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pwm/sunplus,sp7021-pwm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Sunplus SoC SP7021 PWM Controller
|
||||
|
||||
maintainers:
|
||||
- Hammer Hsieh <hammerh0314@gmail.com>
|
||||
|
||||
allOf:
|
||||
- $ref: pwm.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: sunplus,sp7021-pwm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
'#pwm-cells':
|
||||
const: 2
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- reg
|
||||
- clocks
|
||||
|
||||
examples:
|
||||
- |
|
||||
pwm: pwm@9c007a00 {
|
||||
compatible = "sunplus,sp7021-pwm";
|
||||
reg = <0x9c007a00 0x80>;
|
||||
clocks = <&clkc 0xa2>;
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
17
bindings/pwm/ti,twl-pwm.txt
Normal file
17
bindings/pwm/ti,twl-pwm.txt
Normal file
@@ -0,0 +1,17 @@
|
||||
Texas Instruments TWL series PWM drivers
|
||||
|
||||
Supported PWMs:
|
||||
On TWL4030 series: PWM1 and PWM2
|
||||
On TWL6030 series: PWM0 and PWM1
|
||||
|
||||
Required properties:
|
||||
- compatible: "ti,twl4030-pwm" or "ti,twl6030-pwm"
|
||||
- #pwm-cells: should be 2. See pwm.yaml in this directory for a description of
|
||||
the cells format.
|
||||
|
||||
Example:
|
||||
|
||||
twl_pwm: pwm {
|
||||
compatible = "ti,twl6030-pwm";
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
17
bindings/pwm/ti,twl-pwmled.txt
Normal file
17
bindings/pwm/ti,twl-pwmled.txt
Normal file
@@ -0,0 +1,17 @@
|
||||
Texas Instruments TWL series PWM drivers connected to LED terminals
|
||||
|
||||
Supported PWMs:
|
||||
On TWL4030 series: PWMA and PWMB (connected to LEDA and LEDB terminals)
|
||||
On TWL6030 series: LED PWM (mainly used as charging indicator LED)
|
||||
|
||||
Required properties:
|
||||
- compatible: "ti,twl4030-pwmled" or "ti,twl6030-pwmled"
|
||||
- #pwm-cells: should be 2. See pwm.yaml in this directory for a description of
|
||||
the cells format.
|
||||
|
||||
Example:
|
||||
|
||||
twl_pwmled: pwmled {
|
||||
compatible = "ti,twl6030-pwmled";
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
45
bindings/pwm/toshiba,pwm-visconti.yaml
Normal file
45
bindings/pwm/toshiba,pwm-visconti.yaml
Normal file
@@ -0,0 +1,45 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pwm/toshiba,pwm-visconti.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Toshiba Visconti PWM Controller
|
||||
|
||||
maintainers:
|
||||
- Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
|
||||
|
||||
allOf:
|
||||
- $ref: pwm.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: toshiba,visconti-pwm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#pwm-cells':
|
||||
const: 2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pwm: pwm@241c0000 {
|
||||
compatible = "toshiba,visconti-pwm";
|
||||
reg = <0 0x241c0000 0 0x1000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm_mux>;
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
};
|
||||
18
bindings/pwm/vt8500-pwm.txt
Normal file
18
bindings/pwm/vt8500-pwm.txt
Normal file
@@ -0,0 +1,18 @@
|
||||
VIA/Wondermedia VT8500/WM8xxx series SoC PWM controller
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "via,vt8500-pwm"
|
||||
- reg: physical base address and length of the controller's registers
|
||||
- #pwm-cells: should be 3. See pwm.yaml in this directory for a description of
|
||||
the cells format. The only third cell flag supported by this binding is
|
||||
PWM_POLARITY_INVERTED.
|
||||
- clocks: phandle to the PWM source clock
|
||||
|
||||
Example:
|
||||
|
||||
pwm1: pwm@d8220000 {
|
||||
#pwm-cells = <3>;
|
||||
compatible = "via,vt8500-pwm";
|
||||
reg = <0xd8220000 0x1000>;
|
||||
clocks = <&clkpwm>;
|
||||
};
|
||||
Reference in New Issue
Block a user