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dt-bindings: Add devicetree bindings

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Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").

Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
This commit is contained in:
Melody Olvera
2023-04-03 14:38:11 -07:00
parent c334acf377
commit 6f18ce8026
4878 changed files with 424312 additions and 0 deletions
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54
bindings/perf/amlogic,g12-ddr-pmu.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/perf/amlogic,g12-ddr-pmu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic G12 DDR performance monitor
maintainers:
- Jiucheng Xu <jiucheng.xu@amlogic.com>
description: |
Amlogic G12 series SoC integrate DDR bandwidth monitor.
A timer is inside and can generate interrupt when timeout.
The bandwidth is counted in the timer ISR. Different platform
has different subset of event format attribute.
properties:
compatible:
enum:
- amlogic,g12a-ddr-pmu
- amlogic,g12b-ddr-pmu
- amlogic,sm1-ddr-pmu
reg:
items:
- description: DMC bandwidth register space.
- description: DMC PLL register space.
interrupts:
items:
- description: The IRQ of the inside timer timeout.
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
pmu {
#address-cells=<2>;
#size-cells=<2>;
pmu@ff638000 {
compatible = "amlogic,g12a-ddr-pmu";
reg = <0x0 0xff638000 0x0 0x100>,
<0x0 0xff638c00 0x0 0x100>;
interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>;
};
};

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bindings/perf/apm-xgene-pmu.txt Normal file
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* APM X-Gene SoC PMU bindings
This is APM X-Gene SoC PMU (Performance Monitoring Unit) module.
The following PMU devices are supported:
L3C - L3 cache controller
IOB - IO bridge
MCB - Memory controller bridge
MC - Memory controller
The following section describes the SoC PMU DT node binding.
Required properties:
- compatible : Shall be "apm,xgene-pmu" for revision 1 or
"apm,xgene-pmu-v2" for revision 2.
- regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
- regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
- regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
- reg : First resource shall be the CPU bus PMU resource.
- interrupts : Interrupt-specifier for PMU IRQ.
Required properties for L3C subnode:
- compatible : Shall be "apm,xgene-pmu-l3c".
- reg : First resource shall be the L3C PMU resource.
Required properties for IOB subnode:
- compatible : Shall be "apm,xgene-pmu-iob".
- reg : First resource shall be the IOB PMU resource.
Required properties for MCB subnode:
- compatible : Shall be "apm,xgene-pmu-mcb".
- reg : First resource shall be the MCB PMU resource.
- enable-bit-index : The bit indicates if the according MCB is enabled.
Required properties for MC subnode:
- compatible : Shall be "apm,xgene-pmu-mc".
- reg : First resource shall be the MC PMU resource.
- enable-bit-index : The bit indicates if the according MC is enabled.
Example:
csw: csw@7e200000 {
compatible = "apm,xgene-csw", "syscon";
reg = <0x0 0x7e200000 0x0 0x1000>;
};
mcba: mcba@7e700000 {
compatible = "apm,xgene-mcb", "syscon";
reg = <0x0 0x7e700000 0x0 0x1000>;
};
mcbb: mcbb@7e720000 {
compatible = "apm,xgene-mcb", "syscon";
reg = <0x0 0x7e720000 0x0 0x1000>;
};
pmu: pmu@78810000 {
compatible = "apm,xgene-pmu-v2";
#address-cells = <2>;
#size-cells = <2>;
ranges;
regmap-csw = <&csw>;
regmap-mcba = <&mcba>;
regmap-mcbb = <&mcbb>;
reg = <0x0 0x78810000 0x0 0x1000>;
interrupts = <0x0 0x22 0x4>;
pmul3c@7e610000 {
compatible = "apm,xgene-pmu-l3c";
reg = <0x0 0x7e610000 0x0 0x1000>;
};
pmuiob@7e940000 {
compatible = "apm,xgene-pmu-iob";
reg = <0x0 0x7e940000 0x0 0x1000>;
};
pmucmcb@7e710000 {
compatible = "apm,xgene-pmu-mcb";
reg = <0x0 0x7e710000 0x0 0x1000>;
enable-bit-index = <0>;
};
pmucmcb@7e730000 {
compatible = "apm,xgene-pmu-mcb";
reg = <0x0 0x7e730000 0x0 0x1000>;
enable-bit-index = <1>;
};
pmucmc@7e810000 {
compatible = "apm,xgene-pmu-mc";
reg = <0x0 0x7e810000 0x0 0x1000>;
enable-bit-index = <0>;
};
pmucmc@7e850000 {
compatible = "apm,xgene-pmu-mc";
reg = <0x0 0x7e850000 0x0 0x1000>;
enable-bit-index = <1>;
};
pmucmc@7e890000 {
compatible = "apm,xgene-pmu-mc";
reg = <0x0 0x7e890000 0x0 0x1000>;
enable-bit-index = <2>;
};
pmucmc@7e8d0000 {
compatible = "apm,xgene-pmu-mc";
reg = <0x0 0x7e8d0000 0x0 0x1000>;
enable-bit-index = <3>;
};
};

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bindings/perf/arm,ccn.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/perf/arm,ccn.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM CCN (Cache Coherent Network) Performance Monitors
maintainers:
- Robin Murphy <robin.murphy@arm.com>
properties:
compatible:
enum:
- arm,ccn-502
- arm,ccn-504
- arm,ccn-508
- arm,ccn-512
reg:
maxItems: 1
interrupts:
maxItems: 1
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
ccn@20000000 {
compatible = "arm,ccn-504";
reg = <0x20000000 0x1000000>;
interrupts = <0 181 4>;
};
...

69
bindings/perf/arm,cmn.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2020 Arm Ltd.
%YAML 1.2
---
$id: http://devicetree.org/schemas/perf/arm,cmn.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm CMN (Coherent Mesh Network) Performance Monitors
maintainers:
- Robin Murphy <robin.murphy@arm.com>
properties:
compatible:
enum:
- arm,cmn-600
- arm,cmn-650
- arm,cmn-700
- arm,ci-700
reg:
items:
- description: Physical address of the base (PERIPHBASE) and
size of the configuration address space.
interrupts:
minItems: 1
items:
- description: Overflow interrupt for DTC0
- description: Overflow interrupt for DTC1
- description: Overflow interrupt for DTC2
- description: Overflow interrupt for DTC3
description: One interrupt for each DTC domain implemented must
be specified, in order. DTC0 is always present.
arm,root-node:
$ref: /schemas/types.yaml#/definitions/uint32
description: Offset from PERIPHBASE of CMN-600's configuration
discovery node (see TRM definition of ROOTNODEBASE). Not
relevant for newer CMN/CI products.
required:
- compatible
- reg
- interrupts
if:
properties:
compatible:
contains:
const: arm,cmn-600
then:
required:
- arm,root-node
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
pmu@50000000 {
compatible = "arm,cmn-600";
reg = <0x50000000 0x4000000>;
/* 4x2 mesh with one DTC, and CFG node at 0,1,1,0 */
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
arm,root-node = <0x104000>;
};
...

47
bindings/perf/arm,dsu-pmu.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2021 Arm Ltd.
%YAML 1.2
---
$id: http://devicetree.org/schemas/perf/arm,dsu-pmu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
maintainers:
- Suzuki K Poulose <suzuki.poulose@arm.com>
- Robin Murphy <robin.murphy@arm.com>
description:
ARM DynamIQ Shared Unit (DSU) integrates one or more CPU cores with a shared
L3 memory system, control logic and external interfaces to form a multicore
cluster. The PMU enables gathering various statistics on the operation of the
DSU. The PMU provides independent 32-bit counters that can count any of the
supported events, along with a 64-bit cycle counter. The PMU is accessed via
CPU system registers and has no MMIO component.
properties:
compatible:
oneOf:
- const: arm,dsu-pmu
- items:
- const: arm,dsu-110-pmu
- const: arm,dsu-pmu
interrupts:
items:
- description: nCLUSTERPMUIRQ interrupt
cpus:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 12
items:
maxItems: 1
description: List of phandles for the CPUs connected to this DSU instance.
required:
- compatible
- interrupts
- cpus
additionalProperties: false

70
bindings/perf/arm,smmu-v3-pmcg.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/perf/arm,smmu-v3-pmcg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm SMMUv3 Performance Monitor Counter Group
maintainers:
- Will Deacon <will@kernel.org>
- Robin Murphy <robin.murphy@arm.com>
description: |
An SMMUv3 may have several Performance Monitor Counter Group (PMCG).
They are standalone performance monitoring units that support both
architected and IMPLEMENTATION DEFINED event counters.
properties:
$nodename:
pattern: "^pmu@[0-9a-f]*"
compatible:
oneOf:
- items:
- const: arm,mmu-600-pmcg
- const: arm,smmu-v3-pmcg
- const: arm,smmu-v3-pmcg
reg:
items:
- description: Register page 0
- description: Register page 1, if SMMU_PMCG_CFGR.RELOC_CTRS = 1
minItems: 1
interrupts:
maxItems: 1
msi-parent: true
required:
- compatible
- reg
anyOf:
- required:
- interrupts
- required:
- msi-parent
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
pmu@2b420000 {
compatible = "arm,smmu-v3-pmcg";
reg = <0x2b420000 0x1000>,
<0x2b430000 0x1000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>;
msi-parent = <&its 0xff0000>;
};
pmu@2b440000 {
compatible = "arm,smmu-v3-pmcg";
reg = <0x2b440000 0x1000>,
<0x2b450000 0x1000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>;
msi-parent = <&its 0xff0000>;
};

52
bindings/perf/fsl-imx-ddr.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/perf/fsl-imx-ddr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale(NXP) IMX8 DDR performance monitor
maintainers:
- Frank Li <frank.li@nxp.com>
properties:
compatible:
oneOf:
- enum:
- fsl,imx8-ddr-pmu
- fsl,imx8m-ddr-pmu
- fsl,imx8mq-ddr-pmu
- fsl,imx8mm-ddr-pmu
- fsl,imx8mn-ddr-pmu
- fsl,imx8mp-ddr-pmu
- items:
- enum:
- fsl,imx8mm-ddr-pmu
- fsl,imx8mn-ddr-pmu
- fsl,imx8mq-ddr-pmu
- fsl,imx8mp-ddr-pmu
- const: fsl,imx8m-ddr-pmu
reg:
maxItems: 1
interrupts:
maxItems: 1
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
ddr-pmu@5c020000 {
compatible = "fsl,imx8-ddr-pmu";
reg = <0x5c020000 0x10000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
};

37
bindings/perf/marvell-cn10k-ddr.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/perf/marvell-cn10k-ddr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell CN10K DDR performance monitor
maintainers:
- Bharat Bhushan <bbhushan2@marvell.com>
properties:
compatible:
items:
- enum:
- marvell,cn10k-ddr-pmu
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
bus {
#address-cells = <2>;
#size-cells = <2>;
pmu@87e1c0000000 {
compatible = "marvell,cn10k-ddr-pmu";
reg = <0x87e1 0xc0000000 0x0 0x10000>;
};
};

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bindings/perf/marvell-cn10k-tad.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/perf/marvell-cn10k-tad.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell CN10K LLC-TAD performance monitor
maintainers:
- Bhaskara Budiredla <bbudiredla@marvell.com>
description: |
The Tag-and-Data units (TADs) maintain coherence and contain CN10K
shared on-chip last level cache (LLC). The tad pmu measures the
performance of last-level cache. Each tad pmu supports up to eight
counters.
The DT setup comprises of number of tad blocks, the sizes of pmu
regions, tad blocks and overall base address of the HW.
properties:
compatible:
const: marvell,cn10k-tad-pmu
reg:
maxItems: 1
marvell,tad-cnt:
description: specifies the number of tads on the soc
$ref: /schemas/types.yaml#/definitions/uint32
marvell,tad-page-size:
description: specifies the size of each tad page
$ref: /schemas/types.yaml#/definitions/uint32
marvell,tad-pmu-page-size:
description: specifies the size of page that the pmu uses
$ref: /schemas/types.yaml#/definitions/uint32
required:
- compatible
- reg
- marvell,tad-cnt
- marvell,tad-page-size
- marvell,tad-pmu-page-size
additionalProperties: false
examples:
- |
tad {
#address-cells = <2>;
#size-cells = <2>;
tad_pmu@80000000 {
compatible = "marvell,cn10k-tad-pmu";
reg = <0x87e2 0x80000000 0x0 0x1000>;
marvell,tad-cnt = <1>;
marvell,tad-page-size = <0x1000>;
marvell,tad-pmu-page-size = <0x1000>;
};
};

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bindings/perf/spe-pmu.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/perf/spe-pmu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARMv8.2 Statistical Profiling Extension (SPE) Performance Monitor Units (PMU)
maintainers:
- Will Deacon <will@kernel.org>
description:
ARMv8.2 introduces the optional Statistical Profiling Extension for collecting
performance sample data using an in-memory trace buffer.
properties:
compatible:
const: arm,statistical-profiling-extension-v1
interrupts:
maxItems: 1
description: |
The PPI to signal SPE events. For heterogeneous systems where SPE is only
supported on a subset of the CPUs, please consult the arm,gic-v3 binding
for details on describing a PPI partition.
additionalProperties: false
required:
- compatible
- interrupts
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
spe-pmu {
compatible = "arm,statistical-profiling-extension-v1";
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
};