dt-bindings: Add devicetree bindings
Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").
Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
This commit is contained in:
Melody Olvera
39
bindings/pci/83xx-512x-pci.txt
Normal file
39
bindings/pci/83xx-512x-pci.txt
Normal file
@@ -0,0 +1,39 @@
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* Freescale 83xx and 512x PCI bridges
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Freescale 83xx and 512x SOCs include the same PCI bridge core.
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83xx/512x specific notes:
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- reg: should contain two address length tuples
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The first is for the internal PCI bridge registers
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The second is for the PCI config space access registers
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Example (MPC8313ERDB)
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pci0: pci@e0008500 {
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x0E -mini PCI */
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0x7000 0x0 0x0 0x1 &ipic 18 0x8
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0x7000 0x0 0x0 0x2 &ipic 18 0x8
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0x7000 0x0 0x0 0x3 &ipic 18 0x8
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0x7000 0x0 0x0 0x4 &ipic 18 0x8
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/* IDSEL 0x0F - PCI slot */
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0x7800 0x0 0x0 0x1 &ipic 17 0x8
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0x7800 0x0 0x0 0x2 &ipic 18 0x8
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0x7800 0x0 0x0 0x3 &ipic 17 0x8
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0x7800 0x0 0x0 0x4 &ipic 18 0x8>;
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interrupt-parent = <&ipic>;
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interrupts = <66 0x8>;
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bus-range = <0x0 0x0>;
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ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
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0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
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0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
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clock-frequency = <66666666>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xe0008500 0x100 /* internal registers */
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0xe0008300 0x8>; /* config space access registers */
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compatible = "fsl,mpc8349-pci";
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device_type = "pci";
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};
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59
bindings/pci/aardvark-pci.txt
Normal file
59
bindings/pci/aardvark-pci.txt
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@@ -0,0 +1,59 @@
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Aardvark PCIe controller
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This PCIe controller is used on the Marvell Armada 3700 ARM64 SoC.
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The Device Tree node describing an Aardvark PCIe controller must
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contain the following properties:
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- compatible: Should be "marvell,armada-3700-pcie"
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- reg: range of registers for the PCIe controller
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- interrupts: the interrupt line of the PCIe controller
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- #address-cells: set to <3>
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- #size-cells: set to <2>
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- device_type: set to "pci"
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- ranges: ranges for the PCI memory and I/O regions
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- #interrupt-cells: set to <1>
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- msi-controller: indicates that the PCIe controller can itself
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handle MSI interrupts
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- msi-parent: pointer to the MSI controller to be used
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- interrupt-map-mask and interrupt-map: standard PCI properties to
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define the mapping of the PCIe interface to interrupt numbers.
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- bus-range: PCI bus numbers covered
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- phys: the PCIe PHY handle
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- max-link-speed: see pci.txt
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- reset-gpios: see pci.txt
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In addition, the Device Tree describing an Aardvark PCIe controller
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must include a sub-node that describes the legacy interrupt controller
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built into the PCIe controller. This sub-node must have the following
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properties:
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- interrupt-controller
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- #interrupt-cells: set to <1>
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Example:
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pcie0: pcie@d0070000 {
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compatible = "marvell,armada-3700-pcie";
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device_type = "pci";
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reg = <0 0xd0070000 0 0x20000>;
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x00 0xff>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <1>;
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msi-controller;
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msi-parent = <&pcie0>;
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ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
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0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc 0>,
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<0 0 0 2 &pcie_intc 1>,
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<0 0 0 3 &pcie_intc 2>,
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<0 0 0 4 &pcie_intc 3>;
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phys = <&comphy1 0>;
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pcie_intc: interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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27
bindings/pci/altera-pcie-msi.txt
Normal file
27
bindings/pci/altera-pcie-msi.txt
Normal file
@@ -0,0 +1,27 @@
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* Altera PCIe MSI controller
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Required properties:
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- compatible: should contain "altr,msi-1.0"
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- reg: specifies the physical base address of the controller and
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the length of the memory mapped region.
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- reg-names: must include the following entries:
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"csr": CSR registers
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"vector_slave": vectors slave port region
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- interrupts: specifies the interrupt source of the parent interrupt
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controller. The format of the interrupt specifier depends on the
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parent interrupt controller.
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- num-vectors: number of vectors, range 1 to 32.
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- msi-controller: indicates that this is MSI controller node
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Example
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msi0: msi@0xFF200000 {
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compatible = "altr,msi-1.0";
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reg = <0xFF200000 0x00000010
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0xFF200010 0x00000080>;
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reg-names = "csr", "vector_slave";
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interrupt-parent = <&hps_0_arm_gic_0>;
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interrupts = <0 42 4>;
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msi-controller;
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num-vectors = <32>;
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};
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50
bindings/pci/altera-pcie.txt
Normal file
50
bindings/pci/altera-pcie.txt
Normal file
@@ -0,0 +1,50 @@
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* Altera PCIe controller
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Required properties:
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- compatible : should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0"
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- reg: a list of physical base address and length for TXS and CRA.
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For "altr,pcie-root-port-2.0", additional HIP base address and length.
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- reg-names: must include the following entries:
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"Txs": TX slave port region
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"Cra": Control register access region
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"Hip": Hard IP region (if "altr,pcie-root-port-2.0")
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- interrupts: specifies the interrupt source of the parent interrupt
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controller. The format of the interrupt specifier depends
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on the parent interrupt controller.
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- device_type: must be "pci"
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- #address-cells: set to <3>
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- #size-cells: set to <2>
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- #interrupt-cells: set to <1>
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- ranges: describes the translation of addresses for root ports and
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standard PCI regions.
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- interrupt-map-mask and interrupt-map: standard PCI properties to define the
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mapping of the PCIe interface to interrupt numbers.
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Optional properties:
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- msi-parent: Link to the hardware entity that serves as the MSI controller
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for this PCIe controller.
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- bus-range: PCI bus numbers covered
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Example
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pcie_0: pcie@c00000000 {
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compatible = "altr,pcie-root-port-1.0";
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reg = <0xc0000000 0x20000000>,
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<0xff220000 0x00004000>;
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reg-names = "Txs", "Cra";
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interrupt-parent = <&hps_0_arm_gic_0>;
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interrupts = <0 40 4>;
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interrupt-controller;
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#interrupt-cells = <1>;
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bus-range = <0x0 0xFF>;
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device_type = "pci";
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msi-parent = <&msi_to_gic_gen_0>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_0 1>,
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<0 0 0 2 &pcie_0 2>,
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<0 0 0 3 &pcie_0 3>,
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<0 0 0 4 &pcie_0 4>;
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ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
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0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
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};
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70
bindings/pci/amlogic,meson-pcie.txt
Normal file
70
bindings/pci/amlogic,meson-pcie.txt
Normal file
@@ -0,0 +1,70 @@
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Amlogic Meson AXG DWC PCIE SoC controller
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Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.
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It shares common functions with the PCIe DesignWare core driver and
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inherits common properties defined in
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Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
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Additional properties are described here:
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Required properties:
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- compatible:
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should contain :
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- "amlogic,axg-pcie" for AXG SoC Family
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- "amlogic,g12a-pcie" for G12A SoC Family
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to identify the core.
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- reg:
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should contain the configuration address space.
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- reg-names: Must be
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- "elbi" External local bus interface registers
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- "cfg" Meson specific registers
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- "config" PCIe configuration space
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- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
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- clocks: Must contain an entry for each entry in clock-names.
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- clock-names: Must include the following entries:
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- "pclk" PCIe GEN 100M PLL clock
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- "port" PCIe_x(A or B) RC clock gate
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- "general" PCIe Phy clock
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- resets: phandle to the reset lines.
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- reset-names: must contain "port" and "apb"
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- "port" Port A or B reset
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- "apb" Share APB reset
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- phys: should contain a phandle to the PCIE phy
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- phy-names: must contain "pcie"
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- device_type:
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should be "pci". As specified in snps,dw-pcie.yaml
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Example configuration:
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pcie: pcie@f9800000 {
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compatible = "amlogic,axg-pcie", "snps,dw-pcie";
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reg = <0x0 0xf9800000 0x0 0x400000
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0x0 0xff646000 0x0 0x2000
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0x0 0xf9f00000 0x0 0x100000>;
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reg-names = "elbi", "cfg", "config";
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reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
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interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
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bus-range = <0x0 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>;
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clocks = <&clkc CLKID_USB
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&clkc CLKID_PCIE_A
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&clkc CLKID_PCIE_CML_EN0>;
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clock-names = "general",
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"pclk",
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"port";
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resets = <&reset RESET_PCIE_A>,
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<&reset RESET_PCIE_APB>;
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reset-names = "port",
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"apb";
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phys = <&pcie_phy>;
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phy-names = "pcie";
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};
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174
bindings/pci/apple,pcie.yaml
Normal file
174
bindings/pci/apple,pcie.yaml
Normal file
@@ -0,0 +1,174 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/apple,pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Apple PCIe host controller
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maintainers:
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- Mark Kettenis <kettenis@openbsd.org>
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description: |
|
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The Apple PCIe host controller is a PCIe host controller with
|
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multiple root ports present in Apple ARM SoC platforms, including
|
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various iPhone and iPad devices and the "Apple Silicon" Macs.
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The controller incorporates Synopsys DesigWare PCIe logic to
|
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implements its root ports. But the ATU found on most DesignWare
|
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PCIe host bridges is absent.
|
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All root ports share a single ECAM space, but separate GPIOs are
|
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used to take the PCI devices on those ports out of reset. Therefore
|
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the standard "reset-gpios" and "max-link-speed" properties appear on
|
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the child nodes that represent the PCI bridges that correspond to
|
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the individual root ports.
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MSIs are handled by the PCIe controller and translated into regular
|
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interrupts. A range of 32 MSIs is provided. These 32 MSIs can be
|
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distributed over the root ports as the OS sees fit by programming
|
||||
the PCIe controller's port registers.
|
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properties:
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compatible:
|
||||
items:
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- enum:
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- apple,t8103-pcie
|
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- apple,t6000-pcie
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- const: apple,pcie
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reg:
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minItems: 3
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maxItems: 6
|
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reg-names:
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||||
minItems: 3
|
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items:
|
||||
- const: config
|
||||
- const: rc
|
||||
- const: port0
|
||||
- const: port1
|
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- const: port2
|
||||
- const: port3
|
||||
|
||||
ranges:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
interrupts:
|
||||
description:
|
||||
Interrupt specifiers, one for each root port.
|
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minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
msi-parent: true
|
||||
|
||||
msi-ranges:
|
||||
maxItems: 1
|
||||
|
||||
iommu-map: true
|
||||
iommu-map-mask: true
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- bus-range
|
||||
- interrupts
|
||||
- msi-controller
|
||||
- msi-parent
|
||||
- msi-ranges
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-bus.yaml#
|
||||
- $ref: /schemas/interrupt-controller/msi-controller.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: apple,t8103-pcie
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 5
|
||||
interrupts:
|
||||
maxItems: 3
|
||||
|
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examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/apple-aic.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie0: pcie@690000000 {
|
||||
compatible = "apple,t8103-pcie", "apple,pcie";
|
||||
device_type = "pci";
|
||||
|
||||
reg = <0x6 0x90000000 0x0 0x1000000>,
|
||||
<0x6 0x80000000 0x0 0x100000>,
|
||||
<0x6 0x81000000 0x0 0x4000>,
|
||||
<0x6 0x82000000 0x0 0x4000>,
|
||||
<0x6 0x83000000 0x0 0x4000>;
|
||||
reg-names = "config", "rc", "port0", "port1", "port2";
|
||||
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
msi-controller;
|
||||
msi-parent = <&pcie0>;
|
||||
msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>;
|
||||
|
||||
iommu-map = <0x100 &dart0 1 1>,
|
||||
<0x200 &dart1 1 1>,
|
||||
<0x300 &dart2 1 1>;
|
||||
iommu-map-mask = <0xff00>;
|
||||
|
||||
bus-range = <0 3>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>,
|
||||
<0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>;
|
||||
|
||||
power-domains = <&ps_apcie_gp>;
|
||||
pinctrl-0 = <&pcie_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
pci@0,0 {
|
||||
device_type = "pci";
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
reset-gpios = <&pinctrl_ap 152 0>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
|
||||
pci@1,0 {
|
||||
device_type = "pci";
|
||||
reg = <0x800 0x0 0x0 0x0 0x0>;
|
||||
reset-gpios = <&pinctrl_ap 153 0>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
|
||||
pci@2,0 {
|
||||
device_type = "pci";
|
||||
reg = <0x1000 0x0 0x0 0x0 0x0>;
|
||||
reset-gpios = <&pinctrl_ap 33 0>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
};
|
||||
50
bindings/pci/axis,artpec6-pcie.txt
Normal file
50
bindings/pci/axis,artpec6-pcie.txt
Normal file
@@ -0,0 +1,50 @@
|
||||
* Axis ARTPEC-6 PCIe interface
|
||||
|
||||
This PCIe host controller is based on the Synopsys DesignWare PCIe IP
|
||||
and thus inherits all the common properties defined in snps,dw-pcie.yaml.
|
||||
|
||||
Required properties:
|
||||
- compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
|
||||
"axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
|
||||
"axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;
|
||||
"axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;
|
||||
- reg: base addresses and lengths of the PCIe controller (DBI),
|
||||
the PHY controller, and configuration address space.
|
||||
- reg-names: Must include the following entries:
|
||||
- "dbi"
|
||||
- "phy"
|
||||
- "config"
|
||||
- interrupts: A list of interrupt outputs of the controller. Must contain an
|
||||
entry for each entry in the interrupt-names property.
|
||||
- interrupt-names: Must include the following entries:
|
||||
- "msi": The interrupt that is asserted when an MSI is received
|
||||
- axis,syscon-pcie: A phandle pointing to the ARTPEC-6 system controller,
|
||||
used to enable and control the Synopsys IP.
|
||||
|
||||
Example:
|
||||
|
||||
pcie@f8050000 {
|
||||
compatible = "axis,artpec6-pcie", "snps,dw-pcie";
|
||||
reg = <0xf8050000 0x2000
|
||||
0xf8040000 0x1000
|
||||
0xc0000000 0x2000>;
|
||||
reg-names = "dbi", "phy", "config";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
/* downstream I/O */
|
||||
ranges = <0x81000000 0 0 0xc0002000 0 0x00010000
|
||||
/* non-prefetchable memory */
|
||||
0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;
|
||||
num-lanes = <2>;
|
||||
bus-range = <0x00 0xff>;
|
||||
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
|
||||
axis,syscon-pcie = <&syscon>;
|
||||
};
|
||||
184
bindings/pci/brcm,iproc-pcie.yaml
Normal file
184
bindings/pci/brcm,iproc-pcie.yaml
Normal file
@@ -0,0 +1,184 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom iProc PCIe controller with the platform bus interface
|
||||
|
||||
maintainers:
|
||||
- Ray Jui <ray.jui@broadcom.com>
|
||||
- Scott Branden <scott.branden@broadcom.com>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-bus.yaml#
|
||||
- $ref: /schemas/interrupt-controller/msi-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
# for the first generation of PAXB based controller, used in SoCs
|
||||
# including NSP, Cygnus, NS2, and Pegasus
|
||||
- brcm,iproc-pcie
|
||||
# for the second generation of PAXB-based controllers, used in
|
||||
# Stingray
|
||||
- brcm,iproc-pcie-paxb-v2
|
||||
# For the first generation of PAXC based controller, used in NS2
|
||||
- brcm,iproc-pcie-paxc
|
||||
# For the second generation of PAXC based controller, used in Stingray
|
||||
- brcm,iproc-pcie-paxc-v2
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
description: >
|
||||
Base address and length of the PCIe controller I/O register space
|
||||
|
||||
interrupt-map: true
|
||||
|
||||
interrupt-map-mask: true
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 1
|
||||
|
||||
ranges:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
description: >
|
||||
Ranges for the PCI memory and I/O regions
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
phy-names:
|
||||
items:
|
||||
- const: pcie-phy
|
||||
|
||||
bus-range: true
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
"#address-cells": true
|
||||
|
||||
"#size-cells": true
|
||||
|
||||
device_type: true
|
||||
|
||||
brcm,pcie-ob:
|
||||
type: boolean
|
||||
description: >
|
||||
Some iProc SoCs do not have the outbound address mapping done by the
|
||||
ASIC after power on reset. In this case, SW needs to configure it
|
||||
|
||||
brcm,pcie-ob-axi-offset:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: >
|
||||
The offset from the AXI address to the internal address used by the
|
||||
iProc PCIe core (not the PCIe address)
|
||||
|
||||
msi:
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: brcm,iproc-msi
|
||||
|
||||
msi-parent: true
|
||||
|
||||
msi-controller: true
|
||||
|
||||
brcm,pcie-msi-inten:
|
||||
type: boolean
|
||||
description: >
|
||||
Needs to be present for some older iProc platforms that require the
|
||||
interrupt enable registers to be set explicitly to enable MSI
|
||||
|
||||
dependencies:
|
||||
brcm,pcie-ob-axi-offset: ["brcm,pcie-ob"]
|
||||
brcm,pcie-msi-inten: [msi-controller]
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- ranges
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- brcm,iproc-pcie
|
||||
then:
|
||||
required:
|
||||
- interrupt-map
|
||||
- interrupt-map-mask
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
pcie0: pcie@18012000 {
|
||||
compatible = "brcm,iproc-pcie";
|
||||
reg = <0x18012000 0x1000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
|
||||
|
||||
linux,pci-domain = <0>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
ranges = <0x81000000 0 0 0x28000000 0 0x00010000>,
|
||||
<0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
|
||||
|
||||
phys = <&phy 0 5>;
|
||||
phy-names = "pcie-phy";
|
||||
|
||||
brcm,pcie-ob;
|
||||
brcm,pcie-ob-axi-offset = <0x00000000>;
|
||||
|
||||
msi-parent = <&msi0>;
|
||||
|
||||
/* iProc event queue based MSI */
|
||||
msi0: msi {
|
||||
compatible = "brcm,iproc-msi";
|
||||
msi-controller;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>,
|
||||
<GIC_SPI 97 IRQ_TYPE_NONE>,
|
||||
<GIC_SPI 98 IRQ_TYPE_NONE>,
|
||||
<GIC_SPI 99 IRQ_TYPE_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1: pcie@18013000 {
|
||||
compatible = "brcm,iproc-pcie";
|
||||
reg = <0x18013000 0x1000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;
|
||||
|
||||
linux,pci-domain = <1>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
ranges = <0x81000000 0 0 0x48000000 0 0x00010000>,
|
||||
<0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
|
||||
|
||||
phys = <&phy 1 6>;
|
||||
phy-names = "pcie-phy";
|
||||
};
|
||||
};
|
||||
185
bindings/pci/brcm,stb-pcie.yaml
Normal file
185
bindings/pci/brcm,stb-pcie.yaml
Normal file
@@ -0,0 +1,185 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Brcmstb PCIe Host Controller
|
||||
|
||||
maintainers:
|
||||
- Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- brcm,bcm2711-pcie # The Raspberry Pi 4
|
||||
- brcm,bcm4908-pcie
|
||||
- brcm,bcm7211-pcie # Broadcom STB version of RPi4
|
||||
- brcm,bcm7278-pcie # Broadcom 7278 Arm
|
||||
- brcm,bcm7216-pcie # Broadcom 7216 Arm
|
||||
- brcm,bcm7445-pcie # Broadcom 7445 Arm
|
||||
- brcm,bcm7425-pcie # Broadcom 7425 MIPs
|
||||
- brcm,bcm7435-pcie # Broadcom 7435 MIPs
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: PCIe host controller
|
||||
- description: builtin MSI controller
|
||||
|
||||
interrupt-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: pcie
|
||||
- const: msi
|
||||
|
||||
ranges:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
dma-ranges:
|
||||
minItems: 1
|
||||
maxItems: 6
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: sw_pcie
|
||||
|
||||
msi-controller:
|
||||
description: Identifies the node as an MSI controller.
|
||||
|
||||
msi-parent:
|
||||
description: MSI controller the device is capable of using.
|
||||
|
||||
brcm,enable-ssc:
|
||||
description: Indicates usage of spread-spectrum clocking.
|
||||
type: boolean
|
||||
|
||||
aspm-no-l0s: true
|
||||
|
||||
brcm,scb-sizes:
|
||||
description: u64 giving the 64bit PCIe memory
|
||||
viewport size of a memory controller. There may be up to
|
||||
three controllers, and each size must be a power of two
|
||||
with a size greater or equal to the amount of memory the
|
||||
controller supports. Note that each memory controller
|
||||
may have two component regions -- base and extended -- so
|
||||
this information cannot be deduced from the dma-ranges.
|
||||
$ref: /schemas/types.yaml#/definitions/uint64-array
|
||||
items:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- ranges
|
||||
- dma-ranges
|
||||
- "#interrupt-cells"
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- interrupt-map-mask
|
||||
- interrupt-map
|
||||
- msi-controller
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-bus.yaml#
|
||||
- $ref: /schemas/interrupt-controller/msi-controller.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: brcm,bcm4908-pcie
|
||||
then:
|
||||
properties:
|
||||
resets:
|
||||
items:
|
||||
- description: reset controller handling the PERST# signal
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: perst
|
||||
|
||||
required:
|
||||
- resets
|
||||
- reset-names
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: brcm,bcm7216-pcie
|
||||
then:
|
||||
properties:
|
||||
resets:
|
||||
items:
|
||||
- description: phandle pointing to the RESCAL reset controller
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: rescal
|
||||
|
||||
required:
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
scb {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
pcie0: pcie@7d500000 {
|
||||
compatible = "brcm,bcm2711-pcie";
|
||||
reg = <0x0 0x7d500000 0x9310>;
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "pcie", "msi";
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH
|
||||
0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH
|
||||
0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH
|
||||
0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
msi-parent = <&pcie0>;
|
||||
msi-controller;
|
||||
ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>;
|
||||
dma-ranges = <0x42000000 0x1 0x00000000 0x0 0x40000000 0x0 0x80000000>,
|
||||
<0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>;
|
||||
brcm,enable-ssc;
|
||||
brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>;
|
||||
|
||||
/* PCIe bridge, Root Port */
|
||||
pci@0,0 {
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
compatible = "pciclass,0604";
|
||||
device_type = "pci";
|
||||
vpcie3v3-supply = <&vreg7>;
|
||||
ranges;
|
||||
|
||||
/* PCIe endpoint */
|
||||
pci-ep@0,0 {
|
||||
assigned-addresses =
|
||||
<0x82010000 0x0 0xf8000000 0x6 0x00000000 0x0 0x2000>;
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
compatible = "pci14e4,1688";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
50
bindings/pci/cdns,cdns-pcie-ep.yaml
Normal file
50
bindings/pci/cdns,cdns-pcie-ep.yaml
Normal file
@@ -0,0 +1,50 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-ep.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Cadence PCIe EP Controller
|
||||
|
||||
maintainers:
|
||||
- Tom Joseph <tjoseph@cadence.com>
|
||||
|
||||
allOf:
|
||||
- $ref: "cdns-pcie-ep.yaml#"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: cdns,cdns-pcie-ep
|
||||
|
||||
reg:
|
||||
maxItems: 2
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: reg
|
||||
- const: mem
|
||||
|
||||
required:
|
||||
- reg
|
||||
- reg-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie-ep@fc000000 {
|
||||
compatible = "cdns,cdns-pcie-ep";
|
||||
reg = <0x0 0xfc000000 0x0 0x01000000>,
|
||||
<0x0 0x80000000 0x0 0x40000000>;
|
||||
reg-names = "reg", "mem";
|
||||
cdns,max-outbound-regions = <16>;
|
||||
max-functions = /bits/ 8 <8>;
|
||||
phys = <&pcie_phy0>;
|
||||
phy-names = "pcie-phy";
|
||||
};
|
||||
};
|
||||
...
|
||||
75
bindings/pci/cdns,cdns-pcie-host.yaml
Normal file
75
bindings/pci/cdns,cdns-pcie-host.yaml
Normal file
@@ -0,0 +1,75 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-host.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Cadence PCIe host controller
|
||||
|
||||
maintainers:
|
||||
- Tom Joseph <tjoseph@cadence.com>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-bus.yaml#
|
||||
- $ref: "cdns-pcie-host.yaml#"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: cdns,cdns-pcie-host
|
||||
|
||||
reg:
|
||||
maxItems: 2
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: reg
|
||||
- const: cfg
|
||||
|
||||
msi-parent: true
|
||||
|
||||
required:
|
||||
- reg
|
||||
- reg-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie@fb000000 {
|
||||
compatible = "cdns,cdns-pcie-host";
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x0 0xff>;
|
||||
linux,pci-domain = <0>;
|
||||
vendor-id = <0x17cd>;
|
||||
device-id = <0x0200>;
|
||||
|
||||
reg = <0x0 0xfb000000 0x0 0x01000000>,
|
||||
<0x0 0x41000000 0x0 0x00001000>;
|
||||
reg-names = "reg", "cfg";
|
||||
|
||||
ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>,
|
||||
<0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>;
|
||||
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
|
||||
|
||||
#interrupt-cells = <0x1>;
|
||||
|
||||
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 14 0x1>,
|
||||
<0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 15 0x1>,
|
||||
<0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 16 0x1>,
|
||||
<0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 17 0x1>;
|
||||
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
|
||||
msi-parent = <&its_pci>;
|
||||
|
||||
phys = <&pcie_phy0>;
|
||||
phy-names = "pcie-phy";
|
||||
};
|
||||
};
|
||||
...
|
||||
24
bindings/pci/cdns-pcie-ep.yaml
Normal file
24
bindings/pci/cdns-pcie-ep.yaml
Normal file
@@ -0,0 +1,24 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/pci/cdns-pcie-ep.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Cadence PCIe Device
|
||||
|
||||
maintainers:
|
||||
- Tom Joseph <tjoseph@cadence.com>
|
||||
|
||||
allOf:
|
||||
- $ref: "cdns-pcie.yaml#"
|
||||
- $ref: "pci-ep.yaml#"
|
||||
|
||||
properties:
|
||||
cdns,max-outbound-regions:
|
||||
description: maximum number of outbound regions
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 1
|
||||
maximum: 32
|
||||
default: 32
|
||||
|
||||
additionalProperties: true
|
||||
37
bindings/pci/cdns-pcie-host.yaml
Normal file
37
bindings/pci/cdns-pcie-host.yaml
Normal file
@@ -0,0 +1,37 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/pci/cdns-pcie-host.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Cadence PCIe Host
|
||||
|
||||
maintainers:
|
||||
- Tom Joseph <tjoseph@cadence.com>
|
||||
|
||||
allOf:
|
||||
- $ref: "/schemas/pci/pci-bus.yaml#"
|
||||
- $ref: "cdns-pcie.yaml#"
|
||||
|
||||
properties:
|
||||
cdns,max-outbound-regions:
|
||||
description: maximum number of outbound regions
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 1
|
||||
maximum: 32
|
||||
default: 32
|
||||
deprecated: true
|
||||
|
||||
cdns,no-bar-match-nbits:
|
||||
description:
|
||||
Set into the no BAR match register to configure the number of least
|
||||
significant bits kept during inbound (PCIe -> AXI) address translations
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 64
|
||||
default: 32
|
||||
deprecated: true
|
||||
|
||||
msi-parent: true
|
||||
|
||||
additionalProperties: true
|
||||
25
bindings/pci/cdns-pcie.yaml
Normal file
25
bindings/pci/cdns-pcie.yaml
Normal file
@@ -0,0 +1,25 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/pci/cdns-pcie.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Cadence PCIe Core
|
||||
|
||||
maintainers:
|
||||
- Tom Joseph <tjoseph@cadence.com>
|
||||
|
||||
properties:
|
||||
phys:
|
||||
description:
|
||||
One per lane if more than one in the list. If only one PHY listed it must
|
||||
manage all lanes.
|
||||
minItems: 1
|
||||
maxItems: 16
|
||||
|
||||
phy-names:
|
||||
items:
|
||||
- const: pcie-phy
|
||||
# FIXME: names when more than 1
|
||||
|
||||
additionalProperties: true
|
||||
174
bindings/pci/faraday,ftpci100.yaml
Normal file
174
bindings/pci/faraday,ftpci100.yaml
Normal file
@@ -0,0 +1,174 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/faraday,ftpci100.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Faraday Technology FTPCI100 PCI Host Bridge
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
description: |
|
||||
This PCI bridge is found inside that Cortina Systems Gemini SoC platform and
|
||||
is a generic IP block from Faraday Technology. It exists in two variants:
|
||||
plain and dual PCI. The plain version embeds a cascading interrupt controller
|
||||
into the host bridge. The dual version routes the interrupts to the host
|
||||
chips interrupt controller.
|
||||
The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
|
||||
Technology) and product ID 0x4321.
|
||||
I/O space considerations:
|
||||
The plain variant has 128MiB of non-prefetchable memory space, whereas the
|
||||
"dual" variant has 64MiB. Take this into account when describing the ranges.
|
||||
|
||||
Interrupt map considerations:
|
||||
|
||||
The "dual" variant will get INT A, B, C, D from the system interrupt controller
|
||||
and should point to respective interrupt in that controller in its interrupt-map.
|
||||
|
||||
The code which is the only documentation of how the Faraday PCI (the non-dual
|
||||
variant) interrupts assigns the default interrupt mapping/swizzling has
|
||||
typically been like this, doing the swizzling on the interrupt controller side
|
||||
rather than in the interconnect:
|
||||
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map =
|
||||
<0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
|
||||
<0x4800 0 0 2 &pci_intc 1>,
|
||||
<0x4800 0 0 3 &pci_intc 2>,
|
||||
<0x4800 0 0 4 &pci_intc 3>,
|
||||
<0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
|
||||
<0x5000 0 0 2 &pci_intc 2>,
|
||||
<0x5000 0 0 3 &pci_intc 3>,
|
||||
<0x5000 0 0 4 &pci_intc 0>,
|
||||
<0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
|
||||
<0x5800 0 0 2 &pci_intc 3>,
|
||||
<0x5800 0 0 3 &pci_intc 0>,
|
||||
<0x5800 0 0 4 &pci_intc 1>,
|
||||
<0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
|
||||
<0x6000 0 0 2 &pci_intc 0>,
|
||||
<0x6000 0 0 3 &pci_intc 1>,
|
||||
<0x6000 0 0 4 &pci_intc 2>;
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-bus.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: cortina,gemini-pci
|
||||
- const: faraday,ftpci100
|
||||
- items:
|
||||
- const: cortina,gemini-pci-dual
|
||||
- const: faraday,ftpci100-dual
|
||||
- const: faraday,ftpci100
|
||||
- const: faraday,ftpci100-dual
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#address-cells":
|
||||
const: 3
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 1
|
||||
|
||||
ranges:
|
||||
minItems: 2
|
||||
|
||||
dma-ranges:
|
||||
minItems: 3
|
||||
description: |
|
||||
three ranges for the inbound memory region. The ranges must
|
||||
be aligned to a 1MB boundary, and may be 1MB, 2MB, 4MB, 8MB, 16MB, 32MB, 64MB,
|
||||
128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked as
|
||||
pre-fetchable.
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: peripheral clock (PCLK)
|
||||
- description: PCI clock (PCICLK).
|
||||
description: |
|
||||
If these are not present, they are assumed to be
|
||||
hard-wired enabled and always on. The PCI clock will be 33 or 66 MHz.
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: PCLK
|
||||
- const: PCICLK
|
||||
|
||||
interrupt-controller:
|
||||
type: object
|
||||
|
||||
required:
|
||||
- reg
|
||||
- compatible
|
||||
- "#interrupt-cells"
|
||||
- interrupt-map-mask
|
||||
- interrupt-map
|
||||
- dma-ranges
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: faraday,ftpci100
|
||||
then:
|
||||
required:
|
||||
- interrupt-controller
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
pci@50000000 {
|
||||
compatible = "cortina,gemini-pci", "faraday,ftpci100";
|
||||
reg = <0x50000000 0x100>;
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = /* 1MiB I/O space 0x50000000-0x500fffff */
|
||||
<0x01000000 0 0 0x50000000 0 0x00100000>,
|
||||
/* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */
|
||||
<0x02000000 0 0x58000000 0x58000000 0 0x08000000>;
|
||||
|
||||
/* DMA ranges */
|
||||
dma-ranges =
|
||||
/* 128MiB at 0x00000000-0x07ffffff */
|
||||
<0x02000000 0 0x00000000 0x00000000 0 0x08000000>,
|
||||
/* 64MiB at 0x00000000-0x03ffffff */
|
||||
<0x02000000 0 0x00000000 0x00000000 0 0x04000000>,
|
||||
/* 64MiB at 0x00000000-0x03ffffff */
|
||||
<0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
|
||||
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map =
|
||||
<0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
|
||||
<0x4800 0 0 2 &pci_intc 1>,
|
||||
<0x4800 0 0 3 &pci_intc 2>,
|
||||
<0x4800 0 0 4 &pci_intc 3>,
|
||||
<0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
|
||||
<0x5000 0 0 2 &pci_intc 2>,
|
||||
<0x5000 0 0 3 &pci_intc 3>,
|
||||
<0x5000 0 0 4 &pci_intc 0>,
|
||||
<0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
|
||||
<0x5800 0 0 2 &pci_intc 3>,
|
||||
<0x5800 0 0 3 &pci_intc 0>,
|
||||
<0x5800 0 0 4 &pci_intc 1>,
|
||||
<0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
|
||||
<0x6000 0 0 2 &pci_intc 0>,
|
||||
<0x6000 0 0 3 &pci_intc 0>,
|
||||
<0x6000 0 0 4 &pci_intc 0>;
|
||||
pci_intc: interrupt-controller {
|
||||
interrupt-parent = <&intcon>;
|
||||
interrupt-controller;
|
||||
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
210
bindings/pci/fsl,imx6q-pcie.yaml
Normal file
210
bindings/pci/fsl,imx6q-pcie.yaml
Normal file
@@ -0,0 +1,210 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale i.MX6 PCIe host controller
|
||||
|
||||
maintainers:
|
||||
- Lucas Stach <l.stach@pengutronix.de>
|
||||
- Richard Zhu <hongxing.zhu@nxp.com>
|
||||
|
||||
description: |+
|
||||
This PCIe host controller is based on the Synopsys DesignWare PCIe IP
|
||||
and thus inherits all the common properties defined in snps,dw-pcie.yaml.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/snps,dw-pcie.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- fsl,imx6q-pcie
|
||||
- fsl,imx6sx-pcie
|
||||
- fsl,imx6qp-pcie
|
||||
- fsl,imx7d-pcie
|
||||
- fsl,imx8mq-pcie
|
||||
- fsl,imx8mm-pcie
|
||||
- fsl,imx8mp-pcie
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Data Bus Interface (DBI) registers.
|
||||
- description: PCIe configuration space region.
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dbi
|
||||
- const: config
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: builtin MSI controller.
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi
|
||||
|
||||
clocks:
|
||||
minItems: 3
|
||||
items:
|
||||
- description: PCIe bridge clock.
|
||||
- description: PCIe bus clock.
|
||||
- description: PCIe PHY clock.
|
||||
- description: Additional required clock entry for imx6sx-pcie,
|
||||
imx8mq-pcie.
|
||||
|
||||
clock-names:
|
||||
minItems: 3
|
||||
items:
|
||||
- const: pcie
|
||||
- const: pcie_bus
|
||||
- const: pcie_phy
|
||||
- const: pcie_inbound_axi for imx6sx-pcie, pcie_aux for imx8mq-pcie
|
||||
|
||||
num-lanes:
|
||||
const: 1
|
||||
|
||||
fsl,imx7d-pcie-phy:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: A phandle to an fsl,imx7d-pcie-phy node. Additional
|
||||
required properties for imx7d-pcie and imx8mq-pcie.
|
||||
|
||||
power-domains:
|
||||
items:
|
||||
- description: The phandle pointing to the DISPLAY domain for
|
||||
imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and
|
||||
imx8mq-pcie.
|
||||
- description: The phandle pointing to the PCIE_PHY power domains
|
||||
for imx6sx-pcie.
|
||||
|
||||
power-domain-names:
|
||||
items:
|
||||
- const: pcie
|
||||
- const: pcie_phy
|
||||
|
||||
resets:
|
||||
maxItems: 3
|
||||
description: Phandles to PCIe-related reset lines exposed by SRC
|
||||
IP block. Additional required by imx7d-pcie and imx8mq-pcie.
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: pciephy
|
||||
- const: apps
|
||||
- const: turnoff
|
||||
|
||||
fsl,tx-deemph-gen1:
|
||||
description: Gen1 De-emphasis value (optional required).
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
default: 0
|
||||
|
||||
fsl,tx-deemph-gen2-3p5db:
|
||||
description: Gen2 (3.5db) De-emphasis value (optional required).
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
default: 0
|
||||
|
||||
fsl,tx-deemph-gen2-6db:
|
||||
description: Gen2 (6db) De-emphasis value (optional required).
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
default: 20
|
||||
|
||||
fsl,tx-swing-full:
|
||||
description: Gen2 TX SWING FULL value (optional required).
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
default: 127
|
||||
|
||||
fsl,tx-swing-low:
|
||||
description: TX launch amplitude swing_low value (optional required).
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
default: 127
|
||||
|
||||
fsl,max-link-speed:
|
||||
description: Specify PCI Gen for link capability (optional required).
|
||||
Note that the IMX6 LVDS clock outputs do not meet gen2 jitter
|
||||
requirements and thus for gen2 capability a gen2 compliant clock
|
||||
generator should be used and configured.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [1, 2, 3, 4]
|
||||
default: 1
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
phy-names:
|
||||
const: pcie-phy
|
||||
|
||||
reset-gpio:
|
||||
description: Should specify the GPIO for controlling the PCI bus device
|
||||
reset signal. It's not polarity aware and defaults to active-low reset
|
||||
sequence (L=reset state, H=operation state) (optional required).
|
||||
|
||||
reset-gpio-active-high:
|
||||
description: If present then the reset sequence using the GPIO
|
||||
specified in the "reset-gpio" property is reversed (H=reset state,
|
||||
L=operation state) (optional required).
|
||||
type: boolean
|
||||
|
||||
vpcie-supply:
|
||||
description: Should specify the regulator in charge of PCIe port power.
|
||||
The regulator will be enabled when initializing the PCIe host and
|
||||
disabled either as part of the init process or when shutting down
|
||||
the host (optional required).
|
||||
|
||||
vph-supply:
|
||||
description: Should specify the regulator in charge of VPH one of
|
||||
the three PCIe PHY powers. This regulator can be supplied by both
|
||||
1.8v and 3.3v voltage supplies (optional required).
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
- device_type
|
||||
- bus-range
|
||||
- ranges
|
||||
- num-lanes
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- "#interrupt-cells"
|
||||
- interrupt-map-mask
|
||||
- interrupt-map
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/imx6qdl-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
pcie: pcie@1ffc000 {
|
||||
compatible = "fsl,imx6q-pcie";
|
||||
reg = <0x01ffc000 0x04000>,
|
||||
<0x01f00000 0x80000>;
|
||||
reg-names = "dbi", "config";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>,
|
||||
<0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
|
||||
num-lanes = <1>;
|
||||
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
|
||||
<&clks IMX6QDL_CLK_LVDS1_GATE>,
|
||||
<&clks IMX6QDL_CLK_PCIE_REF_125M>;
|
||||
clock-names = "pcie", "pcie_bus", "pcie_phy";
|
||||
};
|
||||
...
|
||||
27
bindings/pci/fsl,pci.txt
Normal file
27
bindings/pci/fsl,pci.txt
Normal file
@@ -0,0 +1,27 @@
|
||||
* Bus Enumeration by Freescale PCI-X Agent
|
||||
|
||||
Typically any Freescale PCI-X bridge hardware strapped into Agent mode
|
||||
is prevented from enumerating the bus. The PrPMC form-factor requires
|
||||
all mezzanines to be PCI-X Agents, but one per system may still
|
||||
enumerate the bus.
|
||||
|
||||
The property defined below will allow a PCI-X bridge to be used for bus
|
||||
enumeration despite being strapped into Agent mode.
|
||||
|
||||
Required properties:
|
||||
- fsl,pci-agent-force-enum : There is no value associated with this
|
||||
property. The property itself is treated as a boolean.
|
||||
|
||||
Example:
|
||||
|
||||
/* PCI-X bridge known to be PrPMC Monarch */
|
||||
pci0: pci@ef008000 {
|
||||
fsl,pci-agent-force-enum;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
...
|
||||
...
|
||||
};
|
||||
180
bindings/pci/hisilicon,kirin-pcie.yaml
Normal file
180
bindings/pci/hisilicon,kirin-pcie.yaml
Normal file
@@ -0,0 +1,180 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: HiSilicon Kirin SoCs PCIe host DT description
|
||||
|
||||
maintainers:
|
||||
- Xiaowei Song <songxiaowei@hisilicon.com>
|
||||
- Binghui Wang <wangbinghui@hisilicon.com>
|
||||
|
||||
description: |
|
||||
Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
|
||||
It shares common functions with the PCIe DesignWare core driver and
|
||||
inherits common properties defined in
|
||||
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/snps,dw-pcie.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- hisilicon,kirin960-pcie
|
||||
- hisilicon,kirin970-pcie
|
||||
|
||||
reg:
|
||||
description: |
|
||||
Should contain dbi, apb, config registers location and length.
|
||||
For hisilicon,kirin960-pcie, it should also contain phy.
|
||||
minItems: 3
|
||||
maxItems: 4
|
||||
|
||||
reg-names:
|
||||
minItems: 3
|
||||
maxItems: 4
|
||||
|
||||
clocks: true
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pcie_phy_ref
|
||||
- const: pcie_aux
|
||||
- const: pcie_apb_phy
|
||||
- const: pcie_apb_sys
|
||||
- const: pcie_aclk
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
hisilicon,clken-gpios:
|
||||
description: |
|
||||
Clock input enablement GPIOs from PCI devices like Ethernet, M.2 and
|
||||
mini-PCIe slots.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/hi3660-clock.h>
|
||||
#include <dt-bindings/clock/hi3670-clock.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie@f4000000 {
|
||||
compatible = "hisilicon,kirin960-pcie";
|
||||
reg = <0x0 0xf4000000 0x0 0x1000>,
|
||||
<0x0 0xff3fe000 0x0 0x1000>,
|
||||
<0x0 0xf3f20000 0x0 0x40000>,
|
||||
<0x0 0xf5000000 0x0 0x2000>;
|
||||
reg-names = "dbi", "apb", "phy", "config";
|
||||
bus-range = <0x0 0xff>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
ranges = <0x02000000 0x0 0x00000000
|
||||
0x0 0xf6000000
|
||||
0x0 0x02000000>;
|
||||
num-lanes = <1>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupts = <0 283 4>;
|
||||
interrupt-names = "msi";
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
|
||||
<&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
|
||||
<&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
|
||||
<&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
|
||||
<&crg_ctrl HI3660_ACLK_GATE_PCIE>;
|
||||
clock-names = "pcie_phy_ref", "pcie_aux", "pcie_apb_phy",
|
||||
"pcie_apb_sys", "pcie_aclk";
|
||||
};
|
||||
|
||||
pcie@f5000000 {
|
||||
compatible = "hisilicon,kirin970-pcie";
|
||||
reg = <0x0 0xf4000000 0x0 0x1000000>,
|
||||
<0x0 0xfc180000 0x0 0x1000>,
|
||||
<0x0 0xf5000000 0x0 0x2000>;
|
||||
reg-names = "dbi", "apb", "config";
|
||||
bus-range = <0x0 0xff>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
phys = <&pcie_phy>;
|
||||
ranges = <0x02000000 0x0 0x00000000
|
||||
0x0 0xf6000000
|
||||
0x0 0x02000000>;
|
||||
num-lanes = <1>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi";
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reset-gpios = <&gpio7 0 0>;
|
||||
hisilicon,clken-gpios = <&gpio27 3 0>, <&gpio17 0 0>, <&gpio20 6 0>;
|
||||
pcie@0,0 { // Lane 0: PCIe switch: Bus 1, Device 0
|
||||
reg = <0 0 0 0 0>;
|
||||
compatible = "pciclass,0604";
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
pcie@0,0 { // Lane 0: upstream
|
||||
reg = <0 0 0 0 0>;
|
||||
compatible = "pciclass,0604";
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
pcie@1,0 { // Lane 4: M.2
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
compatible = "pciclass,0604";
|
||||
device_type = "pci";
|
||||
reset-gpios = <&gpio3 1 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
|
||||
pcie@5,0 { // Lane 5: Mini PCIe
|
||||
reg = <0x2800 0 0 0 0>;
|
||||
compatible = "pciclass,0604";
|
||||
device_type = "pci";
|
||||
reset-gpios = <&gpio27 4 0 >;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
|
||||
pcie@7,0 { // Lane 6: Ethernet
|
||||
reg = <0x03800 0 0 0 0>;
|
||||
compatible = "pciclass,0604";
|
||||
device_type = "pci";
|
||||
reset-gpios = <&gpio25 2 0 >;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
69
bindings/pci/hisilicon-histb-pcie.txt
Normal file
69
bindings/pci/hisilicon-histb-pcie.txt
Normal file
@@ -0,0 +1,69 @@
|
||||
HiSilicon STB PCIe host bridge DT description
|
||||
|
||||
The HiSilicon STB PCIe host controller is based on the DesignWare PCIe core.
|
||||
It shares common functions with the DesignWare PCIe core driver and inherits
|
||||
common properties defined in
|
||||
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
|
||||
|
||||
Additional properties are described here:
|
||||
|
||||
Required properties
|
||||
- compatible: Should be one of the following strings:
|
||||
"hisilicon,hi3798cv200-pcie"
|
||||
- reg: Should contain sysctl, rc_dbi, config registers location and length.
|
||||
- reg-names: Must include the following entries:
|
||||
"control": control registers of PCIe controller;
|
||||
"rc-dbi": configuration space of PCIe controller;
|
||||
"config": configuration transaction space of PCIe controller.
|
||||
- bus-range: PCI bus numbers covered.
|
||||
- interrupts: MSI interrupt.
|
||||
- interrupt-names: Must include "msi" entries.
|
||||
- clocks: List of phandle and clock specifier pairs as listed in clock-names
|
||||
property.
|
||||
- clock-name: Must include the following entries:
|
||||
"aux": auxiliary gate clock;
|
||||
"pipe": pipe gate clock;
|
||||
"sys": sys gate clock;
|
||||
"bus": bus gate clock.
|
||||
- resets: List of phandle and reset specifier pairs as listed in reset-names
|
||||
property.
|
||||
- reset-names: Must include the following entries:
|
||||
"soft": soft reset;
|
||||
"sys": sys reset;
|
||||
"bus": bus reset.
|
||||
|
||||
Optional properties:
|
||||
- reset-gpios: The gpio to generate PCIe PERST# assert and deassert signal.
|
||||
- vpcie-supply: The regulator in charge of PCIe port power.
|
||||
- phys: List of phandle and phy mode specifier, should be 0.
|
||||
- phy-names: Must be "phy".
|
||||
|
||||
Example:
|
||||
pcie@f9860000 {
|
||||
compatible = "hisilicon,hi3798cv200-pcie";
|
||||
reg = <0xf9860000 0x1000>,
|
||||
<0xf0000000 0x2000>,
|
||||
<0xf2000000 0x01000000>;
|
||||
reg-names = "control", "rc-dbi", "config";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0 15>;
|
||||
num-lanes = <1>;
|
||||
ranges=<0x81000000 0 0 0xf4000000 0 0x00010000
|
||||
0x82000000 0 0xf3000000 0xf3000000 0 0x01000000>;
|
||||
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&crg PCIE_AUX_CLK>,
|
||||
<&crg PCIE_PIPE_CLK>,
|
||||
<&crg PCIE_SYS_CLK>,
|
||||
<&crg PCIE_BUS_CLK>;
|
||||
clock-names = "aux", "pipe", "sys", "bus";
|
||||
resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
|
||||
reset-names = "soft", "sys", "bus";
|
||||
phys = <&combphy1 PHY_TYPE_PCIE>;
|
||||
phy-names = "phy";
|
||||
};
|
||||
177
bindings/pci/host-generic-pci.yaml
Normal file
177
bindings/pci/host-generic-pci.yaml
Normal file
@@ -0,0 +1,177 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Generic PCI host controller
|
||||
|
||||
maintainers:
|
||||
- Will Deacon <will@kernel.org>
|
||||
|
||||
description: |
|
||||
Firmware-initialised PCI host controllers and PCI emulations, such as the
|
||||
virtio-pci implementations found in kvmtool and other para-virtualised
|
||||
systems, do not require driver support for complexities such as regulator
|
||||
and clock management. In fact, the controller may not even require the
|
||||
configuration of a control interface by the operating system, instead
|
||||
presenting a set of fixed windows describing a subset of IO, Memory and
|
||||
Configuration Spaces.
|
||||
|
||||
Configuration Space is assumed to be memory-mapped (as opposed to being
|
||||
accessed via an ioport) and laid out with a direct correspondence to the
|
||||
geography of a PCI bus address by concatenating the various components to
|
||||
form an offset.
|
||||
|
||||
For CAM, this 24-bit offset is:
|
||||
|
||||
cfg_offset(bus, device, function, register) =
|
||||
bus << 16 | device << 11 | function << 8 | register
|
||||
|
||||
While ECAM extends this by 4 bits to accommodate 4k of function space:
|
||||
|
||||
cfg_offset(bus, device, function, register) =
|
||||
bus << 20 | device << 15 | function << 12 | register
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
description: Depends on the layout of configuration space (CAM vs ECAM
|
||||
respectively). May also have more specific compatibles.
|
||||
oneOf:
|
||||
- description:
|
||||
PCIe host controller in Arm Juno based on PLDA XpressRICH3-AXI IP
|
||||
items:
|
||||
- const: arm,juno-r1-pcie
|
||||
- const: plda,xpressrich3-axi
|
||||
- const: pci-host-ecam-generic
|
||||
- description: |
|
||||
ThunderX PCI host controller for pass-1.x silicon
|
||||
|
||||
Firmware-initialized PCI host controller to on-chip devices found on
|
||||
some Cavium ThunderX processors. These devices have ECAM-based config
|
||||
access, but the BARs are all at fixed addresses. We handle the fixed
|
||||
addresses by synthesizing Enhanced Allocation (EA) capabilities for
|
||||
these devices.
|
||||
const: cavium,pci-host-thunder-ecam
|
||||
- description:
|
||||
Cavium ThunderX PEM firmware-initialized PCIe host controller
|
||||
const: cavium,pci-host-thunder-pem
|
||||
- description:
|
||||
HiSilicon Hip06/Hip07 PCIe host bridge in almost-ECAM mode. Some
|
||||
firmware places the host controller in a mode where it is ECAM
|
||||
compliant for all devices other than the root complex.
|
||||
enum:
|
||||
- hisilicon,hip06-pcie-ecam
|
||||
- hisilicon,hip07-pcie-ecam
|
||||
- description: |
|
||||
In some cases, firmware may already have configured the Synopsys
|
||||
DesignWare PCIe controller in RC mode with static ATU window mappings
|
||||
that cover all config, MMIO and I/O spaces in a [mostly] ECAM
|
||||
compatible fashion. In this case, there is no need for the OS to
|
||||
perform any low level setup of clocks, PHYs or device registers, nor
|
||||
is there any reason for the driver to reconfigure ATU windows for
|
||||
config and/or IO space accesses at runtime.
|
||||
|
||||
In cases where the IP was synthesized with a minimum ATU window size
|
||||
of 64 KB, it cannot be supported by the generic ECAM driver, because
|
||||
it requires special config space accessors that filter accesses to
|
||||
device #1 and beyond on the first bus.
|
||||
items:
|
||||
- enum:
|
||||
- marvell,armada8k-pcie-ecam
|
||||
- socionext,synquacer-pcie-ecam
|
||||
- const: snps,dw-pcie-ecam
|
||||
- description:
|
||||
CAM or ECAM compliant PCI host controllers without any quirks
|
||||
enum:
|
||||
- pci-host-cam-generic
|
||||
- pci-host-ecam-generic
|
||||
|
||||
reg:
|
||||
description:
|
||||
The Configuration Space base address and size, as accessed from the parent
|
||||
bus. The base address corresponds to the first bus in the "bus-range"
|
||||
property. If no "bus-range" is specified, this will be bus 0 (the
|
||||
default). Some host controllers have a 2nd non-compliant address range,
|
||||
so 2 entries are allowed.
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
ranges:
|
||||
description:
|
||||
As described in IEEE Std 1275-1994, but must provide at least a
|
||||
definition of non-prefetchable memory. One or both of prefetchable Memory
|
||||
and IO Space may also be provided.
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
|
||||
dma-coherent: true
|
||||
iommu-map: true
|
||||
iommu-map-mask: true
|
||||
msi-parent: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- ranges
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-bus.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: arm,juno-r1-pcie
|
||||
then:
|
||||
required:
|
||||
- dma-coherent
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
not:
|
||||
contains:
|
||||
enum:
|
||||
- cavium,pci-host-thunder-pem
|
||||
- hisilicon,hip06-pcie-ecam
|
||||
- hisilicon,hip07-pcie-ecam
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
pcie@40000000 {
|
||||
compatible = "pci-host-cam-generic";
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x0 0x1>;
|
||||
|
||||
// CPU_PHYSICAL(2) SIZE(2)
|
||||
reg = <0x0 0x40000000 0x0 0x1000000>;
|
||||
|
||||
// BUS_ADDRESS(3) CPU_PHYSICAL(2) SIZE(2)
|
||||
ranges = <0x01000000 0x0 0x01000000 0x0 0x01000000 0x0 0x00010000>,
|
||||
<0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x3f000000>;
|
||||
|
||||
#interrupt-cells = <0x1>;
|
||||
|
||||
// PCI_DEVICE(3) INT#(1) CONTROLLER(PHANDLE) CONTROLLER_DATA(3)
|
||||
interrupt-map = < 0x0 0x0 0x0 0x1 &gic 0x0 0x4 0x1>,
|
||||
< 0x800 0x0 0x0 0x1 &gic 0x0 0x5 0x1>,
|
||||
<0x1000 0x0 0x0 0x1 &gic 0x0 0x6 0x1>,
|
||||
<0x1800 0x0 0x0 0x1 &gic 0x0 0x7 0x1>;
|
||||
|
||||
// PCI_DEVICE(3) INT#(1)
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
};
|
||||
};
|
||||
...
|
||||
100
bindings/pci/intel,ixp4xx-pci.yaml
Normal file
100
bindings/pci/intel,ixp4xx-pci.yaml
Normal file
@@ -0,0 +1,100 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/intel,ixp4xx-pci.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Intel IXP4xx PCI controller
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
description: PCI host controller found in the Intel IXP4xx SoC series.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-bus.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- intel,ixp42x-pci
|
||||
- intel,ixp43x-pci
|
||||
description: The two supported variants are ixp42x and ixp43x,
|
||||
though more variants may exist.
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: IXP4xx-specific registers
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: Main PCI interrupt
|
||||
- description: PCI DMA interrupt 1
|
||||
- description: PCI DMA interrupt 2
|
||||
|
||||
ranges:
|
||||
maxItems: 2
|
||||
description: Typically one memory range of 64MB and one IO
|
||||
space range of 64KB.
|
||||
|
||||
dma-ranges:
|
||||
maxItems: 1
|
||||
description: The DMA range tells the PCI host which addresses
|
||||
the RAM is at. It can map only 64MB so if the RAM is bigger
|
||||
than 64MB the DMA access has to be restricted to these
|
||||
addresses.
|
||||
|
||||
"#interrupt-cells": true
|
||||
|
||||
interrupt-map: true
|
||||
|
||||
interrupt-map-mask:
|
||||
items:
|
||||
- const: 0xf800
|
||||
- const: 0
|
||||
- const: 0
|
||||
- const: 7
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- dma-ranges
|
||||
- "#interrupt-cells"
|
||||
- interrupt-map
|
||||
- interrupt-map-mask
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
pci@c0000000 {
|
||||
compatible = "intel,ixp43x-pci";
|
||||
reg = <0xc0000000 0x1000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges =
|
||||
<0x02000000 0 0x48000000 0x48000000 0 0x04000000>,
|
||||
<0x01000000 0 0x00000000 0x4c000000 0 0x00010000>;
|
||||
dma-ranges =
|
||||
<0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map =
|
||||
<0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */
|
||||
<0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */
|
||||
<0x0800 0 0 3 &gpio0 9 3>, /* INT C on slot 1 is irq 9 */
|
||||
<0x0800 0 0 4 &gpio0 8 3>, /* INT D on slot 1 is irq 8 */
|
||||
<0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */
|
||||
<0x1000 0 0 2 &gpio0 9 3>, /* INT B on slot 2 is irq 9 */
|
||||
<0x1000 0 0 3 &gpio0 8 3>, /* INT C on slot 2 is irq 8 */
|
||||
<0x1000 0 0 4 &gpio0 11 3>, /* INT D on slot 2 is irq 11 */
|
||||
<0x1800 0 0 1 &gpio0 9 3>, /* INT A on slot 3 is irq 9 */
|
||||
<0x1800 0 0 2 &gpio0 8 3>, /* INT B on slot 3 is irq 8 */
|
||||
<0x1800 0 0 3 &gpio0 11 3>, /* INT C on slot 3 is irq 11 */
|
||||
<0x1800 0 0 4 &gpio0 10 3>; /* INT D on slot 3 is irq 10 */
|
||||
};
|
||||
69
bindings/pci/intel,keembay-pcie-ep.yaml
Normal file
69
bindings/pci/intel,keembay-pcie-ep.yaml
Normal file
@@ -0,0 +1,69 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/pci/intel,keembay-pcie-ep.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Intel Keem Bay PCIe controller Endpoint mode
|
||||
|
||||
maintainers:
|
||||
- Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
|
||||
- Srikanth Thokala <srikanth.thokala@intel.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: intel,keembay-pcie-ep
|
||||
|
||||
reg:
|
||||
maxItems: 5
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dbi
|
||||
- const: dbi2
|
||||
- const: atu
|
||||
- const: addr_space
|
||||
- const: apb
|
||||
|
||||
interrupts:
|
||||
maxItems: 4
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: pcie
|
||||
- const: pcie_ev
|
||||
- const: pcie_err
|
||||
- const: pcie_mem_access
|
||||
|
||||
num-lanes:
|
||||
description: Number of lanes to use.
|
||||
enum: [ 1, 2 ]
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
pcie-ep@37000000 {
|
||||
compatible = "intel,keembay-pcie-ep";
|
||||
reg = <0x37000000 0x00001000>,
|
||||
<0x37100000 0x00001000>,
|
||||
<0x37300000 0x00001000>,
|
||||
<0x36000000 0x01000000>,
|
||||
<0x37800000 0x00000200>;
|
||||
reg-names = "dbi", "dbi2", "atu", "addr_space", "apb";
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 108 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "pcie", "pcie_ev", "pcie_err", "pcie_mem_access";
|
||||
num-lanes = <2>;
|
||||
};
|
||||
97
bindings/pci/intel,keembay-pcie.yaml
Normal file
97
bindings/pci/intel,keembay-pcie.yaml
Normal file
@@ -0,0 +1,97 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/pci/intel,keembay-pcie.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Intel Keem Bay PCIe controller Root Complex mode
|
||||
|
||||
maintainers:
|
||||
- Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
|
||||
- Srikanth Thokala <srikanth.thokala@intel.com>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-bus.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: intel,keembay-pcie
|
||||
|
||||
ranges:
|
||||
maxItems: 1
|
||||
|
||||
reset-gpios:
|
||||
maxItems: 1
|
||||
|
||||
reg:
|
||||
maxItems: 4
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dbi
|
||||
- const: atu
|
||||
- const: config
|
||||
- const: apb
|
||||
|
||||
clocks:
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: master
|
||||
- const: aux
|
||||
|
||||
interrupts:
|
||||
maxItems: 3
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: pcie
|
||||
- const: pcie_ev
|
||||
- const: pcie_err
|
||||
|
||||
num-lanes:
|
||||
description: Number of lanes to use.
|
||||
enum: [ 1, 2 ]
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- ranges
|
||||
- clocks
|
||||
- clock-names
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- reset-gpios
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#define KEEM_BAY_A53_PCIE
|
||||
#define KEEM_BAY_A53_AUX_PCIE
|
||||
pcie@37000000 {
|
||||
compatible = "intel,keembay-pcie";
|
||||
reg = <0x37000000 0x00001000>,
|
||||
<0x37300000 0x00001000>,
|
||||
<0x36e00000 0x00200000>,
|
||||
<0x37800000 0x00000200>;
|
||||
reg-names = "dbi", "atu", "config", "apb";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
ranges = <0x02000000 0 0x36000000 0x36000000 0 0x00e00000>;
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "pcie", "pcie_ev", "pcie_err";
|
||||
clocks = <&scmi_clk KEEM_BAY_A53_PCIE>,
|
||||
<&scmi_clk KEEM_BAY_A53_AUX_PCIE>;
|
||||
clock-names = "master", "aux";
|
||||
reset-gpios = <&pca2 9 GPIO_ACTIVE_LOW>;
|
||||
num-lanes = <2>;
|
||||
};
|
||||
117
bindings/pci/intel-gw-pcie.yaml
Normal file
117
bindings/pci/intel-gw-pcie.yaml
Normal file
@@ -0,0 +1,117 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: PCIe RC controller on Intel Gateway SoCs
|
||||
|
||||
maintainers:
|
||||
- Rahul Tanwar <rtanwar@maxlinear.com>
|
||||
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: intel,lgm-pcie
|
||||
required:
|
||||
- compatible
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/snps,dw-pcie.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: intel,lgm-pcie
|
||||
- const: snps,dw-pcie
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Controller control and status registers.
|
||||
- description: PCIe configuration registers.
|
||||
- description: Controller application registers.
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dbi
|
||||
- const: config
|
||||
- const: app
|
||||
|
||||
ranges:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
phy-names:
|
||||
const: pcie
|
||||
|
||||
reset-gpios:
|
||||
maxItems: 1
|
||||
|
||||
num-lanes:
|
||||
maximum: 2
|
||||
|
||||
max-link-speed:
|
||||
enum: [1, 2, 3, 4]
|
||||
default: 1
|
||||
|
||||
reset-assert-ms:
|
||||
description: |
|
||||
Delay after asserting reset to the PCIe device.
|
||||
maximum: 500
|
||||
default: 100
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- ranges
|
||||
- resets
|
||||
- clocks
|
||||
- phys
|
||||
- phy-names
|
||||
- reset-gpios
|
||||
- '#interrupt-cells'
|
||||
- interrupt-map
|
||||
- interrupt-map-mask
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
pcie10: pcie@d0e00000 {
|
||||
compatible = "intel,lgm-pcie", "snps,dw-pcie";
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
reg = <0xd0e00000 0x1000>,
|
||||
<0xd2000000 0x800000>,
|
||||
<0xd0a41000 0x1000>;
|
||||
reg-names = "dbi", "config", "app";
|
||||
linux,pci-domain = <0>;
|
||||
max-link-speed = <4>;
|
||||
bus-range = <0x00 0x08>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &ioapic1 27 1>,
|
||||
<0 0 0 2 &ioapic1 28 1>,
|
||||
<0 0 0 3 &ioapic1 29 1>,
|
||||
<0 0 0 4 &ioapic1 30 1>;
|
||||
ranges = <0x02000000 0 0xd4000000 0xd4000000 0 0x04000000>;
|
||||
resets = <&rcu0 0x50 0>;
|
||||
clocks = <&cgu0 120>;
|
||||
phys = <&cb0phy0>;
|
||||
phy-names = "pcie";
|
||||
reset-assert-ms = <500>;
|
||||
reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
|
||||
num-lanes = <2>;
|
||||
};
|
||||
79
bindings/pci/layerscape-pci.txt
Normal file
79
bindings/pci/layerscape-pci.txt
Normal file
@@ -0,0 +1,79 @@
|
||||
Freescale Layerscape PCIe controller
|
||||
|
||||
This PCIe host controller is based on the Synopsys DesignWare PCIe IP
|
||||
and thus inherits all the common properties defined in snps,dw-pcie.yaml.
|
||||
|
||||
This controller derives its clocks from the Reset Configuration Word (RCW)
|
||||
which is used to describe the PLL settings at the time of chip-reset.
|
||||
|
||||
Also as per the available Reference Manuals, there is no specific 'version'
|
||||
register available in the Freescale PCIe controller register set,
|
||||
which can allow determining the underlying DesignWare PCIe controller version
|
||||
information.
|
||||
|
||||
Required properties:
|
||||
- compatible: should contain the platform identifier such as:
|
||||
RC mode:
|
||||
"fsl,ls1021a-pcie"
|
||||
"fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
|
||||
"fsl,ls2088a-pcie"
|
||||
"fsl,ls1088a-pcie"
|
||||
"fsl,ls1046a-pcie"
|
||||
"fsl,ls1043a-pcie"
|
||||
"fsl,ls1012a-pcie"
|
||||
"fsl,ls1028a-pcie"
|
||||
EP mode:
|
||||
"fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep"
|
||||
"fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"
|
||||
"fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"
|
||||
"fsl,ls2088a-pcie-ep", "fsl,ls-pcie-ep"
|
||||
"fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep"
|
||||
- reg: base addresses and lengths of the PCIe controller register blocks.
|
||||
- interrupts: A list of interrupt outputs of the controller. Must contain an
|
||||
entry for each entry in the interrupt-names property.
|
||||
- interrupt-names: It could include the following entries:
|
||||
"aer": Used for interrupt line which reports AER events when
|
||||
non MSI/MSI-X/INTx mode is used
|
||||
"pme": Used for interrupt line which reports PME events when
|
||||
non MSI/MSI-X/INTx mode is used
|
||||
"intr": Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a)
|
||||
which has a single interrupt line for miscellaneous controller
|
||||
events(could include AER and PME events).
|
||||
- fsl,pcie-scfg: Must include two entries.
|
||||
The first entry must be a link to the SCFG device node
|
||||
The second entry is the physical PCIe controller index starting from '0'.
|
||||
This is used to get SCFG PEXN registers
|
||||
- dma-coherent: Indicates that the hardware IP block can ensure the coherency
|
||||
of the data transferred from/to the IP block. This can avoid the software
|
||||
cache flush/invalid actions, and improve the performance significantly.
|
||||
|
||||
Optional properties:
|
||||
- big-endian: If the PEX_LUT and PF register block is in big-endian, specify
|
||||
this property.
|
||||
|
||||
Example:
|
||||
|
||||
pcie@3400000 {
|
||||
compatible = "fsl,ls1088a-pcie";
|
||||
reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
|
||||
<0x20 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
|
||||
interrupt-names = "aer";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
num-viewport = <256>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
msi-parent = <&its>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
|
||||
};
|
||||
52
bindings/pci/layerscape-pcie-gen4.txt
Normal file
52
bindings/pci/layerscape-pcie-gen4.txt
Normal file
@@ -0,0 +1,52 @@
|
||||
NXP Layerscape PCIe Gen4 controller
|
||||
|
||||
This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all
|
||||
the common properties defined in mobiveil-pcie.txt.
|
||||
|
||||
Required properties:
|
||||
- compatible: should contain the platform identifier such as:
|
||||
"fsl,lx2160a-pcie"
|
||||
- reg: base addresses and lengths of the PCIe controller register blocks.
|
||||
"csr_axi_slave": Bridge config registers
|
||||
"config_axi_slave": PCIe controller registers
|
||||
- interrupts: A list of interrupt outputs of the controller. Must contain an
|
||||
entry for each entry in the interrupt-names property.
|
||||
- interrupt-names: It could include the following entries:
|
||||
"intr": The interrupt that is asserted for controller interrupts
|
||||
"aer": Asserted for aer interrupt when chip support the aer interrupt with
|
||||
none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
|
||||
"pme": Asserted for pme interrupt when chip support the pme interrupt with
|
||||
none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
|
||||
- dma-coherent: Indicates that the hardware IP block can ensure the coherency
|
||||
of the data transferred from/to the IP block. This can avoid the software
|
||||
cache flush/invalid actions, and improve the performance significantly.
|
||||
- msi-parent : See the generic MSI binding described in
|
||||
Documentation/devicetree/bindings/interrupt-controller/msi.txt.
|
||||
|
||||
Example:
|
||||
|
||||
pcie@3400000 {
|
||||
compatible = "fsl,lx2160a-pcie";
|
||||
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
|
||||
0x80 0x00000000 0x0 0x00001000>; /* configuration space */
|
||||
reg-names = "csr_axi_slave", "config_axi_slave";
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
|
||||
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
|
||||
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
|
||||
interrupt-names = "aer", "pme", "intr";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
apio-wins = <8>;
|
||||
ppio-wins = <8>;
|
||||
dma-coherent;
|
||||
bus-range = <0x0 0xff>;
|
||||
msi-parent = <&its>;
|
||||
ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
63
bindings/pci/loongson.yaml
Normal file
63
bindings/pci/loongson.yaml
Normal file
@@ -0,0 +1,63 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/loongson.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Loongson PCI Host Controller
|
||||
|
||||
maintainers:
|
||||
- Jiaxun Yang <jiaxun.yang@flygoat.com>
|
||||
|
||||
description: |+
|
||||
PCI host controller found on Loongson PCHs and SoCs.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-bus.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- loongson,ls2k-pci
|
||||
- loongson,ls7a-pci
|
||||
- loongson,rs780e-pci
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: CFG0 standard config space register
|
||||
- description: CFG1 extended config space register
|
||||
|
||||
ranges:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- ranges
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
pcie@1a000000 {
|
||||
compatible = "loongson,rs780e-pci";
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
// CPU_PHYSICAL(2) SIZE(2)
|
||||
reg = <0x0 0x1a000000 0x0 0x2000000>;
|
||||
|
||||
// BUS_ADDRESS(3) CPU_PHYSICAL(2) SIZE(2)
|
||||
ranges = <0x01000000 0x0 0x00004000 0x0 0x00004000 0x0 0x00004000>,
|
||||
<0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
|
||||
};
|
||||
};
|
||||
...
|
||||
145
bindings/pci/mediatek,mt7621-pcie.yaml
Normal file
145
bindings/pci/mediatek,mt7621-pcie.yaml
Normal file
@@ -0,0 +1,145 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek MT7621 PCIe controller
|
||||
|
||||
maintainers:
|
||||
- Sergio Paracuellos <sergio.paracuellos@gmail.com>
|
||||
|
||||
description: |+
|
||||
MediaTek MT7621 PCIe subsys supports a single Root Complex (RC)
|
||||
with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-bus.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: mediatek,mt7621-pci
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: host-pci bridge registers
|
||||
- description: pcie port 0 RC control registers
|
||||
- description: pcie port 1 RC control registers
|
||||
- description: pcie port 2 RC control registers
|
||||
|
||||
ranges:
|
||||
maxItems: 2
|
||||
|
||||
patternProperties:
|
||||
'pcie@[0-2],0':
|
||||
type: object
|
||||
$ref: /schemas/pci/pci-bus.yaml#
|
||||
|
||||
properties:
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
phy-names:
|
||||
pattern: '^pcie-phy[0-2]$'
|
||||
|
||||
required:
|
||||
- "#interrupt-cells"
|
||||
- interrupt-map-mask
|
||||
- interrupt-map
|
||||
- resets
|
||||
- clocks
|
||||
- phys
|
||||
- phy-names
|
||||
- ranges
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- ranges
|
||||
- "#interrupt-cells"
|
||||
- interrupt-map-mask
|
||||
- interrupt-map
|
||||
- reset-gpios
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/mips-gic.h>
|
||||
|
||||
pcie: pcie@1e140000 {
|
||||
compatible = "mediatek,mt7621-pci";
|
||||
reg = <0x1e140000 0x100>,
|
||||
<0x1e142000 0x100>,
|
||||
<0x1e143000 0x100>,
|
||||
<0x1e144000 0x100>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_pins>;
|
||||
device_type = "pci";
|
||||
ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
|
||||
<0x01000000 0 0x1e160000 0x1e160000 0 0x00010000>; /* io space */
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0xF800 0 0 0>;
|
||||
interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pcie@0,0 {
|
||||
reg = <0x0000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
resets = <&rstctrl 24>;
|
||||
clocks = <&clkctrl 24>;
|
||||
phys = <&pcie0_phy 1>;
|
||||
phy-names = "pcie-phy0";
|
||||
ranges;
|
||||
};
|
||||
|
||||
pcie@1,0 {
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
resets = <&rstctrl 25>;
|
||||
clocks = <&clkctrl 25>;
|
||||
phys = <&pcie0_phy 1>;
|
||||
phy-names = "pcie-phy1";
|
||||
ranges;
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
resets = <&rstctrl 26>;
|
||||
clocks = <&clkctrl 26>;
|
||||
phys = <&pcie2_phy 0>;
|
||||
phy-names = "pcie-phy2";
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
...
|
||||
39
bindings/pci/mediatek-pcie-cfg.yaml
Normal file
39
bindings/pci/mediatek-pcie-cfg.yaml
Normal file
@@ -0,0 +1,39 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/mediatek-pcie-cfg.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek PCIECFG controller
|
||||
|
||||
maintainers:
|
||||
- Chuanjia Liu <chuanjia.liu@mediatek.com>
|
||||
- Jianjun Wang <jianjun.wang@mediatek.com>
|
||||
|
||||
description: |
|
||||
The MediaTek PCIECFG controller controls some feature about
|
||||
LTSSM, ASPM and so on.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- mediatek,generic-pciecfg
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
pciecfg: pciecfg@1a140000 {
|
||||
compatible = "mediatek,generic-pciecfg", "syscon";
|
||||
reg = <0x1a140000 0x1000>;
|
||||
};
|
||||
...
|
||||
193
bindings/pci/mediatek-pcie-gen3.yaml
Normal file
193
bindings/pci/mediatek-pcie-gen3.yaml
Normal file
@@ -0,0 +1,193 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Gen3 PCIe controller on MediaTek SoCs
|
||||
|
||||
maintainers:
|
||||
- Jianjun Wang <jianjun.wang@mediatek.com>
|
||||
|
||||
description: |+
|
||||
PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed
|
||||
and compatible with Gen2, Gen1 speed.
|
||||
|
||||
This PCIe controller supports up to 256 MSI vectors, the MSI hardware
|
||||
block diagram is as follows:
|
||||
|
||||
+-----+
|
||||
| GIC |
|
||||
+-----+
|
||||
^
|
||||
|
|
||||
port->irq
|
||||
|
|
||||
+-+-+-+-+-+-+-+-+
|
||||
|0|1|2|3|4|5|6|7| (PCIe intc)
|
||||
+-+-+-+-+-+-+-+-+
|
||||
^ ^ ^
|
||||
| | ... |
|
||||
+-------+ +------+ +-----------+
|
||||
| | |
|
||||
+-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+
|
||||
|0|1|...|30|31| |0|1|...|30|31| |0|1|...|30|31| (MSI sets)
|
||||
+-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+
|
||||
^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
|
||||
| | | | | | | | | | | | (MSI vectors)
|
||||
| | | | | | | | | | | |
|
||||
|
||||
(MSI SET0) (MSI SET1) ... (MSI SET7)
|
||||
|
||||
With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
|
||||
each set has its own address for MSI message, and supports 32 MSI vectors
|
||||
to generate interrupt.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-bus.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8188-pcie
|
||||
- mediatek,mt8195-pcie
|
||||
- const: mediatek,mt8192-pcie
|
||||
- const: mediatek,mt8192-pcie
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: pcie-mac
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
ranges:
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
|
||||
resets:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
reset-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: phy
|
||||
- const: mac
|
||||
|
||||
clocks:
|
||||
maxItems: 6
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pl_250m
|
||||
- const: tl_26m
|
||||
- const: tl_96m
|
||||
- const: tl_32k
|
||||
- const: peri_26m
|
||||
- enum:
|
||||
- top_133m # for MT8192
|
||||
- peri_mem # for MT8188/MT8195
|
||||
|
||||
assigned-clocks:
|
||||
maxItems: 1
|
||||
|
||||
assigned-clock-parents:
|
||||
maxItems: 1
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
phy-names:
|
||||
items:
|
||||
- const: pcie-phy
|
||||
|
||||
'#interrupt-cells':
|
||||
const: 1
|
||||
|
||||
interrupt-controller:
|
||||
description: Interrupt controller node for handling legacy PCI interrupts.
|
||||
type: object
|
||||
properties:
|
||||
'#address-cells':
|
||||
const: 0
|
||||
'#interrupt-cells':
|
||||
const: 1
|
||||
interrupt-controller: true
|
||||
|
||||
required:
|
||||
- '#address-cells'
|
||||
- '#interrupt-cells'
|
||||
- interrupt-controller
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- interrupts
|
||||
- ranges
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#interrupt-cells'
|
||||
- interrupt-controller
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie: pcie@11230000 {
|
||||
compatible = "mediatek,mt8192-pcie";
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
reg = <0x00 0x11230000 0x00 0x4000>;
|
||||
reg-names = "pcie-mac";
|
||||
interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = <0x82000000 0x00 0x12000000 0x00
|
||||
0x12000000 0x00 0x1000000>;
|
||||
clocks = <&infracfg 44>,
|
||||
<&infracfg 40>,
|
||||
<&infracfg 43>,
|
||||
<&infracfg 97>,
|
||||
<&infracfg 99>,
|
||||
<&infracfg 111>;
|
||||
clock-names = "pl_250m", "tl_26m", "tl_96m",
|
||||
"tl_32k", "peri_26m", "top_133m";
|
||||
assigned-clocks = <&topckgen 50>;
|
||||
assigned-clock-parents = <&topckgen 91>;
|
||||
|
||||
phys = <&pciephy>;
|
||||
phy-names = "pcie-phy";
|
||||
|
||||
resets = <&infracfg_rst 2>,
|
||||
<&infracfg_rst 3>;
|
||||
reset-names = "phy", "mac";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc 0>,
|
||||
<0 0 0 2 &pcie_intc 1>,
|
||||
<0 0 0 3 &pcie_intc 2>,
|
||||
<0 0 0 4 &pcie_intc 3>;
|
||||
pcie_intc: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
};
|
||||
289
bindings/pci/mediatek-pcie.txt
Normal file
289
bindings/pci/mediatek-pcie.txt
Normal file
@@ -0,0 +1,289 @@
|
||||
MediaTek Gen2 PCIe controller
|
||||
|
||||
Required properties:
|
||||
- compatible: Should contain one of the following strings:
|
||||
"mediatek,mt2701-pcie"
|
||||
"mediatek,mt2712-pcie"
|
||||
"mediatek,mt7622-pcie"
|
||||
"mediatek,mt7623-pcie"
|
||||
"mediatek,mt7629-pcie"
|
||||
"airoha,en7523-pcie"
|
||||
- device_type: Must be "pci"
|
||||
- reg: Base addresses and lengths of the root ports.
|
||||
- reg-names: Names of the above areas to use during resource lookup.
|
||||
- #address-cells: Address representation for root ports (must be 3)
|
||||
- #size-cells: Size representation for root ports (must be 2)
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names:
|
||||
Mandatory entries:
|
||||
- sys_ckN :transaction layer and data link layer clock
|
||||
Required entries for MT2701/MT7623:
|
||||
- free_ck :for reference clock of PCIe subsys
|
||||
Required entries for MT2712/MT7622:
|
||||
- ahb_ckN :AHB slave interface operating clock for CSR access and RC
|
||||
initiated MMIO access
|
||||
Required entries for MT7622:
|
||||
- axi_ckN :application layer MMIO channel operating clock
|
||||
- aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when
|
||||
pcie_mac_ck/pcie_pipe_ck is turned off
|
||||
- obff_ckN :OBFF functional block operating clock
|
||||
- pipe_ckN :LTSSM and PHY/MAC layer operating clock
|
||||
where N starting from 0 to one less than the number of root ports.
|
||||
- phys: List of PHY specifiers (used by generic PHY framework).
|
||||
- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
|
||||
number of PHYs as specified in *phys* property.
|
||||
- power-domains: A phandle and power domain specifier pair to the power domain
|
||||
which is responsible for collapsing and restoring power to the peripheral.
|
||||
- bus-range: Range of bus numbers associated with this controller.
|
||||
- ranges: Ranges for the PCI memory and I/O regions.
|
||||
|
||||
Required properties for MT7623/MT2701:
|
||||
- #interrupt-cells: Size representation for interrupts (must be 1)
|
||||
- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
|
||||
Please refer to the standard PCI bus binding document for a more detailed
|
||||
explanation.
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
|
||||
number of root ports.
|
||||
|
||||
Required properties for MT2712/MT7622/MT7629:
|
||||
-interrupts: A list of interrupt outputs of the controller, must have one
|
||||
entry for each PCIe port
|
||||
- interrupt-names: Must include the following entries:
|
||||
- "pcie_irq": The interrupt that is asserted when an MSI/INTX is received
|
||||
- linux,pci-domain: PCI domain ID. Should be unique for each host controller
|
||||
|
||||
In addition, the device tree node must have sub-nodes describing each
|
||||
PCIe port interface, having the following mandatory properties:
|
||||
|
||||
Required properties:
|
||||
- device_type: Must be "pci"
|
||||
- reg: Only the first four bytes are used to refer to the correct bus number
|
||||
and device number.
|
||||
- #address-cells: Must be 3
|
||||
- #size-cells: Must be 2
|
||||
- #interrupt-cells: Must be 1
|
||||
- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
|
||||
Please refer to the standard PCI bus binding document for a more detailed
|
||||
explanation.
|
||||
- ranges: Sub-ranges distributed from the PCIe controller node. An empty
|
||||
property is sufficient.
|
||||
|
||||
Examples for MT7623:
|
||||
|
||||
hifsys: syscon@1a000000 {
|
||||
compatible = "mediatek,mt7623-hifsys",
|
||||
"mediatek,mt2701-hifsys",
|
||||
"syscon";
|
||||
reg = <0 0x1a000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
pcie: pcie@1a140000 {
|
||||
compatible = "mediatek,mt7623-pcie";
|
||||
device_type = "pci";
|
||||
reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
|
||||
<0 0x1a142000 0 0x1000>, /* Port0 registers */
|
||||
<0 0x1a143000 0 0x1000>, /* Port1 registers */
|
||||
<0 0x1a144000 0 0x1000>; /* Port2 registers */
|
||||
reg-names = "subsys", "port0", "port1", "port2";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0xf800 0 0 0>;
|
||||
interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
|
||||
<0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
|
||||
<0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
|
||||
<&hifsys CLK_HIFSYS_PCIE0>,
|
||||
<&hifsys CLK_HIFSYS_PCIE1>,
|
||||
<&hifsys CLK_HIFSYS_PCIE2>;
|
||||
clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
|
||||
resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
|
||||
<&hifsys MT2701_HIFSYS_PCIE1_RST>,
|
||||
<&hifsys MT2701_HIFSYS_PCIE2_RST>;
|
||||
reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
|
||||
phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>,
|
||||
<&pcie2_phy PHY_TYPE_PCIE>;
|
||||
phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
|
||||
power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* I/O space */
|
||||
0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */
|
||||
|
||||
pcie@0,0 {
|
||||
reg = <0x0000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
|
||||
ranges;
|
||||
};
|
||||
|
||||
pcie@1,0 {
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
|
||||
ranges;
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
|
||||
Examples for MT2712:
|
||||
|
||||
pcie1: pcie@112ff000 {
|
||||
compatible = "mediatek,mt2712-pcie";
|
||||
device_type = "pci";
|
||||
reg = <0 0x112ff000 0 0x1000>;
|
||||
reg-names = "port1";
|
||||
linux,pci-domain = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "pcie_irq";
|
||||
clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
|
||||
<&pericfg CLK_PERI_PCIE1>;
|
||||
clock-names = "sys_ck1", "ahb_ck1";
|
||||
phys = <&u3port1 PHY_TYPE_PCIE>;
|
||||
phy-names = "pcie-phy1";
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>;
|
||||
status = "disabled";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
|
||||
<0 0 0 2 &pcie_intc1 1>,
|
||||
<0 0 0 3 &pcie_intc1 2>,
|
||||
<0 0 0 4 &pcie_intc1 3>;
|
||||
pcie_intc1: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie0: pcie@11700000 {
|
||||
compatible = "mediatek,mt2712-pcie";
|
||||
device_type = "pci";
|
||||
reg = <0 0x11700000 0 0x1000>;
|
||||
reg-names = "port0";
|
||||
linux,pci-domain = <0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "pcie_irq";
|
||||
clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
|
||||
<&pericfg CLK_PERI_PCIE0>;
|
||||
clock-names = "sys_ck0", "ahb_ck0";
|
||||
phys = <&u3port0 PHY_TYPE_PCIE>;
|
||||
phy-names = "pcie-phy0";
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
|
||||
status = "disabled";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
|
||||
<0 0 0 2 &pcie_intc0 1>,
|
||||
<0 0 0 3 &pcie_intc0 2>,
|
||||
<0 0 0 4 &pcie_intc0 3>;
|
||||
pcie_intc0: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
Examples for MT7622:
|
||||
|
||||
pcie0: pcie@1a143000 {
|
||||
compatible = "mediatek,mt7622-pcie";
|
||||
device_type = "pci";
|
||||
reg = <0 0x1a143000 0 0x1000>;
|
||||
reg-names = "port0";
|
||||
linux,pci-domain = <0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-names = "pcie_irq";
|
||||
clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
|
||||
<&pciesys CLK_PCIE_P0_AHB_EN>,
|
||||
<&pciesys CLK_PCIE_P0_AUX_EN>,
|
||||
<&pciesys CLK_PCIE_P0_AXI_EN>,
|
||||
<&pciesys CLK_PCIE_P0_OBFF_EN>,
|
||||
<&pciesys CLK_PCIE_P0_PIPE_EN>;
|
||||
clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
|
||||
"axi_ck0", "obff_ck0", "pipe_ck0";
|
||||
|
||||
power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
|
||||
status = "disabled";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
|
||||
<0 0 0 2 &pcie_intc0 1>,
|
||||
<0 0 0 3 &pcie_intc0 2>,
|
||||
<0 0 0 4 &pcie_intc0 3>;
|
||||
pcie_intc0: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1: pcie@1a145000 {
|
||||
compatible = "mediatek,mt7622-pcie";
|
||||
device_type = "pci";
|
||||
reg = <0 0x1a145000 0 0x1000>;
|
||||
reg-names = "port1";
|
||||
linux,pci-domain = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-names = "pcie_irq";
|
||||
clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
|
||||
/* designer has connect RC1 with p0_ahb clock */
|
||||
<&pciesys CLK_PCIE_P0_AHB_EN>,
|
||||
<&pciesys CLK_PCIE_P1_AUX_EN>,
|
||||
<&pciesys CLK_PCIE_P1_AXI_EN>,
|
||||
<&pciesys CLK_PCIE_P1_OBFF_EN>,
|
||||
<&pciesys CLK_PCIE_P1_PIPE_EN>;
|
||||
clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
|
||||
"axi_ck1", "obff_ck1", "pipe_ck1";
|
||||
|
||||
power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
|
||||
status = "disabled";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
|
||||
<0 0 0 2 &pcie_intc1 1>,
|
||||
<0 0 0 3 &pcie_intc1 2>,
|
||||
<0 0 0 4 &pcie_intc1 3>;
|
||||
pcie_intc1: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
140
bindings/pci/microchip,pcie-host.yaml
Normal file
140
bindings/pci/microchip,pcie-host.yaml
Normal file
@@ -0,0 +1,140 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Microchip PCIe Root Port Bridge Controller
|
||||
|
||||
maintainers:
|
||||
- Daire McNamara <daire.mcnamara@microchip.com>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-bus.yaml#
|
||||
- $ref: /schemas/interrupt-controller/msi-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: microchip,pcie-host-1.0 # PolarFire
|
||||
|
||||
reg:
|
||||
maxItems: 2
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: cfg
|
||||
- const: apb
|
||||
|
||||
clocks:
|
||||
description:
|
||||
Fabric Interface Controllers, FICs, are the interface between the FPGA
|
||||
fabric and the core complex on PolarFire SoC. The FICs require two clocks,
|
||||
one from each side of the interface. The "FIC clocks" described by this
|
||||
property are on the core complex side & communication through a FIC is not
|
||||
possible unless it's corresponding clock is enabled. A clock must be
|
||||
enabled for each of the interfaces the root port is connected through.
|
||||
This could in theory be all 4 interfaces, one interface or any combination
|
||||
in between.
|
||||
minItems: 1
|
||||
items:
|
||||
- description: FIC0's clock
|
||||
- description: FIC1's clock
|
||||
- description: FIC2's clock
|
||||
- description: FIC3's clock
|
||||
|
||||
clock-names:
|
||||
description:
|
||||
As any FIC connection combination is possible, the names should match the
|
||||
order in the clocks property and take the form "ficN" where N is a number
|
||||
0-3
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
items:
|
||||
pattern: '^fic[0-3]$'
|
||||
|
||||
interrupts:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: PCIe host controller
|
||||
- description: builtin MSI controller
|
||||
|
||||
interrupt-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: pcie
|
||||
- const: msi
|
||||
|
||||
ranges:
|
||||
maxItems: 1
|
||||
|
||||
dma-ranges:
|
||||
minItems: 1
|
||||
maxItems: 6
|
||||
|
||||
msi-controller:
|
||||
description: Identifies the node as an MSI controller.
|
||||
|
||||
msi-parent:
|
||||
description: MSI controller the device is capable of using.
|
||||
|
||||
interrupt-controller:
|
||||
type: object
|
||||
properties:
|
||||
'#address-cells':
|
||||
const: 0
|
||||
|
||||
'#interrupt-cells':
|
||||
const: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
required:
|
||||
- '#address-cells'
|
||||
- '#interrupt-cells'
|
||||
- interrupt-controller
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- reg
|
||||
- reg-names
|
||||
- "#interrupt-cells"
|
||||
- interrupts
|
||||
- interrupt-map-mask
|
||||
- interrupt-map
|
||||
- msi-controller
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
pcie0: pcie@2030000000 {
|
||||
compatible = "microchip,pcie-host-1.0";
|
||||
reg = <0x0 0x70000000 0x0 0x08000000>,
|
||||
<0x0 0x43000000 0x0 0x00010000>;
|
||||
reg-names = "cfg", "apb";
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupts = <119>;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
|
||||
<0 0 0 2 &pcie_intc0 1>,
|
||||
<0 0 0 3 &pcie_intc0 2>,
|
||||
<0 0 0 4 &pcie_intc0 3>;
|
||||
interrupt-parent = <&plic0>;
|
||||
msi-parent = <&pcie0>;
|
||||
msi-controller;
|
||||
bus-range = <0x00 0x7f>;
|
||||
ranges = <0x03000000 0x0 0x78000000 0x0 0x78000000 0x0 0x04000000>;
|
||||
pcie_intc0: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
};
|
||||
72
bindings/pci/mobiveil-pcie.txt
Normal file
72
bindings/pci/mobiveil-pcie.txt
Normal file
@@ -0,0 +1,72 @@
|
||||
* Mobiveil AXI PCIe Root Port Bridge DT description
|
||||
|
||||
Mobiveil's GPEX 4.0 is a PCIe Gen4 root port bridge IP. This configurable IP
|
||||
has up to 8 outbound and inbound windows for the address translation.
|
||||
|
||||
Required properties:
|
||||
- #address-cells: Address representation for root ports, set to <3>
|
||||
- #size-cells: Size representation for root ports, set to <2>
|
||||
- #interrupt-cells: specifies the number of cells needed to encode an
|
||||
interrupt source. The value must be 1.
|
||||
- compatible: Should contain "mbvl,gpex40-pcie"
|
||||
- reg: Should contain PCIe registers location and length
|
||||
Mandatory:
|
||||
"config_axi_slave": PCIe controller registers
|
||||
"csr_axi_slave" : Bridge config registers
|
||||
Optional:
|
||||
"gpio_slave" : GPIO registers to control slot power
|
||||
"apb_csr" : MSI registers
|
||||
|
||||
- device_type: must be "pci"
|
||||
- apio-wins : number of requested apio outbound windows
|
||||
default 2 outbound windows are configured -
|
||||
1. Config window
|
||||
2. Memory window
|
||||
- ppio-wins : number of requested ppio inbound windows
|
||||
default 1 inbound memory window is configured.
|
||||
- bus-range: PCI bus numbers covered
|
||||
- interrupt-controller: identifies the node as an interrupt controller
|
||||
- #interrupt-cells: specifies the number of cells needed to encode an
|
||||
interrupt source. The value must be 1.
|
||||
- interrupts: The interrupt line of the PCIe controller
|
||||
last cell of this field is set to 4 to
|
||||
denote it as IRQ_TYPE_LEVEL_HIGH type interrupt.
|
||||
- interrupt-map-mask,
|
||||
interrupt-map: standard PCI properties to define the mapping of the
|
||||
PCI interface to interrupt numbers.
|
||||
- ranges: ranges for the PCI memory regions (I/O space region is not
|
||||
supported by hardware)
|
||||
Please refer to the standard PCI bus binding document for a more
|
||||
detailed explanation
|
||||
|
||||
|
||||
Example:
|
||||
++++++++
|
||||
pcie0: pcie@a0000000 {
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
compatible = "mbvl,gpex40-pcie";
|
||||
reg = <0xa0000000 0x00001000>,
|
||||
<0xb0000000 0x00010000>,
|
||||
<0xff000000 0x00200000>,
|
||||
<0xb0010000 0x00001000>;
|
||||
reg-names = "config_axi_slave",
|
||||
"csr_axi_slave",
|
||||
"gpio_slave",
|
||||
"apb_csr";
|
||||
device_type = "pci";
|
||||
apio-wins = <2>;
|
||||
ppio-wins = <1>;
|
||||
bus-range = <0x00000000 0x000000ff>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupts = < 0 89 4 >;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 0 &pci_express 0>,
|
||||
<0 0 0 1 &pci_express 1>,
|
||||
<0 0 0 2 &pci_express 2>,
|
||||
<0 0 0 3 &pci_express 3>;
|
||||
ranges = < 0x83000000 0 0x00000000 0xa8000000 0 0x8000000>;
|
||||
|
||||
};
|
||||
310
bindings/pci/mvebu-pci.txt
Normal file
310
bindings/pci/mvebu-pci.txt
Normal file
@@ -0,0 +1,310 @@
|
||||
* Marvell EBU PCIe interfaces
|
||||
|
||||
Mandatory properties:
|
||||
|
||||
- compatible: one of the following values:
|
||||
marvell,armada-370-pcie
|
||||
marvell,armada-xp-pcie
|
||||
marvell,dove-pcie
|
||||
marvell,kirkwood-pcie
|
||||
- #address-cells, set to <3>
|
||||
- #size-cells, set to <2>
|
||||
- #interrupt-cells, set to <1>
|
||||
- bus-range: PCI bus numbers covered
|
||||
- device_type, set to "pci"
|
||||
- ranges: ranges describing the MMIO registers to control the PCIe
|
||||
interfaces, and ranges describing the MBus windows needed to access
|
||||
the memory and I/O regions of each PCIe interface.
|
||||
- msi-parent: Link to the hardware entity that serves as the Message
|
||||
Signaled Interrupt controller for this PCI controller.
|
||||
|
||||
The ranges describing the MMIO registers have the following layout:
|
||||
|
||||
0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
|
||||
|
||||
where:
|
||||
|
||||
* r is a 32-bits value that gives the offset of the MMIO
|
||||
registers of this PCIe interface, from the base of the internal
|
||||
registers.
|
||||
|
||||
* s is a 32-bits value that give the size of this MMIO
|
||||
registers area. This range entry translates the '0x82000000 0 r' PCI
|
||||
address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
|
||||
of the internal register window (as identified by MBUS_ID(0xf0,
|
||||
0x01)).
|
||||
|
||||
The ranges describing the MBus windows have the following layout:
|
||||
|
||||
0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
|
||||
|
||||
where:
|
||||
|
||||
* t is the type of the MBus window (as defined by the standard PCI DT
|
||||
bindings), 1 for I/O and 2 for memory.
|
||||
|
||||
* s is the PCI slot that corresponds to this PCIe interface
|
||||
|
||||
* w is the 'target ID' value for the MBus window
|
||||
|
||||
* a the 'attribute' value for the MBus window.
|
||||
|
||||
Since the location and size of the different MBus windows is not fixed in
|
||||
hardware, and only determined in runtime, those ranges cover the full first
|
||||
4 GB of the physical address space, and do not translate into a valid CPU
|
||||
address.
|
||||
|
||||
In addition, the device tree node must have sub-nodes describing each
|
||||
PCIe interface, having the following mandatory properties:
|
||||
|
||||
- reg: used only for interrupt mapping, so only the first four bytes
|
||||
are used to refer to the correct bus number and device number.
|
||||
- assigned-addresses: reference to the MMIO registers used to control
|
||||
this PCIe interface.
|
||||
- clocks: the clock associated to this PCIe interface
|
||||
- marvell,pcie-port: the physical PCIe port number
|
||||
- status: either "disabled" or "okay"
|
||||
- device_type, set to "pci"
|
||||
- #address-cells, set to <3>
|
||||
- #size-cells, set to <2>
|
||||
- #interrupt-cells, set to <1>
|
||||
- ranges, translating the MBus windows ranges of the parent node into
|
||||
standard PCI addresses.
|
||||
- interrupt-map-mask and interrupt-map, standard PCI properties to
|
||||
define the mapping of the PCIe interface to interrupt numbers.
|
||||
|
||||
and the following optional properties:
|
||||
- marvell,pcie-lane: the physical PCIe lane number, for ports having
|
||||
multiple lanes. If this property is not found, we assume that the
|
||||
value is 0.
|
||||
- num-lanes: number of SerDes PCIe lanes for this link (1 or 4)
|
||||
- reset-gpios: optional GPIO to PERST#
|
||||
- reset-delay-us: delay in us to wait after reset de-assertion, if not
|
||||
specified will default to 100ms, as required by the PCIe specification.
|
||||
- interrupt-names: list of interrupt names, supported are:
|
||||
- "intx" - interrupt line triggered by one of the legacy interrupt
|
||||
- interrupts or interrupts-extended: List of the interrupt sources which
|
||||
corresponding to the "interrupt-names". If non-empty then also additional
|
||||
'interrupt-controller' subnode must be defined.
|
||||
|
||||
Example:
|
||||
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-xp-pcie";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
msi-parent = <&mpic>;
|
||||
|
||||
ranges =
|
||||
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
|
||||
0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
|
||||
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
|
||||
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
|
||||
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
|
||||
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
|
||||
0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
|
||||
0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
|
||||
0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
|
||||
0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
|
||||
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
|
||||
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
|
||||
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
|
||||
0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
|
||||
0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
|
||||
0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
|
||||
0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
|
||||
|
||||
0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
|
||||
0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
|
||||
0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
|
||||
0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
|
||||
0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
|
||||
0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
|
||||
0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
|
||||
0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
|
||||
|
||||
0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
|
||||
0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
|
||||
|
||||
0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
|
||||
0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 58>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
num-lanes = <1>;
|
||||
/* low-active PERST# reset on GPIO 25 */
|
||||
reset-gpios = <&gpio0 25 1>;
|
||||
/* wait 20ms for device settle after reset deassertion */
|
||||
reset-delay-us = <20000>;
|
||||
clocks = <&gateclk 5>;
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 59>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <1>;
|
||||
num-lanes = <1>;
|
||||
clocks = <&gateclk 6>;
|
||||
};
|
||||
|
||||
pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x3 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 60>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <2>;
|
||||
num-lanes = <1>;
|
||||
clocks = <&gateclk 7>;
|
||||
};
|
||||
|
||||
pcie@4,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
|
||||
reg = <0x2000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x4 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 61>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <3>;
|
||||
num-lanes = <1>;
|
||||
clocks = <&gateclk 8>;
|
||||
};
|
||||
|
||||
pcie@5,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
|
||||
reg = <0x2800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x5 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 62>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <0>;
|
||||
num-lanes = <1>;
|
||||
clocks = <&gateclk 9>;
|
||||
};
|
||||
|
||||
pcie@6,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
|
||||
reg = <0x3000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x6 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 63>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <1>;
|
||||
num-lanes = <1>;
|
||||
clocks = <&gateclk 10>;
|
||||
};
|
||||
|
||||
pcie@7,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
|
||||
reg = <0x3800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x7 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 64>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <2>;
|
||||
num-lanes = <1>;
|
||||
clocks = <&gateclk 11>;
|
||||
};
|
||||
|
||||
pcie@8,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
|
||||
reg = <0x4000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x8 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 65>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <3>;
|
||||
num-lanes = <1>;
|
||||
clocks = <&gateclk 12>;
|
||||
};
|
||||
|
||||
pcie@9,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
|
||||
reg = <0x4800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x9 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 99>;
|
||||
marvell,pcie-port = <2>;
|
||||
marvell,pcie-lane = <0>;
|
||||
num-lanes = <1>;
|
||||
clocks = <&gateclk 26>;
|
||||
};
|
||||
|
||||
pcie@a,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
|
||||
reg = <0x5000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
|
||||
0x81000000 0 0 0x81000000 0xa 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 103>;
|
||||
marvell,pcie-port = <3>;
|
||||
marvell,pcie-lane = <0>;
|
||||
num-lanes = <1>;
|
||||
clocks = <&gateclk 27>;
|
||||
};
|
||||
};
|
||||
319
bindings/pci/nvidia,tegra194-pcie-ep.yaml
Normal file
319
bindings/pci/nvidia,tegra194-pcie-ep.yaml
Normal file
@@ -0,0 +1,319 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra194 (and later) PCIe Endpoint controller (Synopsys DesignWare Core based)
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
- Vidya Sagar <vidyas@nvidia.com>
|
||||
|
||||
description: |
|
||||
This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
|
||||
inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some
|
||||
of the controller instances are dual mode; they can work either in Root
|
||||
Port mode or Endpoint mode but one at a time.
|
||||
|
||||
On Tegra194, controllers C0, C4 and C5 support Endpoint mode.
|
||||
On Tegra234, controllers C5, C6, C7 and C10 support Endpoint mode.
|
||||
|
||||
Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
|
||||
operate in the Endpoint mode because of the way the platform is designed.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra194-pcie-ep
|
||||
- nvidia,tegra234-pcie-ep
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: controller's application logic registers
|
||||
- description: iATU and DMA registers. This is where the iATU (internal
|
||||
Address Translation Unit) registers of the PCIe core are made
|
||||
available for software access.
|
||||
- description: aperture where the Root Port's own configuration
|
||||
registers are available.
|
||||
- description: aperture used to map the remote Root Complex address space
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: appl
|
||||
- const: atu_dma
|
||||
- const: dbi
|
||||
- const: addr_space
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: controller interrupt
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: intr
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: module clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: core
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: APB bus interface reset
|
||||
- description: module reset
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: apb
|
||||
- const: core
|
||||
|
||||
reset-gpios:
|
||||
description: Must contain a phandle to a GPIO controller followed by GPIO
|
||||
that is being used as PERST input signal. Please refer to pci.txt.
|
||||
|
||||
phys:
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
|
||||
phy-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: p2u-0
|
||||
- const: p2u-1
|
||||
- const: p2u-2
|
||||
- const: p2u-3
|
||||
- const: p2u-4
|
||||
- const: p2u-5
|
||||
- const: p2u-6
|
||||
- const: p2u-7
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
description: |
|
||||
A phandle to the node that controls power to the respective PCIe
|
||||
controller and a specifier name for the PCIe controller.
|
||||
|
||||
Tegra194 specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h"
|
||||
Tegra234 specifiers are defined in "include/dt-bindings/power/tegra234-powergate.h"
|
||||
|
||||
interconnects:
|
||||
items:
|
||||
- description: memory read client
|
||||
- description: memory write client
|
||||
|
||||
interconnect-names:
|
||||
items:
|
||||
- const: dma-mem # read
|
||||
- const: write
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
nvidia,bpmp:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
description: |
|
||||
Must contain a pair of phandles to BPMP controller node followed by
|
||||
controller ID. Following are the controller IDs for each controller:
|
||||
|
||||
Tegra194
|
||||
|
||||
0: C0
|
||||
1: C1
|
||||
2: C2
|
||||
3: C3
|
||||
4: C4
|
||||
5: C5
|
||||
|
||||
Tegra234
|
||||
|
||||
0 : C0
|
||||
1 : C1
|
||||
2 : C2
|
||||
3 : C3
|
||||
4 : C4
|
||||
5 : C5
|
||||
6 : C6
|
||||
7 : C7
|
||||
8 : C8
|
||||
9 : C9
|
||||
10: C10
|
||||
|
||||
items:
|
||||
- items:
|
||||
- description: phandle to BPMP controller node
|
||||
- description: PCIe controller ID
|
||||
maximum: 10
|
||||
|
||||
nvidia,aspm-cmrt-us:
|
||||
description: Common Mode Restore Time for proper operation of ASPM to be
|
||||
specified in microseconds
|
||||
|
||||
nvidia,aspm-pwr-on-t-us:
|
||||
description: Power On time for proper operation of ASPM to be specified in
|
||||
microseconds
|
||||
|
||||
nvidia,aspm-l0s-entrance-latency-us:
|
||||
description: ASPM L0s entrance latency to be specified in microseconds
|
||||
|
||||
vddio-pex-ctl-supply:
|
||||
description: A phandle to the regulator supply for PCIe side band signals
|
||||
|
||||
nvidia,refclk-select-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO used to enable REFCLK to controller from the host
|
||||
|
||||
nvidia,enable-ext-refclk:
|
||||
description: |
|
||||
This boolean property needs to be present if the controller is configured
|
||||
to receive Reference Clock from the host.
|
||||
NOTE: This is applicable only for Tegra234.
|
||||
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
nvidia,enable-srns:
|
||||
description: |
|
||||
This boolean property needs to be present if the controller is
|
||||
configured to operate in SRNS (Separate Reference Clocks with No
|
||||
Spread-Spectrum Clocking). NOTE: This is applicable only for
|
||||
Tegra234.
|
||||
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- reset-names
|
||||
- power-domains
|
||||
- reset-gpios
|
||||
- vddio-pex-ctl-supply
|
||||
- num-lanes
|
||||
- phys
|
||||
- phy-names
|
||||
- nvidia,bpmp
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra194-clock.h>
|
||||
#include <dt-bindings/gpio/tegra194-gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/tegra194-powergate.h>
|
||||
#include <dt-bindings/reset/tegra194-reset.h>
|
||||
|
||||
bus@0 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x0 0x0 0x0 0x8 0x0>;
|
||||
|
||||
pcie-ep@141a0000 {
|
||||
compatible = "nvidia,tegra194-pcie-ep";
|
||||
reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
|
||||
<0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
|
||||
<0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
|
||||
<0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
|
||||
reg-names = "appl", "atu_dma", "dbi", "addr_space";
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
|
||||
interrupt-names = "intr";
|
||||
|
||||
clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
|
||||
clock-names = "core";
|
||||
|
||||
resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
|
||||
<&bpmp TEGRA194_RESET_PEX1_CORE_5>;
|
||||
reset-names = "apb", "core";
|
||||
|
||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&clkreq_c5_bi_dir_state>;
|
||||
|
||||
nvidia,bpmp = <&bpmp 5>;
|
||||
|
||||
nvidia,aspm-cmrt-us = <60>;
|
||||
nvidia,aspm-pwr-on-t-us = <20>;
|
||||
nvidia,aspm-l0s-entrance-latency-us = <3>;
|
||||
|
||||
vddio-pex-ctl-supply = <&vdd_1v8ao>;
|
||||
|
||||
reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>;
|
||||
|
||||
nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
|
||||
GPIO_ACTIVE_HIGH>;
|
||||
|
||||
num-lanes = <8>;
|
||||
|
||||
phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
|
||||
<&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
|
||||
<&p2u_nvhs_6>, <&p2u_nvhs_7>;
|
||||
|
||||
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
|
||||
"p2u-5", "p2u-6", "p2u-7";
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra234-clock.h>
|
||||
#include <dt-bindings/gpio/tegra234-gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/tegra234-powergate.h>
|
||||
#include <dt-bindings/reset/tegra234-reset.h>
|
||||
|
||||
bus@0 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x0 0x0 0x0 0x8 0x0>;
|
||||
|
||||
pcie-ep@141a0000 {
|
||||
compatible = "nvidia,tegra234-pcie-ep";
|
||||
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
|
||||
reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
|
||||
<0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
|
||||
<0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
|
||||
<0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */
|
||||
reg-names = "appl", "atu_dma", "dbi", "addr_space";
|
||||
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
|
||||
interrupt-names = "intr";
|
||||
|
||||
clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
|
||||
clock-names = "core";
|
||||
|
||||
resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
|
||||
<&bpmp TEGRA234_RESET_PEX1_CORE_5>;
|
||||
reset-names = "apb", "core";
|
||||
|
||||
nvidia,bpmp = <&bpmp 5>;
|
||||
|
||||
nvidia,enable-ext-refclk;
|
||||
nvidia,aspm-cmrt-us = <60>;
|
||||
nvidia,aspm-pwr-on-t-us = <20>;
|
||||
nvidia,aspm-l0s-entrance-latency-us = <3>;
|
||||
|
||||
vddio-pex-ctl-supply = <&p3701_vdd_1v8_ls>;
|
||||
|
||||
reset-gpios = <&gpio TEGRA234_MAIN_GPIO(AF, 1) GPIO_ACTIVE_LOW>;
|
||||
|
||||
nvidia,refclk-select-gpios = <&gpio_aon
|
||||
TEGRA234_AON_GPIO(AA, 4)
|
||||
GPIO_ACTIVE_HIGH>;
|
||||
|
||||
num-lanes = <8>;
|
||||
|
||||
phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
|
||||
<&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
|
||||
<&p2u_nvhs_6>, <&p2u_nvhs_7>;
|
||||
|
||||
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
|
||||
"p2u-5", "p2u-6", "p2u-7";
|
||||
};
|
||||
};
|
||||
380
bindings/pci/nvidia,tegra194-pcie.yaml
Normal file
380
bindings/pci/nvidia,tegra194-pcie.yaml
Normal file
@@ -0,0 +1,380 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based)
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
- Vidya Sagar <vidyas@nvidia.com>
|
||||
|
||||
description: |
|
||||
This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
|
||||
inherits all the common properties defined in snps,dw-pcie.yaml. Some of
|
||||
the controller instances are dual mode where in they can work either in
|
||||
Root Port mode or Endpoint mode but one at a time.
|
||||
|
||||
See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
|
||||
tree bindings.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra194-pcie
|
||||
- nvidia,tegra234-pcie
|
||||
|
||||
reg:
|
||||
minItems: 4
|
||||
items:
|
||||
- description: controller's application logic registers
|
||||
- description: configuration registers
|
||||
- description: iATU and DMA registers. This is where the iATU (internal
|
||||
Address Translation Unit) registers of the PCIe core are made
|
||||
available for software access.
|
||||
- description: aperture where the Root Port's own configuration
|
||||
registers are available.
|
||||
- description: aperture to access the configuration space through ECAM.
|
||||
|
||||
reg-names:
|
||||
minItems: 4
|
||||
items:
|
||||
- const: appl
|
||||
- const: config
|
||||
- const: atu_dma
|
||||
- const: dbi
|
||||
- const: ecam
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: controller interrupt
|
||||
- description: MSI interrupt
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: intr
|
||||
- const: msi
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: module clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: core
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: APB bus interface reset
|
||||
- description: module reset
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: apb
|
||||
- const: core
|
||||
|
||||
phys:
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
|
||||
phy-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: p2u-0
|
||||
- const: p2u-1
|
||||
- const: p2u-2
|
||||
- const: p2u-3
|
||||
- const: p2u-4
|
||||
- const: p2u-5
|
||||
- const: p2u-6
|
||||
- const: p2u-7
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
description: |
|
||||
A phandle to the node that controls power to the respective PCIe
|
||||
controller and a specifier name for the PCIe controller.
|
||||
|
||||
Tegra194 specifiers defined in "include/dt-bindings/power/tegra194-powergate.h"
|
||||
Tegra234 specifiers defined in "include/dt-bindings/power/tegra234-powergate.h"
|
||||
|
||||
interconnects:
|
||||
items:
|
||||
- description: memory read client
|
||||
- description: memory write client
|
||||
|
||||
interconnect-names:
|
||||
items:
|
||||
- const: dma-mem # read
|
||||
- const: write
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
nvidia,bpmp:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
description: |
|
||||
Must contain a pair of phandles to BPMP controller node followed by
|
||||
controller ID. Following are the controller IDs for each controller:
|
||||
|
||||
Tegra194
|
||||
|
||||
0: C0
|
||||
1: C1
|
||||
2: C2
|
||||
3: C3
|
||||
4: C4
|
||||
5: C5
|
||||
|
||||
Tegra234
|
||||
|
||||
0 : C0
|
||||
1 : C1
|
||||
2 : C2
|
||||
3 : C3
|
||||
4 : C4
|
||||
5 : C5
|
||||
6 : C6
|
||||
7 : C7
|
||||
8 : C8
|
||||
9 : C9
|
||||
10: C10
|
||||
|
||||
items:
|
||||
- items:
|
||||
- description: phandle to BPMP controller node
|
||||
- description: PCIe controller ID
|
||||
maximum: 10
|
||||
|
||||
nvidia,update-fc-fixup:
|
||||
description: |
|
||||
This is a boolean property and needs to be present to improve performance
|
||||
when a platform is designed in such a way that it satisfies at least one
|
||||
of the following conditions thereby enabling Root Port to exchange
|
||||
optimum number of FC (Flow Control) credits with downstream devices:
|
||||
|
||||
NOTE: This is applicable only for Tegra194.
|
||||
|
||||
1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
|
||||
2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
|
||||
a) speed is Gen-2 and MPS is 256B
|
||||
b) speed is >= Gen-3 with any MPS
|
||||
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
nvidia,aspm-cmrt-us:
|
||||
description: Common Mode Restore Time for proper operation of ASPM to be
|
||||
specified in microseconds
|
||||
|
||||
nvidia,aspm-pwr-on-t-us:
|
||||
description: Power On time for proper operation of ASPM to be specified in
|
||||
microseconds
|
||||
|
||||
nvidia,aspm-l0s-entrance-latency-us:
|
||||
description: ASPM L0s entrance latency to be specified in microseconds
|
||||
|
||||
vddio-pex-ctl-supply:
|
||||
description: A phandle to the regulator supply for PCIe side band signals.
|
||||
|
||||
vpcie3v3-supply:
|
||||
description: A phandle to the regulator node that supplies 3.3V to the slot
|
||||
if the platform has one such slot, e.g., x16 slot owned by C5 controller
|
||||
in p2972-0000 platform.
|
||||
|
||||
vpcie12v-supply:
|
||||
description: A phandle to the regulator node that supplies 12V to the slot
|
||||
if the platform has one such slot, e.g., x16 slot owned by C5 controller
|
||||
in p2972-0000 platform.
|
||||
|
||||
nvidia,enable-srns:
|
||||
description: |
|
||||
This boolean property needs to be present if the controller is
|
||||
configured to operate in SRNS (Separate Reference Clocks with No
|
||||
Spread-Spectrum Clocking). NOTE: This is applicable only for
|
||||
Tegra234.
|
||||
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
nvidia,enable-ext-refclk:
|
||||
description: |
|
||||
This boolean property needs to be present if the controller is
|
||||
configured to use the reference clocking coming in from an external
|
||||
clock source instead of using the internal clock source.
|
||||
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/snps,dw-pcie.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- nvidia,tegra194-pcie
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 4
|
||||
reg-names:
|
||||
maxItems: 4
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- nvidia,tegra234-pcie
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 5
|
||||
reg-names:
|
||||
minItems: 5
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- interrupt-map
|
||||
- interrupt-map-mask
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- reset-names
|
||||
- power-domains
|
||||
- vddio-pex-ctl-supply
|
||||
- num-lanes
|
||||
- phys
|
||||
- phy-names
|
||||
- nvidia,bpmp
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra194-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/tegra194-powergate.h>
|
||||
#include <dt-bindings/reset/tegra194-reset.h>
|
||||
|
||||
bus@0 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x0 0x0 0x0 0x8 0x0>;
|
||||
|
||||
pcie@14180000 {
|
||||
compatible = "nvidia,tegra194-pcie";
|
||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
|
||||
reg = <0x0 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
|
||||
<0x0 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
|
||||
<0x0 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
|
||||
<0x0 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
num-lanes = <8>;
|
||||
linux,pci-domain = <0>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
|
||||
|
||||
clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
|
||||
clock-names = "core";
|
||||
|
||||
resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
|
||||
<&bpmp TEGRA194_RESET_PEX0_CORE_0>;
|
||||
reset-names = "apb", "core";
|
||||
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
|
||||
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
|
||||
interrupt-names = "intr", "msi";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
nvidia,bpmp = <&bpmp 0>;
|
||||
|
||||
supports-clkreq;
|
||||
nvidia,aspm-cmrt-us = <60>;
|
||||
nvidia,aspm-pwr-on-t-us = <20>;
|
||||
nvidia,aspm-l0s-entrance-latency-us = <3>;
|
||||
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>, /* downstream I/O */
|
||||
<0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01e00000>, /* non-prefetch memory */
|
||||
<0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory */
|
||||
|
||||
vddio-pex-ctl-supply = <&vdd_1v8ao>;
|
||||
vpcie3v3-supply = <&vdd_3v3_pcie>;
|
||||
vpcie12v-supply = <&vdd_12v_pcie>;
|
||||
|
||||
phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,
|
||||
<&p2u_hsio_5>;
|
||||
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra234-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/tegra234-powergate.h>
|
||||
#include <dt-bindings/reset/tegra234-reset.h>
|
||||
|
||||
bus@0 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x0 0x0 0x0 0x8 0x0>;
|
||||
|
||||
pcie@14160000 {
|
||||
compatible = "nvidia,tegra234-pcie";
|
||||
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
|
||||
reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
|
||||
<0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
|
||||
<0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
|
||||
<0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */
|
||||
<0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
num-lanes = <4>;
|
||||
num-viewport = <8>;
|
||||
linux,pci-domain = <4>;
|
||||
|
||||
clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>;
|
||||
clock-names = "core";
|
||||
|
||||
resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>,
|
||||
<&bpmp TEGRA234_RESET_PEX0_CORE_4>;
|
||||
reset-names = "apb", "core";
|
||||
|
||||
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
|
||||
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
|
||||
interrupt-names = "intr", "msi";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
nvidia,bpmp = <&bpmp 4>;
|
||||
|
||||
nvidia,aspm-cmrt-us = <60>;
|
||||
nvidia,aspm-pwr-on-t-us = <20>;
|
||||
nvidia,aspm-l0s-entrance-latency-us = <3>;
|
||||
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable */
|
||||
<0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable */
|
||||
<0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O */
|
||||
|
||||
vddio-pex-ctl-supply = <&p3701_vdd_AO_1v8>;
|
||||
|
||||
phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
|
||||
<&p2u_hsio_7>;
|
||||
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
|
||||
};
|
||||
};
|
||||
670
bindings/pci/nvidia,tegra20-pcie.txt
Normal file
670
bindings/pci/nvidia,tegra20-pcie.txt
Normal file
@@ -0,0 +1,670 @@
|
||||
NVIDIA Tegra PCIe controller
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be:
|
||||
- "nvidia,tegra20-pcie": for Tegra20
|
||||
- "nvidia,tegra30-pcie": for Tegra30
|
||||
- "nvidia,tegra124-pcie": for Tegra124 and Tegra132
|
||||
- "nvidia,tegra210-pcie": for Tegra210
|
||||
- "nvidia,tegra186-pcie": for Tegra186
|
||||
- power-domains: To ungate power partition by BPMP powergate driver. Must
|
||||
contain BPMP phandle and PCIe power partition ID. This is required only
|
||||
for Tegra186.
|
||||
- device_type: Must be "pci"
|
||||
- reg: A list of physical base address and length for each set of controller
|
||||
registers. Must contain an entry for each entry in the reg-names property.
|
||||
- reg-names: Must include the following entries:
|
||||
"pads": PADS registers
|
||||
"afi": AFI registers
|
||||
"cs": configuration space region
|
||||
- interrupts: A list of interrupt outputs of the controller. Must contain an
|
||||
entry for each entry in the interrupt-names property.
|
||||
- interrupt-names: Must include the following entries:
|
||||
"intr": The Tegra interrupt that is asserted for controller interrupts
|
||||
"msi": The Tegra interrupt that is asserted when an MSI is received
|
||||
- bus-range: Range of bus numbers associated with this controller
|
||||
- #address-cells: Address representation for root ports (must be 3)
|
||||
- cell 0 specifies the bus and device numbers of the root port:
|
||||
[23:16]: bus number
|
||||
[15:11]: device number
|
||||
- cell 1 denotes the upper 32 address bits and should be 0
|
||||
- cell 2 contains the lower 32 address bits and is used to translate to the
|
||||
CPU address space
|
||||
- #size-cells: Size representation for root ports (must be 2)
|
||||
- ranges: Describes the translation of addresses for root ports and standard
|
||||
PCI regions. The entries must be 6 cells each, where the first three cells
|
||||
correspond to the address as described for the #address-cells property
|
||||
above, the fourth cell is the physical CPU address to translate to and the
|
||||
fifth and six cells are as described for the #size-cells property above.
|
||||
- The first two entries are expected to translate the addresses for the root
|
||||
port registers, which are referenced by the assigned-addresses property of
|
||||
the root port nodes (see below).
|
||||
- The remaining entries setup the mapping for the standard I/O, memory and
|
||||
prefetchable PCI regions. The first cell determines the type of region
|
||||
that is setup:
|
||||
- 0x81000000: I/O memory region
|
||||
- 0x82000000: non-prefetchable memory region
|
||||
- 0xc2000000: prefetchable memory region
|
||||
Please refer to the standard PCI bus binding document for a more detailed
|
||||
explanation.
|
||||
- #interrupt-cells: Size representation for interrupts (must be 1)
|
||||
- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
|
||||
Please refer to the standard PCI bus binding document for a more detailed
|
||||
explanation.
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: Must include the following entries:
|
||||
- pex
|
||||
- afi
|
||||
- pll_e
|
||||
- cml (not required for Tegra20)
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- pex
|
||||
- afi
|
||||
- pcie_x
|
||||
|
||||
Optional properties:
|
||||
- pinctrl-names: A list of pinctrl state names. Must contain the following
|
||||
entries:
|
||||
- "default": active state, puts PCIe I/O out of deep power down state
|
||||
- "idle": puts PCIe I/O into deep power down state
|
||||
- pinctrl-0: phandle for the default/active state of pin configurations.
|
||||
- pinctrl-1: phandle for the idle state of pin configurations.
|
||||
|
||||
Required properties on Tegra124 and later (deprecated):
|
||||
- phys: Must contain an entry for each entry in phy-names.
|
||||
- phy-names: Must include the following entries:
|
||||
- pcie
|
||||
|
||||
These properties are deprecated in favour of per-lane PHYs define in each of
|
||||
the root ports (see below).
|
||||
|
||||
Power supplies for Tegra20:
|
||||
- avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
|
||||
- vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
|
||||
- avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
|
||||
supply 1.05 V.
|
||||
- avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must
|
||||
supply 1.05 V.
|
||||
- vddio-pex-clk-supply: Power supply for PCIe clock. Must supply 3.3 V.
|
||||
|
||||
Power supplies for Tegra30:
|
||||
- Required:
|
||||
- avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
|
||||
supply 1.05 V.
|
||||
- avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must
|
||||
supply 1.05 V.
|
||||
- vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
|
||||
supply 1.8 V.
|
||||
- hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
|
||||
Must supply 3.3 V.
|
||||
- Optional:
|
||||
- If lanes 0 to 3 are used:
|
||||
- avdd-pexa-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
|
||||
- vdd-pexa-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
|
||||
- If lanes 4 or 5 are used:
|
||||
- avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
|
||||
- vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
|
||||
|
||||
Power supplies for Tegra124:
|
||||
- Required:
|
||||
- avddio-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
|
||||
- dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
|
||||
- hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
|
||||
Must supply 3.3 V.
|
||||
- vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
|
||||
supply 2.8-3.3 V.
|
||||
|
||||
Power supplies for Tegra210:
|
||||
- Required:
|
||||
- hvddio-pex-supply: High-voltage supply for PCIe I/O and PCIe output
|
||||
clocks. Must supply 1.8 V.
|
||||
- dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
|
||||
- vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
|
||||
supply 1.8 V.
|
||||
|
||||
Power supplies for Tegra186:
|
||||
- Required:
|
||||
- dvdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
|
||||
- hvdd-pex-pll-supply: High-voltage supply for PLLE (shared with USB3). Must
|
||||
supply 1.8 V.
|
||||
- hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
|
||||
Must supply 1.8 V.
|
||||
- vddio-pexctl-aud-supply: Power supply for PCIe side band signals. Must
|
||||
supply 1.8 V.
|
||||
|
||||
Root ports are defined as subnodes of the PCIe controller node.
|
||||
|
||||
Required properties:
|
||||
- device_type: Must be "pci"
|
||||
- assigned-addresses: Address and size of the port configuration registers
|
||||
- reg: PCI bus address of the root port
|
||||
- #address-cells: Must be 3
|
||||
- #size-cells: Must be 2
|
||||
- ranges: Sub-ranges distributed from the PCIe controller node. An empty
|
||||
property is sufficient.
|
||||
- nvidia,num-lanes: Number of lanes to use for this port. Valid combinations
|
||||
are:
|
||||
- Root port 0 uses 4 lanes, root port 1 is unused.
|
||||
- Both root ports use 2 lanes.
|
||||
|
||||
Required properties for Tegra124 and later:
|
||||
- phys: Must contain an phandle to a PHY for each entry in phy-names.
|
||||
- phy-names: Must include an entry for each active lane. Note that the number
|
||||
of entries does not have to (though usually will) be equal to the specified
|
||||
number of lanes in the nvidia,num-lanes property. Entries are of the form
|
||||
"pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
|
||||
|
||||
Examples:
|
||||
=========
|
||||
|
||||
Tegra20:
|
||||
--------
|
||||
|
||||
SoC DTSI:
|
||||
|
||||
pcie-controller@80003000 {
|
||||
compatible = "nvidia,tegra20-pcie";
|
||||
device_type = "pci";
|
||||
reg = <0x80003000 0x00000800 /* PADS registers */
|
||||
0x80003800 0x00000200 /* AFI registers */
|
||||
0x90000000 0x10000000>; /* configuration space */
|
||||
reg-names = "pads", "afi", "cs";
|
||||
interrupts = <0 98 0x04 /* controller interrupt */
|
||||
0 99 0x04>; /* MSI interrupt */
|
||||
interrupt-names = "intr", "msi";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
|
||||
0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
|
||||
0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0 0xa0000000 0xa0000000 0 0x10000000 /* non-prefetchable memory */
|
||||
0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */
|
||||
|
||||
clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 118>;
|
||||
clock-names = "pex", "afi", "pll_e";
|
||||
resets = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>;
|
||||
reset-names = "pex", "afi", "pcie_x";
|
||||
status = "disabled";
|
||||
|
||||
pci@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
|
||||
reg = <0x000800 0 0 0 0>;
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
ranges;
|
||||
|
||||
nvidia,num-lanes = <2>;
|
||||
};
|
||||
|
||||
pci@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
|
||||
reg = <0x001000 0 0 0 0>;
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
ranges;
|
||||
|
||||
nvidia,num-lanes = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
Board DTS:
|
||||
|
||||
pcie-controller@80003000 {
|
||||
status = "okay";
|
||||
|
||||
vdd-supply = <&pci_vdd_reg>;
|
||||
pex-clk-supply = <&pci_clk_reg>;
|
||||
|
||||
/* root port 00:01.0 */
|
||||
pci@1,0 {
|
||||
status = "okay";
|
||||
|
||||
/* bridge 01:00.0 (optional) */
|
||||
pci@0,0 {
|
||||
reg = <0x010000 0 0 0 0>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
device_type = "pci";
|
||||
|
||||
/* endpoint 02:00.0 */
|
||||
pci@0,0 {
|
||||
reg = <0x020000 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Note that devices on the PCI bus are dynamically discovered using PCI's bus
|
||||
enumeration and therefore don't need corresponding device nodes in DT. However
|
||||
if a device on the PCI bus provides a non-probeable bus such as I2C or SPI,
|
||||
device nodes need to be added in order to allow the bus' children to be
|
||||
instantiated at the proper location in the operating system's device tree (as
|
||||
illustrated by the optional nodes in the example above).
|
||||
|
||||
Tegra30:
|
||||
--------
|
||||
|
||||
SoC DTSI:
|
||||
|
||||
pcie-controller@3000 {
|
||||
compatible = "nvidia,tegra30-pcie";
|
||||
device_type = "pci";
|
||||
reg = <0x00003000 0x00000800 /* PADS registers */
|
||||
0x00003800 0x00000200 /* AFI registers */
|
||||
0x10000000 0x10000000>; /* configuration space */
|
||||
reg-names = "pads", "afi", "cs";
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
|
||||
GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
|
||||
interrupt-names = "intr", "msi";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
|
||||
0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
|
||||
0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
|
||||
0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
|
||||
0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
|
||||
|
||||
clocks = <&tegra_car TEGRA30_CLK_PCIE>,
|
||||
<&tegra_car TEGRA30_CLK_AFI>,
|
||||
<&tegra_car TEGRA30_CLK_PLL_E>,
|
||||
<&tegra_car TEGRA30_CLK_CML0>;
|
||||
clock-names = "pex", "afi", "pll_e", "cml";
|
||||
resets = <&tegra_car 70>,
|
||||
<&tegra_car 72>,
|
||||
<&tegra_car 74>;
|
||||
reset-names = "pex", "afi", "pcie_x";
|
||||
status = "disabled";
|
||||
|
||||
pci@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
|
||||
reg = <0x000800 0 0 0 0>;
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
nvidia,num-lanes = <2>;
|
||||
};
|
||||
|
||||
pci@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
|
||||
reg = <0x001000 0 0 0 0>;
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
nvidia,num-lanes = <2>;
|
||||
};
|
||||
|
||||
pci@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
|
||||
reg = <0x001800 0 0 0 0>;
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
nvidia,num-lanes = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
Board DTS:
|
||||
|
||||
pcie-controller@3000 {
|
||||
status = "okay";
|
||||
|
||||
avdd-pexa-supply = <&ldo1_reg>;
|
||||
vdd-pexa-supply = <&ldo1_reg>;
|
||||
avdd-pexb-supply = <&ldo1_reg>;
|
||||
vdd-pexb-supply = <&ldo1_reg>;
|
||||
avdd-pex-pll-supply = <&ldo1_reg>;
|
||||
avdd-plle-supply = <&ldo1_reg>;
|
||||
vddio-pex-ctl-supply = <&sys_3v3_reg>;
|
||||
hvdd-pex-supply = <&sys_3v3_pexs_reg>;
|
||||
|
||||
pci@1,0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pci@3,0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
Tegra124:
|
||||
---------
|
||||
|
||||
SoC DTSI:
|
||||
|
||||
pcie-controller@1003000 {
|
||||
compatible = "nvidia,tegra124-pcie";
|
||||
device_type = "pci";
|
||||
reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
|
||||
0x0 0x01003800 0x0 0x00000800 /* AFI registers */
|
||||
0x0 0x02000000 0x0 0x10000000>; /* configuration space */
|
||||
reg-names = "pads", "afi", "cs";
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
|
||||
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
|
||||
interrupt-names = "intr", "msi";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
|
||||
0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
|
||||
0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
|
||||
0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
|
||||
0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
|
||||
|
||||
clocks = <&tegra_car TEGRA124_CLK_PCIE>,
|
||||
<&tegra_car TEGRA124_CLK_AFI>,
|
||||
<&tegra_car TEGRA124_CLK_PLL_E>,
|
||||
<&tegra_car TEGRA124_CLK_CML0>;
|
||||
clock-names = "pex", "afi", "pll_e", "cml";
|
||||
resets = <&tegra_car 70>,
|
||||
<&tegra_car 72>,
|
||||
<&tegra_car 74>;
|
||||
reset-names = "pex", "afi", "pcie_x";
|
||||
status = "disabled";
|
||||
|
||||
pci@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
|
||||
reg = <0x000800 0 0 0 0>;
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
nvidia,num-lanes = <2>;
|
||||
};
|
||||
|
||||
pci@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
|
||||
reg = <0x001000 0 0 0 0>;
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
nvidia,num-lanes = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
Board DTS:
|
||||
|
||||
pcie-controller@1003000 {
|
||||
status = "okay";
|
||||
|
||||
avddio-pex-supply = <&vdd_1v05_run>;
|
||||
dvddio-pex-supply = <&vdd_1v05_run>;
|
||||
avdd-pex-pll-supply = <&vdd_1v05_run>;
|
||||
hvdd-pex-supply = <&vdd_3v3_lp0>;
|
||||
hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
|
||||
vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
|
||||
avdd-pll-erefe-supply = <&avdd_1v05_run>;
|
||||
|
||||
/* Mini PCIe */
|
||||
pci@1,0 {
|
||||
phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
|
||||
phy-names = "pcie-0";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Gigabit Ethernet */
|
||||
pci@2,0 {
|
||||
phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
|
||||
phy-names = "pcie-0";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
Tegra210:
|
||||
---------
|
||||
|
||||
SoC DTSI:
|
||||
|
||||
pcie-controller@1003000 {
|
||||
compatible = "nvidia,tegra210-pcie";
|
||||
device_type = "pci";
|
||||
reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
|
||||
0x0 0x01003800 0x0 0x00000800 /* AFI registers */
|
||||
0x0 0x02000000 0x0 0x10000000>; /* configuration space */
|
||||
reg-names = "pads", "afi", "cs";
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
|
||||
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
|
||||
interrupt-names = "intr", "msi";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
|
||||
0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
|
||||
0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
|
||||
0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
|
||||
0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
|
||||
|
||||
clocks = <&tegra_car TEGRA210_CLK_PCIE>,
|
||||
<&tegra_car TEGRA210_CLK_AFI>,
|
||||
<&tegra_car TEGRA210_CLK_PLL_E>,
|
||||
<&tegra_car TEGRA210_CLK_CML0>;
|
||||
clock-names = "pex", "afi", "pll_e", "cml";
|
||||
resets = <&tegra_car 70>,
|
||||
<&tegra_car 72>,
|
||||
<&tegra_car 74>;
|
||||
reset-names = "pex", "afi", "pcie_x";
|
||||
status = "disabled";
|
||||
|
||||
pci@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
|
||||
reg = <0x000800 0 0 0 0>;
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
nvidia,num-lanes = <4>;
|
||||
};
|
||||
|
||||
pci@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
|
||||
reg = <0x001000 0 0 0 0>;
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
nvidia,num-lanes = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
Board DTS:
|
||||
|
||||
pcie-controller@1003000 {
|
||||
status = "okay";
|
||||
|
||||
avdd-pll-uerefe-supply = <&avdd_1v05_pll>;
|
||||
hvddio-pex-supply = <&vdd_1v8>;
|
||||
dvddio-pex-supply = <&vdd_pex_1v05>;
|
||||
dvdd-pex-pll-supply = <&vdd_pex_1v05>;
|
||||
hvdd-pex-pll-e-supply = <&vdd_1v8>;
|
||||
vddio-pex-ctl-supply = <&vdd_1v8>;
|
||||
|
||||
pci@1,0 {
|
||||
phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>,
|
||||
<&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
|
||||
<&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>,
|
||||
<&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
|
||||
phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pci@2,0 {
|
||||
phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
|
||||
phy-names = "pcie-0";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
Tegra186:
|
||||
---------
|
||||
|
||||
SoC DTSI:
|
||||
|
||||
pcie@10003000 {
|
||||
compatible = "nvidia,tegra186-pcie";
|
||||
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
|
||||
device_type = "pci";
|
||||
reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */
|
||||
0x0 0x10003800 0x0 0x00000800 /* AFI registers */
|
||||
0x0 0x40000000 0x0 0x10000000>; /* configuration space */
|
||||
reg-names = "pads", "afi", "cs";
|
||||
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
|
||||
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
|
||||
interrupt-names = "intr", "msi";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */
|
||||
0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */
|
||||
0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */
|
||||
0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */
|
||||
0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */
|
||||
0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
|
||||
|
||||
clocks = <&bpmp TEGRA186_CLK_AFI>,
|
||||
<&bpmp TEGRA186_CLK_PCIE>,
|
||||
<&bpmp TEGRA186_CLK_PLLE>;
|
||||
clock-names = "afi", "pex", "pll_e";
|
||||
|
||||
resets = <&bpmp TEGRA186_RESET_AFI>,
|
||||
<&bpmp TEGRA186_RESET_PCIE>,
|
||||
<&bpmp TEGRA186_RESET_PCIEXCLK>;
|
||||
reset-names = "afi", "pex", "pcie_x";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
pci@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
|
||||
reg = <0x000800 0 0 0 0>;
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
nvidia,num-lanes = <2>;
|
||||
};
|
||||
|
||||
pci@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
|
||||
reg = <0x001000 0 0 0 0>;
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
nvidia,num-lanes = <1>;
|
||||
};
|
||||
|
||||
pci@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
|
||||
reg = <0x001800 0 0 0 0>;
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
nvidia,num-lanes = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
Board DTS:
|
||||
|
||||
pcie@10003000 {
|
||||
status = "okay";
|
||||
|
||||
dvdd-pex-supply = <&vdd_pex>;
|
||||
hvdd-pex-pll-supply = <&vdd_1v8>;
|
||||
hvdd-pex-supply = <&vdd_1v8>;
|
||||
vddio-pexctl-aud-supply = <&vdd_1v8>;
|
||||
|
||||
pci@1,0 {
|
||||
nvidia,num-lanes = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pci@2,0 {
|
||||
nvidia,num-lanes = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pci@3,0 {
|
||||
nvidia,num-lanes = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
48
bindings/pci/pci-armada8k.txt
Normal file
48
bindings/pci/pci-armada8k.txt
Normal file
@@ -0,0 +1,48 @@
|
||||
* Marvell Armada 7K/8K PCIe interface
|
||||
|
||||
This PCIe host controller is based on the Synopsys DesignWare PCIe IP
|
||||
and thus inherits all the common properties defined in snps,dw-pcie.yaml.
|
||||
|
||||
Required properties:
|
||||
- compatible: "marvell,armada8k-pcie"
|
||||
- reg: must contain two register regions
|
||||
- the control register region
|
||||
- the config space region
|
||||
- reg-names:
|
||||
- "ctrl" for the control register region
|
||||
- "config" for the config space region
|
||||
- interrupts: Interrupt specifier for the PCIe controller
|
||||
- clocks: reference to the PCIe controller clocks
|
||||
- clock-names: mandatory if there is a second clock, in this case the
|
||||
name must be "core" for the first clock and "reg" for the second
|
||||
one
|
||||
|
||||
Optional properties:
|
||||
- phys: phandle(s) to PHY node(s) following the generic PHY bindings.
|
||||
Either 1, 2 or 4 PHYs might be needed depending on the number of
|
||||
PCIe lanes.
|
||||
- phy-names: names of the PHYs corresponding to the number of lanes.
|
||||
Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for
|
||||
2 PHYs.
|
||||
|
||||
Example:
|
||||
|
||||
pcie@f2600000 {
|
||||
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
|
||||
reg = <0 0xf2600000 0 0x10000>, <0 0xf6f00000 0 0x80000>;
|
||||
reg-names = "ctrl", "config";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
|
||||
bus-range = <0 0xff>;
|
||||
ranges = <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000 /* downstream I/O */
|
||||
0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; /* non-prefetchable memory */
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
num-lanes = <1>;
|
||||
clocks = <&cpm_syscon0 1 13>;
|
||||
};
|
||||
47
bindings/pci/pci-ep.yaml
Normal file
47
bindings/pci/pci-ep.yaml
Normal file
@@ -0,0 +1,47 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/pci-ep.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: PCI Endpoint Controller Schema
|
||||
|
||||
description: |
|
||||
Common properties for PCI Endpoint Controller Nodes.
|
||||
|
||||
maintainers:
|
||||
- Kishon Vijay Abraham I <kishon@ti.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^pcie-ep@"
|
||||
|
||||
max-functions:
|
||||
description: Maximum number of functions that can be configured
|
||||
$ref: /schemas/types.yaml#/definitions/uint8
|
||||
minimum: 1
|
||||
default: 1
|
||||
maximum: 255
|
||||
|
||||
max-virtual-functions:
|
||||
description: Array representing the number of virtual functions corresponding to each physical
|
||||
function
|
||||
$ref: /schemas/types.yaml#/definitions/uint8-array
|
||||
minItems: 1
|
||||
maxItems: 255
|
||||
|
||||
max-link-speed:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [ 1, 2, 3, 4 ]
|
||||
|
||||
num-lanes:
|
||||
description: maximum number of lanes
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 1
|
||||
default: 1
|
||||
maximum: 16
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
additionalProperties: true
|
||||
171
bindings/pci/pci-iommu.txt
Normal file
171
bindings/pci/pci-iommu.txt
Normal file
@@ -0,0 +1,171 @@
|
||||
This document describes the generic device tree binding for describing the
|
||||
relationship between PCI(e) devices and IOMMU(s).
|
||||
|
||||
Each PCI(e) device under a root complex is uniquely identified by its Requester
|
||||
ID (AKA RID). A Requester ID is a triplet of a Bus number, Device number, and
|
||||
Function number.
|
||||
|
||||
For the purpose of this document, when treated as a numeric value, a RID is
|
||||
formatted such that:
|
||||
|
||||
* Bits [15:8] are the Bus number.
|
||||
* Bits [7:3] are the Device number.
|
||||
* Bits [2:0] are the Function number.
|
||||
* Any other bits required for padding must be zero.
|
||||
|
||||
IOMMUs may distinguish PCI devices through sideband data derived from the
|
||||
Requester ID. While a given PCI device can only master through one IOMMU, a
|
||||
root complex may split masters across a set of IOMMUs (e.g. with one IOMMU per
|
||||
bus).
|
||||
|
||||
The generic 'iommus' property is insufficient to describe this relationship,
|
||||
and a mechanism is required to map from a PCI device to its IOMMU and sideband
|
||||
data.
|
||||
|
||||
For generic IOMMU bindings, see
|
||||
Documentation/devicetree/bindings/iommu/iommu.txt.
|
||||
|
||||
|
||||
PCI root complex
|
||||
================
|
||||
|
||||
Optional properties
|
||||
-------------------
|
||||
|
||||
- iommu-map: Maps a Requester ID to an IOMMU and associated IOMMU specifier
|
||||
data.
|
||||
|
||||
The property is an arbitrary number of tuples of
|
||||
(rid-base,iommu,iommu-base,length).
|
||||
|
||||
Any RID r in the interval [rid-base, rid-base + length) is associated with
|
||||
the listed IOMMU, with the IOMMU specifier (r - rid-base + iommu-base).
|
||||
|
||||
- iommu-map-mask: A mask to be applied to each Requester ID prior to being
|
||||
mapped to an IOMMU specifier per the iommu-map property.
|
||||
|
||||
|
||||
Example (1)
|
||||
===========
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
iommu: iommu@a {
|
||||
reg = <0xa 0x1>;
|
||||
compatible = "vendor,some-iommu";
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
pci: pci@f {
|
||||
reg = <0xf 0x1>;
|
||||
compatible = "vendor,pcie-root-complex";
|
||||
device_type = "pci";
|
||||
|
||||
/*
|
||||
* The sideband data provided to the IOMMU is the RID,
|
||||
* identity-mapped.
|
||||
*/
|
||||
iommu-map = <0x0 &iommu 0x0 0x10000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Example (2)
|
||||
===========
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
iommu: iommu@a {
|
||||
reg = <0xa 0x1>;
|
||||
compatible = "vendor,some-iommu";
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
pci: pci@f {
|
||||
reg = <0xf 0x1>;
|
||||
compatible = "vendor,pcie-root-complex";
|
||||
device_type = "pci";
|
||||
|
||||
/*
|
||||
* The sideband data provided to the IOMMU is the RID with the
|
||||
* function bits masked out.
|
||||
*/
|
||||
iommu-map = <0x0 &iommu 0x0 0x10000>;
|
||||
iommu-map-mask = <0xfff8>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Example (3)
|
||||
===========
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
iommu: iommu@a {
|
||||
reg = <0xa 0x1>;
|
||||
compatible = "vendor,some-iommu";
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
pci: pci@f {
|
||||
reg = <0xf 0x1>;
|
||||
compatible = "vendor,pcie-root-complex";
|
||||
device_type = "pci";
|
||||
|
||||
/*
|
||||
* The sideband data provided to the IOMMU is the RID,
|
||||
* but the high bits of the bus number are flipped.
|
||||
*/
|
||||
iommu-map = <0x0000 &iommu 0x8000 0x8000>,
|
||||
<0x8000 &iommu 0x0000 0x8000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Example (4)
|
||||
===========
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
iommu_a: iommu@a {
|
||||
reg = <0xa 0x1>;
|
||||
compatible = "vendor,some-iommu";
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
iommu_b: iommu@b {
|
||||
reg = <0xb 0x1>;
|
||||
compatible = "vendor,some-iommu";
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
iommu_c: iommu@c {
|
||||
reg = <0xc 0x1>;
|
||||
compatible = "vendor,some-iommu";
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
pci: pci@f {
|
||||
reg = <0xf 0x1>;
|
||||
compatible = "vendor,pcie-root-complex";
|
||||
device_type = "pci";
|
||||
|
||||
/*
|
||||
* Devices with bus number 0-127 are mastered via IOMMU
|
||||
* a, with sideband data being RID[14:0].
|
||||
* Devices with bus number 128-255 are mastered via
|
||||
* IOMMU b, with sideband data being RID[14:0].
|
||||
* No devices master via IOMMU c.
|
||||
*/
|
||||
iommu-map = <0x0000 &iommu_a 0x0000 0x8000>,
|
||||
<0x8000 &iommu_b 0x0000 0x8000>;
|
||||
};
|
||||
};
|
||||
220
bindings/pci/pci-msi.txt
Normal file
220
bindings/pci/pci-msi.txt
Normal file
@@ -0,0 +1,220 @@
|
||||
This document describes the generic device tree binding for describing the
|
||||
relationship between PCI devices and MSI controllers.
|
||||
|
||||
Each PCI device under a root complex is uniquely identified by its Requester ID
|
||||
(AKA RID). A Requester ID is a triplet of a Bus number, Device number, and
|
||||
Function number.
|
||||
|
||||
For the purpose of this document, when treated as a numeric value, a RID is
|
||||
formatted such that:
|
||||
|
||||
* Bits [15:8] are the Bus number.
|
||||
* Bits [7:3] are the Device number.
|
||||
* Bits [2:0] are the Function number.
|
||||
* Any other bits required for padding must be zero.
|
||||
|
||||
MSIs may be distinguished in part through the use of sideband data accompanying
|
||||
writes. In the case of PCI devices, this sideband data may be derived from the
|
||||
Requester ID. A mechanism is required to associate a device with both the MSI
|
||||
controllers it can address, and the sideband data that will be associated with
|
||||
its writes to those controllers.
|
||||
|
||||
For generic MSI bindings, see
|
||||
Documentation/devicetree/bindings/interrupt-controller/msi.txt.
|
||||
|
||||
|
||||
PCI root complex
|
||||
================
|
||||
|
||||
Optional properties
|
||||
-------------------
|
||||
|
||||
- msi-map: Maps a Requester ID to an MSI controller and associated
|
||||
msi-specifier data. The property is an arbitrary number of tuples of
|
||||
(rid-base,msi-controller,msi-base,length), where:
|
||||
|
||||
* rid-base is a single cell describing the first RID matched by the entry.
|
||||
|
||||
* msi-controller is a single phandle to an MSI controller
|
||||
|
||||
* msi-base is an msi-specifier describing the msi-specifier produced for the
|
||||
first RID matched by the entry.
|
||||
|
||||
* length is a single cell describing how many consecutive RIDs are matched
|
||||
following the rid-base.
|
||||
|
||||
Any RID r in the interval [rid-base, rid-base + length) is associated with
|
||||
the listed msi-controller, with the msi-specifier (r - rid-base + msi-base).
|
||||
|
||||
- msi-map-mask: A mask to be applied to each Requester ID prior to being mapped
|
||||
to an msi-specifier per the msi-map property.
|
||||
|
||||
- msi-parent: Describes the MSI parent of the root complex itself. Where
|
||||
the root complex and MSI controller do not pass sideband data with MSI
|
||||
writes, this property may be used to describe the MSI controller(s)
|
||||
used by PCI devices under the root complex, if defined as such in the
|
||||
binding for the root complex.
|
||||
|
||||
|
||||
Example (1)
|
||||
===========
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
msi: msi-controller@a {
|
||||
reg = <0xa 0x1>;
|
||||
compatible = "vendor,some-controller";
|
||||
msi-controller;
|
||||
#msi-cells = <1>;
|
||||
};
|
||||
|
||||
pci: pci@f {
|
||||
reg = <0xf 0x1>;
|
||||
compatible = "vendor,pcie-root-complex";
|
||||
device_type = "pci";
|
||||
|
||||
/*
|
||||
* The sideband data provided to the MSI controller is
|
||||
* the RID, identity-mapped.
|
||||
*/
|
||||
msi-map = <0x0 &msi_a 0x0 0x10000>,
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Example (2)
|
||||
===========
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
msi: msi-controller@a {
|
||||
reg = <0xa 0x1>;
|
||||
compatible = "vendor,some-controller";
|
||||
msi-controller;
|
||||
#msi-cells = <1>;
|
||||
};
|
||||
|
||||
pci: pci@f {
|
||||
reg = <0xf 0x1>;
|
||||
compatible = "vendor,pcie-root-complex";
|
||||
device_type = "pci";
|
||||
|
||||
/*
|
||||
* The sideband data provided to the MSI controller is
|
||||
* the RID, masked to only the device and function bits.
|
||||
*/
|
||||
msi-map = <0x0 &msi_a 0x0 0x100>,
|
||||
msi-map-mask = <0xff>
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Example (3)
|
||||
===========
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
msi: msi-controller@a {
|
||||
reg = <0xa 0x1>;
|
||||
compatible = "vendor,some-controller";
|
||||
msi-controller;
|
||||
#msi-cells = <1>;
|
||||
};
|
||||
|
||||
pci: pci@f {
|
||||
reg = <0xf 0x1>;
|
||||
compatible = "vendor,pcie-root-complex";
|
||||
device_type = "pci";
|
||||
|
||||
/*
|
||||
* The sideband data provided to the MSI controller is
|
||||
* the RID, but the high bit of the bus number is
|
||||
* ignored.
|
||||
*/
|
||||
msi-map = <0x0000 &msi 0x0000 0x8000>,
|
||||
<0x8000 &msi 0x0000 0x8000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Example (4)
|
||||
===========
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
msi: msi-controller@a {
|
||||
reg = <0xa 0x1>;
|
||||
compatible = "vendor,some-controller";
|
||||
msi-controller;
|
||||
#msi-cells = <1>;
|
||||
};
|
||||
|
||||
pci: pci@f {
|
||||
reg = <0xf 0x1>;
|
||||
compatible = "vendor,pcie-root-complex";
|
||||
device_type = "pci";
|
||||
|
||||
/*
|
||||
* The sideband data provided to the MSI controller is
|
||||
* the RID, but the high bit of the bus number is
|
||||
* negated.
|
||||
*/
|
||||
msi-map = <0x0000 &msi 0x8000 0x8000>,
|
||||
<0x8000 &msi 0x0000 0x8000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Example (5)
|
||||
===========
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
msi_a: msi-controller@a {
|
||||
reg = <0xa 0x1>;
|
||||
compatible = "vendor,some-controller";
|
||||
msi-controller;
|
||||
#msi-cells = <1>;
|
||||
};
|
||||
|
||||
msi_b: msi-controller@b {
|
||||
reg = <0xb 0x1>;
|
||||
compatible = "vendor,some-controller";
|
||||
msi-controller;
|
||||
#msi-cells = <1>;
|
||||
};
|
||||
|
||||
msi_c: msi-controller@c {
|
||||
reg = <0xc 0x1>;
|
||||
compatible = "vendor,some-controller";
|
||||
msi-controller;
|
||||
#msi-cells = <1>;
|
||||
};
|
||||
|
||||
pci: pci@f {
|
||||
reg = <0xf 0x1>;
|
||||
compatible = "vendor,pcie-root-complex";
|
||||
device_type = "pci";
|
||||
|
||||
/*
|
||||
* The sideband data provided to MSI controller a is the
|
||||
* RID, but the high bit of the bus number is negated.
|
||||
* The sideband data provided to MSI controller b is the
|
||||
* RID, identity-mapped.
|
||||
* MSI controller c is not addressable.
|
||||
*/
|
||||
msi-map = <0x0000 &msi_a 0x8000 0x08000>,
|
||||
<0x8000 &msi_a 0x0000 0x08000>,
|
||||
<0x0000 &msi_b 0x0000 0x10000>;
|
||||
};
|
||||
};
|
||||
84
bindings/pci/pci.txt
Normal file
84
bindings/pci/pci.txt
Normal file
@@ -0,0 +1,84 @@
|
||||
PCI bus bridges have standardized Device Tree bindings:
|
||||
|
||||
PCI Bus Binding to: IEEE Std 1275-1994
|
||||
https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
|
||||
|
||||
And for the interrupt mapping part:
|
||||
|
||||
Open Firmware Recommended Practice: Interrupt Mapping
|
||||
https://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf
|
||||
|
||||
Additionally to the properties specified in the above standards a host bridge
|
||||
driver implementation may support the following properties:
|
||||
|
||||
- linux,pci-domain:
|
||||
If present this property assigns a fixed PCI domain number to a host bridge,
|
||||
otherwise an unstable (across boots) unique number will be assigned.
|
||||
It is required to either not set this property at all or set it for all
|
||||
host bridges in the system, otherwise potentially conflicting domain numbers
|
||||
may be assigned to root buses behind different host bridges. The domain
|
||||
number for each host bridge in the system must be unique.
|
||||
- max-link-speed:
|
||||
If present this property specifies PCI gen for link capability. Host
|
||||
drivers could add this as a strategy to avoid unnecessary operation for
|
||||
unsupported link speed, for instance, trying to do training for
|
||||
unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2'
|
||||
for gen2, and '1' for gen1. Any other values are invalid.
|
||||
- reset-gpios:
|
||||
If present this property specifies PERST# GPIO. Host drivers can parse the
|
||||
GPIO and apply fundamental reset to endpoints.
|
||||
- supports-clkreq:
|
||||
If present this property specifies that CLKREQ signal routing exists from
|
||||
root port to downstream device and host bridge drivers can do programming
|
||||
which depends on CLKREQ signal existence. For example, programming root port
|
||||
not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal.
|
||||
|
||||
PCI-PCI Bridge properties
|
||||
-------------------------
|
||||
|
||||
PCIe root ports and switch ports may be described explicitly in the device
|
||||
tree, as children of the host bridge node. Even though those devices are
|
||||
discoverable by probing, it might be necessary to describe properties that
|
||||
aren't provided by standard PCIe capabilities.
|
||||
|
||||
Required properties:
|
||||
|
||||
- reg:
|
||||
Identifies the PCI-PCI bridge. As defined in the IEEE Std 1275-1994
|
||||
document, it is a five-cell address encoded as (phys.hi phys.mid
|
||||
phys.lo size.hi size.lo). phys.hi should contain the device's BDF as
|
||||
0b00000000 bbbbbbbb dddddfff 00000000. The other cells should be zero.
|
||||
|
||||
The bus number is defined by firmware, through the standard bridge
|
||||
configuration mechanism. If this port is a switch port, then firmware
|
||||
allocates the bus number and writes it into the Secondary Bus Number
|
||||
register of the bridge directly above this port. Otherwise, the bus
|
||||
number of a root port is the first number in the bus-range property,
|
||||
defaulting to zero.
|
||||
|
||||
If firmware leaves the ARI Forwarding Enable bit set in the bridge
|
||||
above this port, then phys.hi contains the 8-bit function number as
|
||||
0b00000000 bbbbbbbb ffffffff 00000000. Note that the PCIe specification
|
||||
recommends that firmware only leaves ARI enabled when it knows that the
|
||||
OS is ARI-aware.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- external-facing:
|
||||
When present, the port is external-facing. All bridges and endpoints
|
||||
downstream of this port are external to the machine. The OS can, for
|
||||
example, use this information to identify devices that cannot be
|
||||
trusted with relaxed DMA protection, as users could easily attach
|
||||
malicious devices to this port.
|
||||
|
||||
Example:
|
||||
|
||||
pcie@10000000 {
|
||||
compatible = "pci-host-ecam-generic";
|
||||
...
|
||||
pcie@0008 {
|
||||
/* Root port 00:01.0 is external-facing */
|
||||
reg = <0x00000800 0 0 0 0>;
|
||||
external-facing;
|
||||
};
|
||||
};
|
||||
46
bindings/pci/pcie-al.txt
Normal file
46
bindings/pci/pcie-al.txt
Normal file
@@ -0,0 +1,46 @@
|
||||
* Amazon Annapurna Labs PCIe host bridge
|
||||
|
||||
Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys DesignWare
|
||||
PCI core. It inherits common properties defined in
|
||||
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
|
||||
|
||||
Properties of the host controller node that differ from it are:
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <stringlist>
|
||||
Definition: Value should contain
|
||||
- "amazon,al-alpine-v2-pcie" for alpine_v2
|
||||
- "amazon,al-alpine-v3-pcie" for alpine_v3
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: Register ranges as listed in the reg-names property
|
||||
|
||||
- reg-names:
|
||||
Usage: required
|
||||
Value type: <stringlist>
|
||||
Definition: Must include the following entries
|
||||
- "config" PCIe ECAM space
|
||||
- "controller" AL proprietary registers
|
||||
- "dbi" Designware PCIe registers
|
||||
|
||||
Example:
|
||||
|
||||
pcie-external0: pcie@fb600000 {
|
||||
compatible = "amazon,al-alpine-v3-pcie";
|
||||
reg = <0x0 0xfb600000 0x0 0x00100000
|
||||
0x0 0xfd800000 0x0 0x00010000
|
||||
0x0 0xfd810000 0x0 0x00001000>;
|
||||
reg-names = "config", "controller", "dbi";
|
||||
bus-range = <0 255>;
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-map-mask = <0x00 0 0 7>;
|
||||
interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; /* INTa */
|
||||
ranges = <0x02000000 0x0 0xc0010000 0x0 0xc0010000 0x0 0x07ff0000>;
|
||||
};
|
||||
202
bindings/pci/qcom,pcie-ep.yaml
Normal file
202
bindings/pci/qcom,pcie-ep.yaml
Normal file
@@ -0,0 +1,202 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm PCIe Endpoint Controller binding
|
||||
|
||||
maintainers:
|
||||
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sdx55-pcie-ep
|
||||
- qcom,sm8450-pcie-ep
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Qualcomm-specific PARF configuration registers
|
||||
- description: DesignWare PCIe registers
|
||||
- description: External local bus interface registers
|
||||
- description: Address Translation Unit (ATU) registers
|
||||
- description: Memory region used to map remote RC address space
|
||||
- description: BAR memory region
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: parf
|
||||
- const: dbi
|
||||
- const: elbi
|
||||
- const: atu
|
||||
- const: addr_space
|
||||
- const: mmio
|
||||
|
||||
clocks:
|
||||
minItems: 7
|
||||
maxItems: 8
|
||||
|
||||
clock-names:
|
||||
minItems: 7
|
||||
maxItems: 8
|
||||
|
||||
qcom,perst-regs:
|
||||
description: Reference to a syscon representing TCSR followed by the two
|
||||
offsets within syscon for Perst enable and Perst separation
|
||||
enable registers
|
||||
$ref: "/schemas/types.yaml#/definitions/phandle-array"
|
||||
items:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: PCIe Global interrupt
|
||||
- description: PCIe Doorbell interrupt
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: global
|
||||
- const: doorbell
|
||||
|
||||
reset-gpios:
|
||||
description: GPIO used as PERST# input signal
|
||||
maxItems: 1
|
||||
|
||||
wake-gpios:
|
||||
description: GPIO used as WAKE# output signal
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
const: core
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
phy-names:
|
||||
const: pciephy
|
||||
|
||||
num-lanes:
|
||||
default: 2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- clock-names
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- reset-gpios
|
||||
- resets
|
||||
- reset-names
|
||||
- power-domains
|
||||
|
||||
allOf:
|
||||
- $ref: pci-ep.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sdx55-pcie-ep
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: PCIe Auxiliary clock
|
||||
- description: PCIe CFG AHB clock
|
||||
- description: PCIe Master AXI clock
|
||||
- description: PCIe Slave AXI clock
|
||||
- description: PCIe Slave Q2A AXI clock
|
||||
- description: PCIe Sleep clock
|
||||
- description: PCIe Reference clock
|
||||
clock-names:
|
||||
items:
|
||||
- const: aux
|
||||
- const: cfg
|
||||
- const: bus_master
|
||||
- const: bus_slave
|
||||
- const: slave_q2a
|
||||
- const: sleep
|
||||
- const: ref
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sm8450-pcie-ep
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: PCIe Auxiliary clock
|
||||
- description: PCIe CFG AHB clock
|
||||
- description: PCIe Master AXI clock
|
||||
- description: PCIe Slave AXI clock
|
||||
- description: PCIe Slave Q2A AXI clock
|
||||
- description: PCIe Reference clock
|
||||
- description: PCIe DDRSS SF TBU clock
|
||||
- description: PCIe AGGRE NOC AXI clock
|
||||
clock-names:
|
||||
items:
|
||||
- const: aux
|
||||
- const: cfg
|
||||
- const: bus_master
|
||||
- const: bus_slave
|
||||
- const: slave_q2a
|
||||
- const: ref
|
||||
- const: ddrss_sf_tbu
|
||||
- const: aggre_noc_axi
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sdx55.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
pcie_ep: pcie-ep@40000000 {
|
||||
compatible = "qcom,sdx55-pcie-ep";
|
||||
reg = <0x01c00000 0x3000>,
|
||||
<0x40000000 0xf1d>,
|
||||
<0x40000f20 0xc8>,
|
||||
<0x40001000 0x1000>,
|
||||
<0x40002000 0x1000>,
|
||||
<0x01c03000 0x3000>;
|
||||
reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
|
||||
"mmio";
|
||||
|
||||
clocks = <&gcc GCC_PCIE_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_SLV_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_SLEEP_CLK>,
|
||||
<&gcc GCC_PCIE_0_CLKREF_CLK>;
|
||||
clock-names = "aux", "cfg", "bus_master", "bus_slave",
|
||||
"slave_q2a", "sleep", "ref";
|
||||
|
||||
qcom,perst-regs = <&tcsr 0xb258 0xb270>;
|
||||
|
||||
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "global", "doorbell";
|
||||
reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
|
||||
resets = <&gcc GCC_PCIE_BCR>;
|
||||
reset-names = "core";
|
||||
power-domains = <&gcc PCIE_GDSC>;
|
||||
phys = <&pcie0_lane>;
|
||||
phy-names = "pciephy";
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <2>;
|
||||
};
|
||||
825
bindings/pci/qcom,pcie.yaml
Normal file
825
bindings/pci/qcom,pcie.yaml
Normal file
@@ -0,0 +1,825 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm PCI express root complex
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
- Stanimir Varbanov <svarbanov@mm-sol.com>
|
||||
|
||||
description: |
|
||||
Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
|
||||
PCIe IP.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,pcie-ipq8064
|
||||
- qcom,pcie-ipq8064-v2
|
||||
- qcom,pcie-apq8064
|
||||
- qcom,pcie-apq8084
|
||||
- qcom,pcie-msm8996
|
||||
- qcom,pcie-ipq4019
|
||||
- qcom,pcie-ipq8074
|
||||
- qcom,pcie-qcs404
|
||||
- qcom,pcie-sa8540p
|
||||
- qcom,pcie-sc7280
|
||||
- qcom,pcie-sc8180x
|
||||
- qcom,pcie-sc8280xp
|
||||
- qcom,pcie-sdm845
|
||||
- qcom,pcie-sm8150
|
||||
- qcom,pcie-sm8250
|
||||
- qcom,pcie-sm8450-pcie0
|
||||
- qcom,pcie-sm8450-pcie1
|
||||
- qcom,pcie-ipq6018
|
||||
|
||||
reg:
|
||||
minItems: 4
|
||||
maxItems: 5
|
||||
|
||||
reg-names:
|
||||
minItems: 4
|
||||
maxItems: 5
|
||||
|
||||
interrupts:
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
|
||||
interrupt-names:
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
|
||||
# Common definitions for clocks, clock-names and reset.
|
||||
# Platform constraints are described later.
|
||||
clocks:
|
||||
minItems: 3
|
||||
maxItems: 13
|
||||
|
||||
clock-names:
|
||||
minItems: 3
|
||||
maxItems: 13
|
||||
|
||||
resets:
|
||||
minItems: 1
|
||||
maxItems: 12
|
||||
|
||||
resets-names:
|
||||
minItems: 1
|
||||
maxItems: 12
|
||||
|
||||
vdda-supply:
|
||||
description: A phandle to the core analog power supply
|
||||
|
||||
vdda_phy-supply:
|
||||
description: A phandle to the core analog power supply for PHY
|
||||
|
||||
vdda_refclk-supply:
|
||||
description: A phandle to the core analog power supply for IC which generates reference clock
|
||||
|
||||
vddpe-3v3-supply:
|
||||
description: A phandle to the PCIe endpoint power supply
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
phy-names:
|
||||
items:
|
||||
- const: pciephy
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
perst-gpios:
|
||||
description: GPIO controlled connection to PERST# signal
|
||||
maxItems: 1
|
||||
|
||||
wake-gpios:
|
||||
description: GPIO controlled connection to WAKE# signal
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- "#interrupt-cells"
|
||||
- interrupt-map-mask
|
||||
- interrupt-map
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-bus.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-apq8064
|
||||
- qcom,pcie-ipq4019
|
||||
- qcom,pcie-ipq8064
|
||||
- qcom,pcie-ipq8064v2
|
||||
- qcom,pcie-ipq8074
|
||||
- qcom,pcie-qcs404
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 4
|
||||
maxItems: 4
|
||||
reg-names:
|
||||
items:
|
||||
- const: dbi # DesignWare PCIe registers
|
||||
- const: elbi # External local bus interface registers
|
||||
- const: parf # Qualcomm specific registers
|
||||
- const: config # PCIe configuration space
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-ipq6018
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 5
|
||||
maxItems: 5
|
||||
reg-names:
|
||||
items:
|
||||
- const: dbi # DesignWare PCIe registers
|
||||
- const: elbi # External local bus interface registers
|
||||
- const: atu # ATU address space
|
||||
- const: parf # Qualcomm specific registers
|
||||
- const: config # PCIe configuration space
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-apq8084
|
||||
- qcom,pcie-msm8996
|
||||
- qcom,pcie-sdm845
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 4
|
||||
maxItems: 4
|
||||
reg-names:
|
||||
items:
|
||||
- const: parf # Qualcomm specific registers
|
||||
- const: dbi # DesignWare PCIe registers
|
||||
- const: elbi # External local bus interface registers
|
||||
- const: config # PCIe configuration space
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-sc7280
|
||||
- qcom,pcie-sc8180x
|
||||
- qcom,pcie-sc8280xp
|
||||
- qcom,pcie-sm8250
|
||||
- qcom,pcie-sm8450-pcie0
|
||||
- qcom,pcie-sm8450-pcie1
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 5
|
||||
maxItems: 5
|
||||
reg-names:
|
||||
items:
|
||||
- const: parf # Qualcomm specific registers
|
||||
- const: dbi # DesignWare PCIe registers
|
||||
- const: elbi # External local bus interface registers
|
||||
- const: atu # ATU address space
|
||||
- const: config # PCIe configuration space
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-apq8064
|
||||
- qcom,pcie-ipq8064
|
||||
- qcom,pcie-ipq8064v2
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 3
|
||||
maxItems: 5
|
||||
clock-names:
|
||||
minItems: 3
|
||||
items:
|
||||
- const: core # Clocks the pcie hw block
|
||||
- const: iface # Configuration AHB clock
|
||||
- const: phy # Clocks the pcie PHY block
|
||||
- const: aux # Clocks the pcie AUX block, not on apq8064
|
||||
- const: ref # Clocks the pcie ref block, not on apq8064
|
||||
resets:
|
||||
minItems: 5
|
||||
maxItems: 6
|
||||
reset-names:
|
||||
minItems: 5
|
||||
items:
|
||||
- const: axi # AXI reset
|
||||
- const: ahb # AHB reset
|
||||
- const: por # POR reset
|
||||
- const: pci # PCI reset
|
||||
- const: phy # PHY reset
|
||||
- const: ext # EXT reset, not on apq8064
|
||||
required:
|
||||
- vdda-supply
|
||||
- vdda_phy-supply
|
||||
- vdda_refclk-supply
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-apq8084
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 4
|
||||
maxItems: 4
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface # Configuration AHB clock
|
||||
- const: master_bus # Master AXI clock
|
||||
- const: slave_bus # Slave AXI clock
|
||||
- const: aux # Auxiliary (AUX) clock
|
||||
resets:
|
||||
maxItems: 1
|
||||
reset-names:
|
||||
items:
|
||||
- const: core # Core reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-ipq4019
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
clock-names:
|
||||
items:
|
||||
- const: aux # Auxiliary (AUX) clock
|
||||
- const: master_bus # Master AXI clock
|
||||
- const: slave_bus # Slave AXI clock
|
||||
resets:
|
||||
minItems: 12
|
||||
maxItems: 12
|
||||
reset-names:
|
||||
items:
|
||||
- const: axi_m # AXI master reset
|
||||
- const: axi_s # AXI slave reset
|
||||
- const: pipe # PIPE reset
|
||||
- const: axi_m_vmid # VMID reset
|
||||
- const: axi_s_xpu # XPU reset
|
||||
- const: parf # PARF reset
|
||||
- const: phy # PHY reset
|
||||
- const: axi_m_sticky # AXI sticky reset
|
||||
- const: pipe_sticky # PIPE sticky reset
|
||||
- const: pwr # PWR reset
|
||||
- const: ahb # AHB reset
|
||||
- const: phy_ahb # PHY AHB reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-msm8996
|
||||
then:
|
||||
oneOf:
|
||||
- properties:
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe # Pipe Clock driving internal logic
|
||||
- const: aux # Auxiliary (AUX) clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- properties:
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe # Pipe Clock driving internal logic
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: aux # Auxiliary (AUX) clock
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 5
|
||||
maxItems: 5
|
||||
resets: false
|
||||
reset-names: false
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-ipq8074
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 5
|
||||
maxItems: 5
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface # PCIe to SysNOC BIU clock
|
||||
- const: axi_m # AXI Master clock
|
||||
- const: axi_s # AXI Slave clock
|
||||
- const: ahb # AHB clock
|
||||
- const: aux # Auxiliary clock
|
||||
resets:
|
||||
minItems: 7
|
||||
maxItems: 7
|
||||
reset-names:
|
||||
items:
|
||||
- const: pipe # PIPE reset
|
||||
- const: sleep # Sleep reset
|
||||
- const: sticky # Core Sticky reset
|
||||
- const: axi_m # AXI Master reset
|
||||
- const: axi_s # AXI Slave reset
|
||||
- const: ahb # AHB Reset
|
||||
- const: axi_m_sticky # AXI Master Sticky reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-ipq6018
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 5
|
||||
maxItems: 5
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface # PCIe to SysNOC BIU clock
|
||||
- const: axi_m # AXI Master clock
|
||||
- const: axi_s # AXI Slave clock
|
||||
- const: axi_bridge # AXI bridge clock
|
||||
- const: rchng
|
||||
resets:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
reset-names:
|
||||
items:
|
||||
- const: pipe # PIPE reset
|
||||
- const: sleep # Sleep reset
|
||||
- const: sticky # Core Sticky reset
|
||||
- const: axi_m # AXI Master reset
|
||||
- const: axi_s # AXI Slave reset
|
||||
- const: ahb # AHB Reset
|
||||
- const: axi_m_sticky # AXI Master Sticky reset
|
||||
- const: axi_s_sticky # AXI Slave Sticky reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-qcs404
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 4
|
||||
maxItems: 4
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface # AHB clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: master_bus # AXI Master clock
|
||||
- const: slave_bus # AXI Slave clock
|
||||
resets:
|
||||
minItems: 6
|
||||
maxItems: 6
|
||||
reset-names:
|
||||
items:
|
||||
- const: axi_m # AXI Master reset
|
||||
- const: axi_s # AXI Slave reset
|
||||
- const: axi_m_sticky # AXI Master Sticky reset
|
||||
- const: pipe_sticky # PIPE sticky reset
|
||||
- const: pwr # PWR reset
|
||||
- const: ahb # AHB reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-sc7280
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 13
|
||||
maxItems: 13
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe # PIPE clock
|
||||
- const: pipe_mux # PIPE MUX
|
||||
- const: phy_pipe # PIPE output clock
|
||||
- const: ref # REFERENCE clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: tbu # PCIe TBU clock
|
||||
- const: ddrss_sf_tbu # PCIe SF TBU clock
|
||||
- const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock
|
||||
- const: aggre1 # Aggre NoC PCIe1 AXI clock
|
||||
resets:
|
||||
maxItems: 1
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci # PCIe core reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-sdm845
|
||||
then:
|
||||
oneOf:
|
||||
# Unfortunately the "optional" ref clock is used in the middle of the list
|
||||
- properties:
|
||||
clocks:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe # PIPE clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: ref # REFERENCE clock
|
||||
- const: tbu # PCIe TBU clock
|
||||
- properties:
|
||||
clocks:
|
||||
minItems: 7
|
||||
maxItems: 7
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe # PIPE clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: tbu # PCIe TBU clock
|
||||
properties:
|
||||
resets:
|
||||
maxItems: 1
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci # PCIe core reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-sc8180x
|
||||
- qcom,pcie-sm8150
|
||||
- qcom,pcie-sm8250
|
||||
then:
|
||||
oneOf:
|
||||
# Unfortunately the "optional" ref clock is used in the middle of the list
|
||||
- properties:
|
||||
clocks:
|
||||
minItems: 9
|
||||
maxItems: 9
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe # PIPE clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: ref # REFERENCE clock
|
||||
- const: tbu # PCIe TBU clock
|
||||
- const: ddrss_sf_tbu # PCIe SF TBU clock
|
||||
- properties:
|
||||
clocks:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe # PIPE clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: tbu # PCIe TBU clock
|
||||
- const: ddrss_sf_tbu # PCIe SF TBU clock
|
||||
properties:
|
||||
resets:
|
||||
maxItems: 1
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci # PCIe core reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-sm8450-pcie0
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 12
|
||||
maxItems: 12
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe # PIPE clock
|
||||
- const: pipe_mux # PIPE MUX
|
||||
- const: phy_pipe # PIPE output clock
|
||||
- const: ref # REFERENCE clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: ddrss_sf_tbu # PCIe SF TBU clock
|
||||
- const: aggre0 # Aggre NoC PCIe0 AXI clock
|
||||
- const: aggre1 # Aggre NoC PCIe1 AXI clock
|
||||
resets:
|
||||
maxItems: 1
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci # PCIe core reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-sm8450-pcie1
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 11
|
||||
maxItems: 11
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe # PIPE clock
|
||||
- const: pipe_mux # PIPE MUX
|
||||
- const: phy_pipe # PIPE output clock
|
||||
- const: ref # REFERENCE clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: ddrss_sf_tbu # PCIe SF TBU clock
|
||||
- const: aggre1 # Aggre NoC PCIe1 AXI clock
|
||||
resets:
|
||||
maxItems: 1
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci # PCIe core reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-sa8540p
|
||||
- qcom,pcie-sc8280xp
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 8
|
||||
maxItems: 9
|
||||
clock-names:
|
||||
minItems: 8
|
||||
items:
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: ddrss_sf_tbu # PCIe SF TBU clock
|
||||
- const: noc_aggr_4 # NoC aggregate 4 clock
|
||||
- const: noc_aggr_south_sf # NoC aggregate South SF clock
|
||||
- const: cnoc_qx # Configuration NoC QX clock
|
||||
resets:
|
||||
maxItems: 1
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci # PCIe core reset
|
||||
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-apq8064
|
||||
- qcom,pcie-ipq4019
|
||||
- qcom,pcie-ipq8064
|
||||
- qcom,pcie-ipq8064v2
|
||||
- qcom,pcie-ipq8074
|
||||
- qcom,pcie-qcs404
|
||||
then:
|
||||
required:
|
||||
- power-domains
|
||||
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-msm8996
|
||||
then:
|
||||
required:
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-msm8996
|
||||
- qcom,pcie-sc7280
|
||||
- qcom,pcie-sc8180x
|
||||
- qcom,pcie-sdm845
|
||||
- qcom,pcie-sm8150
|
||||
- qcom,pcie-sm8250
|
||||
- qcom,pcie-sm8450-pcie0
|
||||
- qcom,pcie-sm8450-pcie1
|
||||
then:
|
||||
oneOf:
|
||||
- properties:
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi
|
||||
- properties:
|
||||
interrupts:
|
||||
minItems: 8
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi0
|
||||
- const: msi1
|
||||
- const: msi2
|
||||
- const: msi3
|
||||
- const: msi4
|
||||
- const: msi5
|
||||
- const: msi6
|
||||
- const: msi7
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-sc8280xp
|
||||
then:
|
||||
properties:
|
||||
interrupts:
|
||||
minItems: 4
|
||||
maxItems: 4
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi0
|
||||
- const: msi1
|
||||
- const: msi2
|
||||
- const: msi3
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-apq8064
|
||||
- qcom,pcie-apq8084
|
||||
- qcom,pcie-ipq4019
|
||||
- qcom,pcie-ipq6018
|
||||
- qcom,pcie-ipq8064
|
||||
- qcom,pcie-ipq8064-v2
|
||||
- qcom,pcie-ipq8074
|
||||
- qcom,pcie-qcs404
|
||||
- qcom,pcie-sa8540p
|
||||
then:
|
||||
properties:
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
pcie@1b500000 {
|
||||
compatible = "qcom,pcie-ipq8064";
|
||||
reg = <0x1b500000 0x1000>,
|
||||
<0x1b502000 0x80>,
|
||||
<0x1b600000 0x100>,
|
||||
<0x0ff00000 0x100000>;
|
||||
reg-names = "dbi", "elbi", "parf", "config";
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <0>;
|
||||
bus-range = <0x00 0xff>;
|
||||
num-lanes = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>,
|
||||
<0x82000000 0 0 0x08000000 0 0x07e00000>;
|
||||
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc 41>,
|
||||
<&gcc 43>,
|
||||
<&gcc 44>,
|
||||
<&gcc 42>,
|
||||
<&gcc 248>;
|
||||
clock-names = "core", "iface", "phy", "aux", "ref";
|
||||
resets = <&gcc 27>,
|
||||
<&gcc 26>,
|
||||
<&gcc 25>,
|
||||
<&gcc 24>,
|
||||
<&gcc 23>,
|
||||
<&gcc 22>;
|
||||
reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
|
||||
pinctrl-0 = <&pcie_pins_default>;
|
||||
pinctrl-names = "default";
|
||||
vdda-supply = <&pm8921_s3>;
|
||||
vdda_phy-supply = <&pm8921_lvs6>;
|
||||
vdda_refclk-supply = <&ext_3p3v>;
|
||||
};
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
pcie@fc520000 {
|
||||
compatible = "qcom,pcie-apq8084";
|
||||
reg = <0xfc520000 0x2000>,
|
||||
<0xff000000 0x1000>,
|
||||
<0xff001000 0x1000>,
|
||||
<0xff002000 0x2000>;
|
||||
reg-names = "parf", "dbi", "elbi", "config";
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <0>;
|
||||
bus-range = <0x00 0xff>;
|
||||
num-lanes = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x81000000 0 0 0xff200000 0 0x00100000>,
|
||||
<0x82000000 0 0x00300000 0xff300000 0 0x00d00000>;
|
||||
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc 324>,
|
||||
<&gcc 325>,
|
||||
<&gcc 327>,
|
||||
<&gcc 323>;
|
||||
clock-names = "iface", "master_bus", "slave_bus", "aux";
|
||||
resets = <&gcc 81>;
|
||||
reset-names = "core";
|
||||
power-domains = <&gcc 1>;
|
||||
vdda-supply = <&pma8084_l3>;
|
||||
phys = <&pciephy0>;
|
||||
phy-names = "pciephy";
|
||||
perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-0 = <&pcie0_pins_default>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
...
|
||||
187
bindings/pci/ralink,rt3883-pci.txt
Normal file
187
bindings/pci/ralink,rt3883-pci.txt
Normal file
@@ -0,0 +1,187 @@
|
||||
* Mediatek/Ralink RT3883 PCI controller
|
||||
|
||||
1) Main node
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: must be "ralink,rt3883-pci"
|
||||
|
||||
- reg: specifies the physical base address of the controller and
|
||||
the length of the memory mapped region.
|
||||
|
||||
- #address-cells: specifies the number of cells needed to encode an
|
||||
address. The value must be 1.
|
||||
|
||||
- #size-cells: specifies the number of cells used to represent the size
|
||||
of an address. The value must be 1.
|
||||
|
||||
- ranges: specifies the translation between child address space and parent
|
||||
address space
|
||||
|
||||
Optional properties:
|
||||
|
||||
- status: indicates the operational status of the device.
|
||||
Value must be either "disabled" or "okay".
|
||||
|
||||
2) Child nodes
|
||||
|
||||
The main node must have two child nodes which describes the built-in
|
||||
interrupt controller and the PCI host bridge.
|
||||
|
||||
a) Interrupt controller:
|
||||
|
||||
Required properties:
|
||||
|
||||
- interrupt-controller: identifies the node as an interrupt controller
|
||||
|
||||
- #address-cells: specifies the number of cells needed to encode an
|
||||
address. The value must be 0. As such, 'interrupt-map' nodes do not
|
||||
have to specify a parent unit address.
|
||||
|
||||
- #interrupt-cells: specifies the number of cells needed to encode an
|
||||
interrupt source. The value must be 1.
|
||||
|
||||
- interrupts: specifies the interrupt source of the parent interrupt
|
||||
controller. The format of the interrupt specifier depends on the
|
||||
parent interrupt controller.
|
||||
|
||||
b) PCI host bridge:
|
||||
|
||||
Required properties:
|
||||
|
||||
- #address-cells: specifies the number of cells needed to encode an
|
||||
address. The value must be 0.
|
||||
|
||||
- #size-cells: specifies the number of cells used to represent the size
|
||||
of an address. The value must be 2.
|
||||
|
||||
- #interrupt-cells: specifies the number of cells needed to encode an
|
||||
interrupt source. The value must be 1.
|
||||
|
||||
- device_type: must be "pci"
|
||||
|
||||
- bus-range: PCI bus numbers covered
|
||||
|
||||
- ranges: specifies the ranges for the PCI memory and I/O regions
|
||||
|
||||
- interrupt-map-mask,
|
||||
- interrupt-map: standard PCI properties to define the mapping of the
|
||||
PCI interface to interrupt numbers.
|
||||
|
||||
The PCI host bridge node might have additional sub-nodes representing
|
||||
the onboard PCI devices/PCI slots. Each such sub-node must have the
|
||||
following mandatory properties:
|
||||
|
||||
- reg: used only for interrupt mapping, so only the first four bytes
|
||||
are used to refer to the correct bus number and device number.
|
||||
|
||||
- device_type: must be "pci"
|
||||
|
||||
If a given sub-node represents a PCI bridge it must have following
|
||||
mandatory properties as well:
|
||||
|
||||
- #address-cells: must be set to <3>
|
||||
|
||||
- #size-cells: must set to <2>
|
||||
|
||||
- #interrupt-cells: must be set to <1>
|
||||
|
||||
- interrupt-map-mask,
|
||||
- interrupt-map: standard PCI properties to define the mapping of the
|
||||
PCI interface to interrupt numbers.
|
||||
|
||||
Besides the required properties the sub-nodes may have these optional
|
||||
properties:
|
||||
|
||||
- status: indicates the operational status of the sub-node.
|
||||
Value must be either "disabled" or "okay".
|
||||
|
||||
3) Example:
|
||||
|
||||
a) SoC specific dtsi file:
|
||||
|
||||
pci@10140000 {
|
||||
compatible = "ralink,rt3883-pci";
|
||||
reg = <0x10140000 0x20000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges; /* direct mapping */
|
||||
|
||||
status = "disabled";
|
||||
|
||||
pciintc: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpuintc>;
|
||||
interrupts = <4>;
|
||||
};
|
||||
|
||||
host-bridge {
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
device_type = "pci";
|
||||
|
||||
bus-range = <0 255>;
|
||||
ranges = <
|
||||
0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
|
||||
0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
|
||||
>;
|
||||
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 17 */
|
||||
0x8800 0 0 1 &pciintc 18
|
||||
0x8800 0 0 2 &pciintc 18
|
||||
0x8800 0 0 3 &pciintc 18
|
||||
0x8800 0 0 4 &pciintc 18
|
||||
/* IDSEL 18 */
|
||||
0x9000 0 0 1 &pciintc 19
|
||||
0x9000 0 0 2 &pciintc 19
|
||||
0x9000 0 0 3 &pciintc 19
|
||||
0x9000 0 0 4 &pciintc 19
|
||||
>;
|
||||
|
||||
pci-bridge@1 {
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
interrupt-map-mask = <0x0 0 0 0>;
|
||||
interrupt-map = <0x0 0 0 0 &pciintc 20>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pci-slot@17 {
|
||||
reg = <0x8800 0 0 0 0>;
|
||||
device_type = "pci";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pci-slot@18 {
|
||||
reg = <0x9000 0 0 0 0>;
|
||||
device_type = "pci";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
b) Board specific dts file:
|
||||
|
||||
pci@10140000 {
|
||||
status = "okay";
|
||||
|
||||
host-bridge {
|
||||
pci-bridge@1 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
93
bindings/pci/rcar-pci-ep.yaml
Normal file
93
bindings/pci/rcar-pci-ep.yaml
Normal file
@@ -0,0 +1,93 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2020 Renesas Electronics Europe GmbH - https://www.renesas.com/eu/en/
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/rcar-pci-ep.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas R-Car PCIe Endpoint
|
||||
|
||||
maintainers:
|
||||
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
|
||||
- Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- renesas,r8a774a1-pcie-ep # RZ/G2M
|
||||
- renesas,r8a774b1-pcie-ep # RZ/G2N
|
||||
- renesas,r8a774c0-pcie-ep # RZ/G2E
|
||||
- renesas,r8a774e1-pcie-ep # RZ/G2H
|
||||
- renesas,r8a7795-pcie-ep # R-Car H3
|
||||
- const: renesas,rcar-gen3-pcie-ep # R-Car Gen3 and RZ/G2
|
||||
|
||||
reg:
|
||||
maxItems: 5
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: apb-base
|
||||
- const: memory0
|
||||
- const: memory1
|
||||
- const: memory2
|
||||
- const: memory3
|
||||
|
||||
interrupts:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pcie
|
||||
|
||||
max-functions:
|
||||
minimum: 1
|
||||
maximum: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- interrupts
|
||||
- resets
|
||||
- power-domains
|
||||
- clocks
|
||||
- clock-names
|
||||
- max-functions
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/r8a774c0-sysc.h>
|
||||
|
||||
pcie0_ep: pcie-ep@fe000000 {
|
||||
compatible = "renesas,r8a774c0-pcie-ep",
|
||||
"renesas,rcar-gen3-pcie-ep";
|
||||
reg = <0xfe000000 0x80000>,
|
||||
<0xfe100000 0x100000>,
|
||||
<0xfe200000 0x200000>,
|
||||
<0x30000000 0x8000000>,
|
||||
<0x38000000 0x8000000>;
|
||||
reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
|
||||
resets = <&cpg 319>;
|
||||
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
|
||||
clocks = <&cpg CPG_MOD 319>;
|
||||
clock-names = "pcie";
|
||||
max-functions = /bits/ 8 <1>;
|
||||
};
|
||||
125
bindings/pci/rcar-pci-host.yaml
Normal file
125
bindings/pci/rcar-pci-host.yaml
Normal file
@@ -0,0 +1,125 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2020 Renesas Electronics Corp.
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/rcar-pci-host.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas R-Car PCIe Host
|
||||
|
||||
maintainers:
|
||||
- Marek Vasut <marek.vasut+renesas@gmail.com>
|
||||
- Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
|
||||
|
||||
allOf:
|
||||
- $ref: pci-bus.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: renesas,pcie-r8a7779 # R-Car H1
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,pcie-r8a7742 # RZ/G1H
|
||||
- renesas,pcie-r8a7743 # RZ/G1M
|
||||
- renesas,pcie-r8a7744 # RZ/G1N
|
||||
- renesas,pcie-r8a7790 # R-Car H2
|
||||
- renesas,pcie-r8a7791 # R-Car M2-W
|
||||
- renesas,pcie-r8a7793 # R-Car M2-N
|
||||
- const: renesas,pcie-rcar-gen2 # R-Car Gen2 and RZ/G1
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,pcie-r8a774a1 # RZ/G2M
|
||||
- renesas,pcie-r8a774b1 # RZ/G2N
|
||||
- renesas,pcie-r8a774c0 # RZ/G2E
|
||||
- renesas,pcie-r8a774e1 # RZ/G2H
|
||||
- renesas,pcie-r8a7795 # R-Car H3
|
||||
- renesas,pcie-r8a7796 # R-Car M3-W
|
||||
- renesas,pcie-r8a77961 # R-Car M3-W+
|
||||
- renesas,pcie-r8a77965 # R-Car M3-N
|
||||
- renesas,pcie-r8a77980 # R-Car V3H
|
||||
- renesas,pcie-r8a77990 # R-Car E3
|
||||
- const: renesas,pcie-rcar-gen3 # R-Car Gen3 and RZ/G2
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
|
||||
clocks:
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pcie
|
||||
- const: pcie_bus
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
phy-names:
|
||||
const: pcie
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- power-domains
|
||||
|
||||
if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: renesas,pcie-r8a7779
|
||||
then:
|
||||
required:
|
||||
- resets
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/r8a7791-cpg-mssr.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/r8a7791-sysc.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie: pcie@fe000000 {
|
||||
compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
|
||||
reg = <0 0xfe000000 0 0x80000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x00 0xff>;
|
||||
device_type = "pci";
|
||||
ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
|
||||
<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
|
||||
<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
|
||||
<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
|
||||
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>,
|
||||
<0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
|
||||
clock-names = "pcie", "pcie_bus";
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 319>;
|
||||
};
|
||||
};
|
||||
186
bindings/pci/renesas,pci-rcar-gen2.yaml
Normal file
186
bindings/pci/renesas,pci-rcar-gen2.yaml
Normal file
@@ -0,0 +1,186 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/renesas,pci-rcar-gen2.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas AHB to PCI bridge
|
||||
|
||||
maintainers:
|
||||
- Marek Vasut <marek.vasut+renesas@gmail.com>
|
||||
- Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
|
||||
|
||||
description: |
|
||||
This is the bridge used internally to connect the USB controllers to the
|
||||
AHB. There is one bridge instance per USB port connected to the internal
|
||||
OHCI and EHCI controllers.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,pci-r8a7742 # RZ/G1H
|
||||
- renesas,pci-r8a7743 # RZ/G1M
|
||||
- renesas,pci-r8a7744 # RZ/G1N
|
||||
- renesas,pci-r8a7745 # RZ/G1E
|
||||
- renesas,pci-r8a7790 # R-Car H2
|
||||
- renesas,pci-r8a7791 # R-Car M2-W
|
||||
- renesas,pci-r8a7793 # R-Car M2-N
|
||||
- renesas,pci-r8a7794 # R-Car E2
|
||||
- const: renesas,pci-rcar-gen2 # R-Car Gen2 and RZ/G1
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,pci-r9a06g032 # RZ/N1D
|
||||
- const: renesas,pci-rzn1 # RZ/N1
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Operational registers for the OHCI/EHCI controllers.
|
||||
- description: Bridge configuration and control registers.
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks: true
|
||||
|
||||
clock-names: true
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
bus-range:
|
||||
description: |
|
||||
The PCI bus number range; as this is a single bus, the range
|
||||
should be specified as the same value twice.
|
||||
|
||||
dma-ranges:
|
||||
description: |
|
||||
A single range for the inbound memory region. If not supplied,
|
||||
defaults to 1GiB at 0x40000000. Note there are hardware restrictions on
|
||||
the allowed combinations of address and size.
|
||||
maxItems: 1
|
||||
|
||||
patternProperties:
|
||||
'usb@[0-1],0':
|
||||
type: object
|
||||
|
||||
description:
|
||||
This a USB controller PCI device
|
||||
|
||||
properties:
|
||||
reg:
|
||||
description:
|
||||
Identify the correct bus, device and function number in the
|
||||
form <bdf 0 0 0 0>.
|
||||
|
||||
items:
|
||||
minItems: 5
|
||||
maxItems: 5
|
||||
|
||||
phys:
|
||||
description:
|
||||
Reference to the USB phy
|
||||
maxItems: 1
|
||||
|
||||
phy-names:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- reg
|
||||
- phys
|
||||
- phy-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- interrupt-map
|
||||
- interrupt-map-mask
|
||||
- clocks
|
||||
- power-domains
|
||||
- bus-range
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
- "#interrupt-cells"
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-bus.yaml#
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- renesas,pci-rzn1
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: Internal bus clock (AHB) for HOST
|
||||
- description: Internal bus clock (AHB) Power Management
|
||||
- description: PCI clock for USB subsystem
|
||||
clock-names:
|
||||
items:
|
||||
- const: hclkh
|
||||
- const: hclkpm
|
||||
- const: pciclk
|
||||
required:
|
||||
- clock-names
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: Device clock
|
||||
clock-names:
|
||||
items:
|
||||
- const: pclk
|
||||
required:
|
||||
- resets
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/r8a7790-cpg-mssr.h>
|
||||
#include <dt-bindings/power/r8a7790-sysc.h>
|
||||
|
||||
pci@ee090000 {
|
||||
compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
|
||||
device_type = "pci";
|
||||
reg = <0xee090000 0xc00>,
|
||||
<0xee080000 0x1100>;
|
||||
clocks = <&cpg CPG_MOD 703>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 703>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
bus-range = <0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x02000000 0 0xee080000 0xee080000 0 0x00010000>;
|
||||
dma-ranges = <0x42000000 0 0x40000000 0x40000000 0 0x40000000>;
|
||||
interrupt-map-mask = <0xf800 0 0 0x7>;
|
||||
interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
usb@1,0 {
|
||||
reg = <0x800 0 0 0 0>;
|
||||
phys = <&usb0 0>;
|
||||
phy-names = "usb";
|
||||
};
|
||||
|
||||
usb@2,0 {
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
phys = <&usb0 0>;
|
||||
phy-names = "usb";
|
||||
};
|
||||
};
|
||||
131
bindings/pci/rockchip-dw-pcie.yaml
Normal file
131
bindings/pci/rockchip-dw-pcie.yaml
Normal file
@@ -0,0 +1,131 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: DesignWare based PCIe controller on Rockchip SoCs
|
||||
|
||||
maintainers:
|
||||
- Shawn Lin <shawn.lin@rock-chips.com>
|
||||
- Simon Xue <xxm@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |+
|
||||
RK3568 SoC PCIe host controller is based on the Synopsys DesignWare
|
||||
PCIe IP and thus inherits all the common properties defined in
|
||||
designware-pcie.txt.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-bus.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: rockchip,rk3568-pcie
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Data Bus Interface (DBI) registers
|
||||
- description: Rockchip designed configuration registers
|
||||
- description: Config registers
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dbi
|
||||
- const: apb
|
||||
- const: config
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: AHB clock for PCIe master
|
||||
- description: AHB clock for PCIe slave
|
||||
- description: AHB clock for PCIe dbi
|
||||
- description: APB clock for PCIe
|
||||
- description: Auxiliary clock for PCIe
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: aclk_mst
|
||||
- const: aclk_slv
|
||||
- const: aclk_dbi
|
||||
- const: pclk
|
||||
- const: aux
|
||||
|
||||
msi-map: true
|
||||
|
||||
num-lanes: true
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
phy-names:
|
||||
const: pcie-phy
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
ranges:
|
||||
maxItems: 2
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
const: pipe
|
||||
|
||||
vpcie3v3-supply: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- clock-names
|
||||
- msi-map
|
||||
- num-lanes
|
||||
- phys
|
||||
- phy-names
|
||||
- power-domains
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie3x2: pcie@fe280000 {
|
||||
compatible = "rockchip,rk3568-pcie";
|
||||
reg = <0x3 0xc0800000 0x0 0x390000>,
|
||||
<0x0 0xfe280000 0x0 0x10000>,
|
||||
<0x3 0x80000000 0x0 0x100000>;
|
||||
reg-names = "dbi", "apb", "config";
|
||||
bus-range = <0x20 0x2f>;
|
||||
clocks = <&cru 143>, <&cru 144>,
|
||||
<&cru 145>, <&cru 146>,
|
||||
<&cru 147>;
|
||||
clock-names = "aclk_mst", "aclk_slv",
|
||||
"aclk_dbi", "pclk",
|
||||
"aux";
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <2>;
|
||||
max-link-speed = <2>;
|
||||
msi-map = <0x2000 &its 0x2000 0x1000>;
|
||||
num-lanes = <2>;
|
||||
phys = <&pcie30phy>;
|
||||
phy-names = "pcie-phy";
|
||||
power-domains = <&power 15>;
|
||||
ranges = <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>,
|
||||
<0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
|
||||
resets = <&cru 193>;
|
||||
reset-names = "pipe";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
};
|
||||
};
|
||||
...
|
||||
62
bindings/pci/rockchip-pcie-ep.txt
Normal file
62
bindings/pci/rockchip-pcie-ep.txt
Normal file
@@ -0,0 +1,62 @@
|
||||
* Rockchip AXI PCIe Endpoint Controller DT description
|
||||
|
||||
Required properties:
|
||||
- compatible: Should contain "rockchip,rk3399-pcie-ep"
|
||||
- reg: Two register ranges as listed in the reg-names property
|
||||
- reg-names: Must include the following names
|
||||
- "apb-base"
|
||||
- "mem-base"
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: Must include the following entries:
|
||||
- "aclk"
|
||||
- "aclk-perf"
|
||||
- "hclk"
|
||||
- "pm"
|
||||
- resets: Must contain seven entries for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following names
|
||||
- "core"
|
||||
- "mgmt"
|
||||
- "mgmt-sticky"
|
||||
- "pipe"
|
||||
- "pm"
|
||||
- "aclk"
|
||||
- "pclk"
|
||||
- pinctrl-names : The pin control state names
|
||||
- pinctrl-0: The "default" pinctrl state
|
||||
- phys: Must contain an phandle to a PHY for each entry in phy-names.
|
||||
- phy-names: Must include 4 entries for all 4 lanes even if some of
|
||||
them won't be used for your cases. Entries are of the form "pcie-phy-N":
|
||||
where N ranges from 0 to 3.
|
||||
(see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
|
||||
for changing the #phy-cells of phy node to support it)
|
||||
- rockchip,max-outbound-regions: Maximum number of outbound regions
|
||||
|
||||
Optional Property:
|
||||
- num-lanes: number of lanes to use
|
||||
- max-functions: Maximum number of functions that can be configured (default 1).
|
||||
|
||||
pcie0-ep: pcie@f8000000 {
|
||||
compatible = "rockchip,rk3399-pcie-ep";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
rockchip,max-outbound-regions = <16>;
|
||||
clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
|
||||
<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
|
||||
clock-names = "aclk", "aclk-perf",
|
||||
"hclk", "pm";
|
||||
max-functions = /bits/ 8 <8>;
|
||||
num-lanes = <4>;
|
||||
reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0x80000000 0x0 0x20000>;
|
||||
reg-names = "apb-base", "mem-base";
|
||||
resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
|
||||
<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
|
||||
<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
|
||||
reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
|
||||
"pm", "pclk", "aclk";
|
||||
phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
|
||||
phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_clkreq>;
|
||||
};
|
||||
135
bindings/pci/rockchip-pcie-host.txt
Normal file
135
bindings/pci/rockchip-pcie-host.txt
Normal file
@@ -0,0 +1,135 @@
|
||||
* Rockchip AXI PCIe Root Port Bridge DT description
|
||||
|
||||
Required properties:
|
||||
- #address-cells: Address representation for root ports, set to <3>
|
||||
- #size-cells: Size representation for root ports, set to <2>
|
||||
- #interrupt-cells: specifies the number of cells needed to encode an
|
||||
interrupt source. The value must be 1.
|
||||
- compatible: Should contain "rockchip,rk3399-pcie"
|
||||
- reg: Two register ranges as listed in the reg-names property
|
||||
- reg-names: Must include the following names
|
||||
- "axi-base"
|
||||
- "apb-base"
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: Must include the following entries:
|
||||
- "aclk"
|
||||
- "aclk-perf"
|
||||
- "hclk"
|
||||
- "pm"
|
||||
- msi-map: Maps a Requester ID to an MSI controller and associated
|
||||
msi-specifier data. See ./pci-msi.txt
|
||||
- interrupts: Three interrupt entries must be specified.
|
||||
- interrupt-names: Must include the following names
|
||||
- "sys"
|
||||
- "legacy"
|
||||
- "client"
|
||||
- resets: Must contain seven entries for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following names
|
||||
- "core"
|
||||
- "mgmt"
|
||||
- "mgmt-sticky"
|
||||
- "pipe"
|
||||
- "pm"
|
||||
- "aclk"
|
||||
- "pclk"
|
||||
- pinctrl-names : The pin control state names
|
||||
- pinctrl-0: The "default" pinctrl state
|
||||
- #interrupt-cells: specifies the number of cells needed to encode an
|
||||
interrupt source. The value must be 1.
|
||||
- interrupt-map-mask and interrupt-map: standard PCI properties
|
||||
|
||||
Required properties for legacy PHY model (deprecated):
|
||||
- phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
|
||||
- phy-names: MUST be "pcie-phy".
|
||||
|
||||
Required properties for per-lane PHY model (preferred):
|
||||
- phys: Must contain an phandle to a PHY for each entry in phy-names.
|
||||
- phy-names: Must include 4 entries for all 4 lanes even if some of
|
||||
them won't be used for your cases. Entries are of the form "pcie-phy-N":
|
||||
where N ranges from 0 to 3.
|
||||
(see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
|
||||
for changing the #phy-cells of phy node to support it)
|
||||
|
||||
Optional Property:
|
||||
- aspm-no-l0s: RC won't support ASPM L0s. This property is needed if
|
||||
using 24MHz OSC for RC's PHY.
|
||||
- ep-gpios: contain the entry for pre-reset GPIO
|
||||
- num-lanes: number of lanes to use
|
||||
- vpcie12v-supply: The phandle to the 12v regulator to use for PCIe.
|
||||
- vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
|
||||
- vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe.
|
||||
- vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe.
|
||||
|
||||
*Interrupt controller child node*
|
||||
The core controller provides a single interrupt for legacy INTx. The PCIe node
|
||||
should contain an interrupt controller node as a target for the PCI
|
||||
'interrupt-map' property. This node represents the domain at which the four
|
||||
INTx interrupts are decoded and routed.
|
||||
|
||||
|
||||
Required properties for Interrupt controller child node:
|
||||
- interrupt-controller: identifies the node as an interrupt controller
|
||||
- #address-cells: specifies the number of cells needed to encode an
|
||||
address. The value must be 0.
|
||||
- #interrupt-cells: specifies the number of cells needed to encode an
|
||||
interrupt source. The value must be 1.
|
||||
|
||||
Example:
|
||||
|
||||
pcie0: pcie@f8000000 {
|
||||
compatible = "rockchip,rk3399-pcie";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
|
||||
<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
|
||||
clock-names = "aclk", "aclk-perf",
|
||||
"hclk", "pm";
|
||||
bus-range = <0x0 0x1>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "sys", "legacy", "client";
|
||||
assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
|
||||
assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
|
||||
ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
|
||||
0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
|
||||
num-lanes = <4>;
|
||||
msi-map = <0x0 &its 0x0 0x1000>;
|
||||
reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
|
||||
reg-names = "axi-base", "apb-base";
|
||||
resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
|
||||
<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
|
||||
<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
|
||||
reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
|
||||
"pm", "pclk", "aclk";
|
||||
/* deprecated legacy PHY model */
|
||||
phys = <&pcie_phy>;
|
||||
phy-names = "pcie-phy";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_clkreq>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie0_intc 0>,
|
||||
<0 0 0 2 &pcie0_intc 1>,
|
||||
<0 0 0 3 &pcie0_intc 2>,
|
||||
<0 0 0 4 &pcie0_intc 3>;
|
||||
pcie0_intc: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie0: pcie@f8000000 {
|
||||
...
|
||||
|
||||
/* preferred per-lane PHY model */
|
||||
phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
|
||||
phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
|
||||
|
||||
...
|
||||
};
|
||||
119
bindings/pci/samsung,exynos-pcie.yaml
Normal file
119
bindings/pci/samsung,exynos-pcie.yaml
Normal file
@@ -0,0 +1,119 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung SoC series PCIe Host Controller
|
||||
|
||||
maintainers:
|
||||
- Marek Szyprowski <m.szyprowski@samsung.com>
|
||||
- Jaehoon Chung <jh80.chung@samsung.com>
|
||||
|
||||
description: |+
|
||||
Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare
|
||||
PCIe IP and thus inherits all the common properties defined in
|
||||
snps,dw-pcie.yaml.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/snps,dw-pcie.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: samsung,exynos5433-pcie
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Data Bus Interface (DBI) registers.
|
||||
- description: External Local Bus interface (ELBI) registers.
|
||||
- description: PCIe configuration space region.
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dbi
|
||||
- const: elbi
|
||||
- const: config
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: PCIe bridge clock
|
||||
- description: PCIe bus clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pcie
|
||||
- const: pcie_bus
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
vdd10-supply:
|
||||
description:
|
||||
Phandle to a regulator that provides 1.0V power to the PCIe block.
|
||||
|
||||
vdd18-supply:
|
||||
description:
|
||||
Phandle to a regulator that provides 1.8V power to the PCIe block.
|
||||
|
||||
num-lanes:
|
||||
const: 1
|
||||
|
||||
num-viewport:
|
||||
const: 3
|
||||
|
||||
required:
|
||||
- reg
|
||||
- reg-names
|
||||
- interrupts
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
- "#interrupt-cells"
|
||||
- interrupt-map
|
||||
- interrupt-map-mask
|
||||
- ranges
|
||||
- bus-range
|
||||
- device_type
|
||||
- num-lanes
|
||||
- num-viewport
|
||||
- clocks
|
||||
- clock-names
|
||||
- phys
|
||||
- vdd10-supply
|
||||
- vdd18-supply
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/exynos5433.h>
|
||||
|
||||
pcie: pcie@15700000 {
|
||||
compatible = "samsung,exynos5433-pcie";
|
||||
reg = <0x15700000 0x1000>, <0x156b0000 0x1000>, <0x0c000000 0x1000>;
|
||||
reg-names = "dbi", "elbi", "config";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
device_type = "pci";
|
||||
interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cmu_fsys CLK_PCIE>, <&cmu_fsys CLK_PCLK_PCIE_PHY>;
|
||||
clock-names = "pcie", "pcie_bus";
|
||||
phys = <&pcie_phy>;
|
||||
pinctrl-0 = <&pcie_bus &pcie_wlanen>;
|
||||
pinctrl-names = "default";
|
||||
num-lanes = <1>;
|
||||
num-viewport = <3>;
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>,
|
||||
<0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>;
|
||||
vdd10-supply = <&ldo6_reg>;
|
||||
vdd18-supply = <&ldo7_reg>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
...
|
||||
120
bindings/pci/sifive,fu740-pcie.yaml
Normal file
120
bindings/pci/sifive,fu740-pcie.yaml
Normal file
@@ -0,0 +1,120 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/sifive,fu740-pcie.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: SiFive FU740 PCIe host controller
|
||||
|
||||
description: |+
|
||||
SiFive FU740 PCIe host controller is based on the Synopsys DesignWare
|
||||
PCI core. It shares common features with the PCIe DesignWare core and
|
||||
inherits common properties defined in
|
||||
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
|
||||
|
||||
maintainers:
|
||||
- Paul Walmsley <paul.walmsley@sifive.com>
|
||||
- Greentime Hu <greentime.hu@sifive.com>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/snps,dw-pcie.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: sifive,fu740-pcie
|
||||
|
||||
reg:
|
||||
maxItems: 3
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dbi
|
||||
- const: config
|
||||
- const: mgmt
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
num-lanes:
|
||||
const: 8
|
||||
|
||||
msi-parent: true
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi
|
||||
- const: inta
|
||||
- const: intb
|
||||
- const: intc
|
||||
- const: intd
|
||||
|
||||
resets:
|
||||
description: A phandle to the PCIe power up reset line.
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: pcie_aux
|
||||
|
||||
pwren-gpios:
|
||||
description: Should specify the GPIO for controlling the PCI bus device power on.
|
||||
maxItems: 1
|
||||
|
||||
reset-gpios:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- dma-coherent
|
||||
- num-lanes
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- interrupt-map-mask
|
||||
- interrupt-map
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- pwren-gpios
|
||||
- reset-gpios
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
#include <dt-bindings/clock/sifive-fu740-prci.h>
|
||||
|
||||
pcie@e00000000 {
|
||||
compatible = "sifive,fu740-pcie";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0xe 0x00000000 0x0 0x80000000>,
|
||||
<0xd 0xf0000000 0x0 0x10000000>,
|
||||
<0x0 0x100d0000 0x0 0x1000>;
|
||||
reg-names = "dbi", "config", "mgmt";
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */
|
||||
<0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */
|
||||
<0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000>, /* mem */
|
||||
<0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */
|
||||
num-lanes = <0x8>;
|
||||
interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>;
|
||||
interrupt-names = "msi", "inta", "intb", "intc", "intd";
|
||||
interrupt-parent = <&plic0>;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
|
||||
<0x0 0x0 0x0 0x2 &plic0 58>,
|
||||
<0x0 0x0 0x0 0x3 &plic0 59>,
|
||||
<0x0 0x0 0x0 0x4 &plic0 60>;
|
||||
clock-names = "pcie_aux";
|
||||
clocks = <&prci FU740_PRCI_CLK_PCIE_AUX>;
|
||||
resets = <&prci 4>;
|
||||
pwren-gpios = <&gpio 5 0>;
|
||||
reset-gpios = <&gpio 8 0>;
|
||||
};
|
||||
};
|
||||
88
bindings/pci/snps,dw-pcie-ep.yaml
Normal file
88
bindings/pci/snps,dw-pcie-ep.yaml
Normal file
@@ -0,0 +1,88 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Synopsys DesignWare PCIe endpoint interface
|
||||
|
||||
maintainers:
|
||||
- Jingoo Han <jingoohan1@gmail.com>
|
||||
- Gustavo Pimentel <gustavo.pimentel@synopsys.com>
|
||||
|
||||
description: |
|
||||
Synopsys DesignWare PCIe host controller endpoint
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-ep.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
anyOf:
|
||||
- {}
|
||||
- const: snps,dw-pcie-ep
|
||||
|
||||
reg:
|
||||
description: |
|
||||
It should contain Data Bus Interface (dbi) and config registers for all
|
||||
versions.
|
||||
For designware core version >= 4.80, it may contain ATU address space.
|
||||
minItems: 2
|
||||
maxItems: 4
|
||||
|
||||
reg-names:
|
||||
minItems: 2
|
||||
maxItems: 4
|
||||
items:
|
||||
enum: [dbi, dbi2, config, atu, addr_space, link, atu_dma, appl]
|
||||
|
||||
reset-gpio:
|
||||
description: GPIO pin number of PERST# signal
|
||||
maxItems: 1
|
||||
deprecated: true
|
||||
|
||||
reset-gpios:
|
||||
description: GPIO controlled connection to PERST# signal
|
||||
maxItems: 1
|
||||
|
||||
snps,enable-cdm-check:
|
||||
type: boolean
|
||||
description: |
|
||||
This is a boolean property and if present enables
|
||||
automatic checking of CDM (Configuration Dependent Module) registers
|
||||
for data corruption. CDM registers include standard PCIe configuration
|
||||
space registers, Port Logic registers, DMA and iATU (internal Address
|
||||
Translation Unit) registers.
|
||||
|
||||
num-ib-windows:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 256
|
||||
description: number of inbound address translation windows
|
||||
deprecated: true
|
||||
|
||||
num-ob-windows:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 256
|
||||
description: number of outbound address translation windows
|
||||
deprecated: true
|
||||
|
||||
required:
|
||||
- reg
|
||||
- reg-names
|
||||
- compatible
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
examples:
|
||||
- |
|
||||
bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
pcie-ep@dfd00000 {
|
||||
compatible = "snps,dw-pcie-ep";
|
||||
reg = <0xdfc00000 0x0001000>, /* IP registers 1 */
|
||||
<0xdfc01000 0x0001000>, /* IP registers 2 */
|
||||
<0xd0000000 0x2000000>; /* Configuration space */
|
||||
reg-names = "dbi", "dbi2", "addr_space";
|
||||
};
|
||||
};
|
||||
104
bindings/pci/snps,dw-pcie.yaml
Normal file
104
bindings/pci/snps,dw-pcie.yaml
Normal file
@@ -0,0 +1,104 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Synopsys DesignWare PCIe interface
|
||||
|
||||
maintainers:
|
||||
- Jingoo Han <jingoohan1@gmail.com>
|
||||
- Gustavo Pimentel <gustavo.pimentel@synopsys.com>
|
||||
|
||||
description: |
|
||||
Synopsys DesignWare PCIe host controller
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-bus.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
anyOf:
|
||||
- {}
|
||||
- const: snps,dw-pcie
|
||||
|
||||
reg:
|
||||
description: |
|
||||
It should contain Data Bus Interface (dbi) and config registers for all
|
||||
versions.
|
||||
For designware core version >= 4.80, it may contain ATU address space.
|
||||
minItems: 2
|
||||
maxItems: 5
|
||||
|
||||
reg-names:
|
||||
minItems: 2
|
||||
maxItems: 5
|
||||
items:
|
||||
enum: [ dbi, dbi2, config, atu, atu_dma, app, appl, elbi, mgmt, ctrl,
|
||||
parf, cfg, link, ulreg, smu, mpu, apb, phy, ecam ]
|
||||
|
||||
num-lanes:
|
||||
description: |
|
||||
number of lanes to use (this property should be specified unless
|
||||
the link is brought already up in firmware)
|
||||
maximum: 16
|
||||
|
||||
reset-gpio:
|
||||
description: GPIO pin number of PERST# signal
|
||||
maxItems: 1
|
||||
deprecated: true
|
||||
|
||||
reset-gpios:
|
||||
description: GPIO controlled connection to PERST# signal
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
|
||||
interrupt-names: true
|
||||
|
||||
clocks: true
|
||||
|
||||
snps,enable-cdm-check:
|
||||
type: boolean
|
||||
description: |
|
||||
This is a boolean property and if present enables
|
||||
automatic checking of CDM (Configuration Dependent Module) registers
|
||||
for data corruption. CDM registers include standard PCIe configuration
|
||||
space registers, Port Logic registers, DMA and iATU (internal Address
|
||||
Translation Unit) registers.
|
||||
|
||||
num-viewport:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 256
|
||||
description: |
|
||||
number of view ports configured in hardware. If a platform
|
||||
does not specify it, the driver autodetects it.
|
||||
deprecated: true
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
required:
|
||||
- reg
|
||||
- reg-names
|
||||
- compatible
|
||||
|
||||
examples:
|
||||
- |
|
||||
bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
pcie@dfc00000 {
|
||||
device_type = "pci";
|
||||
compatible = "snps,dw-pcie";
|
||||
reg = <0xdfc00000 0x0001000>, /* IP registers */
|
||||
<0xd0000000 0x0002000>; /* Configuration space */
|
||||
reg-names = "dbi", "config";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,
|
||||
<0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
|
||||
interrupts = <25>, <24>;
|
||||
#interrupt-cells = <1>;
|
||||
num-lanes = <1>;
|
||||
};
|
||||
};
|
||||
108
bindings/pci/socionext,uniphier-pcie-ep.yaml
Normal file
108
bindings/pci/socionext,uniphier-pcie-ep.yaml
Normal file
@@ -0,0 +1,108 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Socionext UniPhier PCIe endpoint controller
|
||||
|
||||
description: |
|
||||
UniPhier PCIe endpoint controller is based on the Synopsys DesignWare
|
||||
PCI core. It shares common features with the PCIe DesignWare core and
|
||||
inherits common properties defined in
|
||||
Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml.
|
||||
|
||||
maintainers:
|
||||
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- socionext,uniphier-pro5-pcie-ep
|
||||
- socionext,uniphier-nx1-pcie-ep
|
||||
|
||||
reg:
|
||||
minItems: 4
|
||||
maxItems: 5
|
||||
|
||||
reg-names:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: dbi
|
||||
- const: dbi2
|
||||
- const: link
|
||||
- const: addr_space
|
||||
- items:
|
||||
- const: dbi
|
||||
- const: dbi2
|
||||
- const: link
|
||||
- const: addr_space
|
||||
- const: atu
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
oneOf:
|
||||
- items: # for Pro5
|
||||
- const: gio
|
||||
- const: link
|
||||
- const: link # for NX1
|
||||
|
||||
resets:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
reset-names:
|
||||
oneOf:
|
||||
- items: # for Pro5
|
||||
- const: gio
|
||||
- const: link
|
||||
- const: link # for NX1
|
||||
|
||||
num-ib-windows:
|
||||
const: 16
|
||||
|
||||
num-ob-windows:
|
||||
const: 16
|
||||
|
||||
num-lanes: true
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
phy-names:
|
||||
const: pcie-phy
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
pcie_ep: pcie-ep@66000000 {
|
||||
compatible = "socionext,uniphier-pro5-pcie-ep";
|
||||
reg-names = "dbi", "dbi2", "link", "addr_space";
|
||||
reg = <0x66000000 0x1000>, <0x66001000 0x1000>,
|
||||
<0x66010000 0x10000>, <0x67000000 0x400000>;
|
||||
clock-names = "gio", "link";
|
||||
clocks = <&sys_clk 12>, <&sys_clk 24>;
|
||||
reset-names = "gio", "link";
|
||||
resets = <&sys_rst 12>, <&sys_rst 24>;
|
||||
num-ib-windows = <16>;
|
||||
num-ob-windows = <16>;
|
||||
num-lanes = <4>;
|
||||
phy-names = "pcie-phy";
|
||||
phys = <&pcie_phy>;
|
||||
};
|
||||
117
bindings/pci/socionext,uniphier-pcie.yaml
Normal file
117
bindings/pci/socionext,uniphier-pcie.yaml
Normal file
@@ -0,0 +1,117 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Socionext UniPhier PCIe host controller
|
||||
|
||||
description: |
|
||||
UniPhier PCIe host controller is based on the Synopsys DesignWare
|
||||
PCI core. It shares common features with the PCIe DesignWare core and
|
||||
inherits common properties defined in
|
||||
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
|
||||
|
||||
maintainers:
|
||||
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/snps,dw-pcie.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- socionext,uniphier-pcie
|
||||
|
||||
reg:
|
||||
minItems: 3
|
||||
maxItems: 4
|
||||
|
||||
reg-names:
|
||||
minItems: 3
|
||||
items:
|
||||
- const: dbi
|
||||
- const: link
|
||||
- const: config
|
||||
- const: atu
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
num-viewport: true
|
||||
|
||||
num-lanes: true
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
phy-names:
|
||||
const: pcie-phy
|
||||
|
||||
interrupt-controller:
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
interrupt-controller: true
|
||||
|
||||
'#interrupt-cells':
|
||||
const: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- resets
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
bus {
|
||||
gic: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie: pcie@66000000 {
|
||||
compatible = "socionext,uniphier-pcie";
|
||||
reg-names = "dbi", "link", "config";
|
||||
reg = <0x66000000 0x1000>, <0x66010000 0x10000>, <0x2fff0000 0x10000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
clocks = <&sys_clk 24>;
|
||||
resets = <&sys_rst 24>;
|
||||
num-lanes = <1>;
|
||||
num-viewport = <1>;
|
||||
bus-range = <0x0 0xff>;
|
||||
device_type = "pci";
|
||||
ranges = <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
|
||||
<0x82000000 0 0x00000000 0x20000000 0 0x0ffe0000>;
|
||||
phy-names = "pcie-phy";
|
||||
phys = <&pcie_phy>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-names = "dma", "msi";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 224 4>, <0 225 4>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc 0>,
|
||||
<0 0 0 2 &pcie_intc 1>,
|
||||
<0 0 0 3 &pcie_intc 2>,
|
||||
<0 0 0 4 &pcie_intc 3>;
|
||||
|
||||
pcie_intc: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 226 4>;
|
||||
};
|
||||
};
|
||||
14
bindings/pci/spear13xx-pcie.txt
Normal file
14
bindings/pci/spear13xx-pcie.txt
Normal file
@@ -0,0 +1,14 @@
|
||||
SPEAr13XX PCIe DT detail:
|
||||
================================
|
||||
|
||||
SPEAr13XX uses the Synopsys DesignWare PCIe controller and ST MiPHY as PHY
|
||||
controller.
|
||||
|
||||
Required properties:
|
||||
- compatible : should be "st,spear1340-pcie", "snps,dw-pcie".
|
||||
- phys : phandle to PHY node associated with PCIe controller
|
||||
- phy-names : must be "pcie-phy"
|
||||
- All other definitions as per generic PCI bindings
|
||||
|
||||
Optional properties:
|
||||
- st,pcie-is-gen1 indicates that forced gen1 initialization is needed.
|
||||
76
bindings/pci/ti,am65-pci-ep.yaml
Normal file
76
bindings/pci/ti,am65-pci-ep.yaml
Normal file
@@ -0,0 +1,76 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/ti,am65-pci-ep.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: TI AM65 PCI Endpoint
|
||||
|
||||
maintainers:
|
||||
- Kishon Vijay Abraham I <kishon@ti.com>
|
||||
|
||||
allOf:
|
||||
- $ref: pci-ep.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- ti,am654-pcie-ep
|
||||
|
||||
reg:
|
||||
maxItems: 4
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: app
|
||||
- const: dbics
|
||||
- const: addr_space
|
||||
- const: atu
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
ti,syscon-pcie-mode:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
- items:
|
||||
- description: Phandle to the SYSCON entry
|
||||
- description: pcie_ctrl register offset within SYSCON
|
||||
description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode.
|
||||
|
||||
interrupts:
|
||||
minItems: 1
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- max-link-speed
|
||||
- power-domains
|
||||
- ti,syscon-pcie-mode
|
||||
- dma-coherent
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/soc/ti,sci_pm_domain.h>
|
||||
|
||||
pcie0_ep: pcie-ep@5500000 {
|
||||
compatible = "ti,am654-pcie-ep";
|
||||
reg = <0x5500000 0x1000>,
|
||||
<0x5501000 0x1000>,
|
||||
<0x10000000 0x8000000>,
|
||||
<0x5506000 0x1000>;
|
||||
reg-names = "app", "dbics", "addr_space", "atu";
|
||||
power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
|
||||
ti,syscon-pcie-mode = <&scm_conf 0x4060>;
|
||||
max-link-speed = <2>;
|
||||
dma-coherent;
|
||||
interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
106
bindings/pci/ti,am65-pci-host.yaml
Normal file
106
bindings/pci/ti,am65-pci-host.yaml
Normal file
@@ -0,0 +1,106 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/ti,am65-pci-host.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: TI AM65 PCI Host
|
||||
|
||||
maintainers:
|
||||
- Kishon Vijay Abraham I <kishon@ti.com>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-bus.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- ti,am654-pcie-rc
|
||||
- ti,keystone-pcie
|
||||
|
||||
reg:
|
||||
maxItems: 4
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: app
|
||||
- const: dbics
|
||||
- const: config
|
||||
- const: atu
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
ti,syscon-pcie-id:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
- items:
|
||||
- description: Phandle to the SYSCON entry
|
||||
- description: pcie_device_id register offset within SYSCON
|
||||
description: Phandle to the SYSCON entry required for getting PCIe device/vendor ID
|
||||
|
||||
ti,syscon-pcie-mode:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
- items:
|
||||
- description: Phandle to the SYSCON entry
|
||||
- description: pcie_ctrl register offset within SYSCON
|
||||
description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode.
|
||||
|
||||
msi-map: true
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- max-link-speed
|
||||
- ti,syscon-pcie-id
|
||||
- ti,syscon-pcie-mode
|
||||
- ranges
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- ti,am654-pcie-rc
|
||||
then:
|
||||
required:
|
||||
- dma-coherent
|
||||
- power-domains
|
||||
- msi-map
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/soc/ti,sci_pm_domain.h>
|
||||
|
||||
pcie0_rc: pcie@5500000 {
|
||||
compatible = "ti,am654-pcie-rc";
|
||||
reg = <0x5500000 0x1000>,
|
||||
<0x5501000 0x1000>,
|
||||
<0x10000000 0x2000>,
|
||||
<0x5506000 0x1000>;
|
||||
reg-names = "app", "dbics", "config", "atu";
|
||||
power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x81000000 0 0 0x10020000 0 0x00010000>,
|
||||
<0x82000000 0 0x10030000 0x10030000 0 0x07FD0000>;
|
||||
ti,syscon-pcie-id = <&scm_conf 0x0210>;
|
||||
ti,syscon-pcie-mode = <&scm_conf 0x4060>;
|
||||
bus-range = <0x0 0xff>;
|
||||
max-link-speed = <2>;
|
||||
dma-coherent;
|
||||
interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
|
||||
msi-map = <0x0 &gic_its 0x0 0x10000>;
|
||||
device_type = "pci";
|
||||
};
|
||||
103
bindings/pci/ti,j721e-pci-ep.yaml
Normal file
103
bindings/pci/ti,j721e-pci-ep.yaml
Normal file
@@ -0,0 +1,103 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: TI J721E PCI EP (PCIe Wrapper)
|
||||
|
||||
maintainers:
|
||||
- Kishon Vijay Abraham I <kishon@ti.com>
|
||||
|
||||
allOf:
|
||||
- $ref: "cdns-pcie-ep.yaml#"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: ti,j721e-pcie-ep
|
||||
- description: PCIe EP controller in AM64
|
||||
items:
|
||||
- const: ti,am64-pcie-ep
|
||||
- const: ti,j721e-pcie-ep
|
||||
- description: PCIe EP controller in J7200
|
||||
items:
|
||||
- const: ti,j7200-pcie-ep
|
||||
- const: ti,j721e-pcie-ep
|
||||
|
||||
reg:
|
||||
maxItems: 4
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: intd_cfg
|
||||
- const: user_cfg
|
||||
- const: reg
|
||||
- const: mem
|
||||
|
||||
ti,syscon-pcie-ctrl:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
- items:
|
||||
- description: Phandle to the SYSCON entry
|
||||
- description: pcie_ctrl register offset within SYSCON
|
||||
description: Specifier for configuring PCIe mode and link speed.
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
description: clock-specifier to represent input to the PCIe
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: fck
|
||||
|
||||
dma-coherent:
|
||||
description: Indicates that the PCIe IP block can ensure the coherency
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- ti,syscon-pcie-ctrl
|
||||
- max-link-speed
|
||||
- num-lanes
|
||||
- power-domains
|
||||
- clocks
|
||||
- clock-names
|
||||
- max-functions
|
||||
- phys
|
||||
- phy-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/soc/ti,sci_pm_domain.h>
|
||||
|
||||
bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie0_ep: pcie-ep@d000000 {
|
||||
compatible = "ti,j721e-pcie-ep";
|
||||
reg = <0x00 0x02900000 0x00 0x1000>,
|
||||
<0x00 0x02907000 0x00 0x400>,
|
||||
<0x00 0x0d000000 0x00 0x00800000>,
|
||||
<0x00 0x10000000 0x00 0x08000000>;
|
||||
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
|
||||
ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <2>;
|
||||
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 239 1>;
|
||||
clock-names = "fck";
|
||||
max-functions = /bits/ 8 <6>;
|
||||
dma-coherent;
|
||||
phys = <&serdes0_pcie_link>;
|
||||
phy-names = "pcie-phy";
|
||||
};
|
||||
};
|
||||
137
bindings/pci/ti,j721e-pci-host.yaml
Normal file
137
bindings/pci/ti,j721e-pci-host.yaml
Normal file
@@ -0,0 +1,137 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: TI J721E PCI Host (PCIe Wrapper)
|
||||
|
||||
maintainers:
|
||||
- Kishon Vijay Abraham I <kishon@ti.com>
|
||||
|
||||
allOf:
|
||||
- $ref: "cdns-pcie-host.yaml#"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: ti,j721e-pcie-host
|
||||
- description: PCIe controller in AM64
|
||||
items:
|
||||
- const: ti,am64-pcie-host
|
||||
- const: ti,j721e-pcie-host
|
||||
- description: PCIe controller in J7200
|
||||
items:
|
||||
- const: ti,j7200-pcie-host
|
||||
- const: ti,j721e-pcie-host
|
||||
|
||||
reg:
|
||||
maxItems: 4
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: intd_cfg
|
||||
- const: user_cfg
|
||||
- const: reg
|
||||
- const: cfg
|
||||
|
||||
ti,syscon-pcie-ctrl:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
- items:
|
||||
- description: Phandle to the SYSCON entry
|
||||
- description: pcie_ctrl register offset within SYSCON
|
||||
description: Specifier for configuring PCIe mode and link speed.
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
description: |+
|
||||
clock-specifier to represent input to the PCIe for 1 item.
|
||||
2nd item if present represents reference clock to the connector.
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: fck
|
||||
- const: pcie_refclk
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
vendor-id:
|
||||
const: 0x104c
|
||||
|
||||
device-id:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: 0xb00d
|
||||
- items:
|
||||
- const: 0xb00f
|
||||
- items:
|
||||
- const: 0xb010
|
||||
|
||||
msi-map: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- ti,syscon-pcie-ctrl
|
||||
- max-link-speed
|
||||
- num-lanes
|
||||
- power-domains
|
||||
- clocks
|
||||
- clock-names
|
||||
- vendor-id
|
||||
- device-id
|
||||
- msi-map
|
||||
- dma-ranges
|
||||
- ranges
|
||||
- reset-gpios
|
||||
- phys
|
||||
- phy-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/soc/ti,sci_pm_domain.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie0_rc: pcie@2900000 {
|
||||
compatible = "ti,j721e-pcie-host";
|
||||
reg = <0x00 0x02900000 0x00 0x1000>,
|
||||
<0x00 0x02907000 0x00 0x400>,
|
||||
<0x00 0x0d000000 0x00 0x00800000>,
|
||||
<0x00 0x10000000 0x00 0x00001000>;
|
||||
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
|
||||
ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <2>;
|
||||
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 239 1>;
|
||||
clock-names = "fck";
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x0 0xf>;
|
||||
vendor-id = <0x104c>;
|
||||
device-id = <0xb00d>;
|
||||
msi-map = <0x0 &gic_its 0x0 0x10000>;
|
||||
dma-coherent;
|
||||
reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
|
||||
phys = <&serdes0_pcie_link>;
|
||||
phy-names = "pcie-phy";
|
||||
ranges = <0x01000000 0x0 0x10001000 0x00 0x10001000 0x0 0x0010000>,
|
||||
<0x02000000 0x0 0x10011000 0x00 0x10011000 0x0 0x7fef000>;
|
||||
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
|
||||
};
|
||||
};
|
||||
102
bindings/pci/ti-pci.txt
Normal file
102
bindings/pci/ti-pci.txt
Normal file
@@ -0,0 +1,102 @@
|
||||
TI PCI Controllers
|
||||
|
||||
PCIe DesignWare Controller
|
||||
- compatible: Should be "ti,dra7-pcie" for RC (deprecated)
|
||||
Should be "ti,dra7-pcie-ep" for EP (deprecated)
|
||||
Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
|
||||
Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
|
||||
Should be "ti,dra726-pcie-rc" for dra72x in RC mode
|
||||
Should be "ti,dra726-pcie-ep" for dra72x in EP mode
|
||||
- phys : list of PHY specifiers (used by generic PHY framework)
|
||||
- phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
|
||||
number of PHYs as specified in *phys* property.
|
||||
- ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
|
||||
where <X> is the instance number of the pcie from the HW spec.
|
||||
- num-lanes as specified in ../snps,dw-pcie.yaml
|
||||
- ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control
|
||||
module and the register offset to specify lane
|
||||
selection.
|
||||
|
||||
HOST MODE
|
||||
=========
|
||||
- reg : Two register ranges as listed in the reg-names property
|
||||
- reg-names : The first entry must be "ti-conf" for the TI-specific registers
|
||||
The second entry must be "rc-dbics" for the DesignWare PCIe
|
||||
registers
|
||||
The third entry must be "config" for the PCIe configuration space
|
||||
- interrupts : Two interrupt entries must be specified. The first one is for
|
||||
main interrupt line and the second for MSI interrupt line.
|
||||
- #address-cells,
|
||||
#size-cells,
|
||||
#interrupt-cells,
|
||||
device_type,
|
||||
ranges,
|
||||
interrupt-map-mask,
|
||||
interrupt-map : as specified in ../snps,dw-pcie.yaml
|
||||
- ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument
|
||||
should contain the register offset within syscon
|
||||
and the 2nd argument should contain the bit field
|
||||
for setting the bit to enable unaligned
|
||||
access.
|
||||
|
||||
DEVICE MODE
|
||||
===========
|
||||
- reg : Four register ranges as listed in the reg-names property
|
||||
- reg-names : "ti-conf" for the TI-specific registers
|
||||
"ep_dbics" for the standard configuration registers as
|
||||
they are locally accessed within the DIF CS space
|
||||
"ep_dbics2" for the standard configuration registers as
|
||||
they are locally accessed within the DIF CS2 space
|
||||
"addr_space" used to map remote RC address space
|
||||
- interrupts : one interrupt entries must be specified for main interrupt.
|
||||
- num-ib-windows : number of inbound address translation windows
|
||||
- num-ob-windows : number of outbound address translation windows
|
||||
- ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument
|
||||
should contain the register offset within syscon
|
||||
and the 2nd argument should contain the bit field
|
||||
for setting the bit to enable unaligned
|
||||
access.
|
||||
|
||||
Optional Property:
|
||||
- gpios : Should be added if a GPIO line is required to drive PERST# line
|
||||
|
||||
NOTE: Two DT nodes may be added for each PCI controller; one for host
|
||||
mode and another for device mode. So in order for PCI to
|
||||
work in host mode, EP mode DT node should be disabled and in order to PCI to
|
||||
work in EP mode, host mode DT node should be disabled. Host mode and EP
|
||||
mode are mutually exclusive.
|
||||
|
||||
Example:
|
||||
axi {
|
||||
compatible = "simple-bus";
|
||||
#size-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
ranges = <0x51000000 0x51000000 0x3000
|
||||
0x0 0x20000000 0x10000000>;
|
||||
pcie@51000000 {
|
||||
compatible = "ti,dra7-pcie";
|
||||
reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
|
||||
reg-names = "rc_dbics", "ti_conf", "config";
|
||||
interrupts = <0 232 0x4>, <0 233 0x4>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
ranges = <0x81000000 0 0 0x03000 0 0x00010000
|
||||
0x82000000 0 0x20013000 0x13000 0 0xffed000>;
|
||||
#interrupt-cells = <1>;
|
||||
num-lanes = <1>;
|
||||
ti,hwmods = "pcie1";
|
||||
phys = <&pcie1_phy>;
|
||||
phy-names = "pcie-phy0";
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc 1>,
|
||||
<0 0 0 2 &pcie_intc 2>,
|
||||
<0 0 0 3 &pcie_intc 3>,
|
||||
<0 0 0 4 &pcie_intc 4>;
|
||||
pcie_intc: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
110
bindings/pci/toshiba,visconti-pcie.yaml
Normal file
110
bindings/pci/toshiba,visconti-pcie.yaml
Normal file
@@ -0,0 +1,110 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/toshiba,visconti-pcie.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Toshiba Visconti5 SoC PCIe Host Controller
|
||||
|
||||
maintainers:
|
||||
- Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
|
||||
|
||||
description:
|
||||
Toshiba Visconti5 SoC PCIe host controller is based on the Synopsys DesignWare PCIe IP.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/snps,dw-pcie.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: toshiba,visconti-pcie
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Data Bus Interface (DBI) registers.
|
||||
- description: PCIe configuration space region.
|
||||
- description: Visconti specific additional registers.
|
||||
- description: Visconti specific SMU registers
|
||||
- description: Visconti specific memory protection unit registers (MPU)
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dbi
|
||||
- const: config
|
||||
- const: ulreg
|
||||
- const: smu
|
||||
- const: mpu
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: PCIe reference clock
|
||||
- description: PCIe system clock
|
||||
- description: Auxiliary clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ref
|
||||
- const: core
|
||||
- const: aux
|
||||
|
||||
num-lanes:
|
||||
const: 2
|
||||
|
||||
required:
|
||||
- reg
|
||||
- reg-names
|
||||
- interrupts
|
||||
- "#interrupt-cells"
|
||||
- interrupt-map
|
||||
- interrupt-map-mask
|
||||
- num-lanes
|
||||
- clocks
|
||||
- clock-names
|
||||
- max-link-speed
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie: pcie@28400000 {
|
||||
compatible = "toshiba,visconti-pcie";
|
||||
reg = <0x0 0x28400000 0x0 0x00400000>,
|
||||
<0x0 0x70000000 0x0 0x10000000>,
|
||||
<0x0 0x28050000 0x0 0x00010000>,
|
||||
<0x0 0x24200000 0x0 0x00002000>,
|
||||
<0x0 0x24162000 0x0 0x00001000>;
|
||||
reg-names = "dbi", "config", "ulreg", "smu", "mpu";
|
||||
device_type = "pci";
|
||||
bus-range = <0x00 0xff>;
|
||||
num-lanes = <2>;
|
||||
num-viewport = <8>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x81000000 0 0x40000000 0 0x40000000 0 0x00010000>,
|
||||
<0x82000000 0 0x50000000 0 0x50000000 0 0x20000000>;
|
||||
interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "intr";
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map =
|
||||
<0 0 0 1 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
|
||||
0 0 0 2 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
|
||||
0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
|
||||
0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&extclk100mhz>, <&clk600mhz>, <&clk25mhz>;
|
||||
clock-names = "ref", "core", "aux";
|
||||
max-link-speed = <2>;
|
||||
};
|
||||
};
|
||||
...
|
||||
76
bindings/pci/v3-v360epc-pci.txt
Normal file
76
bindings/pci/v3-v360epc-pci.txt
Normal file
@@ -0,0 +1,76 @@
|
||||
V3 Semiconductor V360 EPC PCI bridge
|
||||
|
||||
This bridge is found in the ARM Integrator/AP (Application Platform)
|
||||
|
||||
Required properties:
|
||||
- compatible: should be one of:
|
||||
"v3,v360epc-pci"
|
||||
"arm,integrator-ap-pci", "v3,v360epc-pci"
|
||||
- reg: should contain two register areas:
|
||||
first the base address of the V3 host bridge controller, 64KB
|
||||
second the configuration area register space, 16MB
|
||||
- interrupts: should contain a reference to the V3 error interrupt
|
||||
as routed on the system.
|
||||
- bus-range: see pci.txt
|
||||
- ranges: this follows the standard PCI bindings in the IEEE Std
|
||||
1275-1994 (see pci.txt) with the following restriction:
|
||||
- The non-prefetchable and prefetchable memory windows must
|
||||
each be exactly 256MB (0x10000000) in size.
|
||||
- The prefetchable memory window must be immediately adjacent
|
||||
to the non-prefetcable memory window
|
||||
- dma-ranges: three ranges for the inbound memory region. The ranges must
|
||||
be aligned to a 1MB boundary, and may be 1MB, 2MB, 4MB, 8MB, 16MB, 32MB,
|
||||
64MB, 128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked
|
||||
as pre-fetchable. Two ranges are supported by the hardware.
|
||||
|
||||
Integrator-specific required properties:
|
||||
- syscon: should contain a link to the syscon device node, since
|
||||
on the Integrator, some registers in the syscon are required to
|
||||
operate the V3 host bridge.
|
||||
|
||||
Example:
|
||||
|
||||
pci: pciv3@62000000 {
|
||||
compatible = "arm,integrator-ap-pci", "v3,v360epc-pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
|
||||
interrupt-parent = <&pic>;
|
||||
interrupts = <17>; /* Bus error IRQ */
|
||||
clocks = <&pciclk>;
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = 0x01000000 0 0x00000000 /* I/O space @00000000 */
|
||||
0x60000000 0 0x01000000 /* 16 MiB @ LB 60000000 */
|
||||
0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
|
||||
0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
|
||||
0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
|
||||
0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
|
||||
dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
|
||||
0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */
|
||||
0x02000000 0 0x80000000 /* Core module alias memory */
|
||||
0x80000000 0 0x40000000>; /* 1GB @ LB 80000000 */
|
||||
interrupt-map-mask = <0xf800 0 0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 9 */
|
||||
0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
|
||||
0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
|
||||
0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
|
||||
0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
|
||||
/* IDSEL 10 */
|
||||
0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
|
||||
0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
|
||||
0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
|
||||
0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
|
||||
/* IDSEL 11 */
|
||||
0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
|
||||
0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
|
||||
0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
|
||||
0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
|
||||
/* IDSEL 12 */
|
||||
0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
|
||||
0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
|
||||
0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
|
||||
0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
|
||||
>;
|
||||
};
|
||||
94
bindings/pci/versatile.yaml
Normal file
94
bindings/pci/versatile.yaml
Normal file
@@ -0,0 +1,94 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/versatile.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM Versatile Platform Baseboard PCI interface
|
||||
|
||||
maintainers:
|
||||
- Rob Herring <robh@kernel.org>
|
||||
|
||||
description: |+
|
||||
PCI host controller found on the ARM Versatile PB board's FPGA.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-bus.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: arm,versatile-pci
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Versatile-specific registers
|
||||
- description: Self Config space
|
||||
- description: Config space
|
||||
|
||||
ranges:
|
||||
maxItems: 3
|
||||
|
||||
"#interrupt-cells": true
|
||||
|
||||
interrupt-map:
|
||||
maxItems: 16
|
||||
|
||||
interrupt-map-mask:
|
||||
items:
|
||||
- const: 0x1800
|
||||
- const: 0
|
||||
- const: 0
|
||||
- const: 7
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- ranges
|
||||
- "#interrupt-cells"
|
||||
- interrupt-map
|
||||
- interrupt-map-mask
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
pci@10001000 {
|
||||
compatible = "arm,versatile-pci";
|
||||
device_type = "pci";
|
||||
reg = <0x10001000 0x1000>,
|
||||
<0x41000000 0x10000>,
|
||||
<0x42000000 0x100000>;
|
||||
bus-range = <0 0xff>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
ranges =
|
||||
<0x01000000 0 0x00000000 0x43000000 0 0x00010000>, /* downstream I/O */
|
||||
<0x02000000 0 0x50000000 0x50000000 0 0x10000000>, /* non-prefetchable memory */
|
||||
<0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */
|
||||
|
||||
interrupt-map-mask = <0x1800 0 0 7>;
|
||||
interrupt-map = <0x1800 0 0 1 &sic 28>,
|
||||
<0x1800 0 0 2 &sic 29>,
|
||||
<0x1800 0 0 3 &sic 30>,
|
||||
<0x1800 0 0 4 &sic 27>,
|
||||
|
||||
<0x1000 0 0 1 &sic 27>,
|
||||
<0x1000 0 0 2 &sic 28>,
|
||||
<0x1000 0 0 3 &sic 29>,
|
||||
<0x1000 0 0 4 &sic 30>,
|
||||
|
||||
<0x0800 0 0 1 &sic 30>,
|
||||
<0x0800 0 0 2 &sic 27>,
|
||||
<0x0800 0 0 3 &sic 28>,
|
||||
<0x0800 0 0 4 &sic 29>,
|
||||
|
||||
<0x0000 0 0 1 &sic 29>,
|
||||
<0x0000 0 0 2 &sic 30>,
|
||||
<0x0000 0 0 3 &sic 27>,
|
||||
<0x0000 0 0 4 &sic 28>;
|
||||
};
|
||||
|
||||
|
||||
...
|
||||
68
bindings/pci/xgene-pci-msi.txt
Normal file
68
bindings/pci/xgene-pci-msi.txt
Normal file
@@ -0,0 +1,68 @@
|
||||
* AppliedMicro X-Gene v1 PCIe MSI controller
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: should be "apm,xgene1-msi" to identify
|
||||
X-Gene v1 PCIe MSI controller block.
|
||||
- msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
|
||||
- reg: physical base address (0x79000000) and length (0x900000) for controller
|
||||
registers. These registers include the MSI termination address and data
|
||||
registers as well as the MSI interrupt status registers.
|
||||
- reg-names: not required
|
||||
- interrupts: A list of 16 interrupt outputs of the controller, starting from
|
||||
interrupt number 0x10 to 0x1f.
|
||||
- interrupt-names: not required
|
||||
|
||||
Each PCIe node needs to have property msi-parent that points to an MSI
|
||||
controller node
|
||||
|
||||
Examples:
|
||||
|
||||
SoC DTSI:
|
||||
|
||||
+ MSI node:
|
||||
msi@79000000 {
|
||||
compatible = "apm,xgene1-msi";
|
||||
msi-controller;
|
||||
reg = <0x00 0x79000000 0x0 0x900000>;
|
||||
interrupts = <0x0 0x10 0x4>
|
||||
<0x0 0x11 0x4>
|
||||
<0x0 0x12 0x4>
|
||||
<0x0 0x13 0x4>
|
||||
<0x0 0x14 0x4>
|
||||
<0x0 0x15 0x4>
|
||||
<0x0 0x16 0x4>
|
||||
<0x0 0x17 0x4>
|
||||
<0x0 0x18 0x4>
|
||||
<0x0 0x19 0x4>
|
||||
<0x0 0x1a 0x4>
|
||||
<0x0 0x1b 0x4>
|
||||
<0x0 0x1c 0x4>
|
||||
<0x0 0x1d 0x4>
|
||||
<0x0 0x1e 0x4>
|
||||
<0x0 0x1f 0x4>;
|
||||
};
|
||||
|
||||
+ PCIe controller node with msi-parent property pointing to MSI node:
|
||||
pcie0: pcie@1f2b0000 {
|
||||
device_type = "pci";
|
||||
compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
|
||||
0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
|
||||
reg-names = "csr", "cfg";
|
||||
ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
|
||||
0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
|
||||
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
|
||||
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
|
||||
0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
|
||||
0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
|
||||
0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
|
||||
dma-coherent;
|
||||
clocks = <&pcie0clk 0>;
|
||||
msi-parent= <&msi>;
|
||||
};
|
||||
50
bindings/pci/xgene-pci.txt
Normal file
50
bindings/pci/xgene-pci.txt
Normal file
@@ -0,0 +1,50 @@
|
||||
* AppliedMicro X-Gene PCIe interface
|
||||
|
||||
Required properties:
|
||||
- device_type: set to "pci"
|
||||
- compatible: should contain "apm,xgene-pcie" to identify the core.
|
||||
- reg: A list of physical base address and length for each set of controller
|
||||
registers. Must contain an entry for each entry in the reg-names
|
||||
property.
|
||||
- reg-names: Must include the following entries:
|
||||
"csr": controller configuration registers.
|
||||
"cfg": PCIe configuration space registers.
|
||||
- #address-cells: set to <3>
|
||||
- #size-cells: set to <2>
|
||||
- ranges: ranges for the outbound memory, I/O regions.
|
||||
- dma-ranges: ranges for the inbound memory regions.
|
||||
- #interrupt-cells: set to <1>
|
||||
- interrupt-map-mask and interrupt-map: standard PCI properties
|
||||
to define the mapping of the PCIe interface to interrupt
|
||||
numbers.
|
||||
- clocks: from common clock binding: handle to pci clock.
|
||||
|
||||
Optional properties:
|
||||
- status: Either "ok" or "disabled".
|
||||
- dma-coherent: Present if DMA operations are coherent
|
||||
|
||||
Example:
|
||||
|
||||
pcie0: pcie@1f2b0000 {
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
|
||||
0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
|
||||
reg-names = "csr", "cfg";
|
||||
ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
|
||||
0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
|
||||
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
|
||||
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
|
||||
0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
|
||||
0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
|
||||
0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
|
||||
dma-coherent;
|
||||
clocks = <&pcie0clk 0>;
|
||||
};
|
||||
|
||||
73
bindings/pci/xilinx-nwl-pcie.txt
Normal file
73
bindings/pci/xilinx-nwl-pcie.txt
Normal file
@@ -0,0 +1,73 @@
|
||||
* Xilinx NWL PCIe Root Port Bridge DT description
|
||||
|
||||
Required properties:
|
||||
- compatible: Should contain "xlnx,nwl-pcie-2.11"
|
||||
- #address-cells: Address representation for root ports, set to <3>
|
||||
- #size-cells: Size representation for root ports, set to <2>
|
||||
- #interrupt-cells: specifies the number of cells needed to encode an
|
||||
interrupt source. The value must be 1.
|
||||
- reg: Should contain Bridge, PCIe Controller registers location,
|
||||
configuration space, and length
|
||||
- reg-names: Must include the following entries:
|
||||
"breg": bridge registers
|
||||
"pcireg": PCIe controller registers
|
||||
"cfg": configuration space region
|
||||
- device_type: must be "pci"
|
||||
- interrupts: Should contain NWL PCIe interrupt
|
||||
- interrupt-names: Must include the following entries:
|
||||
"msi1, msi0": interrupt asserted when an MSI is received
|
||||
"intx": interrupt asserted when a legacy interrupt is received
|
||||
"misc": interrupt asserted when miscellaneous interrupt is received
|
||||
- interrupt-map-mask and interrupt-map: standard PCI properties to define the
|
||||
mapping of the PCI interface to interrupt numbers.
|
||||
- ranges: ranges for the PCI memory regions (I/O space region is not
|
||||
supported by hardware)
|
||||
Please refer to the standard PCI bus binding document for a more
|
||||
detailed explanation
|
||||
- msi-controller: indicates that this is MSI controller node
|
||||
- msi-parent: MSI parent of the root complex itself
|
||||
- legacy-interrupt-controller: Interrupt controller device node for Legacy
|
||||
interrupts
|
||||
- interrupt-controller: identifies the node as an interrupt controller
|
||||
- #interrupt-cells: should be set to 1
|
||||
- #address-cells: specifies the number of cells needed to encode an
|
||||
address. The value must be 0.
|
||||
|
||||
Optional properties:
|
||||
- dma-coherent: present if DMA operations are coherent
|
||||
- clocks: Input clock specifier. Refer to common clock bindings
|
||||
|
||||
Example:
|
||||
++++++++
|
||||
|
||||
nwl_pcie: pcie@fd0e0000 {
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
compatible = "xlnx,nwl-pcie-2.11";
|
||||
#interrupt-cells = <1>;
|
||||
msi-controller;
|
||||
device_type = "pci";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 114 4>, <0 115 4>, <0 116 4>, <0 117 4>, <0 118 4>;
|
||||
interrupt-names = "msi0", "msi1", "intx", "dummy", "misc";
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
|
||||
<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
|
||||
<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
|
||||
<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
|
||||
|
||||
msi-parent = <&nwl_pcie>;
|
||||
reg = <0x0 0xfd0e0000 0x0 0x1000>,
|
||||
<0x0 0xfd480000 0x0 0x1000>,
|
||||
<0x80 0x00000000 0x0 0x1000000>;
|
||||
reg-names = "breg", "pcireg", "cfg";
|
||||
ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
|
||||
0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
|
||||
|
||||
pcie_intc: legacy-interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
};
|
||||
88
bindings/pci/xilinx-pcie.txt
Normal file
88
bindings/pci/xilinx-pcie.txt
Normal file
@@ -0,0 +1,88 @@
|
||||
* Xilinx AXI PCIe Root Port Bridge DT description
|
||||
|
||||
Required properties:
|
||||
- #address-cells: Address representation for root ports, set to <3>
|
||||
- #size-cells: Size representation for root ports, set to <2>
|
||||
- #interrupt-cells: specifies the number of cells needed to encode an
|
||||
interrupt source. The value must be 1.
|
||||
- compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
|
||||
- reg: Should contain AXI PCIe registers location and length
|
||||
- device_type: must be "pci"
|
||||
- interrupts: Should contain AXI PCIe interrupt
|
||||
- interrupt-map-mask,
|
||||
interrupt-map: standard PCI properties to define the mapping of the
|
||||
PCI interface to interrupt numbers.
|
||||
- ranges: ranges for the PCI memory regions (I/O space region is not
|
||||
supported by hardware)
|
||||
Please refer to the standard PCI bus binding document for a more
|
||||
detailed explanation
|
||||
|
||||
Optional properties for Zynq/Microblaze:
|
||||
- bus-range: PCI bus numbers covered
|
||||
|
||||
Interrupt controller child node
|
||||
+++++++++++++++++++++++++++++++
|
||||
Required properties:
|
||||
- interrupt-controller: identifies the node as an interrupt controller
|
||||
- #address-cells: specifies the number of cells needed to encode an
|
||||
address. The value must be 0.
|
||||
- #interrupt-cells: specifies the number of cells needed to encode an
|
||||
interrupt source. The value must be 1.
|
||||
|
||||
NOTE:
|
||||
The core provides a single interrupt for both INTx/MSI messages. So,
|
||||
created a interrupt controller node to support 'interrupt-map' DT
|
||||
functionality. The driver will create an IRQ domain for this map, decode
|
||||
the four INTx interrupts in ISR and route them to this domain.
|
||||
|
||||
|
||||
Example:
|
||||
++++++++
|
||||
Zynq:
|
||||
pci_express: axi-pcie@50000000 {
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "xlnx,axi-pcie-host-1.00.a";
|
||||
reg = < 0x50000000 0x1000000 >;
|
||||
device_type = "pci";
|
||||
interrupts = < 0 52 4 >;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc 1>,
|
||||
<0 0 0 2 &pcie_intc 2>,
|
||||
<0 0 0 3 &pcie_intc 3>,
|
||||
<0 0 0 4 &pcie_intc 4>;
|
||||
ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >;
|
||||
|
||||
pcie_intc: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Microblaze:
|
||||
pci_express: axi-pcie@10000000 {
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "xlnx,axi-pcie-host-1.00.a";
|
||||
reg = <0x10000000 0x4000000>;
|
||||
device_type = "pci";
|
||||
interrupt-parent = <µblaze_0_intc>;
|
||||
interrupts = <1 2>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc 1>,
|
||||
<0 0 0 2 &pcie_intc 2>,
|
||||
<0 0 0 3 &pcie_intc 3>,
|
||||
<0 0 0 4 &pcie_intc 4>;
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x10000000>;
|
||||
|
||||
pcie_intc: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
};
|
||||
134
bindings/pci/xilinx-versal-cpm.yaml
Normal file
134
bindings/pci/xilinx-versal-cpm.yaml
Normal file
@@ -0,0 +1,134 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: CPM Host Controller device tree for Xilinx Versal SoCs
|
||||
|
||||
maintainers:
|
||||
- Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-bus.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- xlnx,versal-cpm-host-1.00
|
||||
- xlnx,versal-cpm5-host
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: CPM system level control and status registers.
|
||||
- description: Configuration space region and bridge registers.
|
||||
- description: CPM5 control and status registers.
|
||||
minItems: 2
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: cpm_slcr
|
||||
- const: cfg
|
||||
- const: cpm_csr
|
||||
minItems: 2
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
msi-map:
|
||||
description:
|
||||
Maps a Requester ID to an MSI controller and associated MSI sideband data.
|
||||
|
||||
ranges:
|
||||
maxItems: 2
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 1
|
||||
|
||||
interrupt-controller:
|
||||
description: Interrupt controller node for handling legacy PCI interrupts.
|
||||
type: object
|
||||
properties:
|
||||
"#address-cells":
|
||||
const: 0
|
||||
"#interrupt-cells":
|
||||
const: 1
|
||||
"interrupt-controller": true
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- reg
|
||||
- reg-names
|
||||
- "#interrupt-cells"
|
||||
- interrupts
|
||||
- interrupt-map
|
||||
- interrupt-map-mask
|
||||
- bus-range
|
||||
- msi-map
|
||||
- interrupt-controller
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
versal {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
cpm_pcie: pcie@fca10000 {
|
||||
compatible = "xlnx,versal-cpm-host-1.00";
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
interrupts = <0 72 4>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
|
||||
<0 0 0 2 &pcie_intc_0 1>,
|
||||
<0 0 0 3 &pcie_intc_0 2>,
|
||||
<0 0 0 4 &pcie_intc_0 3>;
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
|
||||
<0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
|
||||
msi-map = <0x0 &its_gic 0x0 0x10000>;
|
||||
reg = <0x0 0xfca10000 0x0 0x1000>,
|
||||
<0x6 0x00000000 0x0 0x10000000>;
|
||||
reg-names = "cpm_slcr", "cfg";
|
||||
pcie_intc_0: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
cpm5_pcie: pcie@fcdd0000 {
|
||||
compatible = "xlnx,versal-cpm5-host";
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
interrupts = <0 72 4>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc_1 0>,
|
||||
<0 0 0 2 &pcie_intc_1 1>,
|
||||
<0 0 0 3 &pcie_intc_1 2>,
|
||||
<0 0 0 4 &pcie_intc_1 3>;
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
|
||||
<0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
|
||||
msi-map = <0x0 &its_gic 0x0 0x10000>;
|
||||
reg = <0x00 0xfcdd0000 0x00 0x1000>,
|
||||
<0x06 0x00000000 0x00 0x1000000>,
|
||||
<0x00 0xfce20000 0x00 0x1000000>;
|
||||
reg-names = "cpm_slcr", "cfg", "cpm_csr";
|
||||
|
||||
pcie_intc_1: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
Reference in New Issue
Block a user