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dt-bindings: Add devicetree bindings

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Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").

Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
This commit is contained in:
Melody Olvera
2023-04-03 14:38:11 -07:00
parent c334acf377
commit 6f18ce8026
4878 changed files with 424312 additions and 0 deletions
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147
bindings/net/dsa/ar9331.txt Normal file
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Atheros AR9331 built-in switch
=============================
It is a switch built-in to Atheros AR9331 WiSoC and addressable over internal
MDIO bus. All PHYs are built-in as well.
Required properties:
- compatible: should be: "qca,ar9331-switch"
- reg: Address on the MII bus for the switch.
- resets : Must contain an entry for each entry in reset-names.
- reset-names : Must include the following entries: "switch"
- interrupt-parent: Phandle to the parent interrupt controller
- interrupts: IRQ line for the switch
- interrupt-controller: Indicates the switch is itself an interrupt
controller. This is used for the PHY interrupts.
- #interrupt-cells: must be 1
- mdio: Container of PHY and devices on the switches MDIO bus.
See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional
required and optional properties.
Examples:
eth0: ethernet@19000000 {
compatible = "qca,ar9330-eth";
reg = <0x19000000 0x200>;
interrupts = <4>;
resets = <&rst 9>, <&rst 22>;
reset-names = "mac", "mdio";
clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
clock-names = "eth", "mdio";
phy-mode = "mii";
phy-handle = <&phy_port4>;
};
eth1: ethernet@1a000000 {
compatible = "qca,ar9330-eth";
reg = <0x1a000000 0x200>;
interrupts = <5>;
resets = <&rst 13>, <&rst 23>;
reset-names = "mac", "mdio";
clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
clock-names = "eth", "mdio";
phy-mode = "gmii";
fixed-link {
speed = <1000>;
full-duplex;
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch10: switch@10 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qca,ar9331-switch";
reg = <0x10>;
resets = <&rst 8>;
reset-names = "switch";
interrupt-parent = <&miscintc>;
interrupts = <12>;
interrupt-controller;
#interrupt-cells = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
switch_port0: port@0 {
reg = <0x0>;
ethernet = <&eth1>;
phy-mode = "gmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
switch_port1: port@1 {
reg = <0x1>;
phy-handle = <&phy_port0>;
phy-mode = "internal";
};
switch_port2: port@2 {
reg = <0x2>;
phy-handle = <&phy_port1>;
phy-mode = "internal";
};
switch_port3: port@3 {
reg = <0x3>;
phy-handle = <&phy_port2>;
phy-mode = "internal";
};
switch_port4: port@4 {
reg = <0x4>;
phy-handle = <&phy_port3>;
phy-mode = "internal";
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&switch10>;
phy_port0: phy@0 {
reg = <0x0>;
interrupts = <0>;
};
phy_port1: phy@1 {
reg = <0x1>;
interrupts = <0>;
};
phy_port2: phy@2 {
reg = <0x2>;
interrupts = <0>;
};
phy_port3: phy@3 {
reg = <0x3>;
interrupts = <0>;
};
phy_port4: phy@4 {
reg = <0x4>;
interrupts = <0>;
};
};
};
};
};

74
bindings/net/dsa/arrow,xrs700x.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/arrow,xrs700x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arrow SpeedChips XRS7000 Series Switch Device Tree Bindings
allOf:
- $ref: dsa.yaml#
maintainers:
- George McCollister <george.mccollister@gmail.com>
description:
The Arrow SpeedChips XRS7000 Series of single chip gigabit Ethernet switches
are designed for critical networking applications. They have up to three
RGMII ports and one RMII port and are managed via i2c or mdio.
properties:
compatible:
oneOf:
- enum:
- arrow,xrs7003e
- arrow,xrs7003f
- arrow,xrs7004e
- arrow,xrs7004f
reg:
maxItems: 1
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
switch@8 {
compatible = "arrow,xrs7004e";
reg = <0x8>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
ethernet-port@1 {
reg = <1>;
label = "lan0";
phy-handle = <&swphy0>;
phy-mode = "rgmii-id";
};
ethernet-port@2 {
reg = <2>;
label = "lan1";
phy-handle = <&swphy1>;
phy-mode = "rgmii-id";
};
ethernet-port@3 {
reg = <3>;
ethernet = <&fec1>;
phy-mode = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};

264
bindings/net/dsa/brcm,b53.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/brcm,b53.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM53xx Ethernet switches
maintainers:
- Florian Fainelli <f.fainelli@gmail.com>
description:
Broadcom BCM53xx Ethernet switches
properties:
compatible:
oneOf:
- const: brcm,bcm5325
- const: brcm,bcm53115
- const: brcm,bcm53125
- const: brcm,bcm53128
- const: brcm,bcm5365
- const: brcm,bcm5395
- const: brcm,bcm5389
- const: brcm,bcm5397
- const: brcm,bcm5398
- items:
- const: brcm,bcm11360-srab
- const: brcm,cygnus-srab
- items:
- enum:
- brcm,bcm53010-srab
- brcm,bcm53011-srab
- brcm,bcm53012-srab
- brcm,bcm53018-srab
- brcm,bcm53019-srab
- const: brcm,bcm5301x-srab
- items:
- enum:
- brcm,bcm11404-srab
- brcm,bcm11407-srab
- brcm,bcm11409-srab
- brcm,bcm58310-srab
- brcm,bcm58311-srab
- brcm,bcm58313-srab
- const: brcm,omega-srab
- items:
- enum:
- brcm,bcm58522-srab
- brcm,bcm58523-srab
- brcm,bcm58525-srab
- brcm,bcm58622-srab
- brcm,bcm58623-srab
- brcm,bcm58625-srab
- brcm,bcm88312-srab
- const: brcm,nsp-srab
- items:
- enum:
- brcm,bcm3384-switch
- brcm,bcm6328-switch
- brcm,bcm6368-switch
- const: brcm,bcm63xx-switch
required:
- compatible
- reg
allOf:
- $ref: dsa.yaml#
- if:
properties:
compatible:
contains:
enum:
- brcm,bcm5325
- brcm,bcm53115
- brcm,bcm53125
- brcm,bcm53128
- brcm,bcm5365
- brcm,bcm5395
- brcm,bcm5397
- brcm,bcm5398
then:
$ref: /schemas/spi/spi-peripheral-props.yaml
# BCM585xx/586xx/88312 SoCs
- if:
properties:
compatible:
contains:
enum:
- brcm,bcm58522-srab
- brcm,bcm58523-srab
- brcm,bcm58525-srab
- brcm,bcm58622-srab
- brcm,bcm58623-srab
- brcm,bcm58625-srab
- brcm,bcm88312-srab
then:
properties:
reg:
minItems: 3
maxItems: 3
reg-names:
items:
- const: srab
- const: mux_config
- const: sgmii_config
interrupts:
minItems: 13
maxItems: 13
interrupt-names:
items:
- const: link_state_p0
- const: link_state_p1
- const: link_state_p2
- const: link_state_p3
- const: link_state_p4
- const: link_state_p5
- const: link_state_p7
- const: link_state_p8
- const: phy
- const: ts
- const: imp_sleep_timer_p5
- const: imp_sleep_timer_p7
- const: imp_sleep_timer_p8
required:
- interrupts
else:
properties:
reg:
maxItems: 1
unevaluatedProperties: false
examples:
- |
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethernet-switch@1e {
compatible = "brcm,bcm53125";
reg = <30>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@5 {
reg = <5>;
label = "cable-modem";
phy-mode = "rgmii-txid";
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@8 {
reg = <8>;
phy-mode = "rgmii-txid";
ethernet = <&eth0>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
axi {
#address-cells = <1>;
#size-cells = <1>;
switch@36000 {
compatible = "brcm,bcm58623-srab", "brcm,nsp-srab";
reg = <0x36000 0x1000>,
<0x3f308 0x8>,
<0x3f410 0xc>;
reg-names = "srab", "mux_config", "sgmii_config";
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "link_state_p0",
"link_state_p1",
"link_state_p2",
"link_state_p3",
"link_state_p4",
"link_state_p5",
"link_state_p7",
"link_state_p8",
"phy",
"ts",
"imp_sleep_timer_p5",
"imp_sleep_timer_p7",
"imp_sleep_timer_p8";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
label = "port0";
reg = <0>;
};
port@1 {
label = "port1";
reg = <1>;
};
port@2 {
label = "port2";
reg = <2>;
};
port@3 {
label = "port3";
reg = <3>;
};
port@4 {
label = "port4";
reg = <4>;
};
port@8 {
ethernet = <&amac2>;
reg = <8>;
phy-mode = "internal";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};

171
bindings/net/dsa/brcm,sf2.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/brcm,sf2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom Starfighter 2 integrated swich
maintainers:
- Florian Fainelli <f.fainelli@gmail.com>
properties:
compatible:
items:
- enum:
- brcm,bcm4908-switch
- brcm,bcm7278-switch-v4.0
- brcm,bcm7278-switch-v4.8
- brcm,bcm7445-switch-v4.0
reg:
minItems: 6
maxItems: 6
reg-names:
items:
- const: core
- const: reg
- const: intrl2_0
- const: intrl2_1
- const: fcb
- const: acb
interrupts:
minItems: 2
maxItems: 2
interrupt-names:
items:
- const: switch_0
- const: switch_1
resets:
maxItems: 1
reset-names:
const: switch
clocks:
minItems: 1
items:
- description: switch's main clock
- description: dividing of the switch core clock
clock-names:
minItems: 1
items:
- const: sw_switch
- const: sw_switch_mdiv
brcm,num-gphy:
$ref: /schemas/types.yaml#/definitions/uint32
description: maximum number of integrated gigabit PHYs in the switch
brcm,num-rgmii-ports:
$ref: /schemas/types.yaml#/definitions/uint32
description: maximum number of RGMII interfaces supported by the switch
brcm,fcb-pause-override:
description: if present indicates that the switch supports Failover Control
Block pause override capability
type: boolean
brcm,acb-packets-inflight:
description: if present indicates that the switch Admission Control Block
supports reporting the number of packets in-flight in a switch queue
type: boolean
"#address-cells":
const: 1
"#size-cells":
const: 0
ports:
type: object
properties:
brcm,use-bcm-hdr:
description: if present, indicates that the switch port has Broadcom
tags enabled (per-packet metadata)
type: boolean
required:
- reg
- interrupts
- "#address-cells"
- "#size-cells"
allOf:
- $ref: "dsa.yaml#"
- if:
properties:
compatible:
contains:
enum:
- brcm,bcm7278-switch-v4.0
- brcm,bcm7278-switch-v4.8
then:
properties:
clocks:
minItems: 1
maxItems: 1
clock-names:
minItems: 1
maxItems: 1
required:
- clocks
- clock-names
- if:
properties:
compatible:
contains:
const: brcm,bcm7445-switch-v4.0
then:
properties:
clocks:
minItems: 2
maxItems: 2
clock-names:
minItems: 2
maxItems: 2
required:
- clocks
- clock-names
additionalProperties: false
examples:
- |
switch@f0b00000 {
compatible = "brcm,bcm7445-switch-v4.0";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xf0b00000 0x40000>,
<0xf0b40000 0x110>,
<0xf0b40340 0x30>,
<0xf0b40380 0x30>,
<0xf0b40400 0x34>,
<0xf0b40600 0x208>;
reg-names = "core", "reg", "intrl2_0", "intrl2_1",
"fcb", "acb";
interrupts = <0 0x18 0>,
<0 0x19 0>;
clocks = <&sw_switch>, <&sw_switch_mdiv>;
clock-names = "sw_switch", "sw_switch_mdiv";
brcm,num-gphy = <1>;
brcm,num-rgmii-ports = <2>;
brcm,fcb-pause-override;
brcm,acb-packets-inflight;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
label = "gphy";
reg = <0>;
};
};
};

98
bindings/net/dsa/dsa-port.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/dsa-port.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ethernet Switch port Device Tree Bindings
maintainers:
- Andrew Lunn <andrew@lunn.ch>
- Florian Fainelli <f.fainelli@gmail.com>
- Vivien Didelot <vivien.didelot@gmail.com>
description:
Ethernet switch port Description
allOf:
- $ref: /schemas/net/ethernet-controller.yaml#
properties:
reg:
description: Port number
label:
description:
Describes the label associated with this port, which will become
the netdev name
$ref: /schemas/types.yaml#/definitions/string
link:
description:
Should be a list of phandles to other switch's DSA port. This
port is used as the outgoing port towards the phandle ports. The
full routing information must be given, not just the one hop
routes to neighbouring switches
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
maxItems: 1
ethernet:
description:
Should be a phandle to a valid Ethernet device node. This host
device is what the switch port is connected to
$ref: /schemas/types.yaml#/definitions/phandle
dsa-tag-protocol:
description:
Instead of the default, the switch will use this tag protocol if
possible. Useful when a device supports multiple protocols and
the default is incompatible with the Ethernet device.
enum:
- dsa
- edsa
- ocelot
- ocelot-8021q
- rtl8_4
- rtl8_4t
- seville
phy-handle: true
phy-mode: true
fixed-link: true
mac-address: true
sfp: true
managed: true
rx-internal-delay-ps: true
tx-internal-delay-ps: true
required:
- reg
# CPU and DSA ports must have phylink-compatible link descriptions
if:
oneOf:
- required: [ ethernet ]
- required: [ link ]
then:
allOf:
- required:
- phy-mode
- oneOf:
- required:
- fixed-link
- required:
- phy-handle
- required:
- managed
additionalProperties: true
...

4
bindings/net/dsa/dsa.txt Normal file
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Distributed Switch Architecture Device Tree Bindings
----------------------------------------------------
See Documentation/devicetree/bindings/net/dsa/dsa.yaml for the documentation.

61
bindings/net/dsa/dsa.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/dsa.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ethernet Switch Device Tree Bindings
maintainers:
- Andrew Lunn <andrew@lunn.ch>
- Florian Fainelli <f.fainelli@gmail.com>
- Vivien Didelot <vivien.didelot@gmail.com>
description:
This binding represents Ethernet Switches which have a dedicated CPU
port. That port is usually connected to an Ethernet Controller of the
SoC. Such setups are typical for embedded devices.
select: false
properties:
$nodename:
pattern: "^(ethernet-)?switch(@.*)?$"
dsa,member:
minItems: 2
maxItems: 2
description:
A two element list indicates which DSA cluster, and position within the
cluster a switch takes. <0 0> is cluster 0, switch 0. <0 1> is cluster 0,
switch 1. <1 0> is cluster 1, switch 0. A switch not part of any cluster
(single device hanging off a CPU port) must not specify this property
$ref: /schemas/types.yaml#/definitions/uint32-array
patternProperties:
"^(ethernet-)?ports$":
type: object
properties:
'#address-cells':
const: 1
'#size-cells':
const: 0
patternProperties:
"^(ethernet-)?port@[0-9]+$":
type: object
description: Ethernet switch ports
$ref: dsa-port.yaml#
unevaluatedProperties: false
oneOf:
- required:
- ports
- required:
- ethernet-ports
additionalProperties: true
...

132
bindings/net/dsa/hirschmann,hellcreek.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/hirschmann,hellcreek.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Hirschmann Hellcreek TSN Switch Device Tree Bindings
allOf:
- $ref: dsa.yaml#
maintainers:
- Andrew Lunn <andrew@lunn.ch>
- Florian Fainelli <f.fainelli@gmail.com>
- Vivien Didelot <vivien.didelot@gmail.com>
- Kurt Kanzenbach <kurt@linutronix.de>
description:
The Hellcreek TSN Switch IP is a 802.1Q Ethernet compliant switch. It supports
the Precision Time Protocol, Hardware Timestamping as well the Time Aware
Shaper.
properties:
compatible:
items:
- const: hirschmann,hellcreek-de1soc-r1
reg:
description:
The physical base address and size of TSN and PTP memory base
minItems: 2
maxItems: 2
reg-names:
items:
- const: tsn
- const: ptp
leds:
type: object
properties:
'#address-cells':
const: 1
'#size-cells':
const: 0
patternProperties:
"^led@[01]$":
type: object
description: Hellcreek leds
$ref: /schemas/leds/common.yaml#
properties:
reg:
items:
- enum: [0, 1]
description: Led number
label: true
default-state: true
required:
- reg
additionalProperties: false
additionalProperties: false
required:
- compatible
- reg
- reg-names
- ethernet-ports
- leds
unevaluatedProperties: false
examples:
- |
switch0: switch@ff240000 {
compatible = "hirschmann,hellcreek-de1soc-r1";
reg = <0xff240000 0x1000>,
<0xff250000 0x1000>;
reg-names = "tsn", "ptp";
dsa,member = <0 0>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ethernet = <&gmac0>;
phy-mode = "mii";
fixed-link {
speed = <100>;
full-duplex;
};
};
port@2 {
reg = <2>;
label = "lan0";
phy-handle = <&phy1>;
};
port@3 {
reg = <3>;
label = "lan1";
phy-handle = <&phy2>;
};
};
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
label = "sync_good";
default-state = "on";
};
led@1 {
reg = <1>;
label = "is_gm";
default-state = "off";
};
};
};

100
bindings/net/dsa/lan9303.txt Normal file
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SMSC/MicroChip LAN9303 three port ethernet switch
-------------------------------------------------
Required properties:
- compatible: should be
- "smsc,lan9303-i2c" for I2C managed mode
or
- "smsc,lan9303-mdio" for mdio managed mode
Optional properties:
- reset-gpios: GPIO to be used to reset the whole device
- reset-duration: reset duration in milliseconds, defaults to 200 ms
Subnodes:
The integrated switch subnode should be specified according to the binding
described in dsa/dsa.txt. The CPU port of this switch is always port 0.
Note: always use 'reg = <0/1/2>;' for the three DSA ports, even if the device is
configured to use 1/2/3 instead. This hardware configuration will be
auto-detected and mapped accordingly.
Example:
I2C managed mode:
master: masterdevice@X {
fixed-link { /* RMII fixed link to LAN9303 */
speed = <100>;
full-duplex;
};
};
switch: switch@a {
compatible = "smsc,lan9303-i2c";
reg = <0xa>;
reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
reset-duration = <200>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 { /* RMII fixed link to master */
reg = <0>;
ethernet = <&master>;
};
port@1 { /* external port 1 */
reg = <1>;
label = "lan1";
};
port@2 { /* external port 2 */
reg = <2>;
label = "lan2";
};
};
};
MDIO managed mode:
master: masterdevice@X {
phy-handle = <&switch>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch: switch-phy@0 {
compatible = "smsc,lan9303-mdio";
reg = <0>;
reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
reset-duration = <100>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ethernet = <&master>;
};
port@1 { /* external port 1 */
reg = <1>;
label = "lan1";
};
port@2 { /* external port 2 */
reg = <2>;
label = "lan2";
};
};
};
};
};

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Lantiq GSWIP Ethernet switches
==================================
Required properties for GSWIP core:
- compatible : "lantiq,xrx200-gswip" for the embedded GSWIP in the
xRX200 SoC
"lantiq,xrx300-gswip" for the embedded GSWIP in the
xRX300 SoC
"lantiq,xrx330-gswip" for the embedded GSWIP in the
xRX330 SoC
- reg : memory range of the GSWIP core registers
: memory range of the GSWIP MDIO registers
: memory range of the GSWIP MII registers
See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of
additional required and optional properties.
Required properties for MDIO bus:
- compatible : "lantiq,xrx200-mdio" for the MDIO bus inside the GSWIP
core of the xRX200 SoC and the PHYs connected to it.
See Documentation/devicetree/bindings/net/mdio.txt for a list of additional
required and optional properties.
Required properties for GPHY firmware loading:
- compatible : "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw"
"lantiq,xrx300-gphy-fw", "lantiq,gphy-fw"
"lantiq,xrx330-gphy-fw", "lantiq,gphy-fw"
for the loading of the firmware into the embedded
GPHY core of the SoC.
- lantiq,rcu : reference to the rcu syscon
The GPHY firmware loader has a list of GPHY entries, one for each
embedded GPHY
- reg : Offset of the GPHY firmware register in the RCU
register range
- resets : list of resets of the embedded GPHY
- reset-names : list of names of the resets
Example:
Ethernet switch on the VRX200 SoC:
switch@e108000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "lantiq,xrx200-gswip";
reg = < 0xe108000 0x3100 /* switch */
0xe10b100 0xd8 /* mdio */
0xe10b1d8 0x130 /* mii */
>;
dsa,member = <0 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan3";
phy-mode = "rgmii";
phy-handle = <&phy0>;
};
port@1 {
reg = <1>;
label = "lan4";
phy-mode = "rgmii";
phy-handle = <&phy1>;
};
port@2 {
reg = <2>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy11>;
};
port@4 {
reg = <4>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy13>;
};
port@5 {
reg = <5>;
label = "wan";
phy-mode = "rgmii";
phy-handle = <&phy5>;
};
port@6 {
reg = <0x6>;
ethernet = <&eth0>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "lantiq,xrx200-mdio";
reg = <0>;
phy0: ethernet-phy@0 {
reg = <0x0>;
};
phy1: ethernet-phy@1 {
reg = <0x1>;
};
phy5: ethernet-phy@5 {
reg = <0x5>;
};
phy11: ethernet-phy@11 {
reg = <0x11>;
};
phy13: ethernet-phy@13 {
reg = <0x13>;
};
};
gphy-fw {
compatible = "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw";
lantiq,rcu = <&rcu0>;
#address-cells = <1>;
#size-cells = <0>;
gphy@20 {
reg = <0x20>;
resets = <&reset0 31 30>;
reset-names = "gphy";
};
gphy@68 {
reg = <0x68>;
resets = <&reset0 29 28>;
reset-names = "gphy";
};
};
};

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Marvell DSA Switch Device Tree Bindings
---------------------------------------
WARNING: This binding is currently unstable. Do not program it into a
FLASH never to be changed again. Once this binding is stable, this
warning will be removed.
If you need a stable binding, use the old dsa.txt binding.
Marvell Switches are MDIO devices. The following properties should be
placed as a child node of an mdio device.
The properties described here are those specific to Marvell devices.
Additional required and optional properties can be found in dsa.txt.
The compatibility string is used only to find an identification register,
which is at a different MDIO base address in different switch families.
- "marvell,mv88e6085" : Switch has base address 0x10. Use with models:
6085, 6095, 6097, 6123, 6131, 6141, 6161, 6165,
6171, 6172, 6175, 6176, 6185, 6240, 6320, 6321,
6341, 6350, 6351, 6352
- "marvell,mv88e6190" : Switch has base address 0x00. Use with models:
6190, 6190X, 6191, 6290, 6390, 6390X
- "marvell,mv88e6250" : Switch has base address 0x08 or 0x18. Use with model:
6220, 6250
Required properties:
- compatible : Should be one of "marvell,mv88e6085",
"marvell,mv88e6190" or "marvell,mv88e6250" as
indicated above
- reg : Address on the MII bus for the switch.
Optional properties:
- reset-gpios : Should be a gpio specifier for a reset line
- interrupts : Interrupt from the switch
- interrupt-controller : Indicates the switch is itself an interrupt
controller. This is used for the PHY interrupts.
#interrupt-cells = <2> : Controller uses two cells, number and flag
- eeprom-length : Set to the length of an EEPROM connected to the
switch. Must be set if the switch can not detect
the presence and/or size of a connected EEPROM,
otherwise optional.
- mdio : Container of PHY and devices on the switches MDIO
bus.
- mdio? : Container of PHYs and devices on the external MDIO
bus. The node must contains a compatible string of
"marvell,mv88e6xxx-mdio-external"
Example:
mdio {
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&gpio0>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
switch0: switch@0 {
compatible = "marvell,mv88e6085";
reg = <0>;
reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch1phy0: switch1phy0@0 {
reg = <0>;
interrupt-parent = <&switch0>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&gpio0>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
switch0: switch@0 {
compatible = "marvell,mv88e6190";
reg = <0>;
reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch1phy0: switch1phy0@0 {
reg = <0>;
interrupt-parent = <&switch0>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
};
};
mdio1 {
compatible = "marvell,mv88e6xxx-mdio-external";
#address-cells = <1>;
#size-cells = <0>;
switch1phy9: switch1phy0@9 {
reg = <9>;
};
};
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/mediatek,mt7530.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek MT7530 and MT7531 Ethernet Switches
maintainers:
- Arınç ÜNAL <arinc.unal@arinc9.com>
- Landen Chao <Landen.Chao@mediatek.com>
- DENG Qingfang <dqfext@gmail.com>
- Sean Wang <sean.wang@mediatek.com>
description: |
There are two versions of MT7530, standalone and in a multi-chip module.
MT7530 is a part of the multi-chip module in MT7620AN, MT7620DA, MT7620DAN,
MT7620NN, MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs.
MT7530 in MT7620AN, MT7620DA, MT7620DAN and MT7620NN SoCs has got 10/100 PHYs
and the switch registers are directly mapped into SoC's memory map rather than
using MDIO. The DSA driver currently doesn't support this.
There is only the standalone version of MT7531.
Port 5 on MT7530 has got various ways of configuration.
For standalone MT7530:
- Port 5 can be used as a CPU port.
- PHY 0 or 4 of the switch can be muxed to connect to the gmac of the SoC
which port 5 is wired to. Usually used for connecting the wan port
directly to the CPU to achieve 2 Gbps routing in total.
The driver looks up the reg on the ethernet-phy node which the phy-handle
property refers to on the gmac node to mux the specified phy.
The driver requires the gmac of the SoC to have "mediatek,eth-mac" as the
compatible string and the reg must be 1. So, for now, only gmac1 of an
MediaTek SoC can benefit this. Banana Pi BPI-R2 suits this.
Check out example 5 for a similar configuration.
- Port 5 can be wired to an external phy. Port 5 becomes a DSA slave.
Check out example 7 for a similar configuration.
For multi-chip module MT7530:
- Port 5 can be used as a CPU port.
- PHY 0 or 4 of the switch can be muxed to connect to gmac1 of the SoC.
Usually used for connecting the wan port directly to the CPU to achieve 2
Gbps routing in total.
The driver looks up the reg on the ethernet-phy node which the phy-handle
property refers to on the gmac node to mux the specified phy.
For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function.
Check out example 5.
- In case of an external phy wired to gmac1 of the SoC, port 5 must not be
enabled.
In case of muxing PHY 0 or 4, the external phy must not be enabled.
For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function.
Check out example 6.
- Port 5 can be muxed to an external phy. Port 5 becomes a DSA slave.
The external phy must be wired TX to TX to gmac1 of the SoC for this to
work. Ubiquiti EdgeRouter X SFP is wired this way.
Muxing PHY 0 or 4 won't work when the external phy is connected TX to TX.
For the MT7621 SoCs, rgmii2 group must be claimed with gpio function.
Check out example 7.
properties:
compatible:
oneOf:
- description:
Standalone MT7530 and multi-chip module MT7530 in MT7623AI SoC
const: mediatek,mt7530
- description:
Standalone MT7531
const: mediatek,mt7531
- description:
Multi-chip module MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs
const: mediatek,mt7621
reg:
maxItems: 1
core-supply:
description:
Phandle to the regulator node necessary for the core power.
"#gpio-cells":
const: 2
gpio-controller:
type: boolean
description:
If defined, LED controller of the MT7530 switch will run on GPIO mode.
There are 15 controllable pins.
port 0 LED 0..2 as GPIO 0..2
port 1 LED 0..2 as GPIO 3..5
port 2 LED 0..2 as GPIO 6..8
port 3 LED 0..2 as GPIO 9..11
port 4 LED 0..2 as GPIO 12..14
"#interrupt-cells":
const: 1
interrupt-controller: true
interrupts:
maxItems: 1
io-supply:
description:
Phandle to the regulator node necessary for the I/O power.
See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt for
details for the regulator setup on these boards.
mediatek,mcm:
type: boolean
description:
Used for MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs which the MT7530
switch is a part of the multi-chip module.
reset-gpios:
description:
GPIO to reset the switch. Use this if mediatek,mcm is not used.
This property is optional because some boards share the reset line with
other components which makes it impossible to probe the switch if the
reset line is used.
maxItems: 1
reset-names:
const: mcm
resets:
description:
Phandle pointing to the system reset controller with line index for the
ethsys.
maxItems: 1
patternProperties:
"^(ethernet-)?ports$":
type: object
patternProperties:
"^(ethernet-)?port@[0-9]+$":
type: object
description: Ethernet switch ports
unevaluatedProperties: false
properties:
reg:
description:
Port address described must be 5 or 6 for CPU port and from 0 to 5
for user ports.
allOf:
- $ref: dsa-port.yaml#
- if:
required: [ ethernet ]
then:
properties:
reg:
enum:
- 5
- 6
required:
- compatible
- reg
$defs:
mt7530-dsa-port:
patternProperties:
"^(ethernet-)?ports$":
patternProperties:
"^(ethernet-)?port@[0-9]+$":
if:
required: [ ethernet ]
then:
if:
properties:
reg:
const: 5
then:
properties:
phy-mode:
enum:
- gmii
- mii
- rgmii
else:
properties:
phy-mode:
enum:
- rgmii
- trgmii
mt7531-dsa-port:
patternProperties:
"^(ethernet-)?ports$":
patternProperties:
"^(ethernet-)?port@[0-9]+$":
if:
required: [ ethernet ]
then:
if:
properties:
reg:
const: 5
then:
properties:
phy-mode:
enum:
- 1000base-x
- 2500base-x
- rgmii
- sgmii
else:
properties:
phy-mode:
enum:
- 1000base-x
- 2500base-x
- sgmii
allOf:
- $ref: dsa.yaml#
- if:
required:
- mediatek,mcm
then:
properties:
reset-gpios: false
required:
- resets
- reset-names
- dependencies:
interrupt-controller: [ interrupts ]
- if:
properties:
compatible:
const: mediatek,mt7530
then:
$ref: "#/$defs/mt7530-dsa-port"
required:
- core-supply
- io-supply
- if:
properties:
compatible:
const: mediatek,mt7531
then:
$ref: "#/$defs/mt7531-dsa-port"
properties:
gpio-controller: false
mediatek,mcm: false
- if:
properties:
compatible:
const: mediatek,mt7621
then:
$ref: "#/$defs/mt7530-dsa-port"
required:
- mediatek,mcm
unevaluatedProperties: false
examples:
# Example 1: Standalone MT7530
- |
#include <dt-bindings/gpio/gpio.h>
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch@1f {
compatible = "mediatek,mt7530";
reg = <0x1f>;
reset-gpios = <&pio 33 0>;
core-supply = <&mt6323_vpa_reg>;
io-supply = <&mt6323_vemc3v3_reg>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
port@4 {
reg = <4>;
label = "wan";
};
port@6 {
reg = <6>;
ethernet = <&gmac0>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
};
};
};
# Example 2: MT7530 in MT7623AI SoC
- |
#include <dt-bindings/reset/mt2701-resets.h>
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch@1f {
compatible = "mediatek,mt7530";
reg = <0x1f>;
mediatek,mcm;
resets = <&ethsys MT2701_ETHSYS_MCM_RST>;
reset-names = "mcm";
core-supply = <&mt6323_vpa_reg>;
io-supply = <&mt6323_vemc3v3_reg>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
port@4 {
reg = <4>;
label = "wan";
};
port@6 {
reg = <6>;
ethernet = <&gmac0>;
phy-mode = "trgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
};
};
};
# Example 3: Standalone MT7531
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch@0 {
compatible = "mediatek,mt7531";
reg = <0>;
reset-gpios = <&pio 54 0>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&pio>;
interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
port@4 {
reg = <4>;
label = "wan";
};
port@6 {
reg = <6>;
ethernet = <&gmac0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
};
};
# Example 4: MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs
- |
#include <dt-bindings/interrupt-controller/mips-gic.h>
#include <dt-bindings/reset/mt7621-reset.h>
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch@1f {
compatible = "mediatek,mt7621";
reg = <0x1f>;
mediatek,mcm;
resets = <&sysc MT7621_RST_MCM>;
reset-names = "mcm";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
port@4 {
reg = <4>;
label = "wan";
};
port@6 {
reg = <6>;
ethernet = <&gmac0>;
phy-mode = "trgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
};
};
};
# Example 5: MT7621: mux MT7530's phy4 to SoC's gmac1
- |
#include <dt-bindings/interrupt-controller/mips-gic.h>
#include <dt-bindings/reset/mt7621-reset.h>
ethernet {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&rgmii2_pins>;
mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "rgmii";
phy-handle = <&example5_ethphy4>;
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
/* MT7530's phy4 */
example5_ethphy4: ethernet-phy@4 {
reg = <4>;
};
switch@1f {
compatible = "mediatek,mt7621";
reg = <0x1f>;
mediatek,mcm;
resets = <&sysc MT7621_RST_MCM>;
reset-names = "mcm";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
/* Commented out, phy4 is muxed to gmac1.
port@4 {
reg = <4>;
label = "wan";
};
*/
port@6 {
reg = <6>;
ethernet = <&gmac0>;
phy-mode = "trgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
};
};
};
};
# Example 6: MT7621: mux external phy to SoC's gmac1
- |
#include <dt-bindings/interrupt-controller/mips-gic.h>
#include <dt-bindings/reset/mt7621-reset.h>
ethernet {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&rgmii2_pins>;
mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "rgmii";
phy-handle = <&example6_ethphy7>;
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
/* External PHY */
example6_ethphy7: ethernet-phy@7 {
reg = <7>;
phy-mode = "rgmii";
};
switch@1f {
compatible = "mediatek,mt7621";
reg = <0x1f>;
mediatek,mcm;
resets = <&sysc MT7621_RST_MCM>;
reset-names = "mcm";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
port@4 {
reg = <4>;
label = "wan";
};
port@6 {
reg = <6>;
ethernet = <&gmac0>;
phy-mode = "trgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
};
};
};
};
# Example 7: MT7621: mux external phy to MT7530's port 5
- |
#include <dt-bindings/interrupt-controller/mips-gic.h>
#include <dt-bindings/reset/mt7621-reset.h>
ethernet {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&rgmii2_pins>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
/* External PHY */
example7_ethphy7: ethernet-phy@7 {
reg = <7>;
phy-mode = "rgmii";
};
switch@1f {
compatible = "mediatek,mt7621";
reg = <0x1f>;
mediatek,mcm;
resets = <&sysc MT7621_RST_MCM>;
reset-names = "mcm";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
port@4 {
reg = <4>;
label = "wan";
};
port@5 {
reg = <5>;
label = "extphy";
phy-mode = "rgmii-txid";
phy-handle = <&example7_ethphy7>;
};
port@6 {
reg = <6>;
ethernet = <&gmac0>;
phy-mode = "trgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
};
};
};
};

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# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/microchip,ksz.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip KSZ Series Ethernet switches
maintainers:
- Marek Vasut <marex@denx.de>
- Woojung Huh <Woojung.Huh@microchip.com>
allOf:
- $ref: dsa.yaml#
- $ref: /schemas/spi/spi-peripheral-props.yaml#
properties:
# See Documentation/devicetree/bindings/net/dsa/dsa.yaml for a list of additional
# required and optional properties.
compatible:
enum:
- microchip,ksz8765
- microchip,ksz8794
- microchip,ksz8795
- microchip,ksz8863
- microchip,ksz8873
- microchip,ksz9477
- microchip,ksz9897
- microchip,ksz9896
- microchip,ksz9567
- microchip,ksz8565
- microchip,ksz9893
- microchip,ksz9563
- microchip,ksz8563
reset-gpios:
description:
Should be a gpio specifier for a reset line.
maxItems: 1
microchip,synclko-125:
$ref: /schemas/types.yaml#/definitions/flag
description:
Set if the output SYNCLKO frequency should be set to 125MHz instead of 25MHz.
microchip,synclko-disable:
$ref: /schemas/types.yaml#/definitions/flag
description:
Set if the output SYNCLKO clock should be disabled. Do not mix with
microchip,synclko-125.
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
// Ethernet switch connected via SPI to the host, CPU port wired to eth0:
eth0 {
fixed-link {
speed = <1000>;
full-duplex;
};
};
spi0 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&pinctrl_spi_ksz>;
cs-gpios = <&pioC 25 0>;
id = <1>;
ksz9477: switch@0 {
compatible = "microchip,ksz9477";
reg = <0>;
reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
spi-max-frequency = <44000000>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
port@4 {
reg = <4>;
label = "lan5";
};
port@5 {
reg = <5>;
ethernet = <&eth0>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
ksz8565: switch@1 {
compatible = "microchip,ksz8565";
reg = <1>;
spi-max-frequency = <44000000>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
port@6 {
reg = <6>;
ethernet = <&eth0>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};
...

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/microchip,lan937x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: LAN937x Ethernet Switch Series Tree Bindings
maintainers:
- UNGLinuxDriver@microchip.com
allOf:
- $ref: dsa.yaml#
properties:
compatible:
enum:
- microchip,lan9370
- microchip,lan9371
- microchip,lan9372
- microchip,lan9373
- microchip,lan9374
reg:
maxItems: 1
spi-max-frequency:
maximum: 50000000
reset-gpios:
description: Optional gpio specifier for a reset line
maxItems: 1
mdio:
$ref: /schemas/net/mdio.yaml#
unevaluatedProperties: false
patternProperties:
"^(ethernet-)?ports$":
patternProperties:
"^(ethernet-)?port@[0-9]+$":
allOf:
- if:
properties:
phy-mode:
contains:
enum:
- rgmii
- rgmii-id
- rgmii-txid
- rgmii-rxid
then:
properties:
rx-internal-delay-ps:
enum: [0, 2000]
default: 0
tx-internal-delay-ps:
enum: [0, 2000]
default: 0
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
macb0 {
#address-cells = <1>;
#size-cells = <0>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
spi {
#address-cells = <1>;
#size-cells = <0>;
lan9374: switch@0 {
compatible = "microchip,lan9374";
reg = <0>;
spi-max-frequency = <44000000>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&t1phy0>;
};
port@1 {
reg = <1>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&t1phy1>;
};
port@2 {
reg = <2>;
label = "lan4";
phy-mode = "internal";
phy-handle = <&t1phy2>;
};
port@3 {
reg = <3>;
label = "lan6";
phy-mode = "internal";
phy-handle = <&t1phy3>;
};
port@4 {
reg = <4>;
phy-mode = "rgmii";
tx-internal-delay-ps = <2000>;
rx-internal-delay-ps = <2000>;
ethernet = <&macb0>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@5 {
reg = <5>;
label = "lan7";
phy-mode = "rgmii";
tx-internal-delay-ps = <2000>;
rx-internal-delay-ps = <2000>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@6 {
reg = <6>;
label = "lan5";
phy-mode = "internal";
phy-handle = <&t1phy6>;
};
port@7 {
reg = <7>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&t1phy7>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
t1phy0: ethernet-phy@0{
reg = <0x0>;
};
t1phy1: ethernet-phy@1{
reg = <0x1>;
};
t1phy2: ethernet-phy@2{
reg = <0x2>;
};
t1phy3: ethernet-phy@3{
reg = <0x3>;
};
t1phy6: ethernet-phy@6{
reg = <0x6>;
};
t1phy7: ethernet-phy@7{
reg = <0x7>;
};
};
};
};

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# SPDX-License-Identifier: (GPL-2.0 OR MIT)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/mscc,ocelot.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip Ocelot Switch Family Device Tree Bindings
maintainers:
- Vladimir Oltean <vladimir.oltean@nxp.com>
- Claudiu Manoil <claudiu.manoil@nxp.com>
- Alexandre Belloni <alexandre.belloni@bootlin.com>
- UNGLinuxDriver@microchip.com
description: |
There are multiple switches which are either part of the Ocelot-1 family, or
derivatives of this architecture. These switches can be found embedded in
various SoCs and accessed using MMIO, or as discrete chips and accessed over
SPI or PCIe. The present DSA binding shall be used when the host controlling
them performs packet I/O primarily through an Ethernet port of the switch
(which is attached to an Ethernet port of the host), rather than through
Frame DMA or register-based I/O.
VSC9953 (Seville):
This is found in the NXP T1040, where it is a memory-mapped platform
device.
The following PHY interface types are supported:
- phy-mode = "internal": on ports 8 and 9
- phy-mode = "sgmii": on ports 0, 1, 2, 3, 4, 5, 6, 7
- phy-mode = "qsgmii": on ports 0, 1, 2, 3, 4, 5, 6, 7
- phy-mode = "1000base-x": on ports 0, 1, 2, 3, 4, 5, 6, 7
VSC9959 (Felix):
This is found in the NXP LS1028A. It is a PCI device, part of the larger
enetc root complex. As a result, the ethernet-switch node is a sub-node of
the PCIe root complex node and its "reg" property conforms to the parent
node bindings, describing it as PF 5 of device 0, bus 0.
If any external switch port is enabled, the enetc PF2 (enetc_port2) should
be enabled as well. This is because the internal MDIO bus (exposed through
EA BAR 0) used to access the MAC PCS registers truly belongs to the enetc
port 2 and not to Felix.
The following PHY interface types are supported:
- phy-mode = "internal": on ports 4 and 5
- phy-mode = "sgmii": on ports 0, 1, 2, 3
- phy-mode = "qsgmii": on ports 0, 1, 2, 3
- phy-mode = "usxgmii": on ports 0, 1, 2, 3
- phy-mode = "1000base-x": on ports 0, 1, 2, 3
- phy-mode = "2500base-x": on ports 0, 1, 2, 3
properties:
compatible:
enum:
- mscc,vsc9953-switch
- pci1957,eef0
reg:
maxItems: 1
interrupts:
maxItems: 1
description:
Used to signal availability of PTP TX timestamps, and state changes of
the MAC merge layer of ports that support Frame Preemption.
little-endian: true
big-endian: true
required:
- compatible
- reg
allOf:
- $ref: dsa.yaml#
- if:
properties:
compatible:
const: pci1957,eef0
then:
required:
- interrupts
unevaluatedProperties: false
examples:
# Felix VSC9959 (NXP LS1028A)
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
pcie { /* Integrated Endpoint Root Complex */
#address-cells = <3>;
#size-cells = <2>;
ethernet-switch@0,5 {
compatible = "pci1957,eef0";
reg = <0x000500 0 0 0 0>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
phy-mode = "qsgmii";
phy-handle = <&phy0>;
managed = "in-band-status";
};
port@1 {
reg = <1>;
phy-mode = "qsgmii";
phy-handle = <&phy1>;
managed = "in-band-status";
};
port@2 {
reg = <2>;
phy-mode = "qsgmii";
phy-handle = <&phy2>;
managed = "in-band-status";
};
port@3 {
reg = <3>;
phy-mode = "qsgmii";
phy-handle = <&phy3>;
managed = "in-band-status";
};
port@4 {
reg = <4>;
ethernet = <&enetc_port2>;
phy-mode = "internal";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
port@5 {
reg = <5>;
ethernet = <&enetc_port3>;
phy-mode = "internal";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
};
};
};
# Seville VSC9953 (NXP T1040)
- |
soc {
#address-cells = <1>;
#size-cells = <1>;
ethernet-switch@800000 {
compatible = "mscc,vsc9953-switch";
reg = <0x800000 0x290000>;
little-endian;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
phy-mode = "qsgmii";
phy-handle = <&phy0>;
managed = "in-band-status";
};
port@1 {
reg = <1>;
phy-mode = "qsgmii";
phy-handle = <&phy1>;
managed = "in-band-status";
};
port@2 {
reg = <2>;
phy-mode = "qsgmii";
phy-handle = <&phy2>;
managed = "in-band-status";
};
port@3 {
reg = <3>;
phy-mode = "qsgmii";
phy-handle = <&phy3>;
managed = "in-band-status";
};
port@4 {
reg = <4>;
phy-mode = "qsgmii";
phy-handle = <&phy4>;
managed = "in-band-status";
};
port@5 {
reg = <5>;
phy-mode = "qsgmii";
phy-handle = <&phy5>;
managed = "in-band-status";
};
port@6 {
reg = <6>;
phy-mode = "qsgmii";
phy-handle = <&phy6>;
managed = "in-band-status";
};
port@7 {
reg = <7>;
phy-mode = "qsgmii";
phy-handle = <&phy7>;
managed = "in-band-status";
};
port@8 {
reg = <8>;
phy-mode = "internal";
ethernet = <&enet0>;
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
port@9 {
reg = <9>;
phy-mode = "internal";
ethernet = <&enet1>;
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/nxp,sja1105.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP SJA1105 Automotive Ethernet Switch Family Device Tree Bindings
description:
The SJA1105 SPI interface requires a CS-to-CLK time (t2 in UM10944.pdf) of at
least one half of t_CLK. At an SPI frequency of 1MHz, this means a minimum
cs_sck_delay of 500ns. Ensuring that this SPI timing requirement is observed
depends on the SPI bus master driver.
allOf:
- $ref: "dsa.yaml#"
- $ref: /schemas/spi/spi-peripheral-props.yaml#
maintainers:
- Vladimir Oltean <vladimir.oltean@nxp.com>
properties:
compatible:
enum:
- nxp,sja1105e
- nxp,sja1105t
- nxp,sja1105p
- nxp,sja1105q
- nxp,sja1105r
- nxp,sja1105s
- nxp,sja1110a
- nxp,sja1110b
- nxp,sja1110c
- nxp,sja1110d
reg:
maxItems: 1
# Optional container node for the 2 internal MDIO buses of the SJA1110
# (one for the internal 100base-T1 PHYs and the other for the single
# 100base-TX PHY). The "reg" property does not have physical significance.
# The PHY addresses to port correspondence is as follows: for 100base-T1,
# port 5 has PHY 1, port 6 has PHY 2 etc, while for 100base-TX, port 1 has
# PHY 1.
mdios:
type: object
properties:
'#address-cells':
const: 1
'#size-cells':
const: 0
patternProperties:
"^mdio@[0-1]$":
$ref: /schemas/net/mdio.yaml#
unevaluatedProperties: false
properties:
compatible:
oneOf:
- enum:
- nxp,sja1110-base-t1-mdio
- nxp,sja1110-base-tx-mdio
reg:
oneOf:
- enum:
- 0
- 1
required:
- compatible
- reg
patternProperties:
"^(ethernet-)?ports$":
patternProperties:
"^(ethernet-)?port@[0-9]+$":
allOf:
- if:
properties:
phy-mode:
contains:
enum:
- rgmii
- rgmii-rxid
- rgmii-txid
- rgmii-id
then:
properties:
rx-internal-delay-ps:
$ref: "#/$defs/internal-delay-ps"
tx-internal-delay-ps:
$ref: "#/$defs/internal-delay-ps"
required:
- compatible
- reg
$defs:
internal-delay-ps:
description:
Disable tunable delay lines using 0 ps, or enable them and select
the phase between 1640 ps (73.8 degree shift at 1Gbps) and 2260 ps
(101.7 degree shift) in increments of 0.9 degrees (20 ps).
enum:
[0, 1640, 1660, 1680, 1700, 1720, 1740, 1760, 1780, 1800, 1820, 1840,
1860, 1880, 1900, 1920, 1940, 1960, 1980, 2000, 2020, 2040, 2060, 2080,
2100, 2120, 2140, 2160, 2180, 2200, 2220, 2240, 2260]
unevaluatedProperties: false
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
ethernet-switch@1 {
reg = <0x1>;
compatible = "nxp,sja1105t";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
phy-handle = <&rgmii_phy6>;
phy-mode = "rgmii-id";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
reg = <0>;
};
port@1 {
phy-handle = <&rgmii_phy3>;
phy-mode = "rgmii-id";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
reg = <1>;
};
port@2 {
phy-handle = <&rgmii_phy4>;
phy-mode = "rgmii-id";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
reg = <2>;
};
port@3 {
phy-handle = <&rgmii_phy4>;
phy-mode = "rgmii-id";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
reg = <3>;
};
port@4 {
ethernet = <&enet2>;
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
reg = <4>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/qca8k.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Atheros QCA83xx switch family
maintainers:
- John Crispin <john@phrozen.org>
description:
If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
describing a port needs to have a valid phandle referencing the internal PHY
it is connected to. This is because there is no N:N mapping of port and PHY
ID. To declare the internal mdio-bus configuration, declare an MDIO node in
the switch node and declare the phandle for the port, referencing the internal
PHY it is connected to. In this config, an internal mdio-bus is registered and
the MDIO master is used for communication. Mixed external and internal
mdio-bus configurations are not supported by the hardware.
properties:
compatible:
oneOf:
- enum:
- qca,qca8327
- qca,qca8328
- qca,qca8334
- qca,qca8337
description: |
qca,qca8328: referenced as AR8328(N)-AK1(A/B) QFN 176 pin package
qca,qca8327: referenced as AR8327(N)-AL1A DR-QFN 148 pin package
qca,qca8334: referenced as QCA8334-AL3C QFN 88 pin package
qca,qca8337: referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package
reg:
maxItems: 1
reset-gpios:
description:
GPIO to be used to reset the whole device
maxItems: 1
qca,ignore-power-on-sel:
$ref: /schemas/types.yaml#/definitions/flag
description:
Ignore power-on pin strapping to configure LED open-drain or EEPROM
presence. This is needed for devices with incorrect configuration or when
the OEM has decided not to use pin strapping and falls back to SW regs.
qca,led-open-drain:
$ref: /schemas/types.yaml#/definitions/flag
description:
Set LEDs to open-drain mode. This requires the qca,ignore-power-on-sel to
be set, otherwise the driver will fail at probe. This is required if the
OEM does not use pin strapping to set this mode and prefers to set it
using SW regs. The pin strappings related to LED open-drain mode are
B68 on the QCA832x and B49 on the QCA833x.
mdio:
$ref: /schemas/net/mdio.yaml#
unevaluatedProperties: false
description: Qca8k switch have an internal mdio to access switch port.
If this is not present, the legacy mapping is used and the
internal mdio access is used.
With the legacy mapping the reg corresponding to the internal
mdio is the switch reg with an offset of -1.
patternProperties:
"^(ethernet-)?ports$":
type: object
properties:
'#address-cells':
const: 1
'#size-cells':
const: 0
patternProperties:
"^(ethernet-)?port@[0-6]$":
type: object
description: Ethernet switch ports
$ref: dsa-port.yaml#
properties:
qca,sgmii-rxclk-falling-edge:
$ref: /schemas/types.yaml#/definitions/flag
description:
Set the receive clock phase to falling edge. Mostly commonly used on
the QCA8327 with CPU port 0 set to SGMII.
qca,sgmii-txclk-falling-edge:
$ref: /schemas/types.yaml#/definitions/flag
description:
Set the transmit clock phase to falling edge.
qca,sgmii-enable-pll:
$ref: /schemas/types.yaml#/definitions/flag
description:
For SGMII CPU port, explicitly enable PLL, TX and RX chain along with
Signal Detection. On the QCA8327 this should not be enabled, otherwise
the SGMII port will not initialize. When used on the QCA8337, revision 3
or greater, a warning will be displayed. When the CPU port is set to
SGMII on the QCA8337, it is advised to set this unless a communication
issue is observed.
unevaluatedProperties: false
oneOf:
- required:
- ports
- required:
- ethernet-ports
required:
- compatible
- reg
additionalProperties: true
examples:
- |
#include <dt-bindings/gpio/gpio.h>
mdio {
#address-cells = <1>;
#size-cells = <0>;
external_phy_port1: ethernet-phy@0 {
reg = <0>;
};
external_phy_port2: ethernet-phy@1 {
reg = <1>;
};
external_phy_port3: ethernet-phy@2 {
reg = <2>;
};
external_phy_port4: ethernet-phy@3 {
reg = <3>;
};
external_phy_port5: ethernet-phy@4 {
reg = <4>;
};
switch@10 {
compatible = "qca,qca8337";
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
reg = <0x10>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ethernet = <&gmac1>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@1 {
reg = <1>;
label = "lan1";
phy-handle = <&external_phy_port1>;
};
port@2 {
reg = <2>;
label = "lan2";
phy-handle = <&external_phy_port2>;
};
port@3 {
reg = <3>;
label = "lan3";
phy-handle = <&external_phy_port3>;
};
port@4 {
reg = <4>;
label = "lan4";
phy-handle = <&external_phy_port4>;
};
port@5 {
reg = <5>;
label = "wan";
phy-handle = <&external_phy_port5>;
};
};
};
};
- |
#include <dt-bindings/gpio/gpio.h>
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch@10 {
compatible = "qca,qca8337";
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
reg = <0x10>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ethernet = <&gmac1>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@1 {
reg = <1>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&internal_phy_port1>;
};
port@2 {
reg = <2>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&internal_phy_port2>;
};
port@3 {
reg = <3>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&internal_phy_port3>;
};
port@4 {
reg = <4>;
label = "lan4";
phy-mode = "internal";
phy-handle = <&internal_phy_port4>;
};
port@5 {
reg = <5>;
label = "wan";
phy-mode = "internal";
phy-handle = <&internal_phy_port5>;
};
port@6 {
reg = <0>;
ethernet = <&gmac1>;
phy-mode = "sgmii";
qca,sgmii-rxclk-falling-edge;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
internal_phy_port1: ethernet-phy@0 {
reg = <0>;
};
internal_phy_port2: ethernet-phy@1 {
reg = <1>;
};
internal_phy_port3: ethernet-phy@2 {
reg = <2>;
};
internal_phy_port4: ethernet-phy@3 {
reg = <3>;
};
internal_phy_port5: ethernet-phy@4 {
reg = <4>;
};
};
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/realtek.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Realtek switches for unmanaged switches
allOf:
- $ref: dsa.yaml#
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
description:
Realtek advertises these chips as fast/gigabit switches or unmanaged
switches. They can be controlled using different interfaces, like SMI,
MDIO or SPI.
The SMI "Simple Management Interface" is a two-wire protocol using
bit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does
not use the MDIO protocol. This binding defines how to specify the
SMI-based Realtek devices. The realtek-smi driver is a platform driver
and it must be inserted inside a platform node.
The MDIO-connected switches use MDIO protocol to access their registers.
The realtek-mdio driver is an MDIO driver and it must be inserted inside
an MDIO node.
The compatible string is only used to identify which (silicon) family the
switch belongs to. Roughly speaking, a family is any set of Realtek switches
whose chip identification register(s) have a common location and semantics.
The different models in a given family can be automatically disambiguated by
parsing the chip identification register(s) according to the given family,
avoiding the need for a unique compatible string for each model.
properties:
compatible:
enum:
- realtek,rtl8365mb
- realtek,rtl8366rb
description: |
realtek,rtl8365mb:
Use with models RTL8363NB, RTL8363NB-VB, RTL8363SC, RTL8363SC-VB,
RTL8364NB, RTL8364NB-VB, RTL8365MB, RTL8366SC, RTL8367RB-VB, RTL8367S,
RTL8367SB, RTL8370MB, RTL8310SR
realtek,rtl8366rb:
Use with models RTL8366RB, RTL8366S
mdc-gpios:
description: GPIO line for the MDC clock line.
maxItems: 1
mdio-gpios:
description: GPIO line for the MDIO data line.
maxItems: 1
reset-gpios:
description: GPIO to be used to reset the whole device
maxItems: 1
realtek,disable-leds:
type: boolean
description: |
if the LED drivers are not used in the hardware design,
this will disable them so they are not turned on
and wasting power.
interrupt-controller:
type: object
description: |
This defines an interrupt controller with an IRQ line (typically
a GPIO) that will demultiplex and handle the interrupt from the single
interrupt line coming out of one of the Realtek switch chips. It most
importantly provides link up/down interrupts to the PHY blocks inside
the ASIC.
properties:
interrupt-controller: true
interrupts:
maxItems: 1
description:
A single IRQ line from the switch, either active LOW or HIGH
'#address-cells':
const: 0
'#interrupt-cells':
const: 1
required:
- interrupt-controller
- '#address-cells'
- '#interrupt-cells'
mdio:
$ref: /schemas/net/mdio.yaml#
unevaluatedProperties: false
properties:
compatible:
const: realtek,smi-mdio
if:
required:
- reg
then:
$ref: /schemas/spi/spi-peripheral-props.yaml#
not:
required:
- mdc-gpios
- mdio-gpios
- mdio
properties:
mdc-gpios: false
mdio-gpios: false
mdio: false
else:
required:
- mdc-gpios
- mdio-gpios
- mdio
- reset-gpios
required:
- compatible
# - mdc-gpios
# - mdio-gpios
# - reset-gpios
# - mdio
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
platform {
switch {
compatible = "realtek,rtl8366rb";
/* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */
mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
mdio-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
switch_intc1: interrupt-controller {
/* GPIO 15 provides the interrupt */
interrupt-parent = <&gpio0>;
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan0";
phy-handle = <&phy0>;
};
port@1 {
reg = <1>;
label = "lan1";
phy-handle = <&phy1>;
};
port@2 {
reg = <2>;
label = "lan2";
phy-handle = <&phy2>;
};
port@3 {
reg = <3>;
label = "lan3";
phy-handle = <&phy3>;
};
port@4 {
reg = <4>;
label = "wan";
phy-handle = <&phy4>;
};
port@5 {
reg = <5>;
ethernet = <&gmac0>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
mdio {
compatible = "realtek,smi-mdio";
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
interrupt-parent = <&switch_intc1>;
interrupts = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
interrupt-parent = <&switch_intc1>;
interrupts = <1>;
};
phy2: ethernet-phy@2 {
reg = <2>;
interrupt-parent = <&switch_intc1>;
interrupts = <2>;
};
phy3: ethernet-phy@3 {
reg = <3>;
interrupt-parent = <&switch_intc1>;
interrupts = <3>;
};
phy4: ethernet-phy@4 {
reg = <4>;
interrupt-parent = <&switch_intc1>;
interrupts = <12>;
};
};
};
};
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
platform {
switch {
compatible = "realtek,rtl8365mb";
mdc-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
mdio-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
switch_intc2: interrupt-controller {
interrupt-parent = <&gpio5>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "swp0";
phy-handle = <&ethphy0>;
};
port@1 {
reg = <1>;
label = "swp1";
phy-handle = <&ethphy1>;
};
port@2 {
reg = <2>;
label = "swp2";
phy-handle = <&ethphy2>;
};
port@3 {
reg = <3>;
label = "swp3";
phy-handle = <&ethphy3>;
};
port@6 {
reg = <6>;
ethernet = <&fec1>;
phy-mode = "rgmii";
tx-internal-delay-ps = <2000>;
rx-internal-delay-ps = <2000>;
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
};
mdio {
compatible = "realtek,smi-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
reg = <0>;
interrupt-parent = <&switch_intc2>;
interrupts = <0>;
};
ethphy1: ethernet-phy@1 {
reg = <1>;
interrupt-parent = <&switch_intc2>;
interrupts = <1>;
};
ethphy2: ethernet-phy@2 {
reg = <2>;
interrupt-parent = <&switch_intc2>;
interrupts = <2>;
};
ethphy3: ethernet-phy@3 {
reg = <3>;
interrupt-parent = <&switch_intc2>;
interrupts = <3>;
};
};
};
};
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch@29 {
compatible = "realtek,rtl8365mb";
reg = <29>;
reset-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
switch_intc3: interrupt-controller {
interrupt-parent = <&gpio0>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan4";
};
port@1 {
reg = <1>;
label = "lan3";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan1";
};
port@4 {
reg = <4>;
label = "wan";
};
port@7 {
reg = <7>;
ethernet = <&ethernet>;
phy-mode = "rgmii";
tx-internal-delay-ps = <2000>;
rx-internal-delay-ps = <0>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/renesas,rzn1-a5psw.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/N1 Advanced 5 ports ethernet switch
maintainers:
- Clément Léger <clement.leger@bootlin.com>
description: |
The advanced 5 ports switch is present on the Renesas RZ/N1 SoC family and
handles 4 ports + 1 CPU management port.
allOf:
- $ref: dsa.yaml#
properties:
compatible:
items:
- enum:
- renesas,r9a06g032-a5psw
- const: renesas,rzn1-a5psw
reg:
maxItems: 1
interrupts:
items:
- description: Device Level Ring (DLR) interrupt
- description: Switch interrupt
- description: Parallel Redundancy Protocol (PRP) interrupt
- description: Integrated HUB module interrupt
- description: Receive Pattern Match interrupt
interrupt-names:
items:
- const: dlr
- const: switch
- const: prp
- const: hub
- const: ptrn
power-domains:
maxItems: 1
mdio:
$ref: /schemas/net/mdio.yaml#
unevaluatedProperties: false
clocks:
items:
- description: AHB clock used for the switch register interface
- description: Switch system clock
clock-names:
items:
- const: hclk
- const: clk
ethernet-ports:
type: object
properties:
'#address-cells':
const: 1
'#size-cells':
const: 0
patternProperties:
"^(ethernet-)?port@[0-4]$":
type: object
description: Ethernet switch ports
properties:
pcs-handle:
description:
phandle pointing to a PCS sub-node compatible with
renesas,rzn1-miic.yaml#
$ref: /schemas/types.yaml#/definitions/phandle
unevaluatedProperties: false
required:
- compatible
- reg
- clocks
- clock-names
- power-domains
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/r9a06g032-sysctrl.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
switch@44050000 {
compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw";
reg = <0x44050000 0x10000>;
clocks = <&sysctrl R9A06G032_HCLK_SWITCH>, <&sysctrl R9A06G032_CLK_SWITCH>;
clock-names = "hclk", "clk";
power-domains = <&sysctrl>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dlr", "switch", "prp", "hub", "ptrn";
dsa,member = <0 0>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan0";
phy-handle = <&switch0phy3>;
pcs-handle = <&mii_conv4>;
};
port@1 {
reg = <1>;
label = "lan1";
phy-handle = <&switch0phy1>;
pcs-handle = <&mii_conv3>;
};
port@4 {
reg = <4>;
ethernet = <&gmac2>;
phy-mode = "internal";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&gpio0a 2 GPIO_ACTIVE_HIGH>;
reset-delay-us = <15>;
clock-frequency = <2500000>;
switch0phy1: ethernet-phy@1{
reg = <1>;
};
switch0phy3: ethernet-phy@3{
reg = <3>;
};
};
};

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Vitesse VSC73xx Switches
========================
This defines device tree bindings for the Vitesse VSC73xx switch chips.
The Vitesse company has been acquired by Microsemi and Microsemi has
been acquired Microchip but retains this vendor branding.
The currently supported switch chips are:
Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
This switch could have two different management interface.
If SPI interface is used, the device tree node is an SPI device so it must
reside inside a SPI bus device tree node, see spi/spi-bus.txt
When the chip is connected to a parallel memory bus and work in memory-mapped
I/O mode, a platform device is used to represent the vsc73xx. In this case it
must reside inside a platform bus device tree node.
Required properties:
- compatible: must be exactly one of:
"vitesse,vsc7385"
"vitesse,vsc7388"
"vitesse,vsc7395"
"vitesse,vsc7398"
- gpio-controller: indicates that this switch is also a GPIO controller,
see gpio/gpio.txt
- #gpio-cells: this must be set to <2> and indicates that we are a twocell
GPIO controller, see gpio/gpio.txt
Optional properties:
- reset-gpios: a handle to a GPIO line that can issue reset of the chip.
It should be tagged as active low.
Required subnodes:
See net/dsa/dsa.txt for a list of additional required and optional properties
and subnodes of DSA switches.
Examples:
SPI:
switch@0 {
compatible = "vitesse,vsc7395";
reg = <0>;
/* Specified for 2.5 MHz or below */
spi-max-frequency = <2500000>;
gpio-controller;
#gpio-cells = <2>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
vsc: port@6 {
reg = <6>;
ethernet = <&gmac1>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
};
};
Platform:
switch@2,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "vitesse,vsc7385";
reg = <0x2 0x0 0x20000>;
reset-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
vsc: port@6 {
reg = <6>;
ethernet = <&enet0>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
};
};