dt-bindings: Add devicetree bindings
Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").
Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
This commit is contained in:
Melody Olvera
115
bindings/mmc/allwinner,sun4i-a10-mmc.yaml
Normal file
115
bindings/mmc/allwinner,sun4i-a10-mmc.yaml
Normal file
@@ -0,0 +1,115 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/allwinner,sun4i-a10-mmc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A10 MMC Controller
|
||||
|
||||
allOf:
|
||||
- $ref: "mmc-controller.yaml"
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
properties:
|
||||
"#address-cells": true
|
||||
"#size-cells": true
|
||||
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: allwinner,sun4i-a10-mmc
|
||||
- const: allwinner,sun5i-a13-mmc
|
||||
- const: allwinner,sun7i-a20-mmc
|
||||
- const: allwinner,sun8i-a83t-emmc
|
||||
- const: allwinner,sun9i-a80-mmc
|
||||
- const: allwinner,sun20i-d1-mmc
|
||||
- const: allwinner,sun50i-a64-emmc
|
||||
- const: allwinner,sun50i-a64-mmc
|
||||
- const: allwinner,sun50i-a100-emmc
|
||||
- const: allwinner,sun50i-a100-mmc
|
||||
- items:
|
||||
- const: allwinner,sun8i-a83t-mmc
|
||||
- const: allwinner,sun7i-a20-mmc
|
||||
- items:
|
||||
- const: allwinner,sun8i-r40-emmc
|
||||
- const: allwinner,sun50i-a64-emmc
|
||||
- items:
|
||||
- const: allwinner,sun8i-r40-mmc
|
||||
- const: allwinner,sun50i-a64-mmc
|
||||
- items:
|
||||
- const: allwinner,sun50i-h5-emmc
|
||||
- const: allwinner,sun50i-a64-emmc
|
||||
- items:
|
||||
- const: allwinner,sun50i-h5-mmc
|
||||
- const: allwinner,sun50i-a64-mmc
|
||||
- items:
|
||||
- const: allwinner,sun50i-h6-emmc
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||||
- const: allwinner,sun50i-a64-emmc
|
||||
- items:
|
||||
- const: allwinner,sun50i-h6-mmc
|
||||
- const: allwinner,sun50i-a64-mmc
|
||||
- items:
|
||||
- const: allwinner,sun20i-d1-emmc
|
||||
- const: allwinner,sun50i-a100-emmc
|
||||
- items:
|
||||
- const: allwinner,sun50i-h616-emmc
|
||||
- const: allwinner,sun50i-a100-emmc
|
||||
- items:
|
||||
- const: allwinner,sun50i-h616-mmc
|
||||
- const: allwinner,sun50i-a100-mmc
|
||||
- items:
|
||||
- const: allwinner,suniv-f1c100s-mmc
|
||||
- const: allwinner,sun7i-a20-mmc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
items:
|
||||
- description: Bus Clock
|
||||
- description: Module Clock
|
||||
- description: Output Clock
|
||||
- description: Sample Clock
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
items:
|
||||
- const: ahb
|
||||
- const: mmc
|
||||
- const: output
|
||||
- const: sample
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
const: ahb
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
mmc0: mmc@1c0f000 {
|
||||
compatible = "allwinner,sun5i-a13-mmc";
|
||||
reg = <0x01c0f000 0x1000>;
|
||||
clocks = <&ahb_gates 8>, <&mmc0_clk>;
|
||||
clock-names = "ahb", "mmc";
|
||||
interrupts = <32>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&pio 7 1 0>;
|
||||
};
|
||||
|
||||
...
|
||||
39
bindings/mmc/amlogic,meson-gx.txt
Normal file
39
bindings/mmc/amlogic,meson-gx.txt
Normal file
@@ -0,0 +1,39 @@
|
||||
Amlogic SD / eMMC controller for S905/GXBB family SoCs
|
||||
|
||||
The MMC 5.1 compliant host controller on Amlogic provides the
|
||||
interface for SD, eMMC and SDIO devices.
|
||||
|
||||
This file documents the properties in addition to those available in
|
||||
the MMC core bindings, documented by mmc.txt.
|
||||
|
||||
Required properties:
|
||||
- compatible : contains one of:
|
||||
- "amlogic,meson-gx-mmc"
|
||||
- "amlogic,meson-gxbb-mmc"
|
||||
- "amlogic,meson-gxl-mmc"
|
||||
- "amlogic,meson-gxm-mmc"
|
||||
- "amlogic,meson-axg-mmc"
|
||||
- clocks : A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
|
||||
- clock-names: Should contain the following:
|
||||
"core" - Main peripheral bus clock
|
||||
"clkin0" - Parent clock of internal mux
|
||||
"clkin1" - Other parent clock of internal mux
|
||||
The driver has an internal mux clock which switches between clkin0 and clkin1 depending on the
|
||||
clock rate requested by the MMC core.
|
||||
- resets : phandle of the internal reset line
|
||||
|
||||
Optional properties:
|
||||
- amlogic,dram-access-quirk: set when controller's internal DMA engine cannot access the
|
||||
DRAM memory, like on the G12A dedicated SDIO controller.
|
||||
|
||||
Example:
|
||||
|
||||
sd_emmc_a: mmc@70000 {
|
||||
compatible = "amlogic,meson-gxbb-mmc";
|
||||
reg = <0x0 0x70000 0x0 0x2000>;
|
||||
interrupts = < GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&clkc CLKID_SD_EMMC_A>, <&xtal>, <&clkc CLKID_FCLK_DIV2>;
|
||||
clock-names = "core", "clkin0", "clkin1";
|
||||
pinctrl-0 = <&emmc_pins>;
|
||||
resets = <&reset RESET_SD_EMMC_A>;
|
||||
};
|
||||
70
bindings/mmc/amlogic,meson-mx-sdhc.yaml
Normal file
70
bindings/mmc/amlogic,meson-mx-sdhc.yaml
Normal file
@@ -0,0 +1,70 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/amlogic,meson-mx-sdhc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Amlogic Meson SDHC controller
|
||||
|
||||
allOf:
|
||||
- $ref: "mmc-controller.yaml"
|
||||
|
||||
maintainers:
|
||||
- Martin Blumenstingl <martin.blumenstingl@googlemail.com>
|
||||
|
||||
description: |
|
||||
The SDHC MMC host controller on Amlogic SoCs provides an eMMC and MMC
|
||||
card interface with 1/4/8-bit bus width.
|
||||
It supports eMMC spec 4.4x/4.5x including HS200 (up to 100MHz clock).
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- amlogic,meson8-sdhc
|
||||
- amlogic,meson8b-sdhc
|
||||
- amlogic,meson8m2-sdhc
|
||||
- const: amlogic,meson-mx-sdhc
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
|
||||
interrupts:
|
||||
minItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 5
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: clkin0
|
||||
- const: clkin1
|
||||
- const: clkin2
|
||||
- const: clkin3
|
||||
- const: pclk
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
sdhc: mmc@8e00 {
|
||||
compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";
|
||||
reg = <0x8e00 0x42>;
|
||||
interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&xtal>,
|
||||
<&fclk_div4>,
|
||||
<&fclk_div3>,
|
||||
<&fclk_div5>,
|
||||
<&sdhc_pclk>;
|
||||
clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk";
|
||||
};
|
||||
54
bindings/mmc/amlogic,meson-mx-sdio.txt
Normal file
54
bindings/mmc/amlogic,meson-mx-sdio.txt
Normal file
@@ -0,0 +1,54 @@
|
||||
* Amlogic Meson6, Meson8 and Meson8b SDIO/MMC controller
|
||||
|
||||
The highspeed MMC host controller on Amlogic SoCs provides an interface
|
||||
for MMC, SD, SDIO and SDHC types of memory cards.
|
||||
|
||||
Supported maximum speeds are the ones of the eMMC standard 4.41 as well
|
||||
as the speed of SD standard 2.0.
|
||||
|
||||
The hardware provides an internal "mux" which allows up to three slots
|
||||
to be controlled. Only one slot can be accessed at a time.
|
||||
|
||||
Required properties:
|
||||
- compatible : must be one of
|
||||
- "amlogic,meson8-sdio"
|
||||
- "amlogic,meson8b-sdio"
|
||||
along with the generic "amlogic,meson-mx-sdio"
|
||||
- reg : mmc controller base registers
|
||||
- interrupts : mmc controller interrupt
|
||||
- #address-cells : must be 1
|
||||
- size-cells : must be 0
|
||||
- clocks : phandle to clock providers
|
||||
- clock-names : must contain "core" and "clkin"
|
||||
|
||||
Required child nodes:
|
||||
A node for each slot provided by the MMC controller is required.
|
||||
NOTE: due to a driver limitation currently only one slot (= child node)
|
||||
is supported!
|
||||
|
||||
Required properties on each child node (= slot):
|
||||
- compatible : must be "mmc-slot" (see mmc.txt within this directory)
|
||||
- reg : the slot (or "port") ID
|
||||
|
||||
Optional properties on each child node (= slot):
|
||||
- bus-width : must be 1 or 4 (8-bit bus is not supported)
|
||||
- for cd and all other additional generic mmc parameters
|
||||
please refer to mmc.txt within this directory
|
||||
|
||||
Examples:
|
||||
mmc@c1108c20 {
|
||||
compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
|
||||
reg = <0xc1108c20 0x20>;
|
||||
interrupts = <0 28 1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
|
||||
clock-names = "core", "clkin";
|
||||
|
||||
slot@1 {
|
||||
compatible = "mmc-slot";
|
||||
reg = <1>;
|
||||
|
||||
bus-width = <4>;
|
||||
};
|
||||
};
|
||||
330
bindings/mmc/arasan,sdhci.yaml
Normal file
330
bindings/mmc/arasan,sdhci.yaml
Normal file
@@ -0,0 +1,330 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/mmc/arasan,sdhci.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Device Tree Bindings for the Arasan SDHCI Controller
|
||||
|
||||
maintainers:
|
||||
- Adrian Hunter <adrian.hunter@intel.com>
|
||||
|
||||
allOf:
|
||||
- $ref: "mmc-controller.yaml#"
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: arasan,sdhci-5.1
|
||||
then:
|
||||
required:
|
||||
- phys
|
||||
- phy-names
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- xlnx,zynqmp-8.9a
|
||||
- xlnx,versal-8.9a
|
||||
then:
|
||||
properties:
|
||||
clock-output-names:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: clk_out_sd0
|
||||
- const: clk_in_sd0
|
||||
- items:
|
||||
- const: clk_out_sd1
|
||||
- const: clk_in_sd1
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: arasan,sdhci-8.9a # generic Arasan SDHCI 8.9a PHY
|
||||
- const: arasan,sdhci-4.9a # generic Arasan SDHCI 4.9a PHY
|
||||
- const: arasan,sdhci-5.1 # generic Arasan SDHCI 5.1 PHY
|
||||
- items:
|
||||
- const: rockchip,rk3399-sdhci-5.1 # rk3399 eMMC PHY
|
||||
- const: arasan,sdhci-5.1
|
||||
description:
|
||||
For this device it is strongly suggested to include
|
||||
arasan,soc-ctl-syscon.
|
||||
- items:
|
||||
- const: xlnx,zynqmp-8.9a # ZynqMP SDHCI 8.9a PHY
|
||||
- const: arasan,sdhci-8.9a
|
||||
description:
|
||||
For this device it is strongly suggested to include
|
||||
clock-output-names and '#clock-cells'.
|
||||
- items:
|
||||
- const: xlnx,versal-8.9a # Versal SDHCI 8.9a PHY
|
||||
- const: arasan,sdhci-8.9a
|
||||
description:
|
||||
For this device it is strongly suggested to include
|
||||
clock-output-names and '#clock-cells'.
|
||||
- items:
|
||||
- const: intel,lgm-sdhci-5.1-emmc # Intel LGM eMMC PHY
|
||||
- const: arasan,sdhci-5.1
|
||||
description:
|
||||
For this device it is strongly suggested to include
|
||||
arasan,soc-ctl-syscon.
|
||||
- items:
|
||||
- const: intel,lgm-sdhci-5.1-sdxc # Intel LGM SDXC PHY
|
||||
- const: arasan,sdhci-5.1
|
||||
description:
|
||||
For this device it is strongly suggested to include
|
||||
arasan,soc-ctl-syscon.
|
||||
- items:
|
||||
- const: intel,keembay-sdhci-5.1-emmc # Intel Keem Bay eMMC PHY
|
||||
- const: arasan,sdhci-5.1
|
||||
description:
|
||||
For this device it is strongly suggested to include
|
||||
arasan,soc-ctl-syscon.
|
||||
- const: intel,keembay-sdhci-5.1-sd # Intel Keem Bay SD controller
|
||||
description:
|
||||
For this device it is strongly suggested to include
|
||||
arasan,soc-ctl-syscon.
|
||||
- const: intel,keembay-sdhci-5.1-sdio # Intel Keem Bay SDIO controller
|
||||
description:
|
||||
For this device it is strongly suggested to include
|
||||
arasan,soc-ctl-syscon.
|
||||
- items:
|
||||
- const: intel,thunderbay-sdhci-5.1 # Intel Thunder Bay eMMC PHY
|
||||
- const: arasan,sdhci-5.1
|
||||
description:
|
||||
For this device it is strongly suggested to include
|
||||
clock-output-names and '#clock-cells'.
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
items:
|
||||
- const: clk_xin
|
||||
- const: clk_ahb
|
||||
- const: gate
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
phy-names:
|
||||
const: phy_arasan
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
arasan,soc-ctl-syscon:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
A phandle to a syscon device (see ../mfd/syscon.txt) used to access
|
||||
core corecfg registers. Offsets of registers in this syscon are
|
||||
determined based on the main compatible string for the device.
|
||||
|
||||
clock-output-names:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
description:
|
||||
Name of the card clock which will be exposed by this device.
|
||||
|
||||
'#clock-cells':
|
||||
enum: [0, 1]
|
||||
description:
|
||||
With this property in place we will export one or two clocks
|
||||
representing the Card Clock. These clocks are expected to be
|
||||
consumed by our PHY.
|
||||
|
||||
xlnx,fails-without-test-cd:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
When present, the controller doesn't work when the CD line is not
|
||||
connected properly, and the line is not connected properly.
|
||||
Test mode can be used to force the controller to function.
|
||||
|
||||
xlnx,int-clock-stable-broken:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
When present, the controller always reports that the internal clock
|
||||
is stable even when it is not.
|
||||
|
||||
xlnx,mio-bank:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2]
|
||||
default: 0
|
||||
description:
|
||||
The MIO bank number in which the command and data lines are configured.
|
||||
|
||||
dependencies:
|
||||
'#clock-cells': [ clock-output-names ]
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
mmc@e0100000 {
|
||||
compatible = "arasan,sdhci-8.9a";
|
||||
reg = <0xe0100000 0x1000>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clocks = <&clkc 21>, <&clkc 32>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 24 4>;
|
||||
};
|
||||
|
||||
- |
|
||||
mmc@e2800000 {
|
||||
compatible = "arasan,sdhci-5.1";
|
||||
reg = <0xe2800000 0x1000>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clocks = <&cru 8>, <&cru 18>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 24 4>;
|
||||
phys = <&emmc_phy>;
|
||||
phy-names = "phy_arasan";
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/clock/rk3399-cru.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
mmc@fe330000 {
|
||||
compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
|
||||
reg = <0xfe330000 0x10000>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
arasan,soc-ctl-syscon = <&grf>;
|
||||
assigned-clocks = <&cru SCLK_EMMC>;
|
||||
assigned-clock-rates = <200000000>;
|
||||
clock-output-names = "emmc_cardclock";
|
||||
phys = <&emmc_phy>;
|
||||
phy-names = "phy_arasan";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
- |
|
||||
mmc@ff160000 {
|
||||
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 48 4>;
|
||||
reg = <0xff160000 0x1000>;
|
||||
clocks = <&clk200>, <&clk200>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clock-output-names = "clk_out_sd0", "clk_in_sd0";
|
||||
#clock-cells = <1>;
|
||||
clk-phase-sd-hs = <63>, <72>;
|
||||
};
|
||||
|
||||
- |
|
||||
mmc@f1040000 {
|
||||
compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 126 4>;
|
||||
reg = <0xf1040000 0x10000>;
|
||||
clocks = <&clk200>, <&clk200>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clock-output-names = "clk_out_sd0", "clk_in_sd0";
|
||||
#clock-cells = <1>;
|
||||
clk-phase-sd-hs = <132>, <60>;
|
||||
};
|
||||
|
||||
- |
|
||||
#define LGM_CLK_EMMC5
|
||||
#define LGM_CLK_NGI
|
||||
#define LGM_GCLK_EMMC
|
||||
mmc@ec700000 {
|
||||
compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
|
||||
reg = <0xec700000 0x300>;
|
||||
interrupt-parent = <&ioapic1>;
|
||||
interrupts = <44 1>;
|
||||
clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>,
|
||||
<&cgu0 LGM_GCLK_EMMC>;
|
||||
clock-names = "clk_xin", "clk_ahb", "gate";
|
||||
clock-output-names = "emmc_cardclock";
|
||||
#clock-cells = <0>;
|
||||
phys = <&emmc_phy>;
|
||||
phy-names = "phy_arasan";
|
||||
arasan,soc-ctl-syscon = <&sysconf>;
|
||||
};
|
||||
|
||||
- |
|
||||
#define LGM_CLK_SDIO
|
||||
#define LGM_GCLK_SDXC
|
||||
mmc@ec600000 {
|
||||
compatible = "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1";
|
||||
reg = <0xec600000 0x300>;
|
||||
interrupt-parent = <&ioapic1>;
|
||||
interrupts = <43 1>;
|
||||
clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>,
|
||||
<&cgu0 LGM_GCLK_SDXC>;
|
||||
clock-names = "clk_xin", "clk_ahb", "gate";
|
||||
clock-output-names = "sdxc_cardclock";
|
||||
#clock-cells = <0>;
|
||||
phys = <&sdxc_phy>;
|
||||
phy-names = "phy_arasan";
|
||||
arasan,soc-ctl-syscon = <&sysconf>;
|
||||
};
|
||||
|
||||
- |
|
||||
#define KEEM_BAY_PSS_AUX_EMMC
|
||||
#define KEEM_BAY_PSS_EMMC
|
||||
mmc@33000000 {
|
||||
compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x33000000 0x300>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>,
|
||||
<&scmi_clk KEEM_BAY_PSS_EMMC>;
|
||||
phys = <&emmc_phy>;
|
||||
phy-names = "phy_arasan";
|
||||
assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
|
||||
assigned-clock-rates = <200000000>;
|
||||
clock-output-names = "emmc_cardclock";
|
||||
#clock-cells = <0>;
|
||||
arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
|
||||
};
|
||||
|
||||
- |
|
||||
#define KEEM_BAY_PSS_AUX_SD0
|
||||
#define KEEM_BAY_PSS_SD0
|
||||
mmc@31000000 {
|
||||
compatible = "intel,keembay-sdhci-5.1-sd";
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x31000000 0x300>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>,
|
||||
<&scmi_clk KEEM_BAY_PSS_SD0>;
|
||||
arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
|
||||
};
|
||||
|
||||
- |
|
||||
#define EMMC_XIN_CLK
|
||||
#define EMMC_AXI_CLK
|
||||
#define TBH_PSS_EMMC_RST_N
|
||||
mmc@80420000 {
|
||||
compatible = "intel,thunderbay-sdhci-5.1", "arasan,sdhci-5.1";
|
||||
interrupts = <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x80420000 0x400>;
|
||||
clocks = <&scmi_clk EMMC_XIN_CLK>,
|
||||
<&scmi_clk EMMC_AXI_CLK>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
phys = <&emmc_phy>;
|
||||
phy-names = "phy_arasan";
|
||||
assigned-clocks = <&scmi_clk EMMC_XIN_CLK>;
|
||||
clock-output-names = "emmc_cardclock";
|
||||
resets = <&rst_pss1 TBH_PSS_EMMC_RST_N>;
|
||||
#clock-cells = <0x0>;
|
||||
};
|
||||
244
bindings/mmc/arm,pl18x.yaml
Normal file
244
bindings/mmc/arm,pl18x.yaml
Normal file
@@ -0,0 +1,244 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/arm,pl18x.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM PrimeCell MultiMedia Card Interface (MMCI) PL180 and PL181
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
- Ulf Hansson <ulf.hansson@linaro.org>
|
||||
|
||||
description:
|
||||
The ARM PrimeCells MMCI PL180 and PL181 provides an interface for
|
||||
reading and writing to MultiMedia and SD cards alike. Over the years
|
||||
vendors have use the VHDL code from ARM to create derivative MMC/SD/SDIO
|
||||
host controllers with very similar characteristics.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/arm/primecell.yaml#
|
||||
- $ref: mmc-controller.yaml#
|
||||
|
||||
# We need a select here so we don't match all nodes with 'arm,primecell'
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- arm,pl180
|
||||
- arm,pl181
|
||||
- arm,pl18x
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: The first version of the block, simply called
|
||||
PL180 and found in the ARM Integrator IM/PD1 logic module.
|
||||
items:
|
||||
- const: arm,pl180
|
||||
- const: arm,primecell
|
||||
- description: The improved version of the block, found in the
|
||||
ARM Versatile and later reference designs. Further revisions
|
||||
exist but get detected at runtime by reading some magic numbers
|
||||
in the PrimeCell ID registers.
|
||||
items:
|
||||
- const: arm,pl181
|
||||
- const: arm,primecell
|
||||
- description: Wildcard entry that will let the operating system
|
||||
inspect the PrimeCell ID registers to determine which hardware
|
||||
variant of PL180 or PL181 this is.
|
||||
items:
|
||||
- const: arm,pl18x
|
||||
- const: arm,primecell
|
||||
- description: Entry for STMicroelectronics variant of PL18x.
|
||||
This dedicated compatible is used by bootloaders.
|
||||
items:
|
||||
- const: st,stm32-sdmmc2
|
||||
- const: arm,pl18x
|
||||
- const: arm,primecell
|
||||
|
||||
clocks:
|
||||
description: One or two clocks, the "apb_pclk" and the "MCLK"
|
||||
which is the core block clock. The names are not compulsory.
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
dmas:
|
||||
maxItems: 2
|
||||
|
||||
dma-names:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: tx
|
||||
- const: rx
|
||||
- items:
|
||||
- const: rx
|
||||
- const: tx
|
||||
|
||||
power-domains: true
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reg:
|
||||
description: the MMIO memory window must be exactly 4KB (0x1000) and the
|
||||
layout should provide the PrimeCell ID registers so that the device can
|
||||
be discovered. On ST Micro variants, a second register window may be
|
||||
defined if a delay block is present and used for tuning.
|
||||
|
||||
interrupts:
|
||||
description: The first interrupt is the command interrupt and corresponds
|
||||
to the event at the end of a command. The second interrupt is the
|
||||
PIO (polled I/O) interrupt and occurs when the FIFO needs to be
|
||||
emptied as part of a bulk read from the card. Some variants have these
|
||||
two interrupts wired into the same line (logic OR) and in that case
|
||||
only one interrupt may be provided.
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
st,sig-dir-dat0:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: ST Micro-specific property, bus signal direction pins used for
|
||||
DAT[0].
|
||||
|
||||
st,sig-dir-dat2:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: ST Micro-specific property, bus signal direction pins used for
|
||||
DAT[2].
|
||||
|
||||
st,sig-dir-dat31:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: ST Micro-specific property, bus signal direction pins used for
|
||||
DAT[3] and DAT[1].
|
||||
|
||||
st,sig-dir-dat74:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: ST Micro-specific property, bus signal direction pins used for
|
||||
DAT[7] and DAT[4].
|
||||
|
||||
st,sig-dir-cmd:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: ST Micro-specific property, CMD signal direction used for
|
||||
pin CMD.
|
||||
|
||||
st,sig-pin-fbclk:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: ST Micro-specific property, feedback clock FBCLK signal pin
|
||||
in use.
|
||||
|
||||
st,sig-dir:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: ST Micro-specific property, signal direction polarity used for
|
||||
pins CMD, DAT[0], DAT[1], DAT[2] and DAT[3].
|
||||
|
||||
st,neg-edge:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: ST Micro-specific property, data and command phase relation,
|
||||
generated on the sd clock falling edge.
|
||||
|
||||
st,use-ckin:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: ST Micro-specific property, use CKIN pin from an external
|
||||
driver to sample the receive data (for example with a voltage switch
|
||||
transceiver).
|
||||
|
||||
st,cmd-gpios:
|
||||
maxItems: 1
|
||||
description:
|
||||
The GPIO matching the CMD pin.
|
||||
|
||||
st,ck-gpios:
|
||||
maxItems: 1
|
||||
description:
|
||||
The GPIO matching the CK pin.
|
||||
|
||||
st,ckin-gpios:
|
||||
maxItems: 1
|
||||
description:
|
||||
The GPIO matching the CKIN pin.
|
||||
|
||||
dependencies:
|
||||
st,cmd-gpios: [ "st,use-ckin" ]
|
||||
st,ck-gpios: [ "st,use-ckin" ]
|
||||
st,ckin-gpios: [ "st,use-ckin" ]
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
mmc@5000 {
|
||||
compatible = "arm,pl180", "arm,primecell";
|
||||
reg = <0x5000 0x1000>;
|
||||
interrupts-extended = <&vic 22 &sic 1>;
|
||||
clocks = <&xtal24mhz>, <&pclk>;
|
||||
clock-names = "mclk", "apb_pclk";
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
mmc@80126000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
reg = <0x80126000 0x1000>;
|
||||
interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&dma 29 0 0x2>, <&dma 29 0 0x0>;
|
||||
dma-names = "rx", "tx";
|
||||
clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
|
||||
clock-names = "sdi", "apb_pclk";
|
||||
max-frequency = <100000000>;
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
cd-gpios = <&gpio2 31 0x4>;
|
||||
st,sig-dir-dat0;
|
||||
st,sig-dir-dat2;
|
||||
st,sig-dir-cmd;
|
||||
st,sig-pin-fbclk;
|
||||
vmmc-supply = <&ab8500_ldo_aux3_reg>;
|
||||
vqmmc-supply = <&vmmci>;
|
||||
};
|
||||
|
||||
- |
|
||||
mmc@101f6000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
reg = <0x101f6000 0x1000>;
|
||||
clocks = <&sdiclk>, <&pclksdi>;
|
||||
clock-names = "mclk", "apb_pclk";
|
||||
interrupts = <22>;
|
||||
max-frequency = <400000>;
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
full-pwr-cycle;
|
||||
st,sig-dir-dat0;
|
||||
st,sig-dir-dat2;
|
||||
st,sig-dir-dat31;
|
||||
st,sig-dir-cmd;
|
||||
st,sig-pin-fbclk;
|
||||
vmmc-supply = <&vmmc_regulator>;
|
||||
};
|
||||
|
||||
- |
|
||||
mmc@52007000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
arm,primecell-periphid = <0x10153180>;
|
||||
reg = <0x52007000 0x1000>;
|
||||
interrupts = <49>;
|
||||
clocks = <&rcc 0>;
|
||||
clock-names = "apb_pclk";
|
||||
resets = <&rcc 1>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
max-frequency = <120000000>;
|
||||
};
|
||||
106
bindings/mmc/aspeed,sdhci.yaml
Normal file
106
bindings/mmc/aspeed,sdhci.yaml
Normal file
@@ -0,0 +1,106 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
# Copyright 2019 IBM Corp.
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/aspeed,sdhci.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ASPEED SD/SDIO/MMC Controller
|
||||
|
||||
maintainers:
|
||||
- Andrew Jeffery <andrew@aj.id.au>
|
||||
- Ryan Chen <ryanchen.aspeed@gmail.com>
|
||||
|
||||
description: |+
|
||||
The ASPEED SD/SDIO/eMMC controller exposes two slots implementing the SDIO
|
||||
Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit data bus if
|
||||
only a single slot is enabled.
|
||||
|
||||
The two slots are supported by a common configuration area. As the SDHCIs for
|
||||
the slots are dependent on the common configuration area, they are described
|
||||
as child nodes.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- aspeed,ast2400-sd-controller
|
||||
- aspeed,ast2500-sd-controller
|
||||
- aspeed,ast2600-sd-controller
|
||||
reg:
|
||||
maxItems: 1
|
||||
description: Common configuration registers
|
||||
"#address-cells":
|
||||
const: 1
|
||||
"#size-cells":
|
||||
const: 1
|
||||
ranges: true
|
||||
clocks:
|
||||
maxItems: 1
|
||||
description: The SD/SDIO controller clock gate
|
||||
|
||||
patternProperties:
|
||||
"^sdhci@[0-9a-f]+$":
|
||||
type: object
|
||||
$ref: mmc-controller.yaml
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- aspeed,ast2400-sdhci
|
||||
- aspeed,ast2500-sdhci
|
||||
- aspeed,ast2600-sdhci
|
||||
reg:
|
||||
maxItems: 1
|
||||
description: The SDHCI registers
|
||||
clocks:
|
||||
maxItems: 1
|
||||
description: The SD bus clock
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
description: The SD interrupt shared between both slots
|
||||
sdhci,auto-cmd12:
|
||||
type: boolean
|
||||
description: Specifies that controller should use auto CMD12
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
- ranges
|
||||
- clocks
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/aspeed-clock.h>
|
||||
sdc@1e740000 {
|
||||
compatible = "aspeed,ast2500-sd-controller";
|
||||
reg = <0x1e740000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x1e740000 0x20000>;
|
||||
clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
|
||||
|
||||
sdhci0: sdhci@100 {
|
||||
compatible = "aspeed,ast2500-sdhci";
|
||||
reg = <0x100 0x100>;
|
||||
interrupts = <26>;
|
||||
sdhci,auto-cmd12;
|
||||
clocks = <&syscon ASPEED_CLK_SDIO>;
|
||||
};
|
||||
|
||||
sdhci1: sdhci@200 {
|
||||
compatible = "aspeed,ast2500-sdhci";
|
||||
reg = <0x200 0x100>;
|
||||
interrupts = <26>;
|
||||
sdhci,auto-cmd12;
|
||||
clocks = <&syscon ASPEED_CLK_SDIO>;
|
||||
};
|
||||
};
|
||||
73
bindings/mmc/atmel-hsmci.txt
Normal file
73
bindings/mmc/atmel-hsmci.txt
Normal file
@@ -0,0 +1,73 @@
|
||||
* Atmel High Speed MultiMedia Card Interface
|
||||
|
||||
This controller on atmel products provides an interface for MMC, SD and SDIO
|
||||
types of memory cards.
|
||||
|
||||
This file documents differences between the core properties described
|
||||
by mmc.txt and the properties used by the atmel-mci driver.
|
||||
|
||||
1) MCI node
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "atmel,hsmci"
|
||||
- #address-cells: should be one. The cell is the slot id.
|
||||
- #size-cells: should be zero.
|
||||
- at least one slot node
|
||||
- clock-names: tuple listing input clock names.
|
||||
Required elements: "mci_clk"
|
||||
- clocks: phandles to input clocks.
|
||||
|
||||
The node contains child nodes for each slot that the platform uses
|
||||
|
||||
Example MCI node:
|
||||
|
||||
mmc0: mmc@f0008000 {
|
||||
compatible = "atmel,hsmci";
|
||||
reg = <0xf0008000 0x600>;
|
||||
interrupts = <12 4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "mci_clk";
|
||||
clocks = <&mci0_clk>;
|
||||
|
||||
[ child node definitions...]
|
||||
};
|
||||
|
||||
2) slot nodes
|
||||
|
||||
Required properties:
|
||||
- reg: should contain the slot id.
|
||||
- bus-width: number of data lines connected to the controller
|
||||
|
||||
Optional properties:
|
||||
- cd-gpios: specify GPIOs for card detection
|
||||
- cd-inverted: invert the value of external card detect gpio line
|
||||
- wp-gpios: specify GPIOs for write protection
|
||||
|
||||
Example slot node:
|
||||
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&pioD 15 0>
|
||||
cd-inverted;
|
||||
};
|
||||
|
||||
Example full MCI node:
|
||||
mmc0: mmc@f0008000 {
|
||||
compatible = "atmel,hsmci";
|
||||
reg = <0xf0008000 0x600>;
|
||||
interrupts = <12 4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&pioD 15 0>
|
||||
cd-inverted;
|
||||
};
|
||||
slot@1 {
|
||||
reg = <1>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
};
|
||||
29
bindings/mmc/bluefield-dw-mshc.txt
Normal file
29
bindings/mmc/bluefield-dw-mshc.txt
Normal file
@@ -0,0 +1,29 @@
|
||||
* Mellanox Bluefield SoC specific extensions to the Synopsys Designware
|
||||
Mobile Storage Host Controller
|
||||
|
||||
Read synopsys-dw-mshc.txt for more details
|
||||
|
||||
The Synopsys designware mobile storage host controller is used to interface
|
||||
a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
|
||||
differences between the core Synopsys dw mshc controller properties described
|
||||
by synopsys-dw-mshc.txt and the properties used by the Mellanox Bluefield SoC
|
||||
specific extensions to the Synopsys Designware Mobile Storage Host Controller.
|
||||
|
||||
Required Properties:
|
||||
|
||||
* compatible: should be one of the following.
|
||||
- "mellanox,bluefield-dw-mshc": for controllers with Mellanox Bluefield SoC
|
||||
specific extensions.
|
||||
|
||||
Example:
|
||||
|
||||
/* Mellanox Bluefield SoC MMC */
|
||||
mmc@6008000 {
|
||||
compatible = "mellanox,bluefield-dw-mshc";
|
||||
reg = <0x6008000 0x400>;
|
||||
interrupts = <32>;
|
||||
fifo-depth = <0x100>;
|
||||
clock-frequency = <24000000>;
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
};
|
||||
23
bindings/mmc/brcm,bcm2835-sdhost.txt
Normal file
23
bindings/mmc/brcm,bcm2835-sdhost.txt
Normal file
@@ -0,0 +1,23 @@
|
||||
Broadcom BCM2835 SDHOST controller
|
||||
|
||||
This file documents differences between the core properties described
|
||||
by mmc.txt and the properties that represent the BCM2835 controller.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "brcm,bcm2835-sdhost".
|
||||
- clocks: The clock feeding the SDHOST controller.
|
||||
|
||||
Optional properties:
|
||||
- dmas: DMA channel for read and write.
|
||||
See Documentation/devicetree/bindings/dma/dma.txt for details
|
||||
|
||||
Example:
|
||||
|
||||
sdhost: mmc@7e202000 {
|
||||
compatible = "brcm,bcm2835-sdhost";
|
||||
reg = <0x7e202000 0x100>;
|
||||
interrupts = <2 24>;
|
||||
clocks = <&clocks BCM2835_CLOCK_VPU>;
|
||||
dmas = <&dma 13>;
|
||||
dma-names = "rx-tx";
|
||||
};
|
||||
64
bindings/mmc/brcm,iproc-sdhci.yaml
Normal file
64
bindings/mmc/brcm,iproc-sdhci.yaml
Normal file
@@ -0,0 +1,64 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/brcm,iproc-sdhci.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom IPROC SDHCI controller
|
||||
|
||||
maintainers:
|
||||
- Ray Jui <ray.jui@broadcom.com>
|
||||
- Scott Branden <scott.branden@broadcom.com>
|
||||
- Nicolas Saenz Julienne <nsaenz@kernel.org>
|
||||
|
||||
allOf:
|
||||
- $ref: mmc-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- brcm,bcm2835-sdhci
|
||||
- brcm,bcm2711-emmc2
|
||||
- brcm,sdhci-iproc-cygnus
|
||||
- brcm,sdhci-iproc
|
||||
- brcm,bcm7211a0-sdhci
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
description:
|
||||
Handle to core clock for the sdhci controller.
|
||||
|
||||
sdhci,auto-cmd12:
|
||||
type: boolean
|
||||
description: Specifies that controller should use auto CMD12
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/bcm-cygnus.h>
|
||||
|
||||
mmc@18041000 {
|
||||
compatible = "brcm,sdhci-iproc-cygnus";
|
||||
reg = <0x18041000 0x100>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&lcpll0_clks BCM_CYGNUS_LCPLL0_SDIO_CLK>;
|
||||
bus-width = <4>;
|
||||
sdhci,auto-cmd12;
|
||||
no-1-8-v;
|
||||
};
|
||||
...
|
||||
21
bindings/mmc/brcm,kona-sdhci.txt
Normal file
21
bindings/mmc/brcm,kona-sdhci.txt
Normal file
@@ -0,0 +1,21 @@
|
||||
Broadcom BCM281xx SDHCI
|
||||
|
||||
This file documents differences between the core properties in mmc.txt
|
||||
and the properties present in the bcm281xx SDHCI
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "brcm,kona-sdhci"
|
||||
- DEPRECATED: compatible : Should be "bcm,kona-sdhci"
|
||||
- clocks: phandle + clock specifier pair of the external clock
|
||||
|
||||
Refer to clocks/clock-bindings.txt for generic clock consumer properties.
|
||||
|
||||
Example:
|
||||
|
||||
sdio2: sdio@3f1a0000 {
|
||||
compatible = "brcm,kona-sdhci";
|
||||
reg = <0x3f1a0000 0x10000>;
|
||||
clocks = <&sdio3_clk>;
|
||||
interrupts = <0x0 74 0x4>;
|
||||
};
|
||||
|
||||
118
bindings/mmc/brcm,sdhci-brcmstb.yaml
Normal file
118
bindings/mmc/brcm,sdhci-brcmstb.yaml
Normal file
@@ -0,0 +1,118 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/brcm,sdhci-brcmstb.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom BRCMSTB/BMIPS SDHCI Controller binding
|
||||
|
||||
maintainers:
|
||||
- Al Cooper <alcooperx@gmail.com>
|
||||
- Florian Fainelli <f.fainelli@gmail.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- brcm,bcm7216-sdhci
|
||||
- const: brcm,bcm7445-sdhci
|
||||
- const: brcm,sdhci-brcmstb
|
||||
- items:
|
||||
- enum:
|
||||
- brcm,bcm7445-sdhci
|
||||
- const: brcm,sdhci-brcmstb
|
||||
- items:
|
||||
- enum:
|
||||
- brcm,bcm7425-sdhci
|
||||
- const: brcm,sdhci-brcmstb
|
||||
|
||||
reg:
|
||||
maxItems: 2
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: host
|
||||
- const: cfg
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: handle to core clock for the sdhci controller
|
||||
- description: handle to improved 150Mhz clock for sdhci controller (Optional clock)
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: sw_sdio
|
||||
- const: sdio_freq # Optional clock
|
||||
|
||||
clock-frequency:
|
||||
description:
|
||||
Maximum operating frequency of sdio_freq sdhci controller clock
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 100000000
|
||||
maximum: 150000000
|
||||
|
||||
sdhci,auto-cmd12:
|
||||
type: boolean
|
||||
description: Specifies that controller should use auto CMD12
|
||||
|
||||
allOf:
|
||||
- $ref: mmc-controller.yaml#
|
||||
- if:
|
||||
properties:
|
||||
clock-names:
|
||||
contains:
|
||||
const: sdio_freq
|
||||
|
||||
then:
|
||||
required:
|
||||
- clock-frequency
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
mmc@84b0000 {
|
||||
compatible = "brcm,bcm7216-sdhci",
|
||||
"brcm,bcm7445-sdhci",
|
||||
"brcm,sdhci-brcmstb";
|
||||
reg = <0x84b0000 0x260>, <0x84b0300 0x200>;
|
||||
reg-names = "host", "cfg";
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-ddr50;
|
||||
sd-uhs-sdr104;
|
||||
sdhci,auto-cmd12;
|
||||
interrupts = <0x0 0x26 0x4>;
|
||||
clocks = <&scmi_clk 245>;
|
||||
clock-names = "sw_sdio";
|
||||
};
|
||||
|
||||
mmc@84b1000 {
|
||||
compatible = "brcm,bcm7216-sdhci",
|
||||
"brcm,bcm7445-sdhci",
|
||||
"brcm,sdhci-brcmstb";
|
||||
reg = <0x84b1000 0x260>, <0x84b1300 0x200>;
|
||||
reg-names = "host", "cfg";
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
mmc-hs400-enhanced-strobe;
|
||||
supports-cqe;
|
||||
non-removable;
|
||||
bus-width = <0x8>;
|
||||
interrupts = <0x0 0x27 0x4>;
|
||||
clocks = <&scmi_clk 245>;
|
||||
clock-names = "sw_sdio";
|
||||
};
|
||||
57
bindings/mmc/cavium-mmc.txt
Normal file
57
bindings/mmc/cavium-mmc.txt
Normal file
@@ -0,0 +1,57 @@
|
||||
* Cavium Octeon & ThunderX MMC controller
|
||||
|
||||
The highspeed MMC host controller on Caviums SoCs provides an interface
|
||||
for MMC and SD types of memory cards.
|
||||
|
||||
Supported maximum speeds are the ones of the eMMC standard 4.41 as well
|
||||
as the speed of SD standard 4.0. Only 3.3 Volt is supported.
|
||||
|
||||
Required properties:
|
||||
- compatible : should be one of:
|
||||
cavium,octeon-6130-mmc
|
||||
cavium,octeon-7890-mmc
|
||||
cavium,thunder-8190-mmc
|
||||
cavium,thunder-8390-mmc
|
||||
mmc-slot
|
||||
- reg : mmc controller base registers
|
||||
- clocks : phandle
|
||||
|
||||
Optional properties:
|
||||
- for cd, bus-width and additional generic mmc parameters
|
||||
please refer to mmc.txt within this directory
|
||||
- cavium,cmd-clk-skew : number of coprocessor clocks before sampling command
|
||||
- cavium,dat-clk-skew : number of coprocessor clocks before sampling data
|
||||
|
||||
Deprecated properties:
|
||||
- spi-max-frequency : use max-frequency instead
|
||||
- cavium,bus-max-width : use bus-width instead
|
||||
- power-gpios : use vmmc-supply instead
|
||||
- cavium,octeon-6130-mmc-slot : use mmc-slot instead
|
||||
|
||||
Examples:
|
||||
mmc_1_4: mmc@1,4 {
|
||||
compatible = "cavium,thunder-8390-mmc";
|
||||
reg = <0x0c00 0 0 0 0>; /* DEVFN = 0x0c (1:4) */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&sclk>;
|
||||
|
||||
mmc-slot@0 {
|
||||
compatible = "mmc-slot";
|
||||
reg = <0>;
|
||||
vmmc-supply = <&mmc_supply_3v3>;
|
||||
max-frequency = <42000000>;
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
};
|
||||
|
||||
mmc-slot@1 {
|
||||
compatible = "mmc-slot";
|
||||
reg = <1>;
|
||||
vmmc-supply = <&mmc_supply_3v3>;
|
||||
max-frequency = <42000000>;
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
non-removable;
|
||||
};
|
||||
};
|
||||
134
bindings/mmc/cdns,sdhci.yaml
Normal file
134
bindings/mmc/cdns,sdhci.yaml
Normal file
@@ -0,0 +1,134 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/cdns,sdhci.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
|
||||
|
||||
maintainers:
|
||||
- Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
|
||||
allOf:
|
||||
- $ref: mmc-controller.yaml
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- microchip,mpfs-sd4hc
|
||||
- socionext,uniphier-sd4hc
|
||||
- const: cdns,sd4hc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
# PHY DLL input delays:
|
||||
# They are used to delay the data valid window, and align the window to
|
||||
# sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
|
||||
# and it is increased by 2.5ns in each step.
|
||||
|
||||
cdns,phy-input-delay-sd-highspeed:
|
||||
description: Value of the delay in the input path for SD high-speed timing
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 0
|
||||
maximum: 0x1f
|
||||
|
||||
cdns,phy-input-delay-legacy:
|
||||
description: Value of the delay in the input path for legacy timing
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 0
|
||||
maximum: 0x1f
|
||||
|
||||
cdns,phy-input-delay-sd-uhs-sdr12:
|
||||
description: Value of the delay in the input path for SD UHS SDR12 timing
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 0
|
||||
maximum: 0x1f
|
||||
|
||||
cdns,phy-input-delay-sd-uhs-sdr25:
|
||||
description: Value of the delay in the input path for SD UHS SDR25 timing
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 0
|
||||
maximum: 0x1f
|
||||
|
||||
cdns,phy-input-delay-sd-uhs-sdr50:
|
||||
description: Value of the delay in the input path for SD UHS SDR50 timing
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 0
|
||||
maximum: 0x1f
|
||||
|
||||
cdns,phy-input-delay-sd-uhs-ddr50:
|
||||
description: Value of the delay in the input path for SD UHS DDR50 timing
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 0
|
||||
maximum: 0x1f
|
||||
|
||||
cdns,phy-input-delay-mmc-highspeed:
|
||||
description: Value of the delay in the input path for MMC high-speed timing
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 0
|
||||
maximum: 0x1f
|
||||
|
||||
cdns,phy-input-delay-mmc-ddr:
|
||||
description: Value of the delay in the input path for eMMC high-speed DDR timing
|
||||
|
||||
# PHY DLL clock delays:
|
||||
# Each delay property represents the fraction of the clock period.
|
||||
# The approximate delay value will be
|
||||
# (<delay property value>/128)*sdmclk_clock_period.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 0
|
||||
maximum: 0x1f
|
||||
|
||||
cdns,phy-dll-delay-sdclk:
|
||||
description: |
|
||||
Value of the delay introduced on the sdclk output for all modes except
|
||||
HS200, HS400 and HS400_ES.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 0
|
||||
maximum: 0x7f
|
||||
|
||||
cdns,phy-dll-delay-sdclk-hsmmc:
|
||||
description: |
|
||||
Value of the delay introduced on the sdclk output for HS200, HS400 and
|
||||
HS400_ES speed modes.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 0
|
||||
maximum: 0x7f
|
||||
|
||||
cdns,phy-dll-delay-strobe:
|
||||
description: |
|
||||
Value of the delay introduced on the dat_strobe input used in
|
||||
HS400 / HS400_ES speed modes.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 0
|
||||
maximum: 0x7f
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
emmc: mmc@5a000000 {
|
||||
compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
|
||||
reg = <0x5a000000 0x400>;
|
||||
interrupts = <0 78 4>;
|
||||
clocks = <&clk 4>;
|
||||
bus-width = <8>;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
cdns,phy-dll-delay-sdclk = <0>;
|
||||
};
|
||||
32
bindings/mmc/davinci_mmc.txt
Normal file
32
bindings/mmc/davinci_mmc.txt
Normal file
@@ -0,0 +1,32 @@
|
||||
* TI Highspeed MMC host controller for DaVinci
|
||||
|
||||
The Highspeed MMC Host Controller on TI DaVinci family
|
||||
provides an interface for MMC, SD and SDIO types of memory cards.
|
||||
|
||||
This file documents the properties used by the davinci_mmc driver.
|
||||
|
||||
Required properties:
|
||||
- compatible:
|
||||
Should be "ti,da830-mmc": for da830, da850, dm365
|
||||
Should be "ti,dm355-mmc": for dm355, dm644x
|
||||
|
||||
Optional properties:
|
||||
- bus-width: Number of data lines, can be <1>, <4>, or <8>, default <1>
|
||||
- max-frequency: Maximum operating clock frequency, default 25MHz.
|
||||
- dmas: List of DMA specifiers with the controller specific format
|
||||
as described in the generic DMA client binding. A tx and rx
|
||||
specifier is required.
|
||||
- dma-names: RX and TX DMA request names. These strings correspond
|
||||
1:1 with the DMA specifiers listed in dmas.
|
||||
|
||||
Example:
|
||||
mmc0: mmc@1c40000 {
|
||||
compatible = "ti,da830-mmc",
|
||||
reg = <0x40000 0x1000>;
|
||||
interrupts = <16>;
|
||||
bus-width = <4>;
|
||||
max-frequency = <50000000>;
|
||||
dmas = <&edma 16
|
||||
&edma 17>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
52
bindings/mmc/fsl-esdhc.txt
Normal file
52
bindings/mmc/fsl-esdhc.txt
Normal file
@@ -0,0 +1,52 @@
|
||||
* Freescale Enhanced Secure Digital Host Controller (eSDHC)
|
||||
|
||||
The Enhanced Secure Digital Host Controller provides an interface
|
||||
for MMC, SD, and SDIO types of memory cards.
|
||||
|
||||
This file documents differences between the core properties described
|
||||
by mmc.txt and the properties used by the sdhci-esdhc driver.
|
||||
|
||||
Required properties:
|
||||
- compatible : should be "fsl,esdhc", or "fsl,<chip>-esdhc".
|
||||
Possible compatibles for PowerPC:
|
||||
"fsl,mpc8536-esdhc"
|
||||
"fsl,mpc8378-esdhc"
|
||||
"fsl,p2020-esdhc"
|
||||
"fsl,p4080-esdhc"
|
||||
"fsl,t1040-esdhc"
|
||||
"fsl,t4240-esdhc"
|
||||
Possible compatibles for ARM:
|
||||
"fsl,ls1012a-esdhc"
|
||||
"fsl,ls1028a-esdhc"
|
||||
"fsl,ls1088a-esdhc"
|
||||
"fsl,ls1043a-esdhc"
|
||||
"fsl,ls1046a-esdhc"
|
||||
"fsl,ls2080a-esdhc"
|
||||
- clock-frequency : specifies eSDHC base clock frequency.
|
||||
|
||||
Optional properties:
|
||||
- sdhci,wp-inverted : specifies that eSDHC controller reports
|
||||
inverted write-protect state; New devices should use the generic
|
||||
"wp-inverted" property.
|
||||
- sdhci,1-bit-only : specifies that a controller can only handle
|
||||
1-bit data transfers. New devices should use the generic
|
||||
"bus-width = <1>" property.
|
||||
- sdhci,auto-cmd12: specifies that a controller can only handle auto
|
||||
CMD12.
|
||||
- voltage-ranges : two cells are required, first cell specifies minimum
|
||||
slot voltage (mV), second cell specifies maximum slot voltage (mV).
|
||||
Several ranges could be specified.
|
||||
- little-endian : If the host controller is little-endian mode, specify
|
||||
this property. The default endian mode is big-endian.
|
||||
|
||||
Example:
|
||||
|
||||
sdhci@2e000 {
|
||||
compatible = "fsl,mpc8378-esdhc", "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <42 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
/* Filled in by U-Boot */
|
||||
clock-frequency = <0>;
|
||||
voltage-ranges = <3300 3300>;
|
||||
};
|
||||
188
bindings/mmc/fsl-imx-esdhc.yaml
Normal file
188
bindings/mmc/fsl-imx-esdhc.yaml
Normal file
@@ -0,0 +1,188 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
|
||||
|
||||
maintainers:
|
||||
- Shawn Guo <shawnguo@kernel.org>
|
||||
|
||||
allOf:
|
||||
- $ref: "mmc-controller.yaml"
|
||||
|
||||
description: |
|
||||
The Enhanced Secure Digital Host Controller on Freescale i.MX family
|
||||
provides an interface for MMC, SD, and SDIO types of memory cards.
|
||||
|
||||
This file documents differences between the core properties described
|
||||
by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- fsl,imx25-esdhc
|
||||
- fsl,imx35-esdhc
|
||||
- fsl,imx51-esdhc
|
||||
- fsl,imx53-esdhc
|
||||
- fsl,imx6q-usdhc
|
||||
- fsl,imx6sl-usdhc
|
||||
- fsl,imx6sll-usdhc
|
||||
- fsl,imx6sx-usdhc
|
||||
- fsl,imx6ull-usdhc
|
||||
- fsl,imx7d-usdhc
|
||||
- fsl,imx7ulp-usdhc
|
||||
- fsl,imx8mm-usdhc
|
||||
- fsl,imxrt1050-usdhc
|
||||
- nxp,s32g2-usdhc
|
||||
- items:
|
||||
- enum:
|
||||
- fsl,imx8mq-usdhc
|
||||
- const: fsl,imx7d-usdhc
|
||||
- items:
|
||||
- enum:
|
||||
- fsl,imx8mn-usdhc
|
||||
- fsl,imx8mp-usdhc
|
||||
- fsl,imx93-usdhc
|
||||
- fsl,imx8ulp-usdhc
|
||||
- const: fsl,imx8mm-usdhc
|
||||
- items:
|
||||
- enum:
|
||||
- fsl,imx8qm-usdhc
|
||||
- const: fsl,imx8qxp-usdhc
|
||||
- items:
|
||||
- enum:
|
||||
- fsl,imx8dxl-usdhc
|
||||
- fsl,imx8mm-usdhc
|
||||
- fsl,imx8mn-usdhc
|
||||
- fsl,imx8mp-usdhc
|
||||
- fsl,imx8qm-usdhc
|
||||
- fsl,imx8qxp-usdhc
|
||||
- const: fsl,imx7d-usdhc
|
||||
deprecated: true
|
||||
- items:
|
||||
- enum:
|
||||
- fsl,imx8mn-usdhc
|
||||
- fsl,imx8mp-usdhc
|
||||
- const: fsl,imx8mm-usdhc
|
||||
- const: fsl,imx7d-usdhc
|
||||
deprecated: true
|
||||
- items:
|
||||
- enum:
|
||||
- fsl,imx8qm-usdhc
|
||||
- const: fsl,imx8qxp-usdhc
|
||||
- const: fsl,imx7d-usdhc
|
||||
deprecated: true
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
fsl,wp-controller:
|
||||
description: |
|
||||
boolean, if present, indicate to use controller internal write protection.
|
||||
type: boolean
|
||||
|
||||
fsl,delay-line:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Specify the number of delay cells for override mode.
|
||||
This is used to set the clock delay for DLL(Delay Line) on override mode
|
||||
to select a proper data sampling window in case the clock quality is not good
|
||||
due to signal path is too long on the board. Please refer to eSDHC/uSDHC
|
||||
chapter, DLL (Delay Line) section in RM for details.
|
||||
default: 0
|
||||
|
||||
voltage-ranges:
|
||||
$ref: '/schemas/types.yaml#/definitions/uint32-matrix'
|
||||
description: |
|
||||
Specify the voltage range in case there are software transparent level
|
||||
shifters on the outputs of the controller. Two cells are required, first
|
||||
cell specifies minimum slot voltage (mV), second cell specifies maximum
|
||||
slot voltage (mV).
|
||||
items:
|
||||
items:
|
||||
- description: value for minimum slot voltage
|
||||
- description: value for maximum slot voltage
|
||||
maxItems: 1
|
||||
|
||||
fsl,tuning-start-tap:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Specify the start delay cell point when send first CMD19 in tuning procedure.
|
||||
default: 0
|
||||
|
||||
fsl,tuning-step:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Specify the increasing delay cell steps in tuning procedure.
|
||||
The uSDHC use one delay cell as default increasing step to do tuning process.
|
||||
This property allows user to change the tuning step to more than one delay
|
||||
cells which is useful for some special boards or cards when the default
|
||||
tuning step can't find the proper delay window within limited tuning retries.
|
||||
default: 0
|
||||
|
||||
fsl,strobe-dll-delay-target:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Specify the strobe dll control slave delay target.
|
||||
This delay target programming host controller loopback read clock, and this
|
||||
property allows user to change the delay target for the strobe input read clock.
|
||||
If not use this property, driver default set the delay target to value 7.
|
||||
Only eMMC HS400 mode need to take care of this property.
|
||||
default: 0
|
||||
|
||||
clocks:
|
||||
maxItems: 3
|
||||
description:
|
||||
Handle clocks for the sdhc controller.
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ipg
|
||||
- const: ahb
|
||||
- const: per
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
pinctrl-names:
|
||||
oneOf:
|
||||
- minItems: 3
|
||||
items:
|
||||
- const: default
|
||||
- const: state_100mhz
|
||||
- const: state_200mhz
|
||||
- const: sleep
|
||||
- minItems: 1
|
||||
items:
|
||||
- const: default
|
||||
- const: sleep
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
mmc@70004000 {
|
||||
compatible = "fsl,imx51-esdhc";
|
||||
reg = <0x70004000 0x4000>;
|
||||
interrupts = <1>;
|
||||
fsl,wp-controller;
|
||||
};
|
||||
|
||||
mmc@70008000 {
|
||||
compatible = "fsl,imx51-esdhc";
|
||||
reg = <0x70008000 0x4000>;
|
||||
interrupts = <2>;
|
||||
cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */
|
||||
wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */
|
||||
};
|
||||
53
bindings/mmc/fsl-imx-mmc.yaml
Normal file
53
bindings/mmc/fsl-imx-mmc.yaml
Normal file
@@ -0,0 +1,53 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/fsl-imx-mmc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale Secure Digital Host Controller for i.MX2/3 series
|
||||
|
||||
maintainers:
|
||||
- Markus Pargmann <mpa@pengutronix.de>
|
||||
|
||||
allOf:
|
||||
- $ref: "mmc-controller.yaml"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: fsl,imx21-mmc
|
||||
- const: fsl,imx31-mmc
|
||||
- items:
|
||||
- const: fsl,imx27-mmc
|
||||
- const: fsl,imx21-mmc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
dmas:
|
||||
maxItems: 1
|
||||
|
||||
dma-names:
|
||||
const: rx-tx
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
mmc@10014000 {
|
||||
compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
|
||||
reg = <0x10014000 0x1000>;
|
||||
interrupts = <11>;
|
||||
dmas = <&dma 7>;
|
||||
dma-names = "rx-tx";
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&gpio3 29>;
|
||||
};
|
||||
40
bindings/mmc/hi3798cv200-dw-mshc.txt
Normal file
40
bindings/mmc/hi3798cv200-dw-mshc.txt
Normal file
@@ -0,0 +1,40 @@
|
||||
* Hisilicon Hi3798CV200 specific extensions to the Synopsys Designware Mobile
|
||||
Storage Host Controller
|
||||
|
||||
Read synopsys-dw-mshc.txt for more details
|
||||
|
||||
The Synopsys designware mobile storage host controller is used to interface
|
||||
a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
|
||||
differences between the core Synopsys dw mshc controller properties described
|
||||
by synopsys-dw-mshc.txt and the properties used by the Hisilicon Hi3798CV200
|
||||
specific extensions to the Synopsys Designware Mobile Storage Host Controller.
|
||||
|
||||
Required Properties:
|
||||
- compatible: Should contain "hisilicon,hi3798cv200-dw-mshc".
|
||||
- clocks: A list of phandle + clock-specifier pairs for the clocks listed
|
||||
in clock-names.
|
||||
- clock-names: Should contain the following:
|
||||
"ciu" - The ciu clock described in synopsys-dw-mshc.txt.
|
||||
"biu" - The biu clock described in synopsys-dw-mshc.txt.
|
||||
"ciu-sample" - Hi3798CV200 extended phase clock for ciu sampling.
|
||||
"ciu-drive" - Hi3798CV200 extended phase clock for ciu driving.
|
||||
|
||||
Example:
|
||||
|
||||
emmc: mmc@9830000 {
|
||||
compatible = "hisilicon,hi3798cv200-dw-mshc";
|
||||
reg = <0x9830000 0x10000>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&crg HISTB_MMC_CIU_CLK>,
|
||||
<&crg HISTB_MMC_BIU_CLK>,
|
||||
<&crg HISTB_MMC_SAMPLE_CLK>,
|
||||
<&crg HISTB_MMC_DRV_CLK>;
|
||||
clock-names = "ciu", "biu", "ciu-sample", "ciu-drive";
|
||||
fifo-depth = <256>;
|
||||
clock-frequency = <200000000>;
|
||||
cap-mmc-highspeed;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
non-removable;
|
||||
bus-width = <8>;
|
||||
};
|
||||
107
bindings/mmc/ingenic,mmc.yaml
Normal file
107
bindings/mmc/ingenic,mmc.yaml
Normal file
@@ -0,0 +1,107 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/ingenic,mmc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Ingenic SoCs MMC Controller DT bindings
|
||||
|
||||
maintainers:
|
||||
- Paul Cercueil <paul@crapouillou.net>
|
||||
|
||||
allOf:
|
||||
- $ref: mmc-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- ingenic,jz4740-mmc
|
||||
- ingenic,jz4725b-mmc
|
||||
- ingenic,jz4760-mmc
|
||||
- ingenic,jz4775-mmc
|
||||
- ingenic,jz4780-mmc
|
||||
- ingenic,x1000-mmc
|
||||
- items:
|
||||
- const: ingenic,jz4770-mmc
|
||||
- const: ingenic,jz4760-mmc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: mmc
|
||||
|
||||
dmas:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
dma-names:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: rx
|
||||
- const: tx
|
||||
- const: tx-rx
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- dmas
|
||||
- dma-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/ingenic,jz4780-cgu.h>
|
||||
#include <dt-bindings/dma/jz4780-dma.h>
|
||||
mmc0: mmc@13450000 {
|
||||
compatible = "ingenic,jz4780-mmc";
|
||||
reg = <0x13450000 0x1000>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <37>;
|
||||
|
||||
clocks = <&cgu JZ4780_CLK_MSC0>;
|
||||
clock-names = "mmc";
|
||||
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
cap-sdio-irq;
|
||||
dmas = <&dma JZ4780_DMA_MSC0_RX 0xffffffff>,
|
||||
<&dma JZ4780_DMA_MSC0_TX 0xffffffff>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
- |
|
||||
#include <dt-bindings/clock/ingenic,jz4780-cgu.h>
|
||||
#include <dt-bindings/dma/jz4780-dma.h>
|
||||
/*
|
||||
* Alternative version of the example above,
|
||||
* but using one single DMA channel for both
|
||||
* TX and RX.
|
||||
*/
|
||||
mmc1: mmc@13460000 {
|
||||
compatible = "ingenic,jz4780-mmc";
|
||||
reg = <0x13460000 0x1000>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <36>;
|
||||
|
||||
clocks = <&cgu JZ4780_CLK_MSC1>;
|
||||
clock-names = "mmc";
|
||||
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
cap-sdio-irq;
|
||||
dmas = <&dma JZ4780_DMA_MSC1_TX JZ4780_DMA_MSC1_RX 0xffffffff>;
|
||||
dma-names = "tx-rx";
|
||||
};
|
||||
73
bindings/mmc/k3-dw-mshc.txt
Normal file
73
bindings/mmc/k3-dw-mshc.txt
Normal file
@@ -0,0 +1,73 @@
|
||||
* Hisilicon specific extensions to the Synopsys Designware Mobile
|
||||
Storage Host Controller
|
||||
|
||||
Read synopsys-dw-mshc.txt for more details
|
||||
|
||||
The Synopsys designware mobile storage host controller is used to interface
|
||||
a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
|
||||
differences between the core Synopsys dw mshc controller properties described
|
||||
by synopsys-dw-mshc.txt and the properties used by the Hisilicon specific
|
||||
extensions to the Synopsys Designware Mobile Storage Host Controller.
|
||||
|
||||
Required Properties:
|
||||
|
||||
* compatible: should be one of the following.
|
||||
- "hisilicon,hi3660-dw-mshc": for controllers with hi3660 specific extensions.
|
||||
- "hisilicon,hi3670-dw-mshc", "hisilicon,hi3660-dw-mshc": for controllers
|
||||
with hi3670 specific extensions.
|
||||
- "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions.
|
||||
- "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions.
|
||||
|
||||
Optional Properties:
|
||||
- hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.
|
||||
|
||||
Example:
|
||||
|
||||
/* for Hi3620 */
|
||||
|
||||
/* SoC portion */
|
||||
dwmmc_0: dwmmc0@fcd03000 {
|
||||
compatible = "hisilicon,hi4511-dw-mshc";
|
||||
reg = <0xfcd03000 0x1000>;
|
||||
interrupts = <0 16 4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&mmc_clock HI3620_SD_CIUCLK>, <&clock HI3620_DDRC_PER_CLK>;
|
||||
clock-names = "ciu", "biu";
|
||||
};
|
||||
|
||||
/* Board portion */
|
||||
dwmmc0@fcd03000 {
|
||||
vmmc-supply = <&ldo12>;
|
||||
fifo-depth = <0x100>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd_pmx_pins &sd_cfg_func1 &sd_cfg_func2>;
|
||||
bus-width = <4>;
|
||||
disable-wp;
|
||||
cd-gpios = <&gpio10 3 0>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
};
|
||||
|
||||
/* for Hi6220 */
|
||||
|
||||
dwmmc_1: dwmmc1@f723e000 {
|
||||
compatible = "hisilicon,hi6220-dw-mshc";
|
||||
bus-width = <0x4>;
|
||||
disable-wp;
|
||||
cap-sd-highspeed;
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
card-detect-delay = <200>;
|
||||
hisilicon,peripheral-syscon = <&ao_ctrl>;
|
||||
reg = <0x0 0xf723e000 0x0 0x1000>;
|
||||
interrupts = <0x0 0x49 0x4>;
|
||||
clocks = <&clock_sys HI6220_MMC1_CIUCLK>, <&clock_sys HI6220_MMC1_CLK>;
|
||||
clock-names = "ciu", "biu";
|
||||
cd-gpios = <&gpio1 0 1>;
|
||||
pinctrl-names = "default", "idle";
|
||||
pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
|
||||
pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
|
||||
vqmmc-supply = <&ldo7>;
|
||||
vmmc-supply = <&ldo10>;
|
||||
};
|
||||
78
bindings/mmc/litex,mmc.yaml
Normal file
78
bindings/mmc/litex,mmc.yaml
Normal file
@@ -0,0 +1,78 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/litex,mmc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: LiteX LiteSDCard device
|
||||
|
||||
maintainers:
|
||||
- Gabriel Somlo <gsomlo@gmail.com>
|
||||
|
||||
description: |
|
||||
LiteSDCard is a small footprint, configurable SDCard core for FPGA based
|
||||
system on chips.
|
||||
|
||||
The hardware source is Open Source and can be found on at
|
||||
https://github.com/enjoy-digital/litesdcard/.
|
||||
|
||||
allOf:
|
||||
- $ref: mmc-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: litex,mmc
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: PHY registers
|
||||
- description: CORE registers
|
||||
- description: DMA Reader buffer
|
||||
- description: DMA Writer buffer
|
||||
- description: IRQ registers
|
||||
minItems: 4
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: phy
|
||||
- const: core
|
||||
- const: reader
|
||||
- const: writer
|
||||
- const: irq
|
||||
minItems: 4
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
description:
|
||||
Handle to reference clock.
|
||||
|
||||
vmmc-supply:
|
||||
description:
|
||||
Handle to fixed-voltage supply for the card power.
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- vmmc-supply
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
mmc: mmc@12005000 {
|
||||
compatible = "litex,mmc";
|
||||
reg = <0x12005000 0x100>,
|
||||
<0x12003800 0x100>,
|
||||
<0x12003000 0x100>,
|
||||
<0x12004800 0x100>,
|
||||
<0x12004000 0x100>;
|
||||
reg-names = "phy", "core", "reader", "writer", "irq";
|
||||
clocks = <&reference_clk>;
|
||||
vmmc-supply = <&vreg_mmc>;
|
||||
interrupts = <4>;
|
||||
};
|
||||
44
bindings/mmc/marvell,dove-sdhci.yaml
Normal file
44
bindings/mmc/marvell,dove-sdhci.yaml
Normal file
@@ -0,0 +1,44 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/marvell,dove-sdhci.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell sdhci-dove controller
|
||||
|
||||
maintainers:
|
||||
- Adrian Hunter <adrian.hunter@intel.com>
|
||||
- Ulf Hansson <ulf.hansson@linaro.org>
|
||||
|
||||
allOf:
|
||||
- $ref: mmc-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: marvell,dove-sdhci
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
sdio0: mmc@92000 {
|
||||
compatible = "marvell,dove-sdhci";
|
||||
reg = <0x92000 0x100>;
|
||||
interrupts = <35>;
|
||||
clocks = <&gate_clk 9>;
|
||||
};
|
||||
44
bindings/mmc/marvell,orion-sdio.yaml
Normal file
44
bindings/mmc/marvell,orion-sdio.yaml
Normal file
@@ -0,0 +1,44 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/marvell,orion-sdio.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell orion-sdio controller
|
||||
|
||||
maintainers:
|
||||
- Nicolas Pitre <nico@fluxnic.net>
|
||||
- Ulf Hansson <ulf.hansson@linaro.org>
|
||||
|
||||
allOf:
|
||||
- $ref: mmc-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: marvell,orion-sdio
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
mmc@d00d4000 {
|
||||
compatible = "marvell,orion-sdio";
|
||||
reg = <0xd00d4000 0x200>;
|
||||
interrupts = <54>;
|
||||
clocks = <&gateclk 17>;
|
||||
};
|
||||
277
bindings/mmc/marvell,xenon-sdhci.yaml
Normal file
277
bindings/mmc/marvell,xenon-sdhci.yaml
Normal file
@@ -0,0 +1,277 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell Xenon SDHCI Controller
|
||||
|
||||
description: |
|
||||
This file documents differences between the core MMC properties described by
|
||||
mmc-controller.yaml and the properties used by the Xenon implementation.
|
||||
|
||||
Multiple SDHCs might be put into a single Xenon IP, to save size and cost.
|
||||
Each SDHC is independent and owns independent resources, such as register
|
||||
sets, clock and PHY.
|
||||
|
||||
Each SDHC should have an independent device tree node.
|
||||
|
||||
maintainers:
|
||||
- Ulf Hansson <ulf.hansson@linaro.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- marvell,armada-cp110-sdhci
|
||||
- marvell,armada-ap806-sdhci
|
||||
|
||||
- items:
|
||||
- const: marvell,armada-ap807-sdhci
|
||||
- const: marvell,armada-ap806-sdhci
|
||||
|
||||
- items:
|
||||
- const: marvell,armada-3700-sdhci
|
||||
- const: marvell,sdhci-xenon
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
description: |
|
||||
For "marvell,armada-3700-sdhci", two register areas. The first one
|
||||
for Xenon IP register. The second one for the Armada 3700 SoC PHY PAD
|
||||
Voltage Control register. Please follow the examples with compatible
|
||||
"marvell,armada-3700-sdhci" in below.
|
||||
Please also check property marvell,pad-type in below.
|
||||
|
||||
For other compatible strings, one register area for Xenon IP.
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: core
|
||||
- const: axi
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
marvell,xenon-sdhc-id:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 7
|
||||
description: |
|
||||
Indicate the corresponding bit index of current SDHC in SDHC System
|
||||
Operation Control Register Bit[7:0]. Set/clear the corresponding bit to
|
||||
enable/disable current SDHC.
|
||||
|
||||
marvell,xenon-phy-type:
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
enum:
|
||||
- "emmc 5.1 phy"
|
||||
- "emmc 5.0 phy"
|
||||
description: |
|
||||
Xenon support multiple types of PHYs. To select eMMC 5.1 PHY, set:
|
||||
marvell,xenon-phy-type = "emmc 5.1 phy" eMMC 5.1 PHY is the default
|
||||
choice if this property is not provided. To select eMMC 5.0 PHY, set:
|
||||
marvell,xenon-phy-type = "emmc 5.0 phy"
|
||||
|
||||
All those types of PHYs can support eMMC, SD and SDIO. Please note that
|
||||
this property only presents the type of PHY. It doesn't stand for the
|
||||
entire SDHC type or property. For example, "emmc 5.1 phy" doesn't mean
|
||||
that this Xenon SDHC only supports eMMC 5.1.
|
||||
|
||||
marvell,xenon-phy-znr:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 0x1f
|
||||
default: 0xf
|
||||
description: |
|
||||
Set PHY ZNR value.
|
||||
Only available for eMMC PHY.
|
||||
|
||||
marvell,xenon-phy-zpr:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 0x1f
|
||||
default: 0xf
|
||||
description: |
|
||||
Set PHY ZPR value.
|
||||
Only available for eMMC PHY.
|
||||
|
||||
marvell,xenon-phy-nr-success-tun:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 1
|
||||
maximum: 7
|
||||
default: 0x4
|
||||
description: |
|
||||
Set the number of required consecutive successful sampling points
|
||||
used to identify a valid sampling window, in tuning process.
|
||||
|
||||
marvell,xenon-phy-tun-step-divider:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
default: 64
|
||||
description: |
|
||||
Set the divider for calculating TUN_STEP.
|
||||
|
||||
marvell,xenon-phy-slow-mode:
|
||||
type: boolean
|
||||
description: |
|
||||
If this property is selected, transfers will bypass PHY.
|
||||
Only available when bus frequency lower than 55MHz in SDR mode.
|
||||
Disabled by default. Please only try this property if timing issues
|
||||
always occur with PHY enabled in eMMC HS SDR, SD SDR12, SD SDR25,
|
||||
SD Default Speed and HS mode and eMMC legacy speed mode.
|
||||
|
||||
marvell,xenon-tun-count:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
default: 0x9
|
||||
description: |
|
||||
Xenon SDHC SoC usually doesn't provide re-tuning counter in
|
||||
Capabilities Register 3 Bit[11:8].
|
||||
This property provides the re-tuning counter.
|
||||
|
||||
allOf:
|
||||
- $ref: mmc-controller.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: marvell,armada-3700-sdhci
|
||||
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
items:
|
||||
- description: Xenon IP registers
|
||||
- description: Armada 3700 SoC PHY PAD Voltage Control register
|
||||
|
||||
marvell,pad-type:
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
enum:
|
||||
- sd
|
||||
- fixed-1-8v
|
||||
description: |
|
||||
Type of Armada 3700 SoC PHY PAD Voltage Controller register.
|
||||
If "sd" is selected, SoC PHY PAD is set as 3.3V at the beginning
|
||||
and is switched to 1.8V when later in higher speed mode.
|
||||
If "fixed-1-8v" is selected, SoC PHY PAD is fixed 1.8V, such as for
|
||||
eMMC.
|
||||
Please follow the examples with compatible
|
||||
"marvell,armada-3700-sdhci" in below.
|
||||
|
||||
required:
|
||||
- marvell,pad-type
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- marvell,armada-cp110-sdhci
|
||||
- marvell,armada-ap807-sdhci
|
||||
- marvell,armada-ap806-sdhci
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: core
|
||||
- const: axi
|
||||
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
// For eMMC
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
mmc@aa0000 {
|
||||
compatible = "marvell,armada-ap807-sdhci", "marvell,armada-ap806-sdhci";
|
||||
reg = <0xaa0000 0x1000>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&emmc_clk 0>, <&axi_clk 0>;
|
||||
clock-names = "core", "axi";
|
||||
bus-width = <4>;
|
||||
marvell,xenon-phy-slow-mode;
|
||||
marvell,xenon-tun-count = <11>;
|
||||
non-removable;
|
||||
no-sd;
|
||||
no-sdio;
|
||||
|
||||
/* Vmmc and Vqmmc are both fixed */
|
||||
};
|
||||
|
||||
- |
|
||||
// For SD/SDIO
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
mmc@ab0000 {
|
||||
compatible = "marvell,armada-cp110-sdhci";
|
||||
reg = <0xab0000 0x1000>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
vqmmc-supply = <&sd_vqmmc_regulator>;
|
||||
vmmc-supply = <&sd_vmmc_regulator>;
|
||||
clocks = <&sdclk 0>, <&axi_clk 0>;
|
||||
clock-names = "core", "axi";
|
||||
bus-width = <4>;
|
||||
marvell,xenon-tun-count = <9>;
|
||||
};
|
||||
|
||||
- |
|
||||
// For eMMC with compatible "marvell,armada-3700-sdhci":
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
mmc@aa0000 {
|
||||
compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon";
|
||||
reg = <0xaa0000 0x1000>,
|
||||
<0x17808 0x4>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&emmcclk 0>;
|
||||
clock-names = "core";
|
||||
bus-width = <8>;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
non-removable;
|
||||
no-sd;
|
||||
no-sdio;
|
||||
|
||||
/* Vmmc and Vqmmc are both fixed */
|
||||
|
||||
marvell,pad-type = "fixed-1-8v";
|
||||
};
|
||||
|
||||
- |
|
||||
// For SD/SDIO with compatible "marvell,armada-3700-sdhci":
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
mmc@ab0000 {
|
||||
compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon";
|
||||
reg = <0xab0000 0x1000>,
|
||||
<0x17808 0x4>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
vqmmc-supply = <&sd_regulator>;
|
||||
/* Vmmc is fixed */
|
||||
clocks = <&sdclk 0>;
|
||||
clock-names = "core";
|
||||
bus-width = <4>;
|
||||
|
||||
marvell,pad-type = "sd";
|
||||
};
|
||||
67
bindings/mmc/microchip,dw-sparx5-sdhci.yaml
Normal file
67
bindings/mmc/microchip,dw-sparx5-sdhci.yaml
Normal file
@@ -0,0 +1,67 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/microchip,dw-sparx5-sdhci.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Microchip Sparx5 Mobile Storage Host Controller Binding
|
||||
|
||||
allOf:
|
||||
- $ref: "mmc-controller.yaml"
|
||||
|
||||
maintainers:
|
||||
- Lars Povlsen <lars.povlsen@microchip.com>
|
||||
|
||||
# Everything else is described in the common file
|
||||
properties:
|
||||
compatible:
|
||||
const: microchip,dw-sparx5-sdhci
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
description:
|
||||
Handle to "core" clock for the sdhci controller.
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: core
|
||||
|
||||
microchip,clock-delay:
|
||||
description: Delay clock to card to meet setup time requirements.
|
||||
Each step increase by 1.25ns.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 1
|
||||
maximum: 15
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/microchip,sparx5.h>
|
||||
sdhci0: mmc@600800000 {
|
||||
compatible = "microchip,dw-sparx5-sdhci";
|
||||
reg = <0x00800000 0x1000>;
|
||||
pinctrl-0 = <&emmc_pins>;
|
||||
pinctrl-names = "default";
|
||||
clocks = <&clks CLK_ID_AUX1>;
|
||||
clock-names = "core";
|
||||
assigned-clocks = <&clks CLK_ID_AUX1>;
|
||||
assigned-clock-rates = <800000000>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
bus-width = <8>;
|
||||
microchip,clock-delay = <10>;
|
||||
};
|
||||
29
bindings/mmc/microchip,sdhci-pic32.txt
Normal file
29
bindings/mmc/microchip,sdhci-pic32.txt
Normal file
@@ -0,0 +1,29 @@
|
||||
* Microchip PIC32 SDHCI Controller
|
||||
|
||||
This file documents differences between the core properties in mmc.txt
|
||||
and the properties used by the sdhci-pic32 driver.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "microchip,pic32mzda-sdhci"
|
||||
- interrupts: Should contain interrupt
|
||||
- clock-names: Should be "base_clk", "sys_clk".
|
||||
See: Documentation/devicetree/bindings/resource-names.txt
|
||||
- clocks: Phandle to the clock.
|
||||
See: Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
- pinctrl-names: A pinctrl state names "default" must be defined.
|
||||
- pinctrl-0: Phandle referencing pin configuration of the SDHCI controller.
|
||||
See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
|
||||
|
||||
Example:
|
||||
|
||||
sdhci@1f8ec000 {
|
||||
compatible = "microchip,pic32mzda-sdhci";
|
||||
reg = <0x1f8ec000 0x100>;
|
||||
interrupts = <191 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rootclk REF4CLK>, <&rootclk PB5CLK>;
|
||||
clock-names = "base_clk", "sys_clk";
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sdhc1>;
|
||||
};
|
||||
48
bindings/mmc/mmc-card.yaml
Normal file
48
bindings/mmc/mmc-card.yaml
Normal file
@@ -0,0 +1,48 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/mmc-card.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MMC Card / eMMC Generic
|
||||
|
||||
maintainers:
|
||||
- Ulf Hansson <ulf.hansson@linaro.org>
|
||||
|
||||
description: |
|
||||
This documents describes the devicetree bindings for a mmc-host controller
|
||||
child node describing a mmc-card / an eMMC.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: mmc-card
|
||||
|
||||
reg:
|
||||
const: 0
|
||||
|
||||
broken-hpi:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
Use this to indicate that the mmc-card has a broken hpi
|
||||
implementation, and that hpi should not be used.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
mmc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
card@0 {
|
||||
compatible = "mmc-card";
|
||||
reg = <0>;
|
||||
broken-hpi;
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
388
bindings/mmc/mmc-controller.yaml
Normal file
388
bindings/mmc/mmc-controller.yaml
Normal file
@@ -0,0 +1,388 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MMC Controller Generic Binding
|
||||
|
||||
maintainers:
|
||||
- Ulf Hansson <ulf.hansson@linaro.org>
|
||||
|
||||
description: |
|
||||
These properties are common to multiple MMC host controllers. Any host
|
||||
that requires the respective functionality should implement them using
|
||||
these definitions.
|
||||
|
||||
It is possible to assign a fixed index mmcN to an MMC host controller
|
||||
(and the corresponding mmcblkN devices) by defining an alias in the
|
||||
/aliases device tree node.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^mmc(@.*)?$"
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
description: |
|
||||
The cell is the slot ID if a function subnode is used.
|
||||
|
||||
"#size-cells":
|
||||
const: 0
|
||||
|
||||
# Card Detection.
|
||||
# If none of these properties are supplied, the host native card
|
||||
# detect will be used. Only one of them should be provided.
|
||||
|
||||
broken-cd:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
There is no card detection available; polling must be used.
|
||||
|
||||
cd-gpios:
|
||||
maxItems: 1
|
||||
description:
|
||||
The card detection will be done using the GPIO provided.
|
||||
|
||||
non-removable:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
Non-removable slot (like eMMC); assume always present.
|
||||
|
||||
# *NOTE* on CD and WP polarity. To use common for all SD/MMC host
|
||||
# controllers line polarity properties, we have to fix the meaning
|
||||
# of the "normal" and "inverted" line levels. We choose to follow
|
||||
# the SDHCI standard, which specifies both those lines as "active
|
||||
# low." Therefore, using the "cd-inverted" property means, that the
|
||||
# CD line is active high, i.e. it is high, when a card is
|
||||
# inserted. Similar logic applies to the "wp-inverted" property.
|
||||
#
|
||||
# CD and WP lines can be implemented on the hardware in one of two
|
||||
# ways: as GPIOs, specified in cd-gpios and wp-gpios properties, or
|
||||
# as dedicated pins. Polarity of dedicated pins can be specified,
|
||||
# using *-inverted properties. GPIO polarity can also be specified
|
||||
# using the GPIO_ACTIVE_LOW flag. This creates an ambiguity in the
|
||||
# latter case. We choose to use the XOR logic for GPIO CD and WP
|
||||
# lines. This means, the two properties are "superimposed," for
|
||||
# example leaving the GPIO_ACTIVE_LOW flag clear and specifying the
|
||||
# respective *-inverted property property results in a
|
||||
# double-inversion and actually means the "normal" line polarity is
|
||||
# in effect.
|
||||
wp-inverted:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
The Write Protect line polarity is inverted.
|
||||
|
||||
cd-inverted:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
The CD line polarity is inverted.
|
||||
|
||||
# Other properties
|
||||
|
||||
bus-width:
|
||||
description:
|
||||
Number of data lines.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [1, 4, 8]
|
||||
default: 1
|
||||
|
||||
max-frequency:
|
||||
description: |
|
||||
Maximum operating frequency of the bus:
|
||||
- for eMMC, the maximum supported frequency is 200MHz,
|
||||
- for SD/SDIO cards the SDR104 mode has a max supported
|
||||
frequency of 208MHz,
|
||||
- some mmc host controllers do support a max frequency upto
|
||||
384MHz.
|
||||
So, lets keep the maximum supported value here.
|
||||
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 400000
|
||||
maximum: 384000000
|
||||
|
||||
disable-wp:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
When set, no physical write-protect line is present. This
|
||||
property should only be specified when the controller has a
|
||||
dedicated write-protect detection logic. If a GPIO is always used
|
||||
for the write-protect detection logic, it is sufficient to not
|
||||
specify the wp-gpios property in the absence of a write-protect
|
||||
line. Not used in combination with eMMC or SDIO.
|
||||
|
||||
wp-gpios:
|
||||
maxItems: 1
|
||||
description:
|
||||
GPIO to use for the write-protect detection.
|
||||
|
||||
cd-debounce-delay-ms:
|
||||
description:
|
||||
Set delay time before detecting card after card insert
|
||||
interrupt.
|
||||
|
||||
no-1-8-v:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
When specified, denotes that 1.8V card voltage is not supported
|
||||
on this system, even if the controller claims it.
|
||||
|
||||
cap-sd-highspeed:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
SD high-speed timing is supported.
|
||||
|
||||
cap-mmc-highspeed:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
MMC high-speed timing is supported.
|
||||
|
||||
sd-uhs-sdr12:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
SD UHS SDR12 speed is supported.
|
||||
|
||||
sd-uhs-sdr25:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
SD UHS SDR25 speed is supported.
|
||||
|
||||
sd-uhs-sdr50:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
SD UHS SDR50 speed is supported.
|
||||
|
||||
sd-uhs-sdr104:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
SD UHS SDR104 speed is supported.
|
||||
|
||||
sd-uhs-ddr50:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
SD UHS DDR50 speed is supported.
|
||||
|
||||
cap-power-off-card:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
Powering off the card is safe.
|
||||
|
||||
cap-mmc-hw-reset:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
eMMC hardware reset is supported
|
||||
|
||||
cap-sdio-irq:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
enable SDIO IRQ signalling on this interface
|
||||
|
||||
full-pwr-cycle:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
Full power cycle of the card is supported.
|
||||
|
||||
full-pwr-cycle-in-suspend:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
Full power cycle of the card in suspend is supported.
|
||||
|
||||
mmc-ddr-1_2v:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
eMMC high-speed DDR mode (1.2V I/O) is supported.
|
||||
|
||||
mmc-ddr-1_8v:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
eMMC high-speed DDR mode (1.8V I/O) is supported.
|
||||
|
||||
mmc-ddr-3_3v:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
eMMC high-speed DDR mode (3.3V I/O) is supported.
|
||||
|
||||
mmc-hs200-1_2v:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
eMMC HS200 mode (1.2V I/O) is supported.
|
||||
|
||||
mmc-hs200-1_8v:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
eMMC HS200 mode (1.8V I/O) is supported.
|
||||
|
||||
mmc-hs400-1_2v:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
eMMC HS400 mode (1.2V I/O) is supported.
|
||||
|
||||
mmc-hs400-1_8v:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
eMMC HS400 mode (1.8V I/O) is supported.
|
||||
|
||||
mmc-hs400-enhanced-strobe:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
eMMC HS400 enhanced strobe mode is supported
|
||||
|
||||
no-mmc-hs400:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
All eMMC HS400 modes are not supported.
|
||||
|
||||
dsr:
|
||||
description:
|
||||
Value the card Driver Stage Register (DSR) should be programmed
|
||||
with.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 0xffff
|
||||
|
||||
no-sdio:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
Controller is limited to send SDIO commands during
|
||||
initialization.
|
||||
|
||||
no-sd:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
Controller is limited to send SD commands during initialization.
|
||||
|
||||
no-mmc:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
Controller is limited to send MMC commands during
|
||||
initialization.
|
||||
|
||||
fixed-emmc-driver-type:
|
||||
description:
|
||||
For non-removable eMMC, enforce this driver type. The value is
|
||||
the driver type as specified in the eMMC specification (table
|
||||
206 in spec version 5.1)
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 4
|
||||
|
||||
post-power-on-delay-ms:
|
||||
description:
|
||||
It was invented for MMC pwrseq-simple which could be referred to
|
||||
mmc-pwrseq-simple.txt. But now it\'s reused as a tunable delay
|
||||
waiting for I/O signalling and card power supply to be stable,
|
||||
regardless of whether pwrseq-simple is used. Default to 10ms if
|
||||
no available.
|
||||
default: 10
|
||||
|
||||
supports-cqe:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
The presence of this property indicates that the corresponding
|
||||
MMC host controller supports HW command queue feature.
|
||||
|
||||
disable-cqe-dcmd:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
The presence of this property indicates that the MMC
|
||||
controller\'s command queue engine (CQE) does not support direct
|
||||
commands (DCMDs).
|
||||
|
||||
keep-power-in-suspend:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
SDIO only. Preserves card power during a suspend/resume cycle.
|
||||
|
||||
# Deprecated: enable-sdio-wakeup
|
||||
wakeup-source:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
SDIO only. Enables wake up of host system on SDIO IRQ assertion.
|
||||
|
||||
vmmc-supply:
|
||||
description:
|
||||
Supply for the card power
|
||||
|
||||
vqmmc-supply:
|
||||
description:
|
||||
Supply for the bus IO line power, such as a level shifter.
|
||||
If the level shifter is controlled by a GPIO line, this shall
|
||||
be modeled as a "regulator-fixed" with a GPIO line for
|
||||
switching the level shifter on/off.
|
||||
|
||||
mmc-pwrseq:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
System-on-Chip designs may specify a specific MMC power
|
||||
sequence. To successfully detect an (e)MMC/SD/SDIO card, that
|
||||
power sequence must be maintained while initializing the card.
|
||||
|
||||
patternProperties:
|
||||
"^.*@[0-9]+$":
|
||||
type: object
|
||||
description: |
|
||||
On embedded systems the cards connected to a host may need
|
||||
additional properties. These can be specified in subnodes to the
|
||||
host controller node. The subnodes are identified by the
|
||||
standard \'reg\' property. Which information exactly can be
|
||||
specified depends on the bindings for the SDIO function driver
|
||||
for the subnode, as specified by the compatible string.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
description: |
|
||||
Name of SDIO function following generic names recommended
|
||||
practice
|
||||
|
||||
reg:
|
||||
items:
|
||||
- minimum: 0
|
||||
maximum: 7
|
||||
description:
|
||||
Must contain the SDIO function number of the function this
|
||||
subnode describes. A value of 0 denotes the memory SD
|
||||
function, values from 1 to 7 denote the SDIO functions.
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
"^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 359
|
||||
description:
|
||||
Set the clock (phase) delays which are to be configured in the
|
||||
controller while switching to particular speed mode. These values
|
||||
are in pair of degrees.
|
||||
|
||||
dependencies:
|
||||
cd-debounce-delay-ms: [ cd-gpios ]
|
||||
fixed-emmc-driver-type: [ non-removable ]
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
examples:
|
||||
- |
|
||||
mmc3: mmc@1c12000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x1c12000 0x200>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc3_pins_a>;
|
||||
vmmc-supply = <®_vmmc3>;
|
||||
bus-width = <4>;
|
||||
non-removable;
|
||||
mmc-pwrseq = <&sdhci0_pwrseq>;
|
||||
|
||||
brcmf: wifi@1 {
|
||||
reg = <1>;
|
||||
compatible = "brcm,bcm4329-fmac";
|
||||
interrupt-parent = <&pio>;
|
||||
interrupts = <10 8>;
|
||||
interrupt-names = "host-wake";
|
||||
};
|
||||
};
|
||||
48
bindings/mmc/mmc-pwrseq-emmc.yaml
Normal file
48
bindings/mmc/mmc-pwrseq-emmc.yaml
Normal file
@@ -0,0 +1,48 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/mmc-pwrseq-emmc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Simple eMMC hardware reset provider binding
|
||||
|
||||
maintainers:
|
||||
- Ulf Hansson <ulf.hansson@linaro.org>
|
||||
|
||||
description:
|
||||
The purpose of this driver is to perform standard eMMC hw reset
|
||||
procedure, as described by Jedec 4.4 specification. This procedure is
|
||||
performed just after MMC core enabled power to the given mmc host (to
|
||||
fix possible issues if bootloader has left eMMC card in initialized or
|
||||
unknown state), and before performing complete system reboot (also in
|
||||
case of emergency reboot call). The latter is needed on boards, which
|
||||
doesn't have hardware reset logic connected to emmc card and (limited or
|
||||
broken) ROM bootloaders are unable to read second stage from the emmc
|
||||
card if the card is left in unknown or already initialized state.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: mmc-pwrseq-emmc
|
||||
|
||||
reset-gpios:
|
||||
minItems: 1
|
||||
description:
|
||||
contains a GPIO specifier. The reset GPIO is asserted
|
||||
and then deasserted to perform eMMC card reset. To perform
|
||||
reset procedure as described in Jedec 4.4 specification, the
|
||||
gpio line should be defined as GPIO_ACTIVE_LOW.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reset-gpios
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
sdhci0_pwrseq {
|
||||
compatible = "mmc-pwrseq-emmc";
|
||||
reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
...
|
||||
43
bindings/mmc/mmc-pwrseq-sd8787.yaml
Normal file
43
bindings/mmc/mmc-pwrseq-sd8787.yaml
Normal file
@@ -0,0 +1,43 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/mmc-pwrseq-sd8787.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell SD8787 power sequence provider binding
|
||||
|
||||
maintainers:
|
||||
- Ulf Hansson <ulf.hansson@linaro.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- mmc-pwrseq-sd8787
|
||||
- mmc-pwrseq-wilc1000
|
||||
|
||||
powerdown-gpios:
|
||||
minItems: 1
|
||||
description:
|
||||
contains a power down GPIO specifier with the default active state
|
||||
|
||||
reset-gpios:
|
||||
minItems: 1
|
||||
description:
|
||||
contains a reset GPIO specifier with the default active state
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- powerdown-gpios
|
||||
- reset-gpios
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
wifi_pwrseq: wifi_pwrseq {
|
||||
compatible = "mmc-pwrseq-sd8787";
|
||||
powerdown-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>;
|
||||
reset-gpios = <&twl_gpio 1 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
...
|
||||
64
bindings/mmc/mmc-pwrseq-simple.yaml
Normal file
64
bindings/mmc/mmc-pwrseq-simple.yaml
Normal file
@@ -0,0 +1,64 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/mmc-pwrseq-simple.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Simple MMC power sequence provider binding
|
||||
|
||||
maintainers:
|
||||
- Ulf Hansson <ulf.hansson@linaro.org>
|
||||
|
||||
description:
|
||||
The purpose of the simple MMC power sequence provider is to supports a set
|
||||
of common properties between various SOC designs. It thus enables us to use
|
||||
the same provider for several SOC designs.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: mmc-pwrseq-simple
|
||||
|
||||
reset-gpios:
|
||||
minItems: 1
|
||||
# Put some limit to avoid false warnings
|
||||
maxItems: 32
|
||||
description:
|
||||
contains a list of GPIO specifiers. The reset GPIOs are asserted
|
||||
at initialization and prior we start the power up procedure of the card.
|
||||
They will be de-asserted right after the power has been provided to the
|
||||
card.
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
description: Handle for the entry in clock-names.
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ext_clock
|
||||
description: External clock provided to the card.
|
||||
|
||||
post-power-on-delay-ms:
|
||||
description:
|
||||
Delay in ms after powering the card and de-asserting the
|
||||
reset-gpios (if any).
|
||||
|
||||
power-off-delay-us:
|
||||
description:
|
||||
Delay in us after asserting the reset-gpios (if any)
|
||||
during power off of the card.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
sdhci0_pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
|
||||
clocks = <&clk_32768_ck>;
|
||||
clock-names = "ext_clock";
|
||||
};
|
||||
...
|
||||
75
bindings/mmc/mmc-spi-slot.yaml
Normal file
75
bindings/mmc/mmc-spi-slot.yaml
Normal file
@@ -0,0 +1,75 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/mmc-spi-slot.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MMC/SD/SDIO slot directly connected to a SPI bus
|
||||
|
||||
maintainers:
|
||||
- Ulf Hansson <ulf.hansson@linaro.org>
|
||||
|
||||
allOf:
|
||||
- $ref: "mmc-controller.yaml"
|
||||
- $ref: /schemas/spi/spi-peripheral-props.yaml
|
||||
|
||||
description: |
|
||||
The extra properties used by an mmc connected via SPI.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: mmc-spi-slot
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
voltage-ranges:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
description: |
|
||||
Two cells are required, first cell specifies minimum slot voltage (mV),
|
||||
second cell specifies maximum slot voltage (mV).
|
||||
items:
|
||||
- description: |
|
||||
value for minimum slot voltage in mV
|
||||
default: 3200
|
||||
- description: |
|
||||
value for maximum slot voltage in mV
|
||||
default: 3400
|
||||
|
||||
gpios:
|
||||
description: |
|
||||
For historical reasons, this does not follow the generic mmc-controller
|
||||
binding.
|
||||
minItems: 1
|
||||
items:
|
||||
- description: Card-Detect GPIO
|
||||
- description: Write-Protect GPIO
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- spi-max-frequency
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
mmc@0 {
|
||||
compatible = "mmc-spi-slot";
|
||||
reg = <0>;
|
||||
gpios = <&gpio 14 GPIO_ACTIVE_LOW>, <&gpio 15 GPIO_ACTIVE_HIGH>;
|
||||
voltage-ranges = <3300 3300>;
|
||||
spi-max-frequency = <50000000>;
|
||||
interrupts = <42>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
1
bindings/mmc/mmc.txt
Normal file
1
bindings/mmc/mmc.txt
Normal file
@@ -0,0 +1 @@
|
||||
This file has moved to mmc-controller.yaml.
|
||||
30
bindings/mmc/moxa,moxart-mmc.txt
Normal file
30
bindings/mmc/moxa,moxart-mmc.txt
Normal file
@@ -0,0 +1,30 @@
|
||||
MOXA ART MMC Host Controller Interface
|
||||
|
||||
Inherits from mmc binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/mmc/mmc.txt
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : Must be "moxa,moxart-mmc" or "faraday,ftsdc010"
|
||||
- reg : Should contain registers location and length
|
||||
- interrupts : Should contain the interrupt number
|
||||
- clocks : Should contain phandle for the clock feeding the MMC controller
|
||||
|
||||
Optional properties:
|
||||
|
||||
- dmas : Should contain two DMA channels, line request number must be 5 for
|
||||
both channels
|
||||
- dma-names : Must be "tx", "rx"
|
||||
|
||||
Example:
|
||||
|
||||
mmc: mmc@98e00000 {
|
||||
compatible = "moxa,moxart-mmc";
|
||||
reg = <0x98e00000 0x5C>;
|
||||
interrupts = <5 0>;
|
||||
clocks = <&clk_apb>;
|
||||
dmas = <&dma 5>,
|
||||
<&dma 5>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
258
bindings/mmc/mtk-sd.yaml
Normal file
258
bindings/mmc/mtk-sd.yaml
Normal file
@@ -0,0 +1,258 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MTK MSDC Storage Host Controller Binding
|
||||
|
||||
maintainers:
|
||||
- Chaotian Jing <chaotian.jing@mediatek.com>
|
||||
- Wenbin Mei <wenbin.mei@mediatek.com>
|
||||
|
||||
allOf:
|
||||
- $ref: mmc-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- mediatek,mt2701-mmc
|
||||
- mediatek,mt2712-mmc
|
||||
- mediatek,mt6779-mmc
|
||||
- mediatek,mt6795-mmc
|
||||
- mediatek,mt7620-mmc
|
||||
- mediatek,mt7622-mmc
|
||||
- mediatek,mt8135-mmc
|
||||
- mediatek,mt8173-mmc
|
||||
- mediatek,mt8183-mmc
|
||||
- mediatek,mt8516-mmc
|
||||
- items:
|
||||
- const: mediatek,mt7623-mmc
|
||||
- const: mediatek,mt2701-mmc
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8186-mmc
|
||||
- mediatek,mt8188-mmc
|
||||
- mediatek,mt8192-mmc
|
||||
- mediatek,mt8195-mmc
|
||||
- const: mediatek,mt8183-mmc
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: base register (required).
|
||||
- description: top base register (required for MT8183).
|
||||
|
||||
clocks:
|
||||
description:
|
||||
Should contain phandle for the clock feeding the MMC controller.
|
||||
minItems: 2
|
||||
items:
|
||||
- description: source clock (required).
|
||||
- description: HCLK which used for host (required).
|
||||
- description: independent source clock gate (required for MT2712).
|
||||
- description: bus clock used for internal register access (required for MT2712 MSDC0/3).
|
||||
- description: msdc subsys clock gate (required for MT8192).
|
||||
- description: peripheral bus clock gate (required for MT8192).
|
||||
- description: AXI bus clock gate (required for MT8192).
|
||||
- description: AHB bus clock gate (required for MT8192).
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
items:
|
||||
- const: source
|
||||
- const: hclk
|
||||
- const: source_cg
|
||||
- const: bus_clk
|
||||
- const: sys_cg
|
||||
- const: pclk_cg
|
||||
- const: axi_cg
|
||||
- const: ahb_cg
|
||||
|
||||
interrupts:
|
||||
description:
|
||||
Should at least contain MSDC GIC interrupt. To support SDIO in-band wakeup, an extended
|
||||
interrupt is required and be configured as wakeup source irq.
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msdc
|
||||
- const: sdio_wakeup
|
||||
|
||||
pinctrl-names:
|
||||
description:
|
||||
Should at least contain default and state_uhs. To support SDIO in-band wakeup, dat1 pin
|
||||
will be switched between GPIO mode and SDIO DAT1 mode, state_eint is mandatory in this
|
||||
scenario.
|
||||
minItems: 2
|
||||
items:
|
||||
- const: default
|
||||
- const: state_uhs
|
||||
- const: state_eint
|
||||
|
||||
pinctrl-0:
|
||||
description:
|
||||
should contain default/high speed pin ctrl.
|
||||
maxItems: 1
|
||||
|
||||
pinctrl-1:
|
||||
description:
|
||||
should contain uhs mode pin ctrl.
|
||||
maxItems: 1
|
||||
|
||||
pinctrl-2:
|
||||
description:
|
||||
should switch dat1 pin to GPIO mode.
|
||||
maxItems: 1
|
||||
|
||||
assigned-clocks:
|
||||
description:
|
||||
PLL of the source clock.
|
||||
maxItems: 1
|
||||
|
||||
assigned-clock-parents:
|
||||
description:
|
||||
parent of source clock, used for HS400 mode to get 400Mhz source clock.
|
||||
maxItems: 1
|
||||
|
||||
hs400-ds-delay:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
HS400 DS delay setting.
|
||||
minimum: 0
|
||||
maximum: 0xffffffff
|
||||
|
||||
mediatek,hs200-cmd-int-delay:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
HS200 command internal delay setting.
|
||||
This field has total 32 stages.
|
||||
The value is an integer from 0 to 31.
|
||||
minimum: 0
|
||||
maximum: 31
|
||||
|
||||
mediatek,hs400-cmd-int-delay:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
HS400 command internal delay setting.
|
||||
This field has total 32 stages.
|
||||
The value is an integer from 0 to 31.
|
||||
minimum: 0
|
||||
maximum: 31
|
||||
|
||||
mediatek,hs400-cmd-resp-sel-rising:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
HS400 command response sample selection.
|
||||
If present, HS400 command responses are sampled on rising edges.
|
||||
If not present, HS400 command responses are sampled on falling edges.
|
||||
|
||||
mediatek,hs400-ds-dly3:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Gear of the third delay line for DS for input data latch in data
|
||||
pad macro, there are 32 stages from 0 to 31.
|
||||
For different corner IC, the time is different about one step, it is
|
||||
about 100ps.
|
||||
The value is confirmed by doing scan and calibration to find a best
|
||||
value with corner IC and it is valid only for HS400 mode.
|
||||
minimum: 0
|
||||
maximum: 31
|
||||
|
||||
mediatek,latch-ck:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Some SoCs do not support enhance_rx, need set correct latch-ck to avoid
|
||||
data crc error caused by stop clock(fifo full) Valid range = [0:0x7].
|
||||
if not present, default value is 0.
|
||||
applied to compatible "mediatek,mt2701-mmc".
|
||||
minimum: 0
|
||||
maximum: 7
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
const: hrst
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- pinctrl-names
|
||||
- pinctrl-0
|
||||
- pinctrl-1
|
||||
- vmmc-supply
|
||||
- vqmmc-supply
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: mediatek,mt8183-mmc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 2
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/mt8173-clk.h>
|
||||
mmc0: mmc@11230000 {
|
||||
compatible = "mediatek,mt8173-mmc";
|
||||
reg = <0x11230000 0x1000>;
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
|
||||
vmmc-supply = <&mt6397_vemc_3v3_reg>;
|
||||
vqmmc-supply = <&mt6397_vio18_reg>;
|
||||
clocks = <&pericfg CLK_PERI_MSDC30_0>,
|
||||
<&topckgen CLK_TOP_MSDC50_0_H_SEL>;
|
||||
clock-names = "source", "hclk";
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
pinctrl-0 = <&mmc0_pins_default>;
|
||||
pinctrl-1 = <&mmc0_pins_uhs>;
|
||||
assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
|
||||
hs400-ds-delay = <0x14015>;
|
||||
mediatek,hs200-cmd-int-delay = <26>;
|
||||
mediatek,hs400-cmd-int-delay = <14>;
|
||||
mediatek,hs400-cmd-resp-sel-rising;
|
||||
};
|
||||
|
||||
mmc3: mmc@11260000 {
|
||||
compatible = "mediatek,mt8173-mmc";
|
||||
reg = <0x11260000 0x1000>;
|
||||
clock-names = "source", "hclk";
|
||||
clocks = <&pericfg CLK_PERI_MSDC30_3>,
|
||||
<&topckgen CLK_TOP_MSDC50_2_H_SEL>;
|
||||
interrupt-names = "msdc", "sdio_wakeup";
|
||||
interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_LOW 0>,
|
||||
<&pio 23 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default", "state_uhs", "state_eint";
|
||||
pinctrl-0 = <&mmc2_pins_default>;
|
||||
pinctrl-1 = <&mmc2_pins_uhs>;
|
||||
pinctrl-2 = <&mmc2_pins_eint>;
|
||||
bus-width = <4>;
|
||||
max-frequency = <200000000>;
|
||||
cap-sd-highspeed;
|
||||
sd-uhs-sdr104;
|
||||
keep-power-in-suspend;
|
||||
wakeup-source;
|
||||
cap-sdio-irq;
|
||||
no-mmc;
|
||||
no-sd;
|
||||
non-removable;
|
||||
vmmc-supply = <&sdio_fixed_3v3>;
|
||||
vqmmc-supply = <&mt6397_vgp3_reg>;
|
||||
mmc-pwrseq = <&wifi_pwrseq>;
|
||||
};
|
||||
|
||||
...
|
||||
58
bindings/mmc/mxs-mmc.yaml
Normal file
58
bindings/mmc/mxs-mmc.yaml
Normal file
@@ -0,0 +1,58 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/mxs-mmc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale MXS MMC controller
|
||||
|
||||
maintainers:
|
||||
- Shawn Guo <shawnguo@kernel.org>
|
||||
|
||||
description: |
|
||||
The Freescale MXS Synchronous Serial Ports (SSP) can act as a MMC controller
|
||||
to support MMC, SD, and SDIO types of memory cards.
|
||||
|
||||
This file documents differences between the core properties in mmc.txt
|
||||
and the properties used by the mxsmmc driver.
|
||||
|
||||
allOf:
|
||||
- $ref: "mmc-controller.yaml"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- fsl,imx23-mmc
|
||||
- fsl,imx28-mmc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
dmas:
|
||||
maxItems: 1
|
||||
|
||||
dma-names:
|
||||
const: rx-tx
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- dmas
|
||||
- dma-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
mmc@80010000 {
|
||||
compatible = "fsl,imx28-mmc";
|
||||
reg = <0x80010000 2000>;
|
||||
interrupts = <96>;
|
||||
dmas = <&dma_apbh 0>;
|
||||
dma-names = "rx-tx";
|
||||
bus-width = <8>;
|
||||
};
|
||||
314
bindings/mmc/nvidia,tegra20-sdhci.yaml
Normal file
314
bindings/mmc/nvidia,tegra20-sdhci.yaml
Normal file
@@ -0,0 +1,314 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/nvidia,tegra20-sdhci.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra Secure Digital Host Controller
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
description: |
|
||||
This controller on Tegra family SoCs provides an interface for MMC, SD, and
|
||||
SDIO types of memory cards.
|
||||
|
||||
This file documents differences between the core properties described by
|
||||
mmc-controller.yaml and the properties for the Tegra SDHCI controller.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- nvidia,tegra20-sdhci
|
||||
- nvidia,tegra30-sdhci
|
||||
- nvidia,tegra114-sdhci
|
||||
- nvidia,tegra124-sdhci
|
||||
- nvidia,tegra210-sdhci
|
||||
- nvidia,tegra186-sdhci
|
||||
- nvidia,tegra194-sdhci
|
||||
|
||||
- items:
|
||||
- const: nvidia,tegra132-sdhci
|
||||
- const: nvidia,tegra124-sdhci
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,tegra194-sdhci
|
||||
- nvidia,tegra234-sdhci
|
||||
- const: nvidia,tegra186-sdhci
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
assigned-clocks: true
|
||||
assigned-clock-parents: true
|
||||
assigned-clock-rates: true
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: module reset
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: sdhci
|
||||
|
||||
power-gpios:
|
||||
description: specify GPIOs for power control
|
||||
maxItems: 1
|
||||
|
||||
interconnects:
|
||||
items:
|
||||
- description: memory read client
|
||||
- description: memory write client
|
||||
|
||||
interconnect-names:
|
||||
items:
|
||||
- const: dma-mem # read
|
||||
- const: write
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
operating-points-v2:
|
||||
$ref: "/schemas/types.yaml#/definitions/phandle"
|
||||
|
||||
power-domains:
|
||||
items:
|
||||
- description: phandle to the core power domain
|
||||
|
||||
nvidia,default-tap:
|
||||
description: Specify the default inbound sampling clock trimmer value for
|
||||
non-tunable modes.
|
||||
|
||||
The values are used for compensating trace length differences by
|
||||
adjusting the sampling point. The values are programmed to the Vendor
|
||||
Clock Control Register. Please refer to the reference manual of the SoC
|
||||
for correct values.
|
||||
|
||||
The DQS trim values are only used on controllers which support HS400
|
||||
timing. Only SDMMC4 on Tegra210 and Tegra186 supports HS400.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,default-trim:
|
||||
description: Specify the default outbound clock trimmer value.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,dqs-trim:
|
||||
description: Specify DQS trim value for HS400 timing.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-down-offset-1v8:
|
||||
description: Specify drive strength calibration offsets for 1.8 V
|
||||
signaling modes.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-down-offset-1v8-timeout:
|
||||
description: Specify drive strength used as a fallback in case the
|
||||
automatic calibration times out on a 1.8 V signaling mode.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-down-offset-3v3:
|
||||
description: Specify drive strength calibration offsets for 3.3 V
|
||||
signaling modes.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-down-offset-3v3-timeout:
|
||||
description: Specify drive strength used as a fallback in case the
|
||||
automatic calibration times out on a 3.3 V signaling mode.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-down-offset-sdr104:
|
||||
description: Specify drive strength calibration offsets for SDR104 mode.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-down-offset-hs400:
|
||||
description: Specify drive strength calibration offsets for HS400 mode.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-up-offset-1v8:
|
||||
description: Specify drive strength calibration offsets for 1.8 V
|
||||
signaling modes.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-up-offset-1v8-timeout:
|
||||
description: Specify drive strength used as a fallback in case the
|
||||
automatic calibration times out on a 1.8 V signaling mode.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-up-offset-3v3:
|
||||
description: Specify drive strength calibration offsets for 3.3 V
|
||||
signaling modes.
|
||||
|
||||
The property values are drive codes which are programmed into the
|
||||
PD_OFFSET and PU_OFFSET sections of the SDHCI_TEGRA_AUTO_CAL_CONFIG
|
||||
register. A higher value corresponds to higher drive strength. Please
|
||||
refer to the reference manual of the SoC for correct values. The SDR104
|
||||
and HS400 timing specific values are used in corresponding modes if
|
||||
specified.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-up-offset-3v3-timeout:
|
||||
description: Specify drive strength used as a fallback in case the
|
||||
automatic calibration times out on a 3.3 V signaling mode.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-up-offset-sdr104:
|
||||
description: Specify drive strength calibration offsets for SDR104 mode.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-up-offset-hs400:
|
||||
description: Specify drive strength calibration offsets for HS400 mode.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,only-1-8v:
|
||||
description: The presence of this property indicates that the controller
|
||||
operates at a 1.8 V fixed I/O voltage.
|
||||
$ref: "/schemas/types.yaml#/definitions/flag"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
allOf:
|
||||
- $ref: "mmc-controller.yaml"
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- nvidia,tegra20-sdhci
|
||||
- nvidia,tegra30-sdhci
|
||||
- nvidia,tegra114-sdhci
|
||||
- nvidia,tegra124-sdhci
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: module clock
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: module clock
|
||||
- description: timeout clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: sdhci
|
||||
- const: tmclk
|
||||
required:
|
||||
- clock-names
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: nvidia,tegra210-sdhci
|
||||
then:
|
||||
properties:
|
||||
pinctrl-names:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: sdmmc-3v3
|
||||
description: pad configuration for 3.3 V
|
||||
- const: sdmmc-1v8
|
||||
description: pad configuration for 1.8 V
|
||||
- const: sdmmc-3v3-drv
|
||||
description: pull-up/down configuration for 3.3 V
|
||||
- const: sdmmc-1v8-drv
|
||||
description: pull-up/down configuration for 1.8 V
|
||||
- items:
|
||||
- const: sdmmc-3v3-drv
|
||||
description: pull-up/down configuration for 3.3 V
|
||||
- const: sdmmc-1v8-drv
|
||||
description: pull-up/down configuration for 1.8 V
|
||||
- items:
|
||||
- const: sdmmc-1v8-drv
|
||||
description: pull-up/down configuration for 1.8 V
|
||||
required:
|
||||
- clock-names
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- nvidia,tegra186-sdhci
|
||||
- nvidia,tegra194-sdhci
|
||||
then:
|
||||
properties:
|
||||
pinctrl-names:
|
||||
items:
|
||||
- const: sdmmc-3v3
|
||||
description: pad configuration for 3.3 V
|
||||
- const: sdmmc-1v8
|
||||
description: pad configuration for 1.8 V
|
||||
required:
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
mmc@c8000200 {
|
||||
compatible = "nvidia,tegra20-sdhci";
|
||||
reg = <0xc8000200 0x200>;
|
||||
interrupts = <47>;
|
||||
clocks = <&tegra_car 14>;
|
||||
resets = <&tegra_car 14>;
|
||||
reset-names = "sdhci";
|
||||
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
|
||||
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
|
||||
power-gpios = <&gpio 155 0>; /* gpio PT3 */
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra210-car.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
mmc@700b0000 {
|
||||
compatible = "nvidia,tegra210-sdhci";
|
||||
reg = <0x700b0000 0x200>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
|
||||
<&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
|
||||
clock-names = "sdhci", "tmclk";
|
||||
resets = <&tegra_car 14>;
|
||||
reset-names = "sdhci";
|
||||
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
|
||||
"sdmmc-3v3-drv", "sdmmc-1v8-drv";
|
||||
pinctrl-0 = <&sdmmc1_3v3>;
|
||||
pinctrl-1 = <&sdmmc1_1v8>;
|
||||
pinctrl-2 = <&sdmmc1_3v3_drv>;
|
||||
pinctrl-3 = <&sdmmc1_1v8_drv>;
|
||||
nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
|
||||
nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
|
||||
nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
|
||||
nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
|
||||
nvidia,default-tap = <0x2>;
|
||||
nvidia,default-trim = <0x4>;
|
||||
assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
|
||||
<&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
|
||||
<&tegra_car TEGRA210_CLK_PLL_C4>;
|
||||
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
|
||||
assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
|
||||
};
|
||||
67
bindings/mmc/owl-mmc.yaml
Normal file
67
bindings/mmc/owl-mmc.yaml
Normal file
@@ -0,0 +1,67 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/owl-mmc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Actions Semi Owl SoCs SD/MMC/SDIO controller
|
||||
|
||||
allOf:
|
||||
- $ref: "mmc-controller.yaml"
|
||||
|
||||
maintainers:
|
||||
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: actions,owl-mmc
|
||||
- items:
|
||||
- enum:
|
||||
- actions,s500-mmc
|
||||
- actions,s700-mmc
|
||||
- const: actions,owl-mmc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
dmas:
|
||||
maxItems: 1
|
||||
|
||||
dma-names:
|
||||
const: mmc
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- resets
|
||||
- dmas
|
||||
- dma-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
mmc0: mmc@e0330000 {
|
||||
compatible = "actions,owl-mmc";
|
||||
reg = <0xe0330000 0x4000>;
|
||||
interrupts = <0 42 4>;
|
||||
clocks = <&cmu 56>;
|
||||
resets = <&cmu 23>;
|
||||
dmas = <&dma 2>;
|
||||
dma-names = "mmc";
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
...
|
||||
25
bindings/mmc/pxa-mmc.txt
Normal file
25
bindings/mmc/pxa-mmc.txt
Normal file
@@ -0,0 +1,25 @@
|
||||
* PXA MMC drivers
|
||||
|
||||
Driver bindings for the PXA MCI (MMC/SDIO) interfaces
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "marvell,pxa-mmc".
|
||||
- vmmc-supply: A regulator for VMMC
|
||||
|
||||
Optional properties:
|
||||
- marvell,detect-delay-ms: sets the detection delay timeout in ms.
|
||||
|
||||
In addition to the properties described in this docuent, the details
|
||||
described in mmc.txt are supported.
|
||||
|
||||
Examples:
|
||||
|
||||
mmc0: mmc@41100000 {
|
||||
compatible = "marvell,pxa-mmc";
|
||||
reg = <0x41100000 0x1000>;
|
||||
interrupts = <23>;
|
||||
vmmc-supply = <&mmc_regulator>;
|
||||
cd-gpios = <&gpio 23 0>;
|
||||
wp-gpios = <&gpio 24 0>;
|
||||
};
|
||||
|
||||
135
bindings/mmc/renesas,mmcif.yaml
Normal file
135
bindings/mmc/renesas,mmcif.yaml
Normal file
@@ -0,0 +1,135 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/renesas,mmcif.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas Multi Media Card Interface (MMCIF) Controller
|
||||
|
||||
maintainers:
|
||||
- Wolfram Sang <wsa+renesas@sang-engineering.com>
|
||||
|
||||
allOf:
|
||||
- $ref: "mmc-controller.yaml"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- renesas,mmcif-r7s72100 # RZ/A1H
|
||||
- renesas,mmcif-r8a73a4 # R-Mobile APE6
|
||||
- renesas,mmcif-r8a7740 # R-Mobile A1
|
||||
- renesas,mmcif-r8a7742 # RZ/G1H
|
||||
- renesas,mmcif-r8a7743 # RZ/G1M
|
||||
- renesas,mmcif-r8a7744 # RZ/G1N
|
||||
- renesas,mmcif-r8a7745 # RZ/G1E
|
||||
- renesas,mmcif-r8a7778 # R-Car M1A
|
||||
- renesas,mmcif-r8a7790 # R-Car H2
|
||||
- renesas,mmcif-r8a7791 # R-Car M2-W
|
||||
- renesas,mmcif-r8a7793 # R-Car M2-N
|
||||
- renesas,mmcif-r8a7794 # R-Car E2
|
||||
- renesas,mmcif-sh73a0 # SH-Mobile AG5
|
||||
- const: renesas,sh-mmcif
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
dmas:
|
||||
minItems: 2
|
||||
maxItems: 4
|
||||
description:
|
||||
Must contain a list of pairs of references to DMA specifiers, one for
|
||||
transmission, and one for reception.
|
||||
|
||||
dma-names:
|
||||
minItems: 2
|
||||
maxItems: 4
|
||||
items:
|
||||
enum:
|
||||
- tx
|
||||
- rx
|
||||
|
||||
max-frequency: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- power-domains
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: renesas,mmcif-r7s72100
|
||||
then:
|
||||
properties:
|
||||
interrupts:
|
||||
items:
|
||||
- description: Error interrupt
|
||||
- description: Normal operation interrupt
|
||||
- description: Card detection interrupt
|
||||
else:
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- renesas,mmcif-r8a7740
|
||||
- renesas,mmcif-sh73a0
|
||||
then:
|
||||
properties:
|
||||
interrupts:
|
||||
items:
|
||||
- description: Error interrupt
|
||||
- description: Normal operation interrupt
|
||||
else:
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- renesas,mmcif-r8a73a4
|
||||
- renesas,mmcif-r8a7778
|
||||
then:
|
||||
properties:
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
else:
|
||||
properties:
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
required:
|
||||
- resets
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/r8a7790-cpg-mssr.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/r8a7790-sysc.h>
|
||||
|
||||
mmcif0: mmc@ee200000 {
|
||||
compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
|
||||
reg = <0xee200000 0x80>;
|
||||
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 315>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 315>;
|
||||
dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, <&dmac1 0xd1>, <&dmac1 0xd2>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
max-frequency = <97500000>;
|
||||
};
|
||||
269
bindings/mmc/renesas,sdhi.yaml
Normal file
269
bindings/mmc/renesas,sdhi.yaml
Normal file
@@ -0,0 +1,269 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/mmc/renesas,sdhi.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Renesas SDHI SD/MMC controller
|
||||
|
||||
maintainers:
|
||||
- Wolfram Sang <wsa+renesas@sang-engineering.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: renesas,sdhi-sh73a0 # R-Mobile APE6
|
||||
- items:
|
||||
- const: renesas,sdhi-r7s72100 # RZ/A1H
|
||||
- items:
|
||||
- const: renesas,sdhi-r7s9210 # SH-Mobile AG5
|
||||
- items:
|
||||
- const: renesas,sdhi-r8a73a4 # R-Mobile APE6
|
||||
- items:
|
||||
- const: renesas,sdhi-r8a7740 # R-Mobile A1
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,sdhi-r8a7778 # R-Car M1
|
||||
- renesas,sdhi-r8a7779 # R-Car H1
|
||||
- const: renesas,rcar-gen1-sdhi # R-Car Gen1
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,sdhi-r8a7742 # RZ/G1H
|
||||
- renesas,sdhi-r8a7743 # RZ/G1M
|
||||
- renesas,sdhi-r8a7744 # RZ/G1N
|
||||
- renesas,sdhi-r8a7745 # RZ/G1E
|
||||
- renesas,sdhi-r8a77470 # RZ/G1C
|
||||
- renesas,sdhi-r8a7790 # R-Car H2
|
||||
- renesas,sdhi-r8a7791 # R-Car M2-W
|
||||
- renesas,sdhi-r8a7792 # R-Car V2H
|
||||
- renesas,sdhi-r8a7793 # R-Car M2-N
|
||||
- renesas,sdhi-r8a7794 # R-Car E2
|
||||
- const: renesas,rcar-gen2-sdhi # R-Car Gen2 and RZ/G1
|
||||
- items:
|
||||
- const: renesas,sdhi-mmc-r8a77470 # RZ/G1C (SDHI/MMC IP)
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,sdhi-r8a774a1 # RZ/G2M
|
||||
- renesas,sdhi-r8a774b1 # RZ/G2N
|
||||
- renesas,sdhi-r8a774c0 # RZ/G2E
|
||||
- renesas,sdhi-r8a774e1 # RZ/G2H
|
||||
- renesas,sdhi-r8a7795 # R-Car H3
|
||||
- renesas,sdhi-r8a7796 # R-Car M3-W
|
||||
- renesas,sdhi-r8a77961 # R-Car M3-W+
|
||||
- renesas,sdhi-r8a77965 # R-Car M3-N
|
||||
- renesas,sdhi-r8a77970 # R-Car V3M
|
||||
- renesas,sdhi-r8a77980 # R-Car V3H
|
||||
- renesas,sdhi-r8a77990 # R-Car E3
|
||||
- renesas,sdhi-r8a77995 # R-Car D3
|
||||
- renesas,sdhi-r9a07g043 # RZ/G2UL
|
||||
- renesas,sdhi-r9a07g044 # RZ/G2{L,LC}
|
||||
- renesas,sdhi-r9a07g054 # RZ/V2L
|
||||
- const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,sdhi-r8a779a0 # R-Car V3U
|
||||
- renesas,sdhi-r8a779f0 # R-Car S4-8
|
||||
- const: renesas,rcar-gen4-sdhi # R-Car Gen4
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
|
||||
clocks: true
|
||||
|
||||
clock-names: true
|
||||
|
||||
dmas:
|
||||
minItems: 4
|
||||
maxItems: 4
|
||||
|
||||
dma-names:
|
||||
minItems: 4
|
||||
maxItems: 4
|
||||
items:
|
||||
enum:
|
||||
- tx
|
||||
- rx
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
pinctrl-0:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
pinctrl-1:
|
||||
maxItems: 1
|
||||
|
||||
pinctrl-names: true
|
||||
|
||||
max-frequency: true
|
||||
|
||||
allOf:
|
||||
- $ref: "mmc-controller.yaml"
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- renesas,sdhi-r9a07g043
|
||||
- renesas,sdhi-r9a07g044
|
||||
- renesas,sdhi-r9a07g054
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: IMCLK, SDHI channel main clock1.
|
||||
- description: CLK_HS, SDHI channel High speed clock which operates
|
||||
4 times that of SDHI channel main clock1.
|
||||
- description: IMCLK2, SDHI channel main clock2. When this clock is
|
||||
turned off, external SD card detection cannot be
|
||||
detected.
|
||||
- description: ACLK, SDHI channel bus clock.
|
||||
clock-names:
|
||||
items:
|
||||
- const: core
|
||||
- const: clkh
|
||||
- const: cd
|
||||
- const: aclk
|
||||
required:
|
||||
- clock-names
|
||||
- resets
|
||||
else:
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- renesas,rcar-gen2-sdhi
|
||||
- renesas,rcar-gen3-sdhi
|
||||
- renesas,rcar-gen4-sdhi
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
clock-names:
|
||||
minItems: 1
|
||||
uniqueItems: true
|
||||
items:
|
||||
- const: core
|
||||
- enum: [ clkh, cd ]
|
||||
- const: cd
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: core
|
||||
- const: cd
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: renesas,sdhi-mmc-r8a77470
|
||||
then:
|
||||
properties:
|
||||
pinctrl-names:
|
||||
items:
|
||||
- const: state_uhs
|
||||
else:
|
||||
properties:
|
||||
pinctrl-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: default
|
||||
- const: state_uhs
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- renesas,sdhi-r7s72100
|
||||
- renesas,sdhi-r7s9210
|
||||
then:
|
||||
required:
|
||||
- clock-names
|
||||
description:
|
||||
The internal card detection logic that exists in these controllers is
|
||||
sectioned off to be run by a separate second clock source to allow
|
||||
the main core clock to be turned off to save power.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- power-domains
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/r8a7790-cpg-mssr.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/r8a7790-sysc.h>
|
||||
|
||||
sdhi0: mmc@ee100000 {
|
||||
compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
|
||||
reg = <0xee100000 0x328>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 314>;
|
||||
dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
max-frequency = <195000000>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 314>;
|
||||
};
|
||||
|
||||
sdhi1: mmc@ee120000 {
|
||||
compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
|
||||
reg = <0xee120000 0x328>;
|
||||
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 313>;
|
||||
dmas = <&dmac0 0xc9>, <&dmac0 0xca>, <&dmac1 0xc9>, <&dmac1 0xca>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
max-frequency = <195000000>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 313>;
|
||||
};
|
||||
|
||||
sdhi2: mmc@ee140000 {
|
||||
compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
|
||||
reg = <0xee140000 0x100>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 312>;
|
||||
dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
max-frequency = <97500000>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 312>;
|
||||
};
|
||||
|
||||
sdhi3: mmc@ee160000 {
|
||||
compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
|
||||
reg = <0xee160000 0x100>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 311>;
|
||||
dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
max-frequency = <97500000>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 311>;
|
||||
};
|
||||
121
bindings/mmc/rockchip-dw-mshc.yaml
Normal file
121
bindings/mmc/rockchip-dw-mshc.yaml
Normal file
@@ -0,0 +1,121 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/rockchip-dw-mshc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip designware mobile storage host controller
|
||||
|
||||
description:
|
||||
Rockchip uses the Synopsys designware mobile storage host controller
|
||||
to interface a SoC with storage medium such as eMMC or SD/MMC cards.
|
||||
This file documents the combined properties for the core Synopsys dw mshc
|
||||
controller that are not already included in the synopsys-dw-mshc-common.yaml
|
||||
file and the Rockchip specific extensions.
|
||||
|
||||
allOf:
|
||||
- $ref: "synopsys-dw-mshc-common.yaml#"
|
||||
|
||||
maintainers:
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
# Everything else is described in the common file
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
# for Rockchip RK2928 and before RK3288
|
||||
- const: rockchip,rk2928-dw-mshc
|
||||
# for Rockchip RK3288
|
||||
- const: rockchip,rk3288-dw-mshc
|
||||
- items:
|
||||
- enum:
|
||||
- rockchip,px30-dw-mshc
|
||||
- rockchip,rk1808-dw-mshc
|
||||
- rockchip,rk3036-dw-mshc
|
||||
- rockchip,rk3128-dw-mshc
|
||||
- rockchip,rk3228-dw-mshc
|
||||
- rockchip,rk3308-dw-mshc
|
||||
- rockchip,rk3328-dw-mshc
|
||||
- rockchip,rk3368-dw-mshc
|
||||
- rockchip,rk3399-dw-mshc
|
||||
- rockchip,rk3568-dw-mshc
|
||||
- rockchip,rv1108-dw-mshc
|
||||
- rockchip,rv1126-dw-mshc
|
||||
- const: rockchip,rk3288-dw-mshc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 4
|
||||
description:
|
||||
Handle to "biu" and "ciu" clocks for the bus interface unit clock and
|
||||
the card interface unit clock. If "ciu-drive" and "ciu-sample" are
|
||||
specified in clock-names, it should also contain
|
||||
handles to these clocks.
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
items:
|
||||
- const: biu
|
||||
- const: ciu
|
||||
- const: ciu-drive
|
||||
- const: ciu-sample
|
||||
description:
|
||||
Apart from the clock-names "biu" and "ciu" two more clocks
|
||||
"ciu-drive" and "ciu-sample" are supported. They are used
|
||||
to control the clock phases, "ciu-sample" is required for tuning
|
||||
high speed modes.
|
||||
|
||||
rockchip,default-sample-phase:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 360
|
||||
default: 0
|
||||
description:
|
||||
The default phase to set "ciu-sample" at probing,
|
||||
low speeds or in case where all phases work at tuning time.
|
||||
If not specified 0 deg will be used.
|
||||
|
||||
rockchip,desired-num-phases:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 360
|
||||
default: 360
|
||||
description:
|
||||
The desired number of times that the host execute tuning when needed.
|
||||
If not specified, the host will do tuning for 360 times,
|
||||
namely tuning for each degree.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/rk3288-cru.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
sdmmc: mmc@ff0c0000 {
|
||||
compatible = "rockchip,rk3288-dw-mshc";
|
||||
reg = <0xff0c0000 0x4000>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
|
||||
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
|
||||
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
||||
resets = <&cru SRST_MMC0>;
|
||||
reset-names = "reset";
|
||||
fifo-depth = <0x100>;
|
||||
max-frequency = <150000000>;
|
||||
};
|
||||
|
||||
...
|
||||
160
bindings/mmc/samsung,exynos-dw-mshc.yaml
Normal file
160
bindings/mmc/samsung,exynos-dw-mshc.yaml
Normal file
@@ -0,0 +1,160 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/samsung,exynos-dw-mshc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title:
|
||||
Samsung Exynos SoC specific extensions to the Synopsys Designware Mobile
|
||||
Storage Host Controller
|
||||
|
||||
maintainers:
|
||||
- Jaehoon Chung <jh80.chung@samsung.com>
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynos4210-dw-mshc
|
||||
- samsung,exynos4412-dw-mshc
|
||||
- samsung,exynos5250-dw-mshc
|
||||
- samsung,exynos5420-dw-mshc
|
||||
- samsung,exynos5420-dw-mshc-smu
|
||||
- samsung,exynos7-dw-mshc
|
||||
- samsung,exynos7-dw-mshc-smu
|
||||
- axis,artpec8-dw-mshc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 2
|
||||
description:
|
||||
Handle to "biu" and "ciu" clocks for the
|
||||
bus interface unit clock and the card interface unit clock.
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: biu
|
||||
- const: ciu
|
||||
|
||||
samsung,dw-mshc-ciu-div:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 7
|
||||
description:
|
||||
The divider value for the card interface unit (ciu) clock.
|
||||
|
||||
samsung,dw-mshc-ddr-timing:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
items:
|
||||
- description: CIU clock phase shift value for tx mode
|
||||
minimum: 0
|
||||
maximum: 7
|
||||
- description: CIU clock phase shift value for rx mode
|
||||
minimum: 0
|
||||
maximum: 7
|
||||
description:
|
||||
The value of CUI clock phase shift value in transmit mode and CIU clock
|
||||
phase shift value in receive mode for double data rate mode operation.
|
||||
See also samsung,dw-mshc-hs400-timing property.
|
||||
|
||||
samsung,dw-mshc-hs400-timing:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
items:
|
||||
- description: CIU clock phase shift value for tx mode
|
||||
minimum: 0
|
||||
maximum: 7
|
||||
- description: CIU clock phase shift value for rx mode
|
||||
minimum: 0
|
||||
maximum: 7
|
||||
description: |
|
||||
The value of CIU TX and RX clock phase shift value for HS400 mode
|
||||
operation.
|
||||
Valid values for SDR and DDR CIU clock timing::
|
||||
- valid value for tx phase shift and rx phase shift is 0 to 7.
|
||||
- when CIU clock divider value is set to 3, all possible 8 phase shift
|
||||
values can be used.
|
||||
- if CIU clock divider value is 0 (that is divide by 1), both tx and rx
|
||||
phase shift clocks should be 0.
|
||||
If missing, values from samsung,dw-mshc-ddr-timing property are used.
|
||||
|
||||
samsung,dw-mshc-sdr-timing:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
items:
|
||||
- description: CIU clock phase shift value for tx mode
|
||||
minimum: 0
|
||||
maximum: 7
|
||||
- description: CIU clock phase shift value for rx mode
|
||||
minimum: 0
|
||||
maximum: 7
|
||||
description:
|
||||
The value of CIU clock phase shift value in transmit mode and CIU clock
|
||||
phase shift value in receive mode for single data rate mode operation.
|
||||
See also samsung,dw-mshc-hs400-timing property.
|
||||
|
||||
samsung,read-strobe-delay:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
RCLK (Data strobe) delay to control HS400 mode (Latency value for delay
|
||||
line in Read path). If missing, default from hardware is used.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- samsung,dw-mshc-ddr-timing
|
||||
- samsung,dw-mshc-sdr-timing
|
||||
|
||||
allOf:
|
||||
- $ref: "synopsys-dw-mshc-common.yaml#"
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- samsung,exynos5250-dw-mshc
|
||||
- samsung,exynos5420-dw-mshc
|
||||
- samsung,exynos7-dw-mshc
|
||||
- samsung,exynos7-dw-mshc-smu
|
||||
- axis,artpec8-dw-mshc
|
||||
then:
|
||||
required:
|
||||
- samsung,dw-mshc-ciu-div
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/exynos5420.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
mmc@12220000 {
|
||||
compatible = "samsung,exynos5420-dw-mshc";
|
||||
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x12220000 0x1000>;
|
||||
clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
|
||||
clock-names = "biu", "ciu";
|
||||
fifo-depth = <0x40>;
|
||||
card-detect-delay = <200>;
|
||||
samsung,dw-mshc-ciu-div = <3>;
|
||||
samsung,dw-mshc-sdr-timing = <0 4>;
|
||||
samsung,dw-mshc-ddr-timing = <0 2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>;
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
max-frequency = <200000000>;
|
||||
vmmc-supply = <&ldo19_reg>;
|
||||
vqmmc-supply = <&ldo13_reg>;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
sd-uhs-ddr50;
|
||||
};
|
||||
81
bindings/mmc/samsung,s3c6410-sdhci.yaml
Normal file
81
bindings/mmc/samsung,s3c6410-sdhci.yaml
Normal file
@@ -0,0 +1,81 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/samsung,s3c6410-sdhci.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung SoC SDHCI Controller
|
||||
|
||||
maintainers:
|
||||
- Jaehoon Chung <jh80.chung@samsung.com>
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,s3c6410-sdhci
|
||||
- samsung,exynos4210-sdhci
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 5
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
items:
|
||||
- const: hsmmc
|
||||
- pattern: "^mmc_busclk.[0-3]$"
|
||||
- pattern: "^mmc_busclk.[0-3]$"
|
||||
- pattern: "^mmc_busclk.[0-3]$"
|
||||
- pattern: "^mmc_busclk.[0-3]$"
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
allOf:
|
||||
- $ref: mmc-controller.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- samsung,exynos4210-sdhci
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
items:
|
||||
- const: hsmmc
|
||||
- const: mmc_busclk.2
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/exynos4.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
mmc@12510000 {
|
||||
compatible = "samsung,exynos4210-sdhci";
|
||||
reg = <0x12510000 0x100>;
|
||||
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
|
||||
clock-names = "hsmmc", "mmc_busclk.2";
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sdhci2_cd>;
|
||||
pinctrl-names = "default";
|
||||
vmmc-supply = <&ldo21_reg>;
|
||||
};
|
||||
42
bindings/mmc/samsung,s3cmci.txt
Normal file
42
bindings/mmc/samsung,s3cmci.txt
Normal file
@@ -0,0 +1,42 @@
|
||||
* Samsung's S3C24XX MMC/SD/SDIO controller device tree bindings
|
||||
|
||||
Samsung's S3C24XX MMC/SD/SDIO controller is used as a connectivity interface
|
||||
with external MMC, SD and SDIO storage mediums.
|
||||
|
||||
This file documents differences between the core mmc properties described by
|
||||
mmc.txt and the properties used by the Samsung S3C24XX MMC/SD/SDIO controller
|
||||
implementation.
|
||||
|
||||
Required SoC Specific Properties:
|
||||
- compatible: should be one of the following
|
||||
- "samsung,s3c2410-sdi": for controllers compatible with s3c2410
|
||||
- "samsung,s3c2412-sdi": for controllers compatible with s3c2412
|
||||
- "samsung,s3c2440-sdi": for controllers compatible with s3c2440
|
||||
- reg: register location and length
|
||||
- interrupts: mmc controller interrupt
|
||||
- clocks: Should reference the controller clock
|
||||
- clock-names: Should contain "sdi"
|
||||
|
||||
Required Board Specific Properties:
|
||||
- pinctrl-0: Should specify pin control groups used for this controller.
|
||||
- pinctrl-names: Should contain only one value - "default".
|
||||
|
||||
Optional Properties:
|
||||
- bus-width: number of data lines (see mmc.txt)
|
||||
- cd-gpios: gpio for card detection (see mmc.txt)
|
||||
- wp-gpios: gpio for write protection (see mmc.txt)
|
||||
|
||||
Example:
|
||||
|
||||
mmc0: mmc@5a000000 {
|
||||
compatible = "samsung,s3c2440-sdi";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdi_pins>;
|
||||
reg = <0x5a000000 0x100000>;
|
||||
interrupts = <0 0 21 3>;
|
||||
clocks = <&clocks PCLK_SDI>;
|
||||
clock-names = "sdi";
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&gpg 8 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gph 8 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
237
bindings/mmc/sdhci-am654.yaml
Normal file
237
bindings/mmc/sdhci-am654.yaml
Normal file
@@ -0,0 +1,237 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/mmc/sdhci-am654.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: TI AM654 MMC Controller
|
||||
|
||||
maintainers:
|
||||
- Ulf Hansson <ulf.hansson@linaro.org>
|
||||
|
||||
allOf:
|
||||
- $ref: mmc-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: ti,am654-sdhci-5.1
|
||||
- const: ti,j721e-sdhci-8bit
|
||||
- const: ti,j721e-sdhci-4bit
|
||||
- const: ti,am64-sdhci-8bit
|
||||
- const: ti,am64-sdhci-4bit
|
||||
- const: ti,am62-sdhci
|
||||
- items:
|
||||
- const: ti,j7200-sdhci-8bit
|
||||
- const: ti,j721e-sdhci-8bit
|
||||
- items:
|
||||
- const: ti,j7200-sdhci-4bit
|
||||
- const: ti,j721e-sdhci-4bit
|
||||
|
||||
reg:
|
||||
maxItems: 2
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
description: Handles to input clocks
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: clk_ahb
|
||||
- const: clk_xin
|
||||
|
||||
sdhci-caps-mask: true
|
||||
|
||||
dma-coherent:
|
||||
type: boolean
|
||||
|
||||
# PHY output tap delays:
|
||||
# Used to delay the data valid window and align it to the sampling clock.
|
||||
# Binding needs to be provided for each supported speed mode otherwise the
|
||||
# corresponding mode will be disabled.
|
||||
|
||||
ti,otap-del-sel-legacy:
|
||||
description: Output tap delay for SD/MMC legacy timing
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 0
|
||||
maximum: 0xf
|
||||
|
||||
ti,otap-del-sel-mmc-hs:
|
||||
description: Output tap delay for MMC high speed timing
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 0
|
||||
maximum: 0xf
|
||||
|
||||
ti,otap-del-sel-sd-hs:
|
||||
description: Output tap delay for SD high speed timing
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 0
|
||||
maximum: 0xf
|
||||
|
||||
ti,otap-del-sel-sdr12:
|
||||
description: Output tap delay for SD UHS SDR12 timing
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 0
|
||||
maximum: 0xf
|
||||
|
||||
ti,otap-del-sel-sdr25:
|
||||
description: Output tap delay for SD UHS SDR25 timing
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 0
|
||||
maximum: 0xf
|
||||
|
||||
ti,otap-del-sel-sdr50:
|
||||
description: Output tap delay for SD UHS SDR50 timing
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 0
|
||||
maximum: 0xf
|
||||
|
||||
ti,otap-del-sel-sdr104:
|
||||
description: Output tap delay for SD UHS SDR104 timing
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 0
|
||||
maximum: 0xf
|
||||
|
||||
ti,otap-del-sel-ddr50:
|
||||
description: Output tap delay for SD UHS DDR50 timing
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 0
|
||||
maximum: 0xf
|
||||
|
||||
ti,otap-del-sel-ddr52:
|
||||
description: Output tap delay for eMMC DDR52 timing
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 0
|
||||
maximum: 0xf
|
||||
|
||||
ti,otap-del-sel-hs200:
|
||||
description: Output tap delay for eMMC HS200 timing
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 0
|
||||
maximum: 0xf
|
||||
|
||||
ti,otap-del-sel-hs400:
|
||||
description: Output tap delay for eMMC HS400 timing
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 0
|
||||
maximum: 0xf
|
||||
|
||||
# PHY input tap delays:
|
||||
# Used to delay the data valid window and align it to the sampling clock for
|
||||
# modes that don't support tuning
|
||||
|
||||
ti,itap-del-sel-legacy:
|
||||
description: Input tap delay for SD/MMC legacy timing
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 0
|
||||
maximum: 0x1f
|
||||
|
||||
ti,itap-del-sel-mmc-hs:
|
||||
description: Input tap delay for MMC high speed timing
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 0
|
||||
maximum: 0x1f
|
||||
|
||||
ti,itap-del-sel-sd-hs:
|
||||
description: Input tap delay for SD high speed timing
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 0
|
||||
maximum: 0x1f
|
||||
|
||||
ti,itap-del-sel-sdr12:
|
||||
description: Input tap delay for SD UHS SDR12 timing
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 0
|
||||
maximum: 0x1f
|
||||
|
||||
ti,itap-del-sel-sdr25:
|
||||
description: Input tap delay for SD UHS SDR25 timing
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 0
|
||||
maximum: 0x1f
|
||||
|
||||
ti,itap-del-sel-ddr52:
|
||||
description: Input tap delay for MMC DDR52 timing
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 0
|
||||
maximum: 0x1f
|
||||
|
||||
ti,trm-icp:
|
||||
description: DLL trim select
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 0
|
||||
maximum: 0xf
|
||||
|
||||
ti,driver-strength-ohm:
|
||||
description: DLL drive strength in ohms
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
enum:
|
||||
- 33
|
||||
- 40
|
||||
- 50
|
||||
- 66
|
||||
- 100
|
||||
|
||||
ti,strobe-sel:
|
||||
description: strobe select delay for HS400 speed mode.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
ti,clkbuf-sel:
|
||||
description: Clock Delay Buffer Select
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
ti,fails-without-test-cd:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
When present, indicates that the CD line is not connected
|
||||
and the controller is required to be forced into Test mode
|
||||
to set the TESTCD bit.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- ti,otap-del-sel-legacy
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
mmc0: mmc@4f80000 {
|
||||
compatible = "ti,am654-sdhci-5.1";
|
||||
reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
|
||||
power-domains = <&k3_pds 47>;
|
||||
clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
|
||||
clock-names = "clk_ahb", "clk_xin";
|
||||
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
||||
sdhci-caps-mask = <0x80000007 0x0>;
|
||||
mmc-ddr-1_8v;
|
||||
ti,otap-del-sel-legacy = <0x0>;
|
||||
ti,otap-del-sel-mmc-hs = <0x0>;
|
||||
ti,otap-del-sel-ddr52 = <0x5>;
|
||||
ti,otap-del-sel-hs200 = <0x5>;
|
||||
ti,otap-del-sel-hs400 = <0x0>;
|
||||
ti,itap-del-sel-legacy = <0x10>;
|
||||
ti,itap-del-sel-mmc-hs = <0xa>;
|
||||
ti,itap-del-sel-ddr52 = <0x3>;
|
||||
ti,trm-icp = <0x8>;
|
||||
};
|
||||
};
|
||||
33
bindings/mmc/sdhci-atmel.txt
Normal file
33
bindings/mmc/sdhci-atmel.txt
Normal file
@@ -0,0 +1,33 @@
|
||||
* Atmel SDHCI controller
|
||||
|
||||
This file documents the differences between the core properties in
|
||||
Documentation/devicetree/bindings/mmc/mmc.txt and the properties used by the
|
||||
sdhci-of-at91 driver.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "atmel,sama5d2-sdhci" or "microchip,sam9x60-sdhci".
|
||||
- clocks: Phandlers to the clocks.
|
||||
- clock-names: Must be "hclock", "multclk", "baseclk" for
|
||||
"atmel,sama5d2-sdhci".
|
||||
Must be "hclock", "multclk" for "microchip,sam9x60-sdhci".
|
||||
|
||||
Optional properties:
|
||||
- assigned-clocks: The same with "multclk".
|
||||
- assigned-clock-rates The rate of "multclk" in order to not rely on the
|
||||
gck configuration set by previous components.
|
||||
- microchip,sdcal-inverted: when present, polarity on the SDCAL SoC pin is
|
||||
inverted. The default polarity for this signal is described in the datasheet.
|
||||
For instance on SAMA5D2, the pin is usually tied to the GND with a resistor
|
||||
and a capacitor (see "SDMMC I/O Calibration" chapter).
|
||||
|
||||
Example:
|
||||
|
||||
mmc0: sdio-host@a0000000 {
|
||||
compatible = "atmel,sama5d2-sdhci";
|
||||
reg = <0xa0000000 0x300>;
|
||||
interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
|
||||
clock-names = "hclock", "multclk", "baseclk";
|
||||
assigned-clocks = <&sdmmc0_gclk>;
|
||||
assigned-clock-rates = <480000000>;
|
||||
};
|
||||
32
bindings/mmc/sdhci-fujitsu.txt
Normal file
32
bindings/mmc/sdhci-fujitsu.txt
Normal file
@@ -0,0 +1,32 @@
|
||||
* Fujitsu SDHCI controller
|
||||
|
||||
This file documents differences between the core properties in mmc.txt
|
||||
and the properties used by the sdhci_f_sdh30 driver.
|
||||
|
||||
Required properties:
|
||||
- compatible: "fujitsu,mb86s70-sdhci-3.0"
|
||||
- clocks: Must contain an entry for each entry in clock-names. It is a
|
||||
list of phandles and clock-specifier pairs.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: Should contain the following two entries:
|
||||
"iface" - clock used for sdhci interface
|
||||
"core" - core clock for sdhci controller
|
||||
|
||||
Optional properties:
|
||||
- vqmmc-supply: phandle to the regulator device tree node, mentioned
|
||||
as the VCCQ/VDD_IO supply in the eMMC/SD specs.
|
||||
- fujitsu,cmd-dat-delay-select: boolean property indicating that this host
|
||||
requires the CMD_DAT_DELAY control to be enabled.
|
||||
|
||||
Example:
|
||||
|
||||
sdhci1: mmc@36600000 {
|
||||
compatible = "fujitsu,mb86s70-sdhci-3.0";
|
||||
reg = <0 0x36600000 0x1000>;
|
||||
interrupts = <0 172 0x4>,
|
||||
<0 173 0x4>;
|
||||
bus-width = <4>;
|
||||
vqmmc-supply = <&vccq_sdhci1>;
|
||||
clocks = <&clock 2 2 0>, <&clock 2 3 0>;
|
||||
clock-names = "iface", "core";
|
||||
};
|
||||
30
bindings/mmc/sdhci-milbeaut.txt
Normal file
30
bindings/mmc/sdhci-milbeaut.txt
Normal file
@@ -0,0 +1,30 @@
|
||||
* SOCIONEXT Milbeaut SDHCI controller
|
||||
|
||||
This file documents differences between the core properties in mmc.txt
|
||||
and the properties used by the sdhci_milbeaut driver.
|
||||
|
||||
Required properties:
|
||||
- compatible: "socionext,milbeaut-m10v-sdhci-3.0"
|
||||
- clocks: Must contain an entry for each entry in clock-names. It is a
|
||||
list of phandles and clock-specifier pairs.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: Should contain the following two entries:
|
||||
"iface" - clock used for sdhci interface
|
||||
"core" - core clock for sdhci controller
|
||||
|
||||
Optional properties:
|
||||
- fujitsu,cmd-dat-delay-select: boolean property indicating that this host
|
||||
requires the CMD_DAT_DELAY control to be enabled.
|
||||
|
||||
Example:
|
||||
sdhci3: mmc@1b010000 {
|
||||
compatible = "socionext,milbeaut-m10v-sdhci-3.0";
|
||||
reg = <0x1b010000 0x10000>;
|
||||
interrupts = <0 265 0x4>;
|
||||
voltage-ranges = <3300 3300>;
|
||||
bus-width = <4>;
|
||||
clocks = <&clk 7>, <&ahb_clk>;
|
||||
clock-names = "core", "iface";
|
||||
cap-sdio-irq;
|
||||
fujitsu,cmd-dat-delay-select;
|
||||
};
|
||||
258
bindings/mmc/sdhci-msm.yaml
Normal file
258
bindings/mmc/sdhci-msm.yaml
Normal file
@@ -0,0 +1,258 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/mmc/sdhci-msm.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Qualcomm SDHCI controller (sdhci-msm)
|
||||
|
||||
maintainers:
|
||||
- Bhupesh Sharma <bhupesh.sharma@linaro.org>
|
||||
|
||||
description:
|
||||
Secure Digital Host Controller Interface (SDHCI) present on
|
||||
Qualcomm SOCs supports SD/MMC/SDIO devices.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- qcom,sdhci-msm-v4
|
||||
deprecated: true
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,apq8084-sdhci
|
||||
- qcom,msm8226-sdhci
|
||||
- qcom,msm8953-sdhci
|
||||
- qcom,msm8974-sdhci
|
||||
- qcom,msm8916-sdhci
|
||||
- qcom,msm8992-sdhci
|
||||
- qcom,msm8994-sdhci
|
||||
- qcom,msm8996-sdhci
|
||||
- qcom,msm8998-sdhci
|
||||
- const: qcom,sdhci-msm-v4 # for sdcc versions less than 5.0
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,qcs404-sdhci
|
||||
- qcom,sc7180-sdhci
|
||||
- qcom,sc7280-sdhci
|
||||
- qcom,sdm630-sdhci
|
||||
- qcom,sdm670-sdhci
|
||||
- qcom,sdm845-sdhci
|
||||
- qcom,sdx55-sdhci
|
||||
- qcom,sdx65-sdhci
|
||||
- qcom,sm6115-sdhci
|
||||
- qcom,sm6125-sdhci
|
||||
- qcom,sm6350-sdhci
|
||||
- qcom,sm8150-sdhci
|
||||
- qcom,sm8250-sdhci
|
||||
- qcom,sm8450-sdhci
|
||||
- const: qcom,sdhci-msm-v5 # for sdcc version 5.0
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
reg-names:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
clocks:
|
||||
minItems: 3
|
||||
items:
|
||||
- description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock
|
||||
- description: SDC MMC clock, MCLK
|
||||
- description: TCXO clock
|
||||
- description: clock for Inline Crypto Engine
|
||||
- description: SDCC bus voter clock
|
||||
- description: reference clock for RCLK delay calibration
|
||||
- description: sleep clock for RCLK delay calibration
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
items:
|
||||
- const: iface
|
||||
- const: core
|
||||
- const: xo
|
||||
- const: ice
|
||||
- const: bus
|
||||
- const: cal
|
||||
- const: sleep
|
||||
|
||||
interrupts:
|
||||
maxItems: 2
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: hc_irq
|
||||
- const: pwr_irq
|
||||
|
||||
pinctrl-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: default
|
||||
- const: sleep
|
||||
|
||||
pinctrl-0:
|
||||
description:
|
||||
Should specify pin control groups used for this controller.
|
||||
|
||||
pinctrl-1:
|
||||
description:
|
||||
Should specify sleep pin control groups used for this controller.
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
qcom,ddr-config:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: platform specific settings for DDR_CONFIG reg.
|
||||
|
||||
qcom,dll-config:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: platform specific settings for DLL_CONFIG reg.
|
||||
|
||||
iommus:
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
description: |
|
||||
phandle to apps_smmu node with sid mask.
|
||||
|
||||
interconnects:
|
||||
items:
|
||||
- description: data path, sdhc to ddr
|
||||
- description: config path, cpu to sdhc
|
||||
|
||||
interconnect-names:
|
||||
items:
|
||||
- const: sdhc-ddr
|
||||
- const: cpu-sdhc
|
||||
|
||||
power-domains:
|
||||
description: A phandle to sdhci power domain node
|
||||
maxItems: 1
|
||||
|
||||
mmc-ddr-1_8v: true
|
||||
|
||||
mmc-hs200-1_8v: true
|
||||
|
||||
mmc-hs400-1_8v: true
|
||||
|
||||
bus-width: true
|
||||
|
||||
max-frequency: true
|
||||
|
||||
operating-points-v2: true
|
||||
|
||||
patternProperties:
|
||||
'^opp-table(-[a-z0-9]+)?$':
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
const: operating-points-v2
|
||||
then:
|
||||
patternProperties:
|
||||
'^opp-?[0-9]+$':
|
||||
required:
|
||||
- required-opps
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- interrupts
|
||||
|
||||
allOf:
|
||||
- $ref: mmc-controller.yaml#
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sdhci-msm-v4
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 2
|
||||
items:
|
||||
- description: Host controller register map
|
||||
- description: SD Core register map
|
||||
- description: CQE register map
|
||||
- description: Inline Crypto Engine register map
|
||||
reg-names:
|
||||
minItems: 2
|
||||
items:
|
||||
- const: hc
|
||||
- const: core
|
||||
- const: cqhci
|
||||
- const: ice
|
||||
else:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: Host controller register map
|
||||
- description: CQE register map
|
||||
- description: Inline Crypto Engine register map
|
||||
reg-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: hc
|
||||
- const: cqhci
|
||||
- const: ice
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
sdhc_2: mmc@8804000 {
|
||||
compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
|
||||
reg = <0 0x08804000 0 0x1000>;
|
||||
|
||||
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hc_irq", "pwr_irq";
|
||||
|
||||
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
|
||||
<&gcc GCC_SDCC2_APPS_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "core", "xo";
|
||||
iommus = <&apps_smmu 0x4a0 0x0>;
|
||||
qcom,dll-config = <0x0007642c>;
|
||||
qcom,ddr-config = <0x80040868>;
|
||||
power-domains = <&rpmhpd SM8250_CX>;
|
||||
|
||||
operating-points-v2 = <&sdhc2_opp_table>;
|
||||
|
||||
sdhc2_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-19200000 {
|
||||
opp-hz = /bits/ 64 <19200000>;
|
||||
required-opps = <&rpmhpd_opp_min_svs>;
|
||||
};
|
||||
|
||||
opp-50000000 {
|
||||
opp-hz = /bits/ 64 <50000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-202000000 {
|
||||
opp-hz = /bits/ 64 <202000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
43
bindings/mmc/sdhci-omap.txt
Normal file
43
bindings/mmc/sdhci-omap.txt
Normal file
@@ -0,0 +1,43 @@
|
||||
* TI OMAP SDHCI Controller
|
||||
|
||||
Refer to mmc.txt for standard MMC bindings.
|
||||
|
||||
For UHS devices which require tuning, the device tree should have a "cpu_thermal" node which maps to the appropriate thermal zone. This is used to get the temperature of the zone during tuning.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "ti,omap2430-sdhci" for omap2430 controllers
|
||||
Should be "ti,omap3-sdhci" for omap3 controllers
|
||||
Should be "ti,omap4-sdhci" for omap4 and ti81 controllers
|
||||
Should be "ti,omap5-sdhci" for omap5 controllers
|
||||
Should be "ti,dra7-sdhci" for DRA7 and DRA72 controllers
|
||||
Should be "ti,k2g-sdhci" for K2G
|
||||
Should be "ti,am335-sdhci" for am335x controllers
|
||||
Should be "ti,am437-sdhci" for am437x controllers
|
||||
- ti,hwmods: Must be "mmc<n>", <n> is controller instance starting 1
|
||||
(Not required for K2G).
|
||||
- pinctrl-names: Should be subset of "default", "hs", "sdr12", "sdr25", "sdr50",
|
||||
"ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104",
|
||||
"ddr_1_8v-rev11", "ddr_1_8v" or "ddr_3_3v", "hs200_1_8v-rev11",
|
||||
"hs200_1_8v",
|
||||
- pinctrl-<n> : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt
|
||||
|
||||
Optional properties:
|
||||
- dmas: List of DMA specifiers with the controller specific format as described
|
||||
in the generic DMA client binding. A tx and rx specifier is required.
|
||||
- dma-names: List of DMA request names. These strings correspond 1:1 with the
|
||||
DMA specifiers listed in dmas. The string naming is to be "tx"
|
||||
and "rx" for TX and RX DMA requests, respectively.
|
||||
|
||||
Deprecated properties:
|
||||
- ti,non-removable: Compatible with the generic non-removable property
|
||||
|
||||
Example:
|
||||
mmc1: mmc@4809c000 {
|
||||
compatible = "ti,dra7-sdhci";
|
||||
reg = <0x4809c000 0x400>;
|
||||
ti,hwmods = "mmc1";
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&vmmc>; /* phandle to regulator node */
|
||||
dmas = <&sdma 61 &sdma 62>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
103
bindings/mmc/sdhci-pxa.yaml
Normal file
103
bindings/mmc/sdhci-pxa.yaml
Normal file
@@ -0,0 +1,103 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/sdhci-pxa.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell PXA SDHCI v2/v3 bindings
|
||||
|
||||
maintainers:
|
||||
- Ulf Hansson <ulf.hansson@linaro.org>
|
||||
|
||||
allOf:
|
||||
- $ref: mmc-controller.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: marvell,armada-380-sdhci
|
||||
then:
|
||||
properties:
|
||||
regs:
|
||||
minItems: 3
|
||||
reg-names:
|
||||
minItems: 3
|
||||
required:
|
||||
- reg-names
|
||||
else:
|
||||
properties:
|
||||
regs:
|
||||
maxItems: 1
|
||||
reg-names:
|
||||
maxItems: 1
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- mrvl,pxav2-mmc
|
||||
- mrvl,pxav3-mmc
|
||||
- marvell,armada-380-sdhci
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: sdhci
|
||||
- const: mbus
|
||||
- const: conf-sdio3
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: io
|
||||
- const: core
|
||||
|
||||
mrvl,clk-delay-cycles:
|
||||
description: Specify a number of cycles to delay for tuning.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/berlin2.h>
|
||||
mmc@d4280800 {
|
||||
compatible = "mrvl,pxav3-mmc";
|
||||
reg = <0xd4280800 0x800>;
|
||||
bus-width = <8>;
|
||||
interrupts = <27>;
|
||||
clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>;
|
||||
clock-names = "io", "core";
|
||||
non-removable;
|
||||
mrvl,clk-delay-cycles = <31>;
|
||||
};
|
||||
- |
|
||||
mmc@d8000 {
|
||||
compatible = "marvell,armada-380-sdhci";
|
||||
reg-names = "sdhci", "mbus", "conf-sdio3";
|
||||
reg = <0xd8000 0x1000>,
|
||||
<0xdc000 0x100>,
|
||||
<0x18454 0x4>;
|
||||
interrupts = <0 25 0x4>;
|
||||
clocks = <&gateclk 17>;
|
||||
clock-names = "io";
|
||||
mrvl,clk-delay-cycles = <0x1F>;
|
||||
};
|
||||
|
||||
...
|
||||
18
bindings/mmc/sdhci-spear.txt
Normal file
18
bindings/mmc/sdhci-spear.txt
Normal file
@@ -0,0 +1,18 @@
|
||||
* SPEAr SDHCI Controller
|
||||
|
||||
This file documents differences between the core properties in mmc.txt
|
||||
and the properties used by the sdhci-spear driver.
|
||||
|
||||
Required properties:
|
||||
- compatible: "st,spear300-sdhci"
|
||||
|
||||
Optional properties:
|
||||
- cd-gpios: card detect gpio, with zero flags.
|
||||
|
||||
Example:
|
||||
|
||||
sdhci@fc000000 {
|
||||
compatible = "st,spear300-sdhci";
|
||||
reg = <0xfc000000 0x1000>;
|
||||
cd-gpios = <&gpio0 6 0>;
|
||||
};
|
||||
67
bindings/mmc/sdhci-sprd.txt
Normal file
67
bindings/mmc/sdhci-sprd.txt
Normal file
@@ -0,0 +1,67 @@
|
||||
* Spreadtrum SDHCI controller (sdhci-sprd)
|
||||
|
||||
The Secure Digital (SD) Host controller on Spreadtrum SoCs provides an interface
|
||||
for MMC, SD and SDIO types of cards.
|
||||
|
||||
This file documents differences between the core properties in mmc.txt
|
||||
and the properties used by the sdhci-sprd driver.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should contain "sprd,sdhci-r11".
|
||||
- reg: physical base address of the controller and length.
|
||||
- interrupts: Interrupts used by the SDHCI controller.
|
||||
- clocks: Should contain phandle for the clock feeding the SDHCI controller
|
||||
- clock-names: Should contain the following:
|
||||
"sdio" - SDIO source clock (required)
|
||||
"enable" - gate clock which used for enabling/disabling the device (required)
|
||||
"2x_enable" - gate clock controlling the device for some special platforms (optional)
|
||||
|
||||
Optional properties:
|
||||
- assigned-clocks: the same with "sdio" clock
|
||||
- assigned-clock-parents: the default parent of "sdio" clock
|
||||
- pinctrl-names: should be "default", "state_uhs"
|
||||
- pinctrl-0: should contain default/high speed pin control
|
||||
- pinctrl-1: should contain uhs mode pin control
|
||||
|
||||
PHY DLL delays are used to delay the data valid window, and align the window
|
||||
to sampling clock. PHY DLL delays can be configured by following properties,
|
||||
and each property contains 4 cells which are used to configure the clock data
|
||||
write line delay value, clock read command line delay value, clock read data
|
||||
positive edge delay value and clock read data negative edge delay value.
|
||||
Each cell's delay value unit is cycle of the PHY clock.
|
||||
|
||||
- sprd,phy-delay-legacy: Delay value for legacy timing.
|
||||
- sprd,phy-delay-sd-highspeed: Delay value for SD high-speed timing.
|
||||
- sprd,phy-delay-sd-uhs-sdr50: Delay value for SD UHS SDR50 timing.
|
||||
- sprd,phy-delay-sd-uhs-sdr104: Delay value for SD UHS SDR50 timing.
|
||||
- sprd,phy-delay-mmc-highspeed: Delay value for MMC high-speed timing.
|
||||
- sprd,phy-delay-mmc-ddr52: Delay value for MMC DDR52 timing.
|
||||
- sprd,phy-delay-mmc-hs200: Delay value for MMC HS200 timing.
|
||||
- sprd,phy-delay-mmc-hs400: Delay value for MMC HS400 timing.
|
||||
- sprd,phy-delay-mmc-hs400es: Delay value for MMC HS400 enhanced strobe timing.
|
||||
|
||||
Examples:
|
||||
|
||||
sdio0: sdio@20600000 {
|
||||
compatible = "sprd,sdhci-r11";
|
||||
reg = <0 0x20600000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clock-names = "sdio", "enable";
|
||||
clocks = <&ap_clk CLK_EMMC_2X>,
|
||||
<&apahb_gate CLK_EMMC_EB>;
|
||||
assigned-clocks = <&ap_clk CLK_EMMC_2X>;
|
||||
assigned-clock-parents = <&rpll CLK_RPLL_390M>;
|
||||
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
pinctrl-0 = <&sd0_pins_default>;
|
||||
pinctrl-1 = <&sd0_pins_uhs>;
|
||||
|
||||
sprd,phy-delay-sd-uhs-sdr104 = <0x3f 0x7f 0x2e 0x2e>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
no-sdio;
|
||||
no-sd;
|
||||
cap-mmc-hw-reset;
|
||||
status = "okay";
|
||||
};
|
||||
110
bindings/mmc/sdhci-st.txt
Normal file
110
bindings/mmc/sdhci-st.txt
Normal file
@@ -0,0 +1,110 @@
|
||||
* STMicroelectronics sdhci-st MMC/SD controller
|
||||
|
||||
This file documents the differences between the core properties in
|
||||
Documentation/devicetree/bindings/mmc/mmc.txt and the properties
|
||||
used by the sdhci-st driver.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "st,sdhci" and it can be compatible to "st,sdhci-stih407"
|
||||
to set the internal glue logic used for configuring the MMC
|
||||
subsystem (mmcss) inside the FlashSS (available in STiH407 SoC
|
||||
family).
|
||||
|
||||
- clock-names: Should be "mmc" and "icn". (NB: The latter is not compulsory)
|
||||
See: Documentation/devicetree/bindings/resource-names.txt
|
||||
- clocks: Phandle to the clock.
|
||||
See: Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
- interrupts: One mmc interrupt should be described here.
|
||||
- interrupt-names: Should be "mmcirq".
|
||||
|
||||
- pinctrl-names: A pinctrl state names "default" must be defined.
|
||||
- pinctrl-0: Phandle referencing pin configuration of the sd/emmc controller.
|
||||
See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
|
||||
|
||||
- reg: This must provide the host controller base address and it can also
|
||||
contain the FlashSS Top register for TX/RX delay used by the driver
|
||||
to configure DLL inside the flashSS, if so reg-names must also be
|
||||
specified.
|
||||
|
||||
Optional properties:
|
||||
- reg-names: Should be "mmc" and "top-mmc-delay". "top-mmc-delay" is optional
|
||||
for eMMC on stih407 family silicon to configure DLL inside FlashSS.
|
||||
|
||||
- non-removable: Non-removable slot. Also used for configuring mmcss in STiH407 SoC
|
||||
family.
|
||||
See: Documentation/devicetree/bindings/mmc/mmc.txt.
|
||||
|
||||
- bus-width: Number of data lines.
|
||||
See: Documentation/devicetree/bindings/mmc/mmc.txt.
|
||||
|
||||
- max-frequency: Can be 200MHz, 100MHz or 50MHz (default) and used for
|
||||
configuring the CCONFIG3 in the mmcss.
|
||||
See: Documentation/devicetree/bindings/mmc/mmc.txt.
|
||||
|
||||
- resets: Phandle and reset specifier pair to softreset line of HC IP.
|
||||
See: Documentation/devicetree/bindings/reset/reset.txt
|
||||
|
||||
- vqmmc-supply: Phandle to the regulator dt node, mentioned as the vcc/vdd
|
||||
supply in eMMC/SD specs.
|
||||
|
||||
- sd-uhs-sdr50: To enable the SDR50 in the mmcss.
|
||||
See: Documentation/devicetree/bindings/mmc/mmc.txt.
|
||||
|
||||
- sd-uhs-sdr104: To enable the SDR104 in the mmcss.
|
||||
See: Documentation/devicetree/bindings/mmc/mmc.txt.
|
||||
|
||||
- sd-uhs-ddr50: To enable the DDR50 in the mmcss.
|
||||
See: Documentation/devicetree/bindings/mmc/mmc.txt.
|
||||
|
||||
Example:
|
||||
|
||||
/* Example stih416e eMMC configuration */
|
||||
|
||||
mmc0: sdhci@fe81e000 {
|
||||
compatible = "st,sdhci";
|
||||
reg = <0xfe81e000 0x1000>;
|
||||
interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>;
|
||||
interrupt-names = "mmcirq";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_mmc0>;
|
||||
clock-names = "mmc";
|
||||
clocks = <&clk_s_a1_ls 1>;
|
||||
bus-width = <8>
|
||||
|
||||
/* Example SD stih407 family configuration */
|
||||
|
||||
mmc1: sdhci@9080000 {
|
||||
compatible = "st,sdhci-stih407", "st,sdhci";
|
||||
reg = <0x09080000 0x7ff>;
|
||||
reg-names = "mmc";
|
||||
interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
|
||||
interrupt-names = "mmcirq";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sd1>;
|
||||
clock-names = "mmc";
|
||||
clocks = <&clk_s_c0_flexgen CLK_MMC_1>;
|
||||
resets = <&softreset STIH407_MMC1_SOFTRESET>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
/* Example eMMC stih407 family configuration */
|
||||
|
||||
mmc0: sdhci@9060000 {
|
||||
compatible = "st,sdhci-stih407", "st,sdhci";
|
||||
reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
|
||||
reg-names = "mmc", "top-mmc-delay";
|
||||
interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
|
||||
interrupt-names = "mmcirq";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_mmc0>;
|
||||
clock-names = "mmc";
|
||||
clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
|
||||
vqmmc-supply = <&vmmc_reg>;
|
||||
max-frequency = <200000000>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
sd-uhs-ddr50;
|
||||
};
|
||||
13
bindings/mmc/sdhci.txt
Normal file
13
bindings/mmc/sdhci.txt
Normal file
@@ -0,0 +1,13 @@
|
||||
The properties specific for SD host controllers. For properties shared by MMC
|
||||
host controllers refer to the mmc[1] bindings.
|
||||
|
||||
[1] Documentation/devicetree/bindings/mmc/mmc.txt
|
||||
|
||||
Optional properties:
|
||||
- sdhci-caps-mask: The sdhci capabilities register is incorrect. This 64bit
|
||||
property corresponds to the bits in the sdhci capability register. If the bit
|
||||
is on in the mask then the bit is incorrect in the register and should be
|
||||
turned off, before applying sdhci-caps.
|
||||
- sdhci-caps: The sdhci capabilities register is incorrect. This 64bit
|
||||
property corresponds to the bits in the sdhci capability register. If the
|
||||
bit is on in the property then the bit should be turned on.
|
||||
86
bindings/mmc/snps,dwcmshc-sdhci.yaml
Normal file
86
bindings/mmc/snps,dwcmshc-sdhci.yaml
Normal file
@@ -0,0 +1,86 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/snps,dwcmshc-sdhci.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Synopsys Designware Mobile Storage Host Controller Binding
|
||||
|
||||
maintainers:
|
||||
- Ulf Hansson <ulf.hansson@linaro.org>
|
||||
- Jisheng Zhang <Jisheng.Zhang@synaptics.com>
|
||||
|
||||
allOf:
|
||||
- $ref: mmc-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk3568-dwcmshc
|
||||
- rockchip,rk3588-dwcmshc
|
||||
- snps,dwcmshc-sdhci
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: core clock
|
||||
- description: bus clock for optional
|
||||
- description: axi clock for rockchip specified
|
||||
- description: block clock for rockchip specified
|
||||
- description: timer clock for rockchip specified
|
||||
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: core
|
||||
- const: bus
|
||||
- const: axi
|
||||
- const: block
|
||||
- const: timer
|
||||
|
||||
rockchip,txclk-tapnum:
|
||||
description: Specify the number of delay for tx sampling.
|
||||
$ref: /schemas/types.yaml#/definitions/uint8
|
||||
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
mmc@fe310000 {
|
||||
compatible = "rockchip,rk3568-dwcmshc";
|
||||
reg = <0xfe310000 0x10000>;
|
||||
interrupts = <0 25 0x4>;
|
||||
clocks = <&cru 17>, <&cru 18>, <&cru 19>, <&cru 20>, <&cru 21>;
|
||||
clock-names = "core", "bus", "axi", "block", "timer";
|
||||
bus-width = <8>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
- |
|
||||
mmc@aa0000 {
|
||||
compatible = "snps,dwcmshc-sdhci";
|
||||
reg = <0xaa000 0x1000>;
|
||||
interrupts = <0 25 0x4>;
|
||||
clocks = <&cru 17>, <&cru 18>;
|
||||
clock-names = "core", "bus";
|
||||
bus-width = <8>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
...
|
||||
107
bindings/mmc/socionext,uniphier-sd.yaml
Normal file
107
bindings/mmc/socionext,uniphier-sd.yaml
Normal file
@@ -0,0 +1,107 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/socionext,uniphier-sd.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: UniPhier SD/SDIO/eMMC controller
|
||||
|
||||
maintainers:
|
||||
- Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
description: version 2.91, 3.1, 3.1.1, respectively
|
||||
enum:
|
||||
- socionext,uniphier-sd-v2.91
|
||||
- socionext,uniphier-sd-v3.1
|
||||
- socionext,uniphier-sd-v3.1.1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
dmas:
|
||||
maxItems: 1
|
||||
|
||||
dma-names:
|
||||
const: rx-tx
|
||||
|
||||
reset-names:
|
||||
description: |
|
||||
There are three reset signals at maximum
|
||||
host: mandatory for all variants
|
||||
bridge: exist only for version 2.91
|
||||
hw: optional. exist if eMMC hw reset line is available
|
||||
oneOf:
|
||||
- const: host
|
||||
- items:
|
||||
- const: host
|
||||
- const: bridge
|
||||
- items:
|
||||
- const: host
|
||||
- const: hw
|
||||
- items:
|
||||
- const: host
|
||||
- const: bridge
|
||||
- const: hw
|
||||
|
||||
resets:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
|
||||
allOf:
|
||||
- $ref: mmc-controller.yaml
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: socionext,uniphier-sd-v2.91
|
||||
then:
|
||||
properties:
|
||||
reset-names:
|
||||
contains:
|
||||
const: bridge
|
||||
else:
|
||||
properties:
|
||||
reset-names:
|
||||
not:
|
||||
contains:
|
||||
const: bridge
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- reset-names
|
||||
- resets
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
sd: mmc@5a400000 {
|
||||
compatible = "socionext,uniphier-sd-v2.91";
|
||||
reg = <0x5a400000 0x200>;
|
||||
interrupts = <0 76 4>;
|
||||
pinctrl-names = "default", "uhs";
|
||||
pinctrl-0 = <&pinctrl_sd>;
|
||||
pinctrl-1 = <&pinctrl_sd_uhs>;
|
||||
clocks = <&mio_clk 0>;
|
||||
reset-names = "host", "bridge";
|
||||
resets = <&mio_rst 0>, <&mio_rst 3>;
|
||||
dma-names = "rx-tx";
|
||||
dmas = <&dmac 4>;
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
};
|
||||
66
bindings/mmc/synopsys-dw-mshc-common.yaml
Normal file
66
bindings/mmc/synopsys-dw-mshc-common.yaml
Normal file
@@ -0,0 +1,66 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc-common.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Synopsys Designware Mobile Storage Host Controller Common Properties
|
||||
|
||||
allOf:
|
||||
- $ref: "mmc-controller.yaml#"
|
||||
|
||||
maintainers:
|
||||
- Ulf Hansson <ulf.hansson@linaro.org>
|
||||
|
||||
# Everything else is described in the common file
|
||||
properties:
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
const: reset
|
||||
|
||||
clock-frequency:
|
||||
description:
|
||||
Should be the frequency (in Hz) of the ciu clock. If this
|
||||
is specified and the ciu clock is specified then we'll try to set the ciu
|
||||
clock to this at probe time.
|
||||
|
||||
fifo-depth:
|
||||
description:
|
||||
The maximum size of the tx/rx fifo's. If this property is not
|
||||
specified, the default value of the fifo size is determined from the
|
||||
controller registers.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
card-detect-delay:
|
||||
description:
|
||||
Delay in milli-seconds before detecting card after card
|
||||
insert event. The default value is 0.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
default: 0
|
||||
|
||||
data-addr:
|
||||
description:
|
||||
Override fifo address with value provided by DT. The default FIFO reg
|
||||
offset is assumed as 0x100 (version < 0x240A) and 0x200(version >= 0x240A)
|
||||
by driver. If the controller does not follow this rule, please use
|
||||
this property to set fifo address in device tree.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
fifo-watermark-aligned:
|
||||
description:
|
||||
Data done irq is expected if data length is less than
|
||||
watermark in PIO mode. But fifo watermark is requested to be aligned
|
||||
with data length in some SoC so that TX/RX irq can be generated with
|
||||
data done irq. Add this watermark quirk to mark this requirement and
|
||||
force fifo watermark setting accordingly.
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
dmas:
|
||||
maxItems: 1
|
||||
|
||||
dma-names:
|
||||
const: rx-tx
|
||||
|
||||
additionalProperties: true
|
||||
75
bindings/mmc/synopsys-dw-mshc.yaml
Normal file
75
bindings/mmc/synopsys-dw-mshc.yaml
Normal file
@@ -0,0 +1,75 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Synopsys Designware Mobile Storage Host Controller Binding
|
||||
|
||||
allOf:
|
||||
- $ref: "synopsys-dw-mshc-common.yaml#"
|
||||
|
||||
maintainers:
|
||||
- Ulf Hansson <ulf.hansson@linaro.org>
|
||||
|
||||
# Everything else is described in the common file
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- altr,socfpga-dw-mshc
|
||||
- img,pistachio-dw-mshc
|
||||
- snps,dw-mshc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
description:
|
||||
Handle to "biu" and "ciu" clocks for the
|
||||
bus interface unit clock and the card interface unit clock.
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: biu
|
||||
- const: ciu
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
mmc@12200000 {
|
||||
compatible = "snps,dw-mshc";
|
||||
reg = <0x12200000 0x1000>;
|
||||
interrupts = <0 75 0>;
|
||||
clocks = <&clock 351>, <&clock 132>;
|
||||
clock-names = "biu", "ciu";
|
||||
dmas = <&pdma 12>;
|
||||
dma-names = "rx-tx";
|
||||
resets = <&rst 20>;
|
||||
reset-names = "reset";
|
||||
vmmc-supply = <&buck8>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
broken-cd;
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
card-detect-delay = <200>;
|
||||
max-frequency = <200000000>;
|
||||
clock-frequency = <400000000>;
|
||||
data-addr = <0x200>;
|
||||
fifo-depth = <0x80>;
|
||||
fifo-watermark-aligned;
|
||||
};
|
||||
134
bindings/mmc/ti-omap-hsmmc.txt
Normal file
134
bindings/mmc/ti-omap-hsmmc.txt
Normal file
@@ -0,0 +1,134 @@
|
||||
* TI Highspeed MMC host controller for OMAP and 66AK2G family.
|
||||
|
||||
The Highspeed MMC Host Controller on TI OMAP and 66AK2G family
|
||||
provides an interface for MMC, SD, and SDIO types of memory cards.
|
||||
|
||||
This file documents differences between the core properties described
|
||||
by mmc.txt and the properties used by the omap_hsmmc driver.
|
||||
|
||||
Required properties:
|
||||
--------------------
|
||||
- compatible:
|
||||
Should be "ti,omap2-hsmmc", for OMAP2 controllers
|
||||
Should be "ti,omap3-hsmmc", for OMAP3 controllers
|
||||
Should be "ti,omap3-pre-es3-hsmmc" for OMAP3 controllers pre ES3.0
|
||||
Should be "ti,omap4-hsmmc", for OMAP4 controllers
|
||||
Should be "ti,am33xx-hsmmc", for AM335x controllers
|
||||
Should be "ti,k2g-hsmmc", "ti,omap4-hsmmc" for 66AK2G controllers.
|
||||
|
||||
SoC specific required properties:
|
||||
---------------------------------
|
||||
The following are mandatory properties for OMAPs, AM33xx and AM43xx SoCs only:
|
||||
- ti,hwmods: Must be "mmc<n>", n is controller instance starting 1.
|
||||
|
||||
The following are mandatory properties for 66AK2G SoCs only:
|
||||
- power-domains:Should contain a phandle to a PM domain provider node
|
||||
and an args specifier containing the MMC device id
|
||||
value. This property is as per the binding,
|
||||
Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
|
||||
- clocks: Must contain an entry for each entry in clock-names. Should
|
||||
be defined as per the he appropriate clock bindings consumer
|
||||
usage in Documentation/devicetree/bindings/clock/ti,sci-clk.yaml
|
||||
- clock-names: Shall be "fck" for the functional clock,
|
||||
and "mmchsdb_fck" for the debounce clock.
|
||||
|
||||
|
||||
Optional properties:
|
||||
--------------------
|
||||
- ti,dual-volt: boolean, supports dual voltage cards
|
||||
- <supply-name>-supply: phandle to the regulator device tree node
|
||||
"supply-name" examples are "vmmc",
|
||||
"vmmc_aux"(deprecated)/"vqmmc" etc
|
||||
- ti,non-removable: non-removable slot (like eMMC)
|
||||
- ti,needs-special-reset: Requires a special softreset sequence
|
||||
- ti,needs-special-hs-handling: HSMMC IP needs special setting
|
||||
for handling High Speed
|
||||
- dmas: List of DMA specifiers with the controller specific
|
||||
format as described in the generic DMA client
|
||||
binding. A tx and rx specifier is required.
|
||||
- dma-names: List of DMA request names. These strings correspond
|
||||
1:1 with the DMA specifiers listed in dmas.
|
||||
The string naming is to be "rx" and "tx" for
|
||||
RX and TX DMA requests, respectively.
|
||||
|
||||
Examples:
|
||||
|
||||
[hwmod populated DMA resources]
|
||||
|
||||
mmc1: mmc@4809c000 {
|
||||
compatible = "ti,omap4-hsmmc";
|
||||
reg = <0x4809c000 0x400>;
|
||||
ti,hwmods = "mmc1";
|
||||
ti,dual-volt;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&vmmc>; /* phandle to regulator node */
|
||||
ti,non-removable;
|
||||
};
|
||||
|
||||
[generic DMA request binding]
|
||||
|
||||
mmc1: mmc@4809c000 {
|
||||
compatible = "ti,omap4-hsmmc";
|
||||
reg = <0x4809c000 0x400>;
|
||||
ti,hwmods = "mmc1";
|
||||
ti,dual-volt;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&vmmc>; /* phandle to regulator node */
|
||||
ti,non-removable;
|
||||
dmas = <&edma 24
|
||||
&edma 25>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
[workaround for missing swakeup on am33xx]
|
||||
|
||||
This SOC is missing the swakeup line, it will not detect SDIO irq
|
||||
while in suspend.
|
||||
|
||||
------
|
||||
| PRCM |
|
||||
------
|
||||
^ |
|
||||
swakeup | | fclk
|
||||
| v
|
||||
------ ------- -----
|
||||
| card | -- CIRQ --> | hsmmc | -- IRQ --> | CPU |
|
||||
------ ------- -----
|
||||
|
||||
In suspend the fclk is off and the module is disfunctional. Even register reads
|
||||
will fail. A small logic in the host will request fclk restore, when an
|
||||
external event is detected. Once the clock is restored, the host detects the
|
||||
event normally. Since am33xx doesn't have this line it never wakes from
|
||||
suspend.
|
||||
|
||||
The workaround is to reconfigure the dat1 line as a GPIO upon suspend. To make
|
||||
this work, we need to set the named pinctrl states "default" and "idle".
|
||||
Prepare idle to remux dat1 as a gpio, and default to remux it back as sdio
|
||||
dat1. The MMC driver will then toggle between idle and default state during
|
||||
runtime.
|
||||
|
||||
In summary:
|
||||
1. select matching 'compatible' section, see example below.
|
||||
2. specify pinctrl states "default" and "idle", "sleep" is optional.
|
||||
3. specify the gpio irq used for detecting sdio irq in suspend
|
||||
|
||||
If configuration is incomplete, a warning message is emitted "falling back to
|
||||
polling". Also check the "sdio irq mode" in /sys/kernel/debug/mmc0/regs. Mind
|
||||
not every application needs SDIO irq, e.g. MMC cards.
|
||||
|
||||
mmc1: mmc@48060100 {
|
||||
compatible = "ti,am33xx-hsmmc";
|
||||
...
|
||||
pinctrl-names = "default", "idle", "sleep"
|
||||
pinctrl-0 = <&mmc1_pins>;
|
||||
pinctrl-1 = <&mmc1_idle>;
|
||||
pinctrl-2 = <&mmc1_sleep>;
|
||||
...
|
||||
interrupts-extended = <&intc 64 &gpio2 28 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
mmc1_idle : pinmux_cirq_pin {
|
||||
pinctrl-single,pins = <
|
||||
0x0f8 0x3f /* GPIO2_28 */
|
||||
>;
|
||||
};
|
||||
26
bindings/mmc/ti-omap.txt
Normal file
26
bindings/mmc/ti-omap.txt
Normal file
@@ -0,0 +1,26 @@
|
||||
* TI MMC host controller for OMAP1 and 2420
|
||||
|
||||
The MMC Host Controller on TI OMAP1 and 2420 family provides
|
||||
an interface for MMC, SD, and SDIO types of memory cards.
|
||||
|
||||
This file documents differences between the core properties described
|
||||
by mmc.txt and the properties used by the omap mmc driver.
|
||||
|
||||
Note that this driver will not work with omap2430 or later omaps,
|
||||
please see the omap hsmmc driver for the current omaps.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "ti,omap2420-mmc", for OMAP2420 controllers
|
||||
- ti,hwmods: For 2420, must be "msdi<n>", where n is controller
|
||||
instance starting 1
|
||||
|
||||
Examples:
|
||||
|
||||
msdi1: mmc@4809c000 {
|
||||
compatible = "ti,omap2420-mmc";
|
||||
ti,hwmods = "msdi1";
|
||||
reg = <0x4809c000 0x80>;
|
||||
interrupts = <83>;
|
||||
dmas = <&sdma 61 &sdma 62>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
39
bindings/mmc/usdhi6rol0.txt
Normal file
39
bindings/mmc/usdhi6rol0.txt
Normal file
@@ -0,0 +1,39 @@
|
||||
* Renesas usdhi6rol0 SD/SDIO host controller
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: must be
|
||||
"renesas,usdhi6rol0"
|
||||
- interrupts: 3 interrupts, named "card detect", "data" and "SDIO" must be
|
||||
specified
|
||||
- clocks: a clock binding for the IMCLK input
|
||||
|
||||
Optional properties:
|
||||
|
||||
- vmmc-supply: a phandle of a regulator, supplying Vcc to the card
|
||||
- vqmmc-supply: a phandle of a regulator, supplying VccQ to the card
|
||||
- pinctrl-names: Can contain a "default" entry and a "state_uhs"
|
||||
entry. The state_uhs entry is used together with the default
|
||||
entry when the board requires distinct settings for UHS speeds.
|
||||
|
||||
- pinctrl-N: One property for each name listed in pinctrl-names, see
|
||||
../pinctrl/pinctrl-bindings.txt.
|
||||
|
||||
Additionally any standard mmc bindings from mmc.txt can be used.
|
||||
|
||||
Example:
|
||||
|
||||
sd0: sd@ab000000 {
|
||||
compatible = "renesas,usdhi6rol0";
|
||||
reg = <0xab000000 0x200>;
|
||||
interrupts = <0 23 0x4
|
||||
0 24 0x4
|
||||
0 25 0x4>;
|
||||
interrupt-names = "card detect", "data", "SDIO";
|
||||
bus-width = <4>;
|
||||
max-frequency = <50000000>;
|
||||
cap-power-off-card;
|
||||
clocks = <&imclk>;
|
||||
vmmc-supply = <&vcc_sd0>;
|
||||
vqmmc-supply = <&vccq_sd0>;
|
||||
};
|
||||
23
bindings/mmc/vt8500-sdmmc.txt
Normal file
23
bindings/mmc/vt8500-sdmmc.txt
Normal file
@@ -0,0 +1,23 @@
|
||||
* Wondermedia WM8505/WM8650 SD/MMC Host Controller
|
||||
|
||||
This file documents differences between the core properties described
|
||||
by mmc.txt and the properties used by the wmt-sdmmc driver.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "wm,wm8505-sdhc".
|
||||
- interrupts: Two interrupts are required - regular irq and dma irq.
|
||||
|
||||
Optional properties:
|
||||
- sdon-inverted: SD_ON bit is inverted on the controller
|
||||
|
||||
Examples:
|
||||
|
||||
sdhc@d800a000 {
|
||||
compatible = "wm,wm8505-sdhc";
|
||||
reg = <0xd800a000 0x1000>;
|
||||
interrupts = <20 21>;
|
||||
clocks = <&sdhc>;
|
||||
bus-width = <4>;
|
||||
sdon-inverted;
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user