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dt-bindings: Add devicetree bindings

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Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").

Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
This commit is contained in:
Melody Olvera
2023-04-03 14:38:11 -07:00
parent c334acf377
commit 6f18ce8026
4878 changed files with 424312 additions and 0 deletions
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35
bindings/misc/aspeed,cvic.txt Normal file
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* ASPEED AST2400 and AST2500 coprocessor interrupt controller
This file describes the bindings for the interrupt controller present
in the AST2400 and AST2500 BMC SoCs which provides interrupt to the
ColdFire coprocessor.
It is not a normal interrupt controller and it would be rather
inconvenient to create an interrupt tree for it as it somewhat shares
some of the same sources as the main ARM interrupt controller but with
different numbers.
The AST2500 supports a SW generated interrupt
Required properties:
- reg: address and length of the register for the device.
- compatible: "aspeed,cvic" and one of:
"aspeed,ast2400-cvic"
or
"aspeed,ast2500-cvic"
- valid-sources: One cell, bitmap of supported sources for the implementation
Optional properties;
- copro-sw-interrupts: List of interrupt numbers that can be used as
SW interrupts from the ARM to the coprocessor.
(AST2500 only)
Example:
cvic: copro-interrupt-controller@1e6c2000 {
compatible = "aspeed,ast2500-cvic";
valid-sources = <0xffffffff>;
copro-sw-interrupts = <1>;
reg = <0x1e6c2000 0x80>;
};

46
bindings/misc/aspeed-p2a-ctrl.txt Normal file
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======================================================================
Device tree bindings for Aspeed AST2400/AST2500 PCI-to-AHB Bridge Control Driver
======================================================================
The bridge is available on platforms with the VGA enabled on the Aspeed device.
In this case, the host has access to a 64KiB window into all of the BMC's
memory. The BMC can disable this bridge. If the bridge is enabled, the host
has read access to all the regions of memory, however the host only has read
and write access depending on a register controlled by the BMC.
Required properties:
===================
- compatible: must be one of:
- "aspeed,ast2400-p2a-ctrl"
- "aspeed,ast2500-p2a-ctrl"
Optional properties:
===================
- reg: A hint for the memory regions associated with the P2A controller
- memory-region: A phandle to a reserved_memory region to be used for the PCI
to AHB mapping
The p2a-control node should be the child of a syscon node with the required
property:
- compatible : Should be one of the following:
"aspeed,ast2400-scu", "syscon", "simple-mfd"
"aspeed,ast2500-scu", "syscon", "simple-mfd"
Example
===================
g4 Example
----------
syscon: scu@1e6e2000 {
compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1a8>;
p2a: p2a-control {
compatible = "aspeed,ast2400-p2a-ctrl";
memory-region = <&reserved_memory>;
};
};

50
bindings/misc/atmel-ssc.txt Normal file
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* Atmel SSC driver.
Required properties:
- compatible: "atmel,at91rm9200-ssc" or "atmel,at91sam9g45-ssc"
- atmel,at91rm9200-ssc: support pdc transfer
- atmel,at91sam9g45-ssc: support dma transfer
- reg: Should contain SSC registers location and length
- interrupts: Should contain SSC interrupt
- clock-names: tuple listing input clock names.
Required elements: "pclk"
- clocks: phandles to input clocks.
Required properties for devices compatible with "atmel,at91sam9g45-ssc":
- dmas: DMA specifier, consisting of a phandle to DMA controller node,
the memory interface and SSC DMA channel ID (for tx and rx).
See Documentation/devicetree/bindings/dma/atmel-dma.txt for details.
- dma-names: Must be "tx", "rx".
Optional properties:
- atmel,clk-from-rk-pin: bool property.
- When SSC works in slave mode, according to the hardware design, the
clock can get from TK pin, and also can get from RK pin. So, add
this parameter to choose where the clock from.
- By default the clock is from TK pin, if the clock from RK pin, this
property is needed.
- #sound-dai-cells: Should contain <0>.
- This property makes the SSC into an automatically registered DAI.
Examples:
- PDC transfer:
ssc0: ssc@fffbc000 {
compatible = "atmel,at91rm9200-ssc";
reg = <0xfffbc000 0x4000>;
interrupts = <14 4 5>;
clocks = <&ssc0_clk>;
clock-names = "pclk";
};
- DMA transfer:
ssc0: ssc@f0010000 {
compatible = "atmel,at91sam9g45-ssc";
reg = <0xf0010000 0x4000>;
interrupts = <28 4 5>;
dmas = <&dma0 1 13>,
<&dma0 1 14>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
};

15
bindings/misc/brcm,kona-smc.txt Normal file
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Broadcom Secure Monitor Bounce buffer
-----------------------------------------------------
This binding defines the location of the bounce buffer
used for non-secure to secure communications.
Required properties:
- compatible : "brcm,kona-smc"
- DEPRECATED: compatible : "bcm,kona-smc"
- reg : Location and size of bounce buffer
Example:
smc@3404c000 {
compatible = "brcm,bcm11351-smc", "brcm,kona-smc";
reg = <0x3404c000 0x400>; //1 KiB in SRAM
};

26
bindings/misc/fsl,dpaa2-console.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2020 NXP
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/fsl,dpaa2-console.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: DPAA2 console support
maintainers:
- Laurentiu Tudor <laurentiu.tudor@nxp.com>
properties:
compatible:
const: "fsl,dpaa2-console"
reg:
maxItems: 1
description: A standard property. Specifies the region where the MCFBA
(MC firmware base address) register can be found.
required:
- compatible
- reg
additionalProperties: false

196
bindings/misc/fsl,qoriq-mc.txt Normal file
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* Freescale Management Complex
The Freescale Management Complex (fsl-mc) is a hardware resource
manager that manages specialized hardware objects used in
network-oriented packet processing applications. After the fsl-mc
block is enabled, pools of hardware resources are available, such as
queues, buffer pools, I/O interfaces. These resources are building
blocks that can be used to create functional hardware objects/devices
such as network interfaces, crypto accelerator instances, L2 switches,
etc.
For an overview of the DPAA2 architecture and fsl-mc bus see:
Documentation/networking/device_drivers/ethernet/freescale/dpaa2/overview.rst
As described in the above overview, all DPAA2 objects in a DPRC share the
same hardware "isolation context" and a 10-bit value called an ICID
(isolation context id) is expressed by the hardware to identify
the requester.
The generic 'iommus' property is insufficient to describe the relationship
between ICIDs and IOMMUs, so an iommu-map property is used to define
the set of possible ICIDs under a root DPRC and how they map to
an IOMMU.
For generic IOMMU bindings, see
Documentation/devicetree/bindings/iommu/iommu.txt.
For arm-smmu binding, see:
Documentation/devicetree/bindings/iommu/arm,smmu.yaml.
The MSI writes are accompanied by sideband data which is derived from the ICID.
The msi-map property is used to associate the devices with both the ITS
controller and the sideband data which accompanies the writes.
For generic MSI bindings, see
Documentation/devicetree/bindings/interrupt-controller/msi.txt.
For GICv3 and GIC ITS bindings, see:
Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml.
Required properties:
- compatible
Value type: <string>
Definition: Must be "fsl,qoriq-mc". A Freescale Management Complex
compatible with this binding must have Block Revision
Registers BRR1 and BRR2 at offset 0x0BF8 and 0x0BFC in
the MC control register region.
- reg
Value type: <prop-encoded-array>
Definition: A standard property. Specifies one or two regions
defining the MC's registers:
-the first region is the command portal for the
this machine and must always be present
-the second region is the MC control registers. This
region may not be present in some scenarios, such
as in the device tree presented to a virtual machine.
- ranges
Value type: <prop-encoded-array>
Definition: A standard property. Defines the mapping between the child
MC address space and the parent system address space.
The MC address space is defined by 3 components:
<region type> <offset hi> <offset lo>
Valid values for region type are
0x0 - MC portals
0x1 - QBMAN portals
- #address-cells
Value type: <u32>
Definition: Must be 3. (see definition in 'ranges' property)
- #size-cells
Value type: <u32>
Definition: Must be 1.
Sub-nodes:
The fsl-mc node may optionally have dpmac sub-nodes that describe
the relationship between the Ethernet MACs which belong to the MC
and the Ethernet PHYs on the system board.
The dpmac nodes must be under a node named "dpmacs" which contains
the following properties:
- #address-cells
Value type: <u32>
Definition: Must be present if dpmac sub-nodes are defined and must
have a value of 1.
- #size-cells
Value type: <u32>
Definition: Must be present if dpmac sub-nodes are defined and must
have a value of 0.
These nodes must have the following properties:
- compatible
Value type: <string>
Definition: Must be "fsl,qoriq-mc-dpmac".
- reg
Value type: <prop-encoded-array>
Definition: Specifies the id of the dpmac.
- phy-handle
Value type: <phandle>
Definition: Specifies the phandle to the PHY device node associated
with the this dpmac.
Optional properties:
- iommu-map: Maps an ICID to an IOMMU and associated iommu-specifier
data.
The property is an arbitrary number of tuples of
(icid-base,iommu,iommu-base,length).
Any ICID i in the interval [icid-base, icid-base + length) is
associated with the listed IOMMU, with the iommu-specifier
(i - icid-base + iommu-base).
- msi-map: Maps an ICID to a GIC ITS and associated msi-specifier
data.
The property is an arbitrary number of tuples of
(icid-base,gic-its,msi-base,length).
Any ICID in the interval [icid-base, icid-base + length) is
associated with the listed GIC ITS, with the msi-specifier
(i - icid-base + msi-base).
Deprecated properties:
- msi-parent
Value type: <phandle>
Definition: Describes the MSI controller node handling message
interrupts for the MC. When there is no translation
between the ICID and deviceID this property can be used
to describe the MSI controller used by the devices on the
mc-bus.
The use of this property for mc-bus is deprecated. Please
use msi-map.
Example:
smmu: iommu@5000000 {
compatible = "arm,mmu-500";
#iommu-cells = <1>;
stream-match-mask = <0x7C00>;
...
};
gic: interrupt-controller@6000000 {
compatible = "arm,gic-v3";
...
}
its: gic-its@6020000 {
compatible = "arm,gic-v3-its";
msi-controller;
...
};
fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc";
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
/* define map for ICIDs 23-64 */
iommu-map = <23 &smmu 23 41>;
/* define msi map for ICIDs 23-64 */
msi-map = <23 &its 23 41>;
#address-cells = <3>;
#size-cells = <1>;
/*
* Region type 0x0 - MC portals
* Region type 0x1 - QBMAN portals
*/
ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
dpmacs {
#address-cells = <1>;
#size-cells = <0>;
dpmac@1 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <1>;
phy-handle = <&mdio0_phy0>;
}
}
};

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# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
# Copyright (C) 2021 GE Inc.
# Copyright (C) 2021 Collabora Ltd.
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/ge-achc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: GE Healthcare USB Management Controller
description: |
A device which handles data acquisition from compatible USB based peripherals.
SPI is used for device management.
Note: This device does not expose the peripherals as USB devices.
maintainers:
- Sebastian Reichel <sre@kernel.org>
properties:
compatible:
items:
- const: ge,achc
- const: nxp,kinetis-k20
clocks:
maxItems: 1
vdd-supply:
description: Digital power supply regulator on VDD pin
vdda-supply:
description: Analog power supply regulator on VDDA pin
reg:
items:
- description: Control interface
- description: Firmware programming interface
reset-gpios:
description: GPIO used for hardware reset.
maxItems: 1
required:
- compatible
- clocks
- reg
- reset-gpios
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
spi@1 {
compatible = "ge,achc", "nxp,kinetis-k20";
reg = <1>, <0>;
clocks = <&achc_24M>;
reset-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
};
};

44
bindings/misc/idt_89hpesx.txt Normal file
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EEPROM / CSR SMBus-slave interface of IDT 89HPESx devices
Required properties:
- compatible : should be "<manufacturer>,<type>"
Basically there is only one manufacturer: idt, but some
compatible devices may be produced in future. Following devices
are supported: 89hpes8nt2, 89hpes12nt3, 89hpes24nt6ag2,
89hpes32nt8ag2, 89hpes32nt8bg2, 89hpes12nt12g2, 89hpes16nt16g2,
89hpes24nt24g2, 89hpes32nt24ag2, 89hpes32nt24bg2;
89hpes12n3, 89hpes12n3a, 89hpes24n3, 89hpes24n3a;
89hpes32h8, 89hpes32h8g2, 89hpes48h12, 89hpes48h12g2,
89hpes48h12ag2, 89hpes16h16, 89hpes22h16, 89hpes22h16g2,
89hpes34h16, 89hpes34h16g2, 89hpes64h16, 89hpes64h16g2,
89hpes64h16ag2;
89hpes12t3g2, 89hpes24t3g2, 89hpes16t4, 89hpes4t4g2,
89hpes10t4g2, 89hpes16t4g2, 89hpes16t4ag2, 89hpes5t5,
89hpes6t5, 89hpes8t5, 89hpes8t5a, 89hpes24t6, 89hpes6t6g2,
89hpes24t6g2, 89hpes16t7, 89hpes32t8, 89hpes32t8g2,
89hpes48t12, 89hpes48t12g2.
- reg : I2C address of the IDT 89HPESx device.
Optionally there can be EEPROM-compatible subnode:
- compatible: There are five EEPROM devices supported: 24c32, 24c64, 24c128,
24c256 and 24c512 differed by size.
- reg: Custom address of EEPROM device (If not specified IDT 89HPESx
(optional) device will try to communicate with EEPROM sited by default
address - 0x50)
- read-only : Parameterless property disables writes to the EEPROM
(optional)
Example:
idt@60 {
compatible = "idt,89hpes32nt8ag2";
reg = <0x74>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@50 {
compatible = "onsemi,24c64";
reg = <0x50>;
read-only;
};
};

41
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IFM camera sensor interface on mpc5200 LocalPlus bus
Required properties:
- compatible: "ifm,o2d-csi"
- reg: specifies sensor chip select number and associated address range
- interrupts: external interrupt line number and interrupt sense mode
of the interrupt line signaling frame valid events
- gpios: three gpio-specifiers for "capture", "reset" and "master enable"
GPIOs (strictly in this order).
- ifm,csi-clk-handle: the phandle to a node in the DT describing the sensor
clock generator. This node is usually a general purpose timer controller.
- ifm,csi-addr-bus-width: address bus width (valid values are 16, 24, 25)
- ifm,csi-data-bus-width: data bus width (valid values are 8 and 16)
- ifm,csi-wait-cycles: sensor bus wait cycles
Optional properties:
- ifm,csi-byte-swap: if this property is present, the byte swapping on
the bus will be enabled.
Example:
csi@3,0 {
compatible = "ifm,o2d-csi";
reg = <3 0 0x00100000>; /* CS 3, 1 MiB range */
interrupts = <1 1 2>; /* IRQ1, edge falling */
ifm,csi-clk-handle = <&timer7>;
gpios = <&gpio_simple 23 0 /* image_capture */
&gpio_simple 26 0 /* image_reset */
&gpio_simple 29 0>; /* image_master_en */
ifm,csi-addr-bus-width = <24>;
ifm,csi-data-bus-width = <8>;
ifm,csi-wait-cycles = <0>;
};
The base address of the used chip select is specified in the
ranges property of the parent localbus node, for example:
ranges = <0 0 0xff000000 0x01000000
3 0 0xe3000000 0x00100000>;

51
bindings/misc/intel,ixp4xx-ahb-queue-manager.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 Linaro Ltd.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/misc/intel,ixp4xx-ahb-queue-manager.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Intel IXP4xx AHB Queue Manager
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
description: |
The IXP4xx AHB Queue Manager maintains queues as circular buffers in
an 8KB embedded SRAM along with hardware pointers. It is used by both
the XScale processor and the NPEs (Network Processing Units) in the
IXP4xx for accelerating queues, especially for networking. Clients pick
queues from the queue manager with foo-queue = <&qmgr N> where the
&qmgr is a phandle to the queue manager and N is the queue resource
number. The queue resources available and their specific purpose
on a certain IXP4xx system will vary.
properties:
compatible:
items:
- const: intel,ixp4xx-ahb-queue-manager
reg:
maxItems: 1
interrupts:
items:
- description: Interrupt for queues 0-31
- description: Interrupt for queues 32-63
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
qmgr: queue-manager@60000000 {
compatible = "intel,ixp4xx-ahb-queue-manager";
reg = <0x60000000 0x4000>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>;
};

26
bindings/misc/lwn-bk4.txt Normal file
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* Liebherr's BK4 controller external SPI
A device which handles data acquisition from compatible industrial
peripherals.
The SPI is used for data and management purposes in both master and
slave modes.
Required properties:
- compatible : Should be "lwn,bk4"
Required SPI properties:
- reg : Should be address of the device chip select within
the controller.
- spi-max-frequency : Maximum SPI clocking speed of device in Hz, should be
30MHz at most for the Liebherr's BK4 external bus.
Example:
spidev0: spi@0 {
compatible = "lwn,bk4";
spi-max-frequency = <30000000>;
reg = <0>;
};

43
bindings/misc/nvidia,tegra186-misc.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/nvidia,tegra186-misc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra186 (and later) MISC register block
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
description: The MISC register block found on Tegra186 and later SoCs contains
registers that can be used to identify a given chip and various strapping
options.
properties:
compatible:
enum:
- nvidia,tegra186-misc
- nvidia,tegra194-misc
- nvidia,tegra234-misc
reg:
items:
- description: physical address and length of the registers which
contain revision and debug features
- description: physical address and length of the registers which
indicate strapping options
additionalProperties: false
required:
- compatible
- reg
examples:
- |
misc@100000 {
compatible = "nvidia,tegra186-misc";
reg = <0x00100000 0xf000>,
<0x0010f000 0x1000>;
};

51
bindings/misc/nvidia,tegra20-apbmisc.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/nvidia,tegra20-apbmisc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra APBMISC block
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
compatible:
oneOf:
- items:
- enum:
- nvidia,tegra210-apbmisc
- nvidia,tegra124-apbmisc
- nvidia,tegra114-apbmisc
- nvidia,tegra30-apbmisc
- const: nvidia,tegra20-apbmisc
- items:
- const: nvidia,tegra20-apbmisc
reg:
items:
- description: physical address and length of the registers which
contain revision and debug features
- description: physical address and length of the registers which
indicate strapping options
nvidia,long-ram-code:
description: If present, the RAM code is long (4 bit). If not, short
(2 bit).
type: boolean
additionalProperties: false
required:
- compatible
- reg
examples:
- |
apbmisc@70000800 {
compatible = "nvidia,tegra20-apbmisc";
reg = <0x70000800 0x64>, /* Chip revision */
<0x70000008 0x04>; /* Strapping options */
};

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
# Copyright (C) 2019,2020 Lubomir Rintel <lkundrak@v3.sk>
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/olpc,xo1.75-ec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: OLPC XO-1.75 Embedded Controller bindings
description: |
This binding describes the Embedded Controller acting as a SPI bus master
on a OLPC XO-1.75 laptop computer.
The embedded controller requires the SPI controller driver to signal
readiness to receive a transfer (that is, when TX FIFO contains the
response data) by strobing the ACK pin with the ready signal. See the
"ready-gpios" property of the SSP binding as documented in:
<Documentation/devicetree/bindings/spi/marvell,mmp2-ssp.yaml>.
maintainers:
- Lubomir Rintel <lkundrak@v3.sk>
properties:
compatible:
const: olpc,xo1.75-ec
cmd-gpios:
description: GPIO uspecifier of the CMD pin
maxItems: 1
spi-cpha: true
required:
- compatible
- cmd-gpios
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
spi {
spi-slave;
#address-cells = <0>;
#size-cells = <0>;
ready-gpios = <&gpio 125 GPIO_ACTIVE_HIGH>;
slave {
compatible = "olpc,xo1.75-ec";
spi-cpha;
cmd-gpios = <&gpio 155 GPIO_ACTIVE_HIGH>;
};
};
...

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bindings/misc/pvpanic-mmio.txt Normal file
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* QEMU PVPANIC MMIO Configuration bindings
QEMU's emulation / virtualization targets provide the following PVPANIC
MMIO Configuration interface on the "virt" machine.
type:
- a read-write, 16-bit wide data register.
QEMU exposes the data register to guests as memory mapped registers.
Required properties:
- compatible: "qemu,pvpanic-mmio".
- reg: the MMIO region used by the device.
* Bytes 0x0 Write panic event to the reg when guest OS panics.
* Bytes 0x1 Reserved.
Example:
/ {
#size-cells = <0x2>;
#address-cells = <0x2>;
pvpanic-mmio@9060000 {
compatible = "qemu,pvpanic-mmio";
reg = <0x0 0x9060000 0x0 0x2>;
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/qcom,fastrpc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm FastRPC Driver
maintainers:
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
description: |
The FastRPC implements an IPC (Inter-Processor Communication)
mechanism that allows for clients to transparently make remote method
invocations across DSP and APPS boundaries. This enables developers
to offload tasks to the DSP and free up the application processor for
other tasks.
properties:
compatible:
const: qcom,fastrpc
label:
enum:
- adsp
- mdsp
- sdsp
- cdsp
memory-region:
maxItems: 1
description:
Phandle to a node describing memory to be used for remote heap CMA.
qcom,glink-channels:
description:
A list of channels tied to this function, used for matching
the function to a set of virtual channels.
$ref: "/schemas/types.yaml#/definitions/string-array"
items:
- const: fastrpcglink-apps-dsp
qcom,non-secure-domain:
description:
Used to mark the current domain as non-secure.
type: boolean
qcom,smd-channels:
description:
Channel name used for the RPM communication
$ref: "/schemas/types.yaml#/definitions/string-array"
items:
- const: fastrpcsmd-apps-dsp
qcom,vmids:
description:
Virtual machine IDs for remote processor.
$ref: "/schemas/types.yaml#/definitions/uint32-array"
"#address-cells":
const: 1
"#size-cells":
const: 0
patternProperties:
"(compute-)?cb@[0-9]*$":
type: object
description: >
Each subnode of the Fastrpc represents compute context banks available on the dsp.
properties:
compatible:
const: qcom,fastrpc-compute-cb
reg:
maxItems: 1
iommus:
minItems: 1
maxItems: 2
qcom,nsessions:
$ref: /schemas/types.yaml#/definitions/uint32
default: 1
description: >
A value indicating how many sessions can share this context bank.
required:
- compatible
- reg
additionalProperties: false
required:
- compatible
- label
- "#address-cells"
- "#size-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
label = "lpass";
qcom,remote-pid = <2>;
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "sdsp";
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
compute-cb@1 {
compatible = "qcom,fastrpc-compute-cb";
reg = <1>;
iommus = <&apps_smmu 0x0541 0x0>;
};
compute-cb@2 {
compatible = "qcom,fastrpc-compute-cb";
reg = <2>;
iommus = <&apps_smmu 0x0542 0x0>;
};
compute-cb@3 {
compatible = "qcom,fastrpc-compute-cb";
reg = <3>;
iommus = <&apps_smmu 0x0543 0x0>;
};
};
};

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bindings/misc/qemu,vcpu-stall-detector.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/qemu,vcpu-stall-detector.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: VCPU stall detector
description:
This binding describes a CPU stall detector mechanism for virtual CPUs
which is accessed through MMIO.
maintainers:
- Sebastian Ene <sebastianene@google.com>
properties:
compatible:
enum:
- qemu,vcpu-stall-detector
reg:
maxItems: 1
clock-frequency:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
The internal clock of the stall detector peripheral measure in Hz used
to decrement its internal counter register on each tick.
Defaults to 10 if unset.
default: 10
timeout-sec:
description: |
The stall detector expiration timeout measured in seconds.
Defaults to 8 if unset. Please note that it also takes into account the
time spent while the VCPU is not running.
default: 8
required:
- compatible
additionalProperties: false
examples:
- |
vmwdt@9030000 {
compatible = "qemu,vcpu-stall-detector";
reg = <0x9030000 0x10000>;
clock-frequency = <10>;
timeout-sec = <8>;
};

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* Xilinx SDFEC(16nm) IP *
The Soft Decision Forward Error Correction (SDFEC) Engine is a Hard IP block
which provides high-throughput LDPC and Turbo Code implementations.
The LDPC decode & encode functionality is capable of covering a range of
customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality
principally covers codes used by LTE. The FEC Engine offers significant
power and area savings versus implementations done in the FPGA fabric.
Required properties:
- compatible: Must be "xlnx,sd-fec-1.1"
- clock-names : List of input clock names from the following:
- "core_clk", Main processing clock for processing core (required)
- "s_axi_aclk", AXI4-Lite memory-mapped slave interface clock (required)
- "s_axis_din_aclk", DIN AXI4-Stream Slave interface clock (optional)
- "s_axis_din_words-aclk", DIN_WORDS AXI4-Stream Slave interface clock (optional)
- "s_axis_ctrl_aclk", Control input AXI4-Stream Slave interface clock (optional)
- "m_axis_dout_aclk", DOUT AXI4-Stream Master interface clock (optional)
- "m_axis_dout_words_aclk", DOUT_WORDS AXI4-Stream Master interface clock (optional)
- "m_axis_status_aclk", Status output AXI4-Stream Master interface clock (optional)
- clocks : Clock phandles (see clock_bindings.txt for details).
- reg: Should contain Xilinx SDFEC 16nm Hardened IP block registers
location and length.
- xlnx,sdfec-code : Should contain "ldpc" or "turbo" to describe the codes
being used.
- xlnx,sdfec-din-words : A value 0 indicates that the DIN_WORDS interface is
driven with a fixed value and is not present on the device, a value of 1
configures the DIN_WORDS to be block based, while a value of 2 configures the
DIN_WORDS input to be supplied for each AXI transaction.
- xlnx,sdfec-din-width : Configures the DIN AXI stream where a value of 1
configures a width of "1x128b", 2 a width of "2x128b" and 4 configures a width
of "4x128b".
- xlnx,sdfec-dout-words : A value 0 indicates that the DOUT_WORDS interface is
driven with a fixed value and is not present on the device, a value of 1
configures the DOUT_WORDS to be block based, while a value of 2 configures the
DOUT_WORDS input to be supplied for each AXI transaction.
- xlnx,sdfec-dout-width : Configures the DOUT AXI stream where a value of 1
configures a width of "1x128b", 2 a width of "2x128b" and 4 configures a width
of "4x128b".
Optional properties:
- interrupts: should contain SDFEC interrupt number
Example
---------------------------------------
sd_fec_0: sd-fec@a0040000 {
compatible = "xlnx,sd-fec-1.1";
clock-names = "core_clk","s_axi_aclk","s_axis_ctrl_aclk","s_axis_din_aclk","m_axis_status_aclk","m_axis_dout_aclk";
clocks = <&misc_clk_2>,<&misc_clk_0>,<&misc_clk_1>,<&misc_clk_1>,<&misc_clk_1>, <&misc_clk_1>;
reg = <0x0 0xa0040000 0x0 0x40000>;
interrupt-parent = <&axi_intc>;
interrupts = <1 0>;
xlnx,sdfec-code = "ldpc";
xlnx,sdfec-din-words = <0>;
xlnx,sdfec-din-width = <2>;
xlnx,sdfec-dout-words = <0>;
xlnx,sdfec-dout-width = <1>;
};