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dt-bindings: Add devicetree bindings

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Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").

Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
This commit is contained in:
Melody Olvera
2023-04-03 14:38:11 -07:00
parent c334acf377
commit 6f18ce8026
4878 changed files with 424312 additions and 0 deletions
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77
bindings/memory-controllers/fsl/fsl,ddr.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ddr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale DDR memory controller
maintainers:
- Borislav Petkov <bp@alien8.de>
- York Sun <york.sun@nxp.com>
properties:
$nodename:
pattern: "^memory-controller@[0-9a-f]+$"
compatible:
oneOf:
- items:
- enum:
- fsl,qoriq-memory-controller-v4.4
- fsl,qoriq-memory-controller-v4.5
- fsl,qoriq-memory-controller-v4.7
- fsl,qoriq-memory-controller-v5.0
- const: fsl,qoriq-memory-controller
- enum:
- fsl,bsc9132-memory-controller
- fsl,mpc8536-memory-controller
- fsl,mpc8540-memory-controller
- fsl,mpc8541-memory-controller
- fsl,mpc8544-memory-controller
- fsl,mpc8548-memory-controller
- fsl,mpc8555-memory-controller
- fsl,mpc8560-memory-controller
- fsl,mpc8568-memory-controller
- fsl,mpc8569-memory-controller
- fsl,mpc8572-memory-controller
- fsl,mpc8349-memory-controller
- fsl,p1020-memory-controller
- fsl,p1021-memory-controller
- fsl,p2020-memory-controller
- fsl,qoriq-memory-controller
interrupts:
maxItems: 1
little-endian:
description:
Specifies little-endian access to registers. If omitted, big-endian will
be used.
type: boolean
reg:
maxItems: 1
required:
- compatible
- interrupts
- reg
additionalProperties: false
examples:
- |
memory-controller@2000 {
compatible = "fsl,bsc9132-memory-controller";
reg = <0x2000 0x1000>;
interrupts = <16 2 1 8>;
};
- |
memory-controller@8000 {
compatible = "fsl,qoriq-memory-controller-v4.7",
"fsl,qoriq-memory-controller";
reg = <0x8000 0x1000>;
interrupts = <16 2 1 23>;
};

113
bindings/memory-controllers/fsl/fsl,ifc.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ifc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: FSL/NXP Integrated Flash Controller
maintainers:
- Li Yang <leoyang.li@nxp.com>
description: |
NXP's integrated flash controller (IFC) is an advanced version of the
enhanced local bus controller which includes similar programming and signal
interfaces with an extended feature set. The IFC provides access to multiple
external memory types, such as NAND flash (SLC and MLC), NOR flash, EPROM,
SRAM and other memories where address and data are shared on a bus.
properties:
$nodename:
pattern: "^memory-controller@[0-9a-f]+$"
compatible:
const: fsl,ifc
"#address-cells":
enum: [2, 3]
description: |
Should be either two or three. The first cell is the chipselect
number, and the remaining cells are the offset into the chipselect.
"#size-cells":
enum: [1, 2]
description: |
Either one or two, depending on how large each chipselect can be.
reg:
maxItems: 1
interrupts:
minItems: 1
maxItems: 2
description: |
IFC may have one or two interrupts. If two interrupt specifiers are
present, the first is the "common" interrupt (CM_EVTER_STAT), and the
second is the NAND interrupt (NAND_EVTER_STAT). If there is only one,
that interrupt reports both types of event.
little-endian:
type: boolean
description: |
If this property is absent, the big-endian mode will be in use as default
for registers.
ranges:
description: |
Each range corresponds to a single chipselect, and covers the entire
access window as configured.
patternProperties:
"^.*@[a-f0-9]+(,[a-f0-9]+)+$":
type: object
description: |
Child device nodes describe the devices connected to IFC such as NOR (e.g.
cfi-flash) and NAND (fsl,ifc-nand). There might be board specific devices
like FPGAs, CPLDs, etc.
required:
- compatible
- reg
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
memory-controller@ffe1e000 {
compatible = "fsl,ifc";
#address-cells = <2>;
#size-cells = <1>;
reg = <0x0 0xffe1e000 0 0x2000>;
interrupts = <16 2 19 2>;
little-endian;
/* NOR, NAND Flashes and CPLD on board */
ranges = <0x0 0x0 0x0 0xee000000 0x02000000>,
<0x1 0x0 0x0 0xffa00000 0x00010000>,
<0x3 0x0 0x0 0xffb00000 0x00020000>;
flash@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x2000000>;
bank-width = <2>;
device-width = <1>;
partition@0 {
/* 32MB for user data */
reg = <0x0 0x02000000>;
label = "NOR Data";
};
};
};
};

73
bindings/memory-controllers/fsl/imx8m-ddrc.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: i.MX8M DDR Controller
maintainers:
- Peng Fan <peng.fan@nxp.com>
description:
The DDRC block is integrated in i.MX8M for interfacing with DDR based
memories.
It supports switching between different frequencies at runtime but during
this process RAM itself becomes briefly inaccessible so actual frequency
switching is implemented by TF-A code which runs from a SRAM area.
The Linux driver for the DDRC doesn't even map registers (they're included
for the sake of "describing hardware"), it mostly just exposes firmware
capabilities through standard Linux mechanism like devfreq and OPP tables.
properties:
compatible:
items:
- enum:
- fsl,imx8mn-ddrc
- fsl,imx8mm-ddrc
- fsl,imx8mq-ddrc
- const: fsl,imx8m-ddrc
reg:
maxItems: 1
description:
Base address and size of DDRC CTL area.
This is not currently mapped by the imx8m-ddrc driver.
clocks:
maxItems: 4
clock-names:
items:
- const: core
- const: pll
- const: alt
- const: apb
operating-points-v2: true
opp-table:
type: object
required:
- reg
- compatible
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8mm-clock.h>
ddrc: memory-controller@3d400000 {
compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
reg = <0x3d400000 0x400000>;
clock-names = "core", "pll", "alt", "apb";
clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
<&clk IMX8MM_DRAM_PLL>,
<&clk IMX8MM_CLK_DRAM_ALT>,
<&clk IMX8MM_CLK_DRAM_APB>;
operating-points-v2 = <&ddrc_opp_table>;
};

51
bindings/memory-controllers/fsl/mmdc.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/fsl/mmdc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Multi Mode DDR controller (MMDC)
maintainers:
- Anson Huang <Anson.Huang@nxp.com>
properties:
compatible:
oneOf:
- const: fsl,imx6q-mmdc
- items:
- enum:
- fsl,imx6qp-mmdc
- fsl,imx6sl-mmdc
- fsl,imx6sll-mmdc
- fsl,imx6sx-mmdc
- fsl,imx6ul-mmdc
- fsl,imx7ulp-mmdc
- const: fsl,imx6q-mmdc
reg:
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx6qdl-clock.h>
memory-controller@21b0000 {
compatible = "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>;
clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;
};
memory-controller@21b4000 {
compatible = "fsl,imx6q-mmdc";
reg = <0x021b4000 0x4000>;
};