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dt-bindings: Add devicetree bindings

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Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").

Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
This commit is contained in:
Melody Olvera
2023-04-03 14:38:11 -07:00
parent c334acf377
commit 6f18ce8026
4878 changed files with 424312 additions and 0 deletions
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80
bindings/mailbox/allwinner,sun6i-a31-msgbox.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mailbox/allwinner,sun6i-a31-msgbox.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner sunxi Message Box
maintainers:
- Samuel Holland <samuel@sholland.org>
description: |
The hardware message box on sun6i, sun8i, sun9i, and sun50i SoCs is a
two-user mailbox controller containing 8 unidirectional FIFOs. An interrupt
is raised for received messages, but software must poll to know when a
transmitted message has been acknowledged by the remote user. Each FIFO can
hold four 32-bit messages; when a FIFO is full, clients must wait before
attempting more transmissions.
Refer to ./mailbox.txt for generic information about mailbox device-tree
bindings.
properties:
compatible:
oneOf:
- items:
- enum:
- allwinner,sun8i-a83t-msgbox
- allwinner,sun8i-h3-msgbox
- allwinner,sun9i-a80-msgbox
- allwinner,sun50i-a64-msgbox
- allwinner,sun50i-h6-msgbox
- const: allwinner,sun6i-a31-msgbox
- const: allwinner,sun6i-a31-msgbox
reg:
maxItems: 1
clocks:
maxItems: 1
description: bus clock
resets:
maxItems: 1
description: bus reset
interrupts:
maxItems: 1
'#mbox-cells':
const: 1
description: first cell is the channel number (0-7)
required:
- compatible
- reg
- clocks
- resets
- interrupts
- '#mbox-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/sun8i-h3-ccu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/sun8i-h3-ccu.h>
msgbox: mailbox@1c17000 {
compatible = "allwinner,sun8i-h3-msgbox",
"allwinner,sun6i-a31-msgbox";
reg = <0x01c17000 0x1000>;
clocks = <&ccu CLK_BUS_MSGBOX>;
resets = <&ccu RST_BUS_MSGBOX>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
};
...

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Altera Mailbox Driver
=====================
Required properties:
- compatible : "altr,mailbox-1.0".
- reg : physical base address of the mailbox and length of
memory mapped region.
- #mbox-cells: Common mailbox binding property to identify the number
of cells required for the mailbox specifier. Should be 1.
Optional properties:
- interrupts : interrupt number. The interrupt specifier format
depends on the interrupt controller parent.
Example:
mbox_tx: mailbox@100 {
compatible = "altr,mailbox-1.0";
reg = <0x100 0x8>;
interrupt-parent = < &gic_0 >;
interrupts = <5>;
#mbox-cells = <1>;
};
mbox_rx: mailbox@200 {
compatible = "altr,mailbox-1.0";
reg = <0x200 0x8>;
interrupt-parent = < &gic_0 >;
interrupts = <6>;
#mbox-cells = <1>;
};
Mailbox client
===============
"mboxes" and the optional "mbox-names" (please see
Documentation/devicetree/bindings/mailbox/mailbox.txt for details). Each value
of the mboxes property should contain a phandle to the mailbox controller
device node and second argument is the channel index. It must be 0 (hardware
support only one channel).The equivalent "mbox-names" property value can be
used to give a name to the communication channel to be used by the client user.
Example:
mclient0: mclient0@400 {
compatible = "client-1.0";
reg = <0x400 0x10>;
mbox-names = "mbox-tx", "mbox-rx";
mboxes = <&mbox_tx 0>,
<&mbox_rx 0>;
};

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mailbox/amlogic,meson-gxbb-mhu.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Amlogic Meson Message-Handling-Unit Controller
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
description: |
The Amlogic's Meson SoCs Message-Handling-Unit (MHU) is a mailbox controller
that has 3 independent channels/links to communicate with remote processor(s).
MHU links are hardwired on a platform. A link raises interrupt for any
received data. However, there is no specified way of knowing if the sent
data has been read by the remote. This driver assumes the sender polls
STAT register and the remote clears it after having read the data.
properties:
compatible:
enum:
- amlogic,meson-gxbb-mhu
reg:
maxItems: 1
interrupts:
minItems: 3
description:
Contains the interrupt information corresponding to each of the 3 links
of MHU.
"#mbox-cells":
const: 1
required:
- compatible
- reg
- interrupts
- "#mbox-cells"
additionalProperties: false
examples:
- |
mailbox@c883c404 {
compatible = "amlogic,meson-gxbb-mhu";
reg = <0xc883c404 0x4c>;
interrupts = <208>, <209>, <210>;
#mbox-cells = <1>;
};

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# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mailbox/apple,mailbox.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Apple Mailbox Controller
maintainers:
- Hector Martin <marcan@marcan.st>
- Sven Peter <sven@svenpeter.dev>
description:
The Apple mailbox consists of two FIFOs used to exchange 64+32 bit
messages between the main CPU and a co-processor. Multiple instances
of this mailbox can be found on Apple SoCs.
One of the two FIFOs is used to send data to a co-processor while the other
FIFO is used for the other direction.
Various clients implement different IPC protocols based on these simple
messages and shared memory buffers.
properties:
compatible:
oneOf:
- description:
ASC mailboxes are the most common variant found on the M1 used
for example for the display controller, the system management
controller and the NVMe coprocessor.
items:
- enum:
- apple,t8103-asc-mailbox
- apple,t6000-asc-mailbox
- const: apple,asc-mailbox-v4
- description:
M3 mailboxes are an older variant with a slightly different MMIO
interface still found on the M1. It is used for the Thunderbolt
co-processors.
items:
- enum:
- apple,t8103-m3-mailbox
- apple,t6000-m3-mailbox
- const: apple,m3-mailbox-v2
reg:
maxItems: 1
interrupts:
items:
- description: send fifo is empty interrupt
- description: send fifo is not empty interrupt
- description: receive fifo is empty interrupt
- description: receive fifo is not empty interrupt
interrupt-names:
items:
- const: send-empty
- const: send-not-empty
- const: recv-empty
- const: recv-not-empty
"#mbox-cells":
const: 0
power-domains:
maxItems: 1
required:
- compatible
- reg
- interrupts
- interrupt-names
- "#mbox-cells"
additionalProperties: false
examples:
- |
mailbox@77408000 {
compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4";
reg = <0x77408000 0x4000>;
interrupts = <1 583 4>, <1 584 4>, <1 585 4>, <1 586 4>;
interrupt-names = "send-empty", "send-not-empty",
"recv-empty", "recv-not-empty";
#mbox-cells = <0>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mailbox/arm,mhu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM MHU Mailbox Controller
maintainers:
- Jassi Brar <jaswinder.singh@linaro.org>
description: |
The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has 3
independent channels/links to communicate with remote processor(s). MHU links
are hardwired on a platform. A link raises interrupt for any received data.
However, there is no specified way of knowing if the sent data has been read
by the remote. This driver assumes the sender polls STAT register and the
remote clears it after having read the data. The last channel is specified to
be a 'Secure' resource, hence can't be used by Linux running NS.
The MHU hardware also allows operations in doorbell mode. The MHU drives the
interrupt signal using a 32-bit register, with all 32-bits logically ORed
together. It provides a set of registers to enable software to set, clear and
check the status of each of the bits of this register independently. The use
of 32 bits per interrupt line enables software to provide more information
about the source of the interrupt. For example, each bit of the register can
be associated with a type of event that can contribute to raising the
interrupt. Each of the 32-bits can be used as "doorbell" to alert the remote
processor.
# We need a select here so we don't match all nodes with 'arm,primecell'
select:
properties:
compatible:
contains:
enum:
- arm,mhu
- arm,mhu-doorbell
required:
- compatible
properties:
compatible:
oneOf:
- description: Data transfer mode
items:
- const: arm,mhu
- const: arm,primecell
- description: Doorbell mode
items:
- const: arm,mhu-doorbell
- const: arm,primecell
reg:
maxItems: 1
interrupts:
minItems: 2
items:
- description: low-priority non-secure
- description: high-priority non-secure
- description: Secure
clocks:
maxItems: 1
clock-names:
items:
- const: apb_pclk
'#mbox-cells':
description: |
Set to 1 in data transfer mode and represents index of the channel.
Set to 2 in doorbell mode and represents index of the channel and doorbell
number.
enum: [ 1, 2 ]
required:
- compatible
- reg
- interrupts
- '#mbox-cells'
additionalProperties: false
examples:
# Data transfer mode.
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
mhuA: mailbox@2b1f0000 {
#mbox-cells = <1>;
compatible = "arm,mhu", "arm,primecell";
reg = <0 0x2b1f0000 0 0x1000>;
interrupts = <0 36 4>, /* LP-NonSecure */
<0 35 4>, /* HP-NonSecure */
<0 37 4>; /* Secure */
clocks = <&clock 0 2 1>;
clock-names = "apb_pclk";
};
};
firmware {
scpi {
compatible = "arm,scpi";
mboxes = <&mhuA 1>; /* HP-NonSecure */
shmem = <&cpu_scp_hpri>; /* HP-NonSecure */
scpi_devpd: power-controller {
compatible = "arm,scpi-power-domains";
num-domains = <2>;
#power-domain-cells = <1>;
};
};
};
# Doorbell mode.
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
mhuB: mailbox@2b2f0000 {
#mbox-cells = <2>;
compatible = "arm,mhu-doorbell", "arm,primecell";
reg = <0 0x2b2f0000 0 0x1000>;
interrupts = <0 36 4>, /* LP-NonSecure */
<0 35 4>, /* HP-NonSecure */
<0 37 4>; /* Secure */
clocks = <&clock 0 2 1>;
clock-names = "apb_pclk";
};
};
firmware {
scmi {
compatible = "arm,scmi";
mboxes = <&mhuB 0 0>, /* LP-NonSecure, 1st doorbell */
<&mhuB 0 1>; /* LP-NonSecure, 2nd doorbell */
mbox-names = "tx", "rx";
shmem = <&cpu_scp_lpri0>,
<&cpu_scp_lpri1>;
#address-cells = <1>;
#size-cells = <0>;
scmi_devpd: protocol@11 {
reg = <0x11>;
#power-domain-cells = <1>;
};
scmi_dvfs: protocol@13 {
reg = <0x13>;
#clock-cells = <1>;
mboxes = <&mhuB 1 2>, /* HP-NonSecure, 3rd doorbell */
<&mhuB 1 3>; /* HP-NonSecure, 4th doorbell */
mbox-names = "tx", "rx";
shmem = <&cpu_scp_hpri0>,
<&cpu_scp_hpri1>;
};
};
};
...

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mailbox/arm,mhuv2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM MHUv2 Mailbox Controller
maintainers:
- Tushar Khandelwal <tushar.khandelwal@arm.com>
- Viresh Kumar <viresh.kumar@linaro.org>
description: |
The Arm Message Handling Unit (MHU) Version 2 is a mailbox controller that has
between 1 and 124 channel windows (each 32-bit wide) to provide unidirectional
communication with remote processor(s), where the number of channel windows
are implementation dependent.
Given the unidirectional nature of the controller, an MHUv2 mailbox may only
be written to or read from. If a pair of MHU controllers is implemented
between two processing elements to provide bidirectional communication, these
must be specified as two separate mailboxes.
If the interrupts property is present in device tree node, then its treated as
a "receiver" mailbox, otherwise a "sender".
An MHU controller must be specified along with the supported transport
protocols. The transport protocols determine the method of data transmission
as well as the number of provided mailbox channels.
Following are the possible transport protocols.
- Data-transfer: Each transfer is made of one or more words, using one or more
channel windows.
- Doorbell: Each transfer is made up of single bit flag, using any one of the
bits in a channel window. A channel window can support up to 32 doorbells
and the entire window shall be used in doorbell protocol. Optionally, data
may be transmitted through a shared memory region, wherein the MHU is used
strictly as an interrupt generation mechanism but that is out of the scope
of these bindings.
# We need a select here so we don't match all nodes with 'arm,primecell'
select:
properties:
compatible:
contains:
enum:
- arm,mhuv2-tx
- arm,mhuv2-rx
required:
- compatible
properties:
compatible:
oneOf:
- description: Sender mode
items:
- const: arm,mhuv2-tx
- const: arm,primecell
- description: Receiver-mode
items:
- const: arm,mhuv2-rx
- const: arm,primecell
reg:
maxItems: 1
interrupts:
description: |
The MHUv2 controller always implements an interrupt in the "receiver"
mode, while the interrupt in the "sender" mode was not available in the
version MHUv2.0, but the later versions do have it.
maxItems: 1
clocks:
maxItems: 1
clock-names:
maxItems: 1
arm,mhuv2-protocols:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
description: |
The MHUv2 controller may contain up to 124 channel windows (each 32-bit
wide). The hardware and the DT bindings allows any combination of those to
be used for various transport protocols.
This property allows a platform to describe how these channel windows are
used in various transport protocols. The entries in this property shall be
present as an array of tuples, where each tuple describes details about
one of the transport protocol being implemented over some channel
window(s).
The first field of a tuple signifies the transfer protocol, 0 is reserved
for doorbell protocol, and 1 is reserved for data-transfer protocol.
Using any other value in the first field of a tuple makes it invalid.
The second field of a tuple signifies the number of channel windows where
the protocol would be used and should be set to a non zero value. For
doorbell protocol this field signifies the number of 32-bit channel
windows that implement the doorbell protocol. For data-transfer protocol,
this field signifies the number of 32-bit channel windows that implement
the data-transfer protocol.
The total number of channel windows specified here shouldn't be more than
the ones implemented by the platform, though one can specify lesser number
of windows here than what the platform implements.
mhu: mailbox@2b1f0000 {
...
arm,mhuv2-protocols = <0 2>, <1 1>, <1 5>, <1 7>;
}
The above example defines the protocols of an ARM MHUv2 mailbox
controller, where a total of 15 channel windows are used. The first two
windows are used in doorbell protocol (64 doorbells), followed by 1, 5 and
7 windows (separately) used in data-transfer protocol.
minItems: 1
maxItems: 124
items:
items:
- enum: [ 0, 1 ]
- minimum: 0
maximum: 124
'#mbox-cells':
description: |
It is always set to 2. The first argument in the consumers 'mboxes'
property represents the channel window group, which may be used in
doorbell, or data-transfer protocol, and the second argument (only
relevant in doorbell protocol, should be 0 otherwise) represents the
doorbell number within the 32 bit wide channel window.
From the example given above for arm,mhuv2-protocols, here is how a client
node can reference them.
mboxes = <&mhu 0 5>; // Channel Window Group 0, doorbell 5.
mboxes = <&mhu 1 7>; // Channel Window Group 1, doorbell 7.
mboxes = <&mhu 2 0>; // Channel Window Group 2, data transfer protocol with 1 window.
mboxes = <&mhu 3 0>; // Channel Window Group 3, data transfer protocol with 5 windows.
mboxes = <&mhu 4 0>; // Channel Window Group 4, data transfer protocol with 7 windows.
const: 2
if:
# Interrupt is compulsory for receiver
properties:
compatible:
contains:
const: arm,mhuv2-rx
then:
required:
- interrupts
required:
- compatible
- reg
- '#mbox-cells'
- arm,mhuv2-protocols
additionalProperties: false
examples:
# Multiple transport protocols implemented by the mailbox controllers
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
mhu_tx: mailbox@2b1f0000 {
#mbox-cells = <2>;
compatible = "arm,mhuv2-tx", "arm,primecell";
reg = <0 0x2b1f0000 0 0x1000>;
clocks = <&clock 0>;
clock-names = "apb_pclk";
interrupts = <0 45 4>;
arm,mhuv2-protocols = <1 5>, <1 2>, <1 5>, <1 7>, <0 2>;
};
mhu_rx: mailbox@2b1f1000 {
#mbox-cells = <2>;
compatible = "arm,mhuv2-rx", "arm,primecell";
reg = <0 0x2b1f1000 0 0x1000>;
clocks = <&clock 0>;
clock-names = "apb_pclk";
interrupts = <0 46 4>;
arm,mhuv2-protocols = <1 1>, <1 7>, <0 2>;
};
mhu_client: dsp@596e8000 {
compatible = "fsl,imx8qxp-dsp";
reg = <0 0x596e8000 0 0x88000>;
clocks = <&adma_lpcg 0>, <&adma_lpcg 1>, <&adma_lpcg 2>;
clock-names = "ipg", "ocram", "core";
power-domains = <&pd 0>, <&pd 1>, <&pd 2>, <&pd 3>;
mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1";
mboxes = <&mhu_tx 2 0>, //data-transfer protocol with 5 windows, mhu-tx
<&mhu_tx 3 0>, //data-transfer protocol with 7 windows, mhu-tx
<&mhu_rx 2 27>, //doorbell protocol channel 2, doorbell 27, mhu-rx
<&mhu_rx 0 0>; //data-transfer protocol with 1 window, mhu-rx
memory-region = <&dsp_reserved>;
};
};

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Broadcom BCM2835 VideoCore mailbox IPC
Required properties:
- compatible: Should be "brcm,bcm2835-mbox"
- reg: Specifies base physical address and size of the registers
- interrupts: The interrupt number
See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
- #mbox-cells: Specifies the number of cells needed to encode a mailbox
channel. The value shall be 0, since there is only one
mailbox channel implemented by the device.
Example:
mailbox: mailbox@7e00b880 {
compatible = "brcm,bcm2835-mbox";
reg = <0x7e00b880 0x40>;
interrupts = <0 1>;
#mbox-cells = <0>;
};
firmware: firmware {
compatible = "raspberrypi,firmware";
mboxes = <&mailbox>;
#power-domain-cells = <1>;
};

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Broadcom FlexRM Ring Manager
============================
The Broadcom FlexRM ring manager provides a set of rings which can be
used to submit work to offload engines. An SoC may have multiple FlexRM
hardware blocks. There is one device tree entry per FlexRM block. The
FlexRM driver will create a mailbox-controller instance for given FlexRM
hardware block where each mailbox channel is a separate FlexRM ring.
Required properties:
--------------------
- compatible: Should be "brcm,iproc-flexrm-mbox"
- reg: Specifies base physical address and size of the FlexRM
ring registers
- msi-parent: Phandles (and potential Device IDs) to MSI controllers
The FlexRM engine will send MSIs (instead of wired
interrupts) to CPU. There is one MSI for each FlexRM ring.
Refer devicetree/bindings/interrupt-controller/msi.txt
- #mbox-cells: Specifies the number of cells needed to encode a mailbox
channel. This should be 3.
The 1st cell is the mailbox channel number.
The 2nd cell contains MSI completion threshold. This is the
number of completion messages for which FlexRM will inject
one MSI interrupt to CPU.
The 3nd cell contains MSI timer value representing time for
which FlexRM will wait to accumulate N completion messages
where N is the value specified by 2nd cell above. If FlexRM
does not get required number of completion messages in time
specified by this cell then it will inject one MSI interrupt
to CPU provided atleast one completion message is available.
Optional properties:
--------------------
- dma-coherent: Present if DMA operations made by the FlexRM engine (such
as DMA descriptor access, access to buffers pointed by DMA
descriptors and read/write pointer updates to DDR) are
cache coherent with the CPU.
Example:
--------
crypto_mbox: mbox@67000000 {
compatible = "brcm,iproc-flexrm-mbox";
reg = <0x67000000 0x200000>;
msi-parent = <&gic_its 0x7f00>;
#mbox-cells = <3>;
};
crypto@672c0000 {
compatible = "brcm,spu2-v2-crypto";
reg = <0x672c0000 0x1000>;
mboxes = <&crypto_mbox 0 0x1 0xffff>,
<&crypto_mbox 1 0x1 0xffff>,
<&crypto_mbox 16 0x1 0xffff>,
<&crypto_mbox 17 0x1 0xffff>,
<&crypto_mbox 30 0x1 0xffff>,
<&crypto_mbox 31 0x1 0xffff>;
};

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The PDC driver manages data transfer to and from various offload engines
on some Broadcom SoCs. An SoC may have multiple PDC hardware blocks. There is
one device tree entry per block. On some chips, the PDC functionality is
handled by the FA2 (Northstar Plus).
Required properties:
- compatible : Should be "brcm,iproc-pdc-mbox" or "brcm,iproc-fa2-mbox" for
FA2/Northstar Plus.
- reg: Should contain PDC registers location and length.
- interrupts: Should contain the IRQ line for the PDC.
- #mbox-cells: 1
- brcm,rx-status-len: Length of metadata preceding received frames, in bytes.
Optional properties:
- brcm,use-bcm-hdr: present if a BCM header precedes each frame.
Example:
pdc0: iproc-pdc0@612c0000 {
compatible = "brcm,iproc-pdc-mbox";
reg = <0 0x612c0000 0 0x445>; /* PDC FS0 regs */
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>; /* one cell per mailbox channel */
brcm,rx-status-len = <32>;
brcm,use-bcm-hdr;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mailbox/fsl,mu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX Messaging Unit (MU)
maintainers:
- Dong Aisheng <aisheng.dong@nxp.com>
description: |
The Messaging Unit module enables two processors within the SoC to
communicate and coordinate by passing messages (e.g. data, status
and control) through the MU interface. The MU also provides the ability
for one processor to signal the other processor using interrupts.
Because the MU manages the messaging between processors, the MU uses
different clocks (from each side of the different peripheral buses).
Therefore, the MU must synchronize the accesses from one side to the
other. The MU accomplishes synchronization using two sets of matching
registers (Processor A-facing, Processor B-facing).
properties:
compatible:
oneOf:
- const: fsl,imx6sx-mu
- const: fsl,imx7ulp-mu
- const: fsl,imx8ulp-mu
- const: fsl,imx8-mu-scu
- const: fsl,imx8-mu-seco
- const: fsl,imx93-mu-s4
- const: fsl,imx8ulp-mu-s4
- items:
- const: fsl,imx93-mu
- const: fsl,imx8ulp-mu
- items:
- enum:
- fsl,imx7s-mu
- fsl,imx8mq-mu
- fsl,imx8mm-mu
- fsl,imx8mn-mu
- fsl,imx8mp-mu
- fsl,imx8qm-mu
- fsl,imx8qxp-mu
- const: fsl,imx6sx-mu
- description: To communicate with i.MX8 SCU with fast IPC
items:
- const: fsl,imx8-mu-scu
- enum:
- fsl,imx8qm-mu
- fsl,imx8qxp-mu
- const: fsl,imx6sx-mu
reg:
maxItems: 1
interrupts:
minItems: 1
maxItems: 2
interrupt-names:
minItems: 1
items:
- const: tx
- const: rx
"#mbox-cells":
description: |
<&phandle type channel>
phandle : Label name of controller
type : Channel type
channel : Channel number
This MU support 5 type of unidirectional channels, each type
has 4 channels except RST channel which only has 1 channel.
A total of 17 channels. Following types are
supported:
0 - TX channel with 32bit transmit register and IRQ transmit
acknowledgment support.
1 - RX channel with 32bit receive register and IRQ support
2 - TX doorbell channel. Without own register and no ACK support.
3 - RX doorbell channel.
4 - RST channel
const: 2
clocks:
maxItems: 1
fsl,mu-side-b:
description: boolean, if present, means it is for side B MU.
type: boolean
power-domains:
maxItems: 1
required:
- compatible
- reg
- interrupts
- "#mbox-cells"
allOf:
- if:
properties:
compatible:
enum:
- fsl,imx93-mu-s4
then:
properties:
interrupt-names:
minItems: 2
interrupts:
minItems: 2
else:
properties:
interrupts:
maxItems: 1
not:
required:
- interrupt-names
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
mailbox@5d1b0000 {
compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
reg = <0x5d1b0000 0x10000>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
};

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Hisilicon Hi3660 Mailbox Controller
Hisilicon Hi3660 mailbox controller supports up to 32 channels. Messages
are passed between processors, including application & communication
processors, MCU, HIFI, etc. Each channel is unidirectional and accessed
by using MMIO registers; it supports maximum to 8 words message.
Controller
----------
Required properties:
- compatible: : Shall be "hisilicon,hi3660-mbox"
- reg: : Offset and length of the device's register set
- #mbox-cells: : Must be 3
<&phandle channel dst_irq ack_irq>
phandle : Label name of controller
channel : Channel number
dst_irq : Remote interrupt vector
ack_irq : Local interrupt vector
- interrupts: : Contains the two IRQ lines for mailbox.
Example:
mailbox: mailbox@e896b000 {
compatible = "hisilicon,hi3660-mbox";
reg = <0x0 0xe896b000 0x0 0x1000>;
interrupts = <0x0 0xc0 0x4>,
<0x0 0xc1 0x4>;
#mbox-cells = <3>;
};
Client
------
Required properties:
- compatible : See the client docs
- mboxes : Standard property to specify a Mailbox (See ./mailbox.txt)
Cells must match 'mbox-cells' (See Controller docs above)
Optional properties
- mbox-names : Name given to channels seen in the 'mboxes' property.
Example:
stub_clock: stub_clock@e896b500 {
compatible = "hisilicon,hi3660-stub-clk";
reg = <0x0 0xe896b500 0x0 0x0100>;
#clock-cells = <1>;
mboxes = <&mailbox 13 3 0>;
};

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Hisilicon Hi6220 Mailbox Driver
===============================
Hisilicon Hi6220 mailbox supports up to 32 channels. Each channel
is unidirectional with a maximum message size of 8 words. I/O is
performed using register access (there is no DMA) and the cell
raises an interrupt when messages are received.
Mailbox Device Node:
====================
Required properties:
--------------------
- compatible: Shall be "hisilicon,hi6220-mbox"
- reg: Contains the mailbox register address range (base
address and length); the first item is for IPC
registers, the second item is shared buffer for
slots.
- #mbox-cells: Common mailbox binding property to identify the number
of cells required for the mailbox specifier. Must be 3.
<&phandle slot_id dst_irq ack_irq>
phandle: Label name of mailbox controller
slot_id: Slot id used either for TX or RX
dst_irq: IRQ identifier index number which used by MCU
ack_irq: IRQ identifier index number with generating a
TX/RX interrupt to application processor,
mailbox driver uses it to acknowledge interrupt
- interrupts: Contains the interrupt information for the mailbox
device. The format is dependent on which interrupt
controller the SoCs use.
Optional Properties:
--------------------
- hi6220,mbox-tx-noirq: Property of MCU firmware's feature, so mailbox driver
use this flag to ask MCU to enable "automatic idle
flag" mode or IRQ generated mode to acknowledge a TX
completion.
Example:
--------
mailbox: mailbox@f7510000 {
compatible = "hisilicon,hi6220-mbox";
reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */
<0x0 0x06dff800 0x0 0x0800>; /* Mailbox */
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <3>;
};
Mailbox client
===============
Required properties:
--------------------
- compatible: Many (See the client docs).
- mboxes: Standard property to specify a Mailbox (See ./mailbox.txt)
Cells must match 'mbox-cells' (See Mailbox Device Node above).
Optional Properties:
--------------------
- mbox-names: Name given to channels seen in the 'mboxes' property.
Example:
--------
stub_clock: stub_clock {
compatible = "hisilicon,hi6220-stub-clk";
hisilicon,hi6220-clk-sram = <&sram>;
#clock-cells = <1>;
mbox-names = "mbox-tx", "mbox-rx";
mboxes = <&mailbox 1 0 11>, <&mailbox 0 1 10>;
};

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* Generic Mailbox Controller and client driver bindings
Generic binding to provide a way for Mailbox controller drivers to
assign appropriate mailbox channel to client drivers.
* Mailbox Controller
Required property:
- #mbox-cells: Must be at least 1. Number of cells in a mailbox
specifier.
Example:
mailbox: mailbox {
...
#mbox-cells = <1>;
};
* Mailbox Client
Required property:
- mboxes: List of phandle and mailbox channel specifiers.
Optional property:
- mbox-names: List of identifier strings for each mailbox channel.
- shmem : List of phandle pointing to the shared memory(SHM) area between the
users of these mailboxes for IPC, one for each mailbox. This shared
memory can be part of any memory reserved for the purpose of this
communication between the mailbox client and the remote.
Example:
pwr_cntrl: power {
...
mbox-names = "pwr-ctrl", "rpc";
mboxes = <&mailbox 0 &mailbox 1>;
};
Example with shared memory(shmem):
sram: sram@50000000 {
compatible = "mmio-sram";
reg = <0x50000000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x50000000 0x10000>;
cl_shmem: shmem@0 {
compatible = "client-shmem";
reg = <0x0 0x200>;
};
};
client@2e000000 {
...
mboxes = <&mailbox 0>;
shmem = <&cl_shmem>;
..
};

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* rWTM BIU Mailbox driver for Armada 37xx
Required properties:
- compatible: must be "marvell,armada-3700-rwtm-mailbox"
- reg: physical base address of the mailbox and length of memory mapped
region
- interrupts: the IRQ line for the mailbox
- #mbox-cells: must be 1
Example:
rwtm: mailbox@b0000 {
compatible = "marvell,armada-3700-rwtm-mailbox";
reg = <0xb0000 0x100>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mailbox/mediatek,gce-mailbox.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek Global Command Engine Mailbox
maintainers:
- Houlong Wei <houlong.wei@mediatek.com>
description:
The Global Command Engine (GCE) is used to help read/write registers with
critical time limitation, such as updating display configuration during the
vblank. The GCE can be used to implement the Command Queue (CMDQ) driver.
properties:
compatible:
enum:
- mediatek,mt6779-gce
- mediatek,mt8173-gce
- mediatek,mt8183-gce
- mediatek,mt8186-gce
- mediatek,mt8192-gce
- mediatek,mt8195-gce
"#mbox-cells":
const: 2
description:
The first cell describes the Thread ID of the GCE,
the second cell describes the priority of the GCE thread
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: Global Command Engine clock
clock-names:
items:
- const: gce
required:
- compatible
- "#mbox-cells"
- reg
- interrupts
- clocks
allOf:
- if:
not:
properties:
compatible:
contains:
const: mediatek,mt8195-gce
then:
required:
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
gce: mailbox@10212000 {
compatible = "mediatek,mt8173-gce";
reg = <0 0x10212000 0 0x1000>;
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
#mbox-cells = <2>;
clocks = <&infracfg CLK_INFRA_GCE>;
clock-names = "gce";
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mailbox/microchip,mpfs-mailbox.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) mailbox controller
maintainers:
- Conor Dooley <conor.dooley@microchip.com>
properties:
compatible:
const: microchip,mpfs-mailbox
reg:
oneOf:
- items:
- description: mailbox control & data registers
- description: mailbox interrupt registers
deprecated: true
- items:
- description: mailbox control registers
- description: mailbox interrupt registers
- description: mailbox data registers
interrupts:
maxItems: 1
"#mbox-cells":
const: 1
required:
- compatible
- reg
- interrupts
- "#mbox-cells"
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
mbox: mailbox@37020000 {
compatible = "microchip,mpfs-mailbox";
reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>,
<0x0 0x37020800 0x0 0x100>;
interrupt-parent = <&L1>;
interrupts = <96>;
#mbox-cells = <1>;
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mailbox/mtk,adsp-mbox.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek ADSP mailbox
maintainers:
- Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
description: |
The MTK ADSP mailbox Inter-Processor Communication (IPC) enables the SoC
to communicate with ADSP by passing messages through two mailbox channels.
The MTK ADSP mailbox IPC also provides the ability for one processor to
signal the other processor using interrupts.
properties:
compatible:
enum:
- mediatek,mt8195-adsp-mbox
- mediatek,mt8186-adsp-mbox
"#mbox-cells":
const: 0
reg:
maxItems: 1
interrupts:
maxItems: 1
required:
- compatible
- "#mbox-cells"
- reg
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
adsp_mailbox0:mailbox@10816000 {
compatible = "mediatek,mt8195-adsp-mbox";
#mbox-cells = <0>;
reg = <0x10816000 0x1000>;
interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mailbox/nvidia,tegra186-hsp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra Hardware Synchronization Primitives (HSP)
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
description: |
The HSP modules are used for the processors to share resources and
communicate together. It provides a set of hardware synchronization
primitives for interprocessor communication. So the interprocessor
communication (IPC) protocols can use hardware synchronization
primitives, when operating between two processors not in an SMP
relationship.
The features that HSP supported are shared mailboxes, shared
semaphores, arbitrated semaphores and doorbells.
The mbox specifier of the "mboxes" property in the client node should
contain two cells. The first cell determines the HSP type and the
second cell is used to identify the mailbox that the client is going
to use.
For shared mailboxes, the first cell composed of two fields:
- bits 15..8:
A bit mask of flags that further specifies the type of shared
mailbox to be used (based on the data size). If no flag is
specified then, 32-bit shared mailbox is used.
- bits 7..0:
Defines the type of the mailbox to be used. This field should be
TEGRA_HSP_MBOX_TYPE_SM for shared mailboxes.
For doorbells, the second cell specifies the index of the doorbell to
use.
For shared mailboxes, the second cell is composed of two fields:
- bits 31..24:
A bit mask of flags that further specify how the shared mailbox
will be used. Valid flags are:
- bit 31:
Defines the direction of the mailbox. If set, the mailbox
will be used as a producer (i.e. used to send data). If
cleared, the mailbox is the consumer of data sent by a
producer.
- bits 23..0:
The index of the shared mailbox to use. The number of available
mailboxes may vary by instance of the HSP block and SoC
generation.
The following file contains definitions that can be used to
construct mailbox specifiers:
<dt-bindings/mailbox/tegra186-hsp.h>
properties:
$nodename:
pattern: "^hsp@[0-9a-f]+$"
compatible:
oneOf:
- const: nvidia,tegra186-hsp
- const: nvidia,tegra194-hsp
- items:
- const: nvidia,tegra234-hsp
- const: nvidia,tegra194-hsp
reg:
maxItems: 1
interrupts:
minItems: 1
maxItems: 9
interrupt-names:
oneOf:
# shared interrupts are optional
- items:
- const: doorbell
- items:
- const: doorbell
- pattern: "^shared[0-7]$"
- pattern: "^shared[0-7]$"
- pattern: "^shared[0-7]$"
- pattern: "^shared[0-7]$"
- pattern: "^shared[0-7]$"
- pattern: "^shared[0-7]$"
- pattern: "^shared[0-7]$"
- pattern: "^shared[0-7]$"
- items:
- pattern: "^shared[0-7]$"
- pattern: "^shared[0-7]$"
- pattern: "^shared[0-7]$"
- pattern: "^shared[0-7]$"
"#mbox-cells":
const: 2
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/tegra186-hsp.h>
hsp_top0: hsp@3c00000 {
compatible = "nvidia,tegra186-hsp";
reg = <0x03c00000 0xa0000>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "doorbell";
#mbox-cells = <2>;
};
client {
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_CCPLEX>;
};

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mailbox/qcom,apcs-kpss-global.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Qualcomm APCS global block bindings
description:
This binding describes the APCS "global" block found in various Qualcomm
platforms.
maintainers:
- Jassi Brar <jassisinghbrar@gmail.com>
properties:
compatible:
oneOf:
- items:
- enum:
- qcom,ipq6018-apcs-apps-global
- qcom,ipq8074-apcs-apps-global
- qcom,msm8976-apcs-kpss-global
- qcom,msm8996-apcs-hmss-global
- qcom,msm8998-apcs-hmss-global
- qcom,qcm2290-apcs-hmss-global
- qcom,sc7180-apss-shared
- qcom,sc8180x-apss-shared
- qcom,sdm660-apcs-hmss-global
- qcom,sdm845-apss-shared
- qcom,sm6125-apcs-hmss-global
- qcom,sm6115-apcs-hmss-global
- qcom,sm8150-apss-shared
- items:
- enum:
- qcom,msm8916-apcs-kpss-global
- qcom,msm8939-apcs-kpss-global
- qcom,msm8953-apcs-kpss-global
- qcom,msm8994-apcs-kpss-global
- qcom,qcs404-apcs-apps-global
- const: syscon
reg:
maxItems: 1
clocks:
description: phandles to the parent clocks of the clock driver
minItems: 2
maxItems: 3
'#mbox-cells':
const: 1
'#clock-cells':
enum: [0, 1]
clock-names:
minItems: 2
maxItems: 3
required:
- compatible
- reg
- '#mbox-cells'
additionalProperties: false
allOf:
- if:
properties:
compatible:
enum:
- qcom,msm8916-apcs-kpss-global
- qcom,msm8994-apcs-kpss-global
- qcom,msm8996-apcs-hmss-global
- qcom,msm8998-apcs-hmss-global
- qcom,qcs404-apcs-apps-global
- qcom,sc7180-apss-shared
- qcom,sdm660-apcs-hmss-global
- qcom,sdm845-apss-shared
- qcom,sm6125-apcs-hmss-global
- qcom,sm8150-apss-shared
then:
properties:
clocks:
items:
- description: primary pll parent of the clock driver
- description: auxiliary parent
clock-names:
items:
- const: pll
- const: aux
- if:
properties:
compatible:
enum:
- qcom,sdx55-apcs-gcc
then:
properties:
clocks:
items:
- description: primary pll parent of the clock driver
- description: auxiliary parent
- description: reference clock
clock-names:
items:
- const: pll
- const: aux
- const: ref
- if:
properties:
compatible:
enum:
- qcom,ipq6018-apcs-apps-global
- qcom,ipq8074-apcs-apps-global
then:
properties:
clocks:
items:
- description: primary pll parent of the clock driver
- description: XO clock
clock-names:
items:
- const: pll
- const: xo
- if:
properties:
compatible:
enum:
- qcom,ipq6018-apcs-apps-global
- qcom,ipq8074-apcs-apps-global
then:
properties:
'#clock-cells':
const: 1
else:
properties:
'#clock-cells':
const: 0
examples:
# Example apcs with msm8996
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
apcs_glb: mailbox@9820000 {
compatible = "qcom,msm8996-apcs-hmss-global";
reg = <0x9820000 0x1000>;
#mbox-cells = <1>;
};
rpm-glink {
compatible = "qcom,glink-rpm";
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
mboxes = <&apcs_glb 0>;
mbox-names = "rpm_hlos";
};
# Example apcs with qcs404
- |
#define GCC_APSS_AHB_CLK_SRC 1
#define GCC_GPLL0_AO_OUT_MAIN 123
apcs: mailbox@b011000 {
compatible = "qcom,qcs404-apcs-apps-global", "syscon";
reg = <0x0b011000 0x1000>;
#mbox-cells = <1>;
clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>;
clock-names = "pll", "aux";
#clock-cells = <0>;
};

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# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mailbox/qcom-ipcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Inter-Processor Communication Controller
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
description:
The Inter-Processor Communication Controller (IPCC) is a centralized hardware
to route interrupts across various subsystems. It involves a three-level
addressing scheme called protocol, client and signal. For example, consider an
entity on the Application Processor Subsystem (APSS) that wants to listen to
Modem's interrupts via Shared Memory Point to Point (SMP2P) interface. In such
a case, the client would be Modem (client-id is 2) and the signal would be
SMP2P (signal-id is 2). The SMP2P itself falls under the Multiprocessor (MPROC)
protocol (protocol-id is 0). Refer include/dt-bindings/mailbox/qcom-ipcc.h
for the list of such IDs.
properties:
compatible:
items:
- enum:
- qcom,sm6350-ipcc
- qcom,sm6375-ipcc
- qcom,sm8250-ipcc
- qcom,sm8350-ipcc
- qcom,sm8450-ipcc
- qcom,sc7280-ipcc
- const: qcom,ipcc
reg:
maxItems: 1
interrupts:
maxItems: 1
interrupt-controller: true
"#interrupt-cells":
const: 3
description:
The first cell is the client-id, the second cell is the signal-id and the
third cell is the interrupt type.
"#mbox-cells":
const: 2
description:
The first cell is the client-id, and the second cell is the signal-id.
required:
- compatible
- reg
- interrupts
- interrupt-controller
- "#interrupt-cells"
- "#mbox-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
mailbox@408000 {
compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
reg = <0x408000 0x1000>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};

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Rockchip mailbox
The Rockchip mailbox is used by the Rockchip CPU cores to communicate
requests to MCU processor.
Refer to ./mailbox.txt for generic information about mailbox device-tree
bindings.
Required properties:
- compatible: should be one of the following.
- "rockchip,rk3368-mbox" for rk3368
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: The interrupt number to the cpu. The interrupt specifier format
depends on the interrupt controller.
- #mbox-cells: Common mailbox binding property to identify the number
of cells required for the mailbox specifier. Should be 1
Example:
--------
/* RK3368 */
mbox: mbox@ff6b0000 {
compatible = "rockchip,rk3368-mailbox";
reg = <0x0 0xff6b0000 0x0 0x1000>,
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
};

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mailbox/sprd-mailbox.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Spreadtrum mailbox controller bindings
maintainers:
- Orson Zhai <orsonzhai@gmail.com>
- Baolin Wang <baolin.wang7@gmail.com>
- Chunyan Zhang <zhang.lyra@gmail.com>
properties:
compatible:
enum:
- sprd,sc9860-mailbox
- sprd,sc9863a-mailbox
reg:
items:
- description: inbox registers' base address
- description: outbox registers' base address
interrupts:
minItems: 2
maxItems: 3
interrupt-names:
minItems: 2
items:
- const: inbox
- const: outbox
- const: supp-outbox
clocks:
maxItems: 1
clock-names:
items:
- const: enable
"#mbox-cells":
const: 1
required:
- compatible
- reg
- interrupts
- interrupt-names
- "#mbox-cells"
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
mailbox: mailbox@400a0000 {
compatible = "sprd,sc9860-mailbox";
reg = <0x400a0000 0x8000>, <0x400a8000 0x8000>;
#mbox-cells = <1>;
clock-names = "enable";
clocks = <&aon_gate 53>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "inbox", "outbox";
};
...

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mailbox/st,stm32-ipcc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: STMicroelectronics STM32 IPC controller bindings
description:
The IPCC block provides a non blocking signaling mechanism to post and
retrieve messages in an atomic way between two processors.
It provides the signaling for N bidirectionnal channels. The number of
channels (N) can be read from a dedicated register.
maintainers:
- Fabien Dessenne <fabien.dessenne@foss.st.com>
- Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
properties:
compatible:
const: st,stm32mp1-ipcc
reg:
maxItems: 1
clocks:
maxItems: 1
interrupts:
items:
- description: rx channel occupied
- description: tx channel free
interrupt-names:
items:
- const: rx
- const: tx
wakeup-source: true
"#mbox-cells":
const: 1
st,proc-id:
description: Processor id using the mailbox (0 or 1)
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
required:
- compatible
- reg
- st,proc-id
- clocks
- interrupt-names
- "#mbox-cells"
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
ipcc: mailbox@4c001000 {
compatible = "st,stm32mp1-ipcc";
#mbox-cells = <1>;
reg = <0x4c001000 0x400>;
st,proc-id = <0>;
interrupts-extended = <&exti 61 1>,
<&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "rx", "tx";
clocks = <&rcc_clk IPCC>;
wakeup-source;
};
...

51
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ST Microelectronics Mailbox Driver
Each ST Mailbox IP currently consists of 4 instances of 32 channels. Messages
are passed between Application and Remote processors using shared memory.
Controller
----------
Required properties:
- compatible : Should be "st,stih407-mailbox"
- reg : Offset and length of the device's register set
- mbox-name : Name of the mailbox
- #mbox-cells: : Must be 2
<&phandle instance channel direction>
phandle : Label name of controller
instance : Instance number
channel : Channel number
Optional properties
- interrupts : Contains the IRQ line for a Rx mailbox
Example:
mailbox0: mailbox@0 {
compatible = "st,stih407-mailbox";
reg = <0x08f00000 0x1000>;
interrupts = <GIC_SPI 1 IRQ_TYPE_NONE>;
#mbox-cells = <2>;
mbox-name = "a9";
};
Client
------
Required properties:
- compatible : Many (See the client docs)
- reg : Shared (between Application and Remote) memory address
- mboxes : Standard property to specify a Mailbox (See ./mailbox.txt)
Cells must match 'mbox-cells' (See Controller docs above)
Optional properties
- mbox-names : Name given to channels seen in the 'mboxes' property.
Example:
mailbox_test {
compatible = "mailbox-test";
reg = <0x[shared_memory_address], [shared_memory_size]>;
mboxes = <&mailbox2 0 1>, <&mailbox0 2 1>;
mbox-names = "tx", "rx";
};

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Texas Instruments' Message Manager Driver
========================================
The Texas Instruments' Message Manager is a mailbox controller that has
configurable queues selectable at SoC(System on Chip) integration. The Message
manager is broken up into queues in different address regions that are called
"proxies" - each instance is unidirectional and is instantiated at SoC
integration level to indicate receive or transmit path.
Message Manager Device Node:
===========================
Required properties:
--------------------
- compatible: Shall be: "ti,k2g-message-manager"
- reg-names queue_proxy_region - Map the queue proxy region.
queue_state_debug_region - Map the queue state debug
region.
- reg: Contains the register map per reg-names.
- #mbox-cells Shall be 2. Contains the queue ID and proxy ID in that
order referring to the transfer path.
- interrupt-names: Contains interrupt names matching the rx transfer path
for a given SoC. Receive interrupts shall be of the
format: "rx_<QID>".
For ti,k2g-message-manager, this shall contain:
"rx_005", "rx_057"
- interrupts: Contains the interrupt information corresponding to
interrupt-names property.
Example(K2G):
------------
msgmgr: msgmgr@2a00000 {
compatible = "ti,k2g-message-manager";
#mbox-cells = <2>;
reg-names = "queue_proxy_region", "queue_state_debug_region";
reg = <0x02a00000 0x400000>, <0x028c3400 0x400>;
interrupt-names = "rx_005", "rx_057";
interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
};
pmmc: pmmc {
[...]
mbox-names = "rx", "tx";
# RX queue ID is 5, proxy ID is 2
# TX queue ID is 0, proxy ID is 0
mboxes= <&msgmgr 5 2>,
<&msgmgr 0 0>;
[...]
};

299
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# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI OMAP2+ and K3 Mailbox devices
maintainers:
- Suman Anna <s-anna@ti.com>
description: |
The OMAP Mailbox hardware facilitates communication between different
processors using a queued mailbox interrupt mechanism. The IP block is
external to the various processor subsystems and is connected on an
interconnect bus. The communication is achieved through a set of registers
for message storage and interrupt configuration registers.
Each mailbox IP block/cluster has a certain number of h/w fifo queues and
output interrupt lines. An output interrupt line is routed to an interrupt
controller within a processor subsystem, and there can be more than one line
going to a specific processor's interrupt controller. The interrupt line
connections are fixed for an instance and are dictated by the IP integration
into the SoC (excluding the SoCs that have an Interrupt Crossbar or an
Interrupt Router IP). Each interrupt line is programmable through a set of
interrupt configuration registers, and have a rx and tx interrupt source per
h/w fifo. Communication between different processors is achieved through the
appropriate programming of the rx and tx interrupt sources on the appropriate
interrupt lines.
The number of h/w fifo queues and interrupt lines dictate the usable
registers. All the current OMAP SoCs except for the newest DRA7xx SoC has a
single IP instance. DRA7xx has multiple instances with different number of
h/w fifo queues and interrupt lines between different instances. The interrupt
lines can also be routed to different processor sub-systems on DRA7xx as they
are routed through the Crossbar, a kind of interrupt router/multiplexer. The
K3 AM65x, J721E and J7200 SoCs has each of these instances form a cluster and
combine multiple clusters into a single IP block present within the Main
NavSS. The interrupt lines from all these clusters are multiplexed and routed
to different processor subsystems over a limited number of common interrupt
output lines of an Interrupt Router. The AM64x SoCS also uses a single IP
block comprising of multiple clusters, but the number of clusters are
smaller, and the interrupt output lines are connected directly to various
processors.
Mailbox Controller Nodes
=========================
A Mailbox device node is used to represent a Mailbox IP instance/cluster
within a SoC. The sub-mailboxes (actual communication channels) are
represented as child nodes of this parent node.
Mailbox Users
==============
A device needing to communicate with a target processor device should specify
them using the common mailbox binding properties, "mboxes" and the optional
"mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt
for details). Each value of the mboxes property should contain a phandle to
the mailbox controller device node and an args specifier that will be the
phandle to the intended sub-mailbox child node to be used for communication.
The equivalent "mbox-names" property value can be used to give a name to the
communication channel to be used by the client user.
$defs:
omap-mbox-descriptor:
$ref: /schemas/types.yaml#/definitions/uint32-array
description:
The omap-mbox-descriptor is made of up of 3 cells and represents a single
uni-directional communication channel. A typical sub-mailbox device uses
two such channels - one for transmitting (Tx) and one for receiving (Rx).
items:
- description:
mailbox fifo id used either for transmitting on ti,mbox-tx channel or
for receiving on ti,mbox-rx channel (fifo_id). This is the hardware
fifo number within a mailbox cluster.
- description:
irq identifier index number to use from the parent's interrupts data.
Should be 0 for most of the cases, a positive index value is seen only
on mailboxes that have multiple interrupt lines connected to the MPU
processor (irq_id). This is an index number in the listed interrupts
property in the DT nodes.
- description:
mailbox user id for identifying the interrupt line associated with
generating a tx/rx fifo interrupt (usr_id). This is the hardware
user id number within a mailbox cluster.
omap-sub-mailbox:
type: object
description:
The omap-sub-mailbox is a child node within a Mailbox controller device
node and represents the actual communication channel used to send and
receive messages between the host processor and a remote processor. Each
child node should have a unique node name across all the different mailbox
device nodes.
properties:
ti,mbox-tx:
$ref: "#/$defs/omap-mbox-descriptor"
description: sub-mailbox descriptor property defining a Tx fifo.
ti,mbox-rx:
$ref: "#/$defs/omap-mbox-descriptor"
description: sub-mailbox descriptor property defining a Rx fifo.
ti,mbox-send-noirq:
type: boolean
description:
Quirk flag to allow the client user of this sub-mailbox to send
messages without triggering a Tx ready interrupt, and to control
the Tx ticker. Should be used only on sub-mailboxes used to
communicate with WkupM3 remote processor on AM33xx/AM43xx SoCs.
required:
- ti,mbox-tx
- ti,mbox-rx
properties:
compatible:
enum:
- ti,omap2-mailbox # for OMAP2420, OMAP2430 SoCs
- ti,omap3-mailbox # for OMAP3430, OMAP3630 SoCs
- ti,omap4-mailbox # for OMAP44xx, OMAP54xx, AM33xx, AM43xx and DRA7xx SoCs
- ti,am654-mailbox # for K3 AM65x, J721E and J7200 SoCs
- ti,am64-mailbox # for K3 AM64x SoCs
reg:
maxItems: 1
interrupts:
description:
Contains the interrupt information for the mailbox device. The format is
dependent on which interrupt controller the Mailbox device uses. The
number of interrupts listed will at most be the value specified in
ti,mbox-num-users property, but is usually limited by the number of
interrupts reaching the main processor. An interrupt-parent property
is required on SoCs where the interrupt lines are connected through a
Interrupt Router before reaching the main processor's GIC.
"#mbox-cells":
const: 1
description:
The specifier is a phandle to an omap-sub-mailbox device.
ti,mbox-num-users:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Number of targets (processor devices) that the mailbox device can
interrupt.
ti,mbox-num-fifos:
$ref: /schemas/types.yaml#/definitions/uint32
description: Number of h/w fifo queues within the mailbox IP block.
ti,hwmods:
$ref: /schemas/types.yaml#/definitions/string
deprecated: true
description:
Name of the hwmod associated with the mailbox. This should be defined
in the mailbox node only if the node is not defined as a child node of
a corresponding sysc interconnect node.
This property is only needed on some legacy OMAP SoCs which have not
yet been converted to the ti,sysc interconnect hierarachy, but is
otherwise considered obsolete.
patternProperties:
"^mbox-[a-z0-9-]+$":
$ref: "#/$defs/omap-sub-mailbox"
required:
- compatible
- reg
- interrupts
- "#mbox-cells"
- ti,mbox-num-users
- ti,mbox-num-fifos
allOf:
- if:
properties:
compatible:
enum:
- ti,am654-mailbox
- ti,am64-mailbox
then:
properties:
ti,mbox-num-users:
const: 4
ti,mbox-num-fifos:
const: 16
interrupts:
minItems: 1
maxItems: 4
- if:
properties:
compatible:
enum:
- ti,omap4-mailbox
then:
properties:
ti,mbox-num-users:
enum: [3, 4]
ti,mbox-num-fifos:
enum: [8, 12]
interrupts:
minItems: 1
maxItems: 4
- if:
properties:
compatible:
enum:
- ti,omap3-mailbox
then:
properties:
ti,mbox-num-users:
const: 2
ti,mbox-num-fifos:
const: 2
interrupts:
minItems: 1
maxItems: 1
- if:
properties:
compatible:
enum:
- ti,omap2-mailbox
then:
properties:
ti,mbox-num-users:
const: 4
ti,mbox-num-fifos:
const: 6
interrupts:
minItems: 1
maxItems: 2
additionalProperties: false
examples:
- |
/* OMAP4 */
#include <dt-bindings/interrupt-controller/arm-gic.h>
mailbox: mailbox@4a0f4000 {
compatible = "ti,omap4-mailbox";
reg = <0x4a0f4000 0x200>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
ti,mbox-num-users = <3>;
ti,mbox-num-fifos = <8>;
mbox_ipu: mbox-ipu {
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <1 0 0>;
};
mbox_dsp: mbox-dsp {
ti,mbox-tx = <3 0 0>;
ti,mbox-rx = <2 0 0>;
};
};
dsp {
mboxes = <&mailbox &mbox_dsp>;
};
- |
/* AM33xx */
mailbox1: mailbox@480c8000 {
compatible = "ti,omap4-mailbox";
reg = <0x480c8000 0x200>;
interrupts = <77>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <8>;
mbox_wkupm3: mbox-wkup-m3 {
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <0 0 3>;
ti,mbox-send-noirq;
};
};
- |
/* AM65x */
mailbox0_cluster0: mailbox@31f80000 {
compatible = "ti,am654-mailbox";
reg = <0x31f80000 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
interrupts = <436>;
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
ti,mbox-tx = <1 0 0>;
ti,mbox-rx = <0 0 0>;
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mailbox/ti,secure-proxy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments' Secure Proxy
maintainers:
- Nishanth Menon <nm@ti.com>
description: |
The Texas Instruments' secure proxy is a mailbox controller that has
configurable queues selectable at SoC(System on Chip) integration. The
Message manager is broken up into different address regions that are
called "threads" or "proxies" - each instance is unidirectional and is
instantiated at SoC integration level by system controller to indicate
receive or transmit path.
properties:
$nodename:
pattern: "^mailbox@[0-9a-f]+$"
compatible:
const: ti,am654-secure-proxy
"#mbox-cells":
const: 1
description:
Contains the secure proxy thread ID used for the specific transfer path.
reg-names:
items:
- const: target_data
- const: rt
- const: scfg
reg:
minItems: 3
interrupt-names:
minItems: 1
maxItems: 100
items:
pattern: "^rx_[0-9]{3}$"
description:
Contains the interrupt name information for the Rx interrupt path for
secure proxy thread in the form 'rx_<PID>'.
interrupts:
minItems: 1
maxItems: 100
description:
Contains the interrupt information for the Rx interrupt path for secure
proxy.
required:
- compatible
- reg-names
- reg
- interrupt-names
- interrupts
- "#mbox-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
secure_proxy: mailbox@32c00000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
reg = <0x32c00000 0x100000>,
<0x32400000 0x100000>,
<0x32800000 0x100000>;
interrupt-names = "rx_011";
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};

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The APM X-Gene SLIMpro mailbox is used to communicate messages between
the ARM64 processors and the Cortex M3 (dubbed SLIMpro). It uses a simple
interrupt based door bell mechanism and can exchange simple messages using the
internal registers.
There are total of 8 interrupts in this mailbox. Each used for an individual
door bell (or mailbox channel).
Required properties:
- compatible: Should be as "apm,xgene-slimpro-mbox".
- reg: Contains the mailbox register address range.
- interrupts: 8 interrupts must be from 0 to 7, interrupt 0 define the
the interrupt for mailbox channel 0 and interrupt 1 for
mailbox channel 1 and so likewise for the reminder.
- #mbox-cells: only one to specify the mailbox channel number.
Example:
Mailbox Node:
mailbox: mailbox@10540000 {
compatible = "apm,xgene-slimpro-mbox";
reg = <0x0 0x10540000 0x0 0xa000>;
#mbox-cells = <1>;
interrupts = <0x0 0x0 0x4>,
<0x0 0x1 0x4>,
<0x0 0x2 0x4>,
<0x0 0x3 0x4>,
<0x0 0x4 0x4>,
<0x0 0x5 0x4>,
<0x0 0x6 0x4>,
<0x0 0x7 0x4>,
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mailbox/xlnx,zynqmp-ipi-mailbox.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Xilinx IPI(Inter Processor Interrupt) mailbox controller
description: |
The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
agent owns registers used for notification and buffers for message.
+-------------------------------------+
| Xilinx ZynqMP IPI Controller |
+-------------------------------------+
+--------------------------------------------------+
TF-A | |
| |
| |
+--------------------------+ |
| |
| |
+--------------------------------------------------+
+------------------------------------------+
| +----------------+ +----------------+ |
Hardware | | IPI Agent | | IPI Buffers | |
| | Registers | | | |
| | | | | |
| +----------------+ +----------------+ |
| |
| Xilinx IPI Agent Block |
+------------------------------------------+
maintainers:
- Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
properties:
compatible:
const: xlnx,zynqmp-ipi-mailbox
method:
description: |
The method of calling the PM-API firmware layer.
Permitted values are.
- "smc" : SMC #0, following the SMCCC
- "hvc" : HVC #0, following the SMCCC
$ref: /schemas/types.yaml#/definitions/string
enum:
- smc
- hvc
default: smc
'#address-cells':
const: 2
'#size-cells':
const: 2
xlnx,ipi-id:
description: |
Remote Xilinx IPI agent ID of which the mailbox is connected to.
$ref: /schemas/types.yaml#/definitions/uint32
interrupts:
maxItems: 1
ranges: true
patternProperties:
'^mailbox@[0-9a-f]+$':
description: Internal ipi mailbox node
type: object # DT nodes are json objects
properties:
xlnx,ipi-id:
description:
Remote Xilinx IPI agent ID of which the mailbox is connected to.
$ref: /schemas/types.yaml#/definitions/uint32
'#mbox-cells':
const: 1
description:
It contains tx(0) or rx(1) channel IPI id number.
reg:
maxItems: 4
reg-names:
items:
- const: local_request_region
- const: local_response_region
- const: remote_request_region
- const: remote_response_region
required:
- reg
- reg-names
- "#mbox-cells"
additionalProperties: false
required:
- compatible
- interrupts
- '#address-cells'
- '#size-cells'
- xlnx,ipi-id
examples:
- |
#include<dt-bindings/interrupt-controller/arm-gic.h>
amba {
#address-cells = <0x2>;
#size-cells = <0x2>;
zynqmp-mailbox {
compatible = "xlnx,zynqmp-ipi-mailbox";
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
xlnx,ipi-id = <0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
mailbox: mailbox@ff9905c0 {
reg = <0x0 0xff9905c0 0x0 0x20>,
<0x0 0xff9905e0 0x0 0x20>,
<0x0 0xff990e80 0x0 0x20>,
<0x0 0xff990ea0 0x0 0x20>;
reg-names = "local_request_region",
"local_response_region",
"remote_request_region",
"remote_response_region";
#mbox-cells = <1>;
xlnx,ipi-id = <4>;
};
};
};
...