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dt-bindings: Add devicetree bindings

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Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").

Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
This commit is contained in:
Melody Olvera
2023-04-03 14:38:11 -07:00
parent c334acf377
commit 6f18ce8026
4878 changed files with 424312 additions and 0 deletions
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37
bindings/interrupt-controller/abilis,tb10x-ictl.txt Normal file
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TB10x Top Level Interrupt Controller
====================================
The Abilis TB10x SOC contains a custom interrupt controller. It performs
one-to-one mapping of external interrupt sources to CPU interrupts and
provides support for reconfigurable trigger modes.
Required properties
-------------------
- compatible: Should be "abilis,tb10x-ictl"
- reg: specifies physical base address and size of register range.
- interrupt-congroller: Identifies the node as an interrupt controller.
- #interrupt cells: Specifies the number of cells used to encode an interrupt
source connected to this controller. The value shall be 2.
- interrupts: Specifies the list of interrupt lines which are handled by
the interrupt controller in the parent controller's notation. Interrupts
are mapped one-to-one to parent interrupts.
Example
-------
intc: interrupt-controller { /* Parent interrupt controller */
interrupt-controller;
#interrupt-cells = <1>; /* For example below */
/* ... */
};
tb10x_ictl: pic@2000 { /* TB10x interrupt controller */
compatible = "abilis,tb10x-ictl";
reg = <0x2000 0x20>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29 30 31>;
};

65
bindings/interrupt-controller/actions,owl-sirq.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/actions,owl-sirq.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Actions Semi Owl SoCs SIRQ interrupt controller
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
description: |
This interrupt controller is found in the Actions Semi Owl SoCs (S500, S700
and S900) and provides support for handling up to 3 external interrupt lines.
properties:
compatible:
enum:
- actions,s500-sirq
- actions,s700-sirq
- actions,s900-sirq
reg:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
description:
The first cell is the input IRQ number, between 0 and 2, while the second
cell is the trigger type as defined in interrupt.txt in this directory.
'interrupts':
description: |
Contains the GIC SPI IRQs mapped to the external interrupt lines.
They shall be specified sequentially from output 0 to 2.
minItems: 3
maxItems: 3
required:
- compatible
- reg
- interrupt-controller
- '#interrupt-cells'
- 'interrupts'
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
sirq: interrupt-controller@b01b0200 {
compatible = "actions,s500-sirq";
reg = <0xb01b0200 0x4>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ0 */
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ1 */
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; /* SIRQ2 */
};
...

25
bindings/interrupt-controller/al,alpine-msix.txt Normal file
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Alpine MSIX controller
See arm,gic-v3.txt for SPI and MSI definitions.
Required properties:
- compatible: should be "al,alpine-msix"
- reg: physical base address and size of the registers
- interrupt-controller: identifies the node as an interrupt controller
- msi-controller: identifies the node as an PCI Message Signaled Interrupt
controller
- al,msi-base-spi: SPI base of the MSI frame
- al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0
Example:
msix: msix {
compatible = "al,alpine-msix";
reg = <0x0 0xfbe00000 0x0 0x100000>;
interrupt-parent = <&gic>;
interrupt-controller;
msi-controller;
al,msi-base-spi = <160>;
al,msi-num-spis = <160>;
};

47
bindings/interrupt-controller/allwinner,sun4i-a10-ic.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/allwinner,sun4i-a10-ic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 Interrupt Controller
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
"#interrupt-cells":
const: 1
compatible:
enum:
- allwinner,sun4i-a10-ic
- allwinner,suniv-f1c100s-ic
reg:
maxItems: 1
interrupt-controller: true
required:
- "#interrupt-cells"
- compatible
- reg
- interrupt-controller
additionalProperties: false
examples:
- |
intc: interrupt-controller@1c20400 {
compatible = "allwinner,sun4i-a10-ic";
reg = <0x01c20400 0x400>;
interrupt-controller;
#interrupt-cells = <1>;
};
...

67
bindings/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A31 NMI/Wakeup Interrupt Controller
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
"#interrupt-cells":
const: 3
description:
The first cell is GIC_SPI (0), the second cell is the IRQ number, and
the third cell is the trigger type as defined in interrupt.txt in this
directory.
compatible:
oneOf:
- const: allwinner,sun6i-a31-r-intc
- items:
- enum:
- allwinner,sun8i-a83t-r-intc
- allwinner,sun8i-h3-r-intc
- allwinner,sun50i-a64-r-intc
- const: allwinner,sun6i-a31-r-intc
- const: allwinner,sun50i-h6-r-intc
reg:
maxItems: 1
interrupts:
maxItems: 1
description:
The GIC interrupt labeled as "External NMI".
interrupt-controller: true
required:
- "#interrupt-cells"
- compatible
- reg
- interrupts
- interrupt-controller
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
r_intc: interrupt-controller@1f00c00 {
compatible = "allwinner,sun50i-a64-r-intc",
"allwinner,sun6i-a31-r-intc";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x01f00c00 0x400>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
...

64
bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A20 Non-Maskable Interrupt Controller
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
"#interrupt-cells":
const: 2
description:
The first cell is the IRQ number, the second cell the trigger
type as defined in interrupt.txt in this directory.
compatible:
oneOf:
- const: allwinner,sun6i-a31-sc-nmi
deprecated: true
- const: allwinner,sun7i-a20-sc-nmi
- items:
- const: allwinner,sun8i-v3s-nmi
- const: allwinner,sun9i-a80-nmi
- const: allwinner,sun9i-a80-nmi
- items:
- const: allwinner,sun50i-a100-nmi
- const: allwinner,sun9i-a80-nmi
reg:
maxItems: 1
interrupts:
maxItems: 1
interrupt-controller: true
required:
- "#interrupt-cells"
- compatible
- reg
- interrupts
- interrupt-controller
unevaluatedProperties: false
examples:
- |
interrupt-controller@1c00030 {
compatible = "allwinner,sun7i-a20-sc-nmi";
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x01c00030 0x0c>;
interrupt-parent = <&gic>;
interrupts = <0 0 4>;
};
...

27
bindings/interrupt-controller/amazon,al-fic.txt Normal file
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Amazon's Annapurna Labs Fabric Interrupt Controller
Required properties:
- compatible: should be "amazon,al-fic"
- reg: physical base address and size of the registers
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells : must be 2. Specifies the number of cells needed to encode
an interrupt source. Supported trigger types are low-to-high edge
triggered and active high level-sensitive.
- interrupts: describes which input line in the interrupt parent, this
fic's output is connected to. This field property depends on the parent's
binding
Please refer to interrupts.txt in this directory for details of the common
Interrupt Controllers bindings used by client devices.
Example:
amazon_fic: interrupt-controller@fd8a8500 {
compatible = "amazon,al-fic";
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0xfd8a8500 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 0x0 IRQ_TYPE_LEVEL_HIGH>;
};

38
bindings/interrupt-controller/amlogic,meson-gpio-intc.txt Normal file
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Amlogic meson GPIO interrupt controller
Meson SoCs contains an interrupt controller which is able to watch the SoC
pads and generate an interrupt on edge or level. The controller is essentially
a 256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge
or level and polarity. It does not expose all 256 mux inputs because the
documentation shows that the upper part is not mapped to any pad. The actual
number of interrupt exposed depends on the SoC.
Required properties:
- compatible : must have "amlogic,meson8-gpio-intc" and either
"amlogic,meson8-gpio-intc" for meson8 SoCs (S802) or
"amlogic,meson8b-gpio-intc" for meson8b SoCs (S805) or
"amlogic,meson-gxbb-gpio-intc" for GXBB SoCs (S905) or
"amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912)
"amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X)
"amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2)
"amlogic,meson-sm1-gpio-intc" for SM1 SoCs (S905D3, S905X3, S905Y3)
"amlogic,meson-a1-gpio-intc" for A1 SoCs (A113L)
"amlogic,meson-s4-gpio-intc" for S4 SoCs (S802X2, S905Y4, S805X2G, S905W2)
- reg : Specifies base physical address and size of the registers.
- interrupt-controller : Identifies the node as an interrupt controller.
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value must be 2.
- meson,channel-interrupts: Array with the 8 upstream hwirq numbers. These
are the hwirqs used on the parent interrupt controller.
Example:
gpio_interrupt: interrupt-controller@9880 {
compatible = "amlogic,meson-gxbb-gpio-intc",
"amlogic,meson-gpio-intc";
reg = <0x0 0x9880 0x0 0x10>;
interrupt-controller;
#interrupt-cells = <2>;
meson,channel-interrupts = <64 65 66 67 68 69 70 71>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Apple Interrupt Controller
maintainers:
- Hector Martin <marcan@marcan.st>
description: |
The Apple Interrupt Controller is a simple interrupt controller present on
Apple ARM SoC platforms, including various iPhone and iPad devices and the
"Apple Silicon" Macs.
It provides the following features:
- Level-triggered hardware IRQs wired to SoC blocks
- Single mask bit per IRQ
- Per-IRQ affinity setting
- Automatic masking on event delivery (auto-ack)
- Software triggering (ORed with hw line)
- 2 per-CPU IPIs (meant as "self" and "other", but they are interchangeable
if not symmetric)
- Automatic prioritization (single event/ack register per CPU, lower IRQs =
higher priority)
- Automatic masking on ack
- Default "this CPU" register view and explicit per-CPU views
This device also represents the FIQ interrupt sources on platforms using AIC,
which do not go through a discrete interrupt controller.
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
compatible:
items:
- const: apple,t8103-aic
- const: apple,aic
interrupt-controller: true
'#interrupt-cells':
const: 3
description: |
The 1st cell contains the interrupt type:
- 0: Hardware IRQ
- 1: FIQ
The 2nd cell contains the interrupt number.
- HW IRQs: interrupt number
- FIQs:
- 0: physical HV timer
- 1: virtual HV timer
- 2: physical guest timer
- 3: virtual guest timer
- 4: 'efficient' CPU PMU
- 5: 'performance' CPU PMU
The 3rd cell contains the interrupt flags. This is normally
IRQ_TYPE_LEVEL_HIGH (4).
reg:
description: |
Specifies base physical address and size of the AIC registers.
maxItems: 1
power-domains:
maxItems: 1
affinities:
type: object
additionalProperties: false
description:
FIQ affinity can be expressed as a single "affinities" node,
containing a set of sub-nodes, one per FIQ with a non-default
affinity.
patternProperties:
"^.+-affinity$":
type: object
additionalProperties: false
properties:
apple,fiq-index:
description:
The interrupt number specified as a FIQ, and for which
the affinity is not the default.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 5
cpus:
$ref: /schemas/types.yaml#/definitions/phandle-array
description:
Should be a list of phandles to CPU nodes (as described in
Documentation/devicetree/bindings/arm/cpus.yaml).
required:
- apple,fiq-index
- cpus
required:
- compatible
- '#interrupt-cells'
- interrupt-controller
- reg
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
aic: interrupt-controller@23b100000 {
compatible = "apple,t8103-aic", "apple,aic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x2 0x3b100000 0x0 0x8000>;
};
};

127
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Apple Interrupt Controller 2
maintainers:
- Hector Martin <marcan@marcan.st>
description: |
The Apple Interrupt Controller 2 is a simple interrupt controller present on
Apple ARM SoC platforms starting with t600x (M1 Pro and Max).
It provides the following features:
- Level-triggered hardware IRQs wired to SoC blocks
- Single mask bit per IRQ
- Automatic masking on event delivery (auto-ack)
- Software triggering (ORed with hw line)
- Automatic prioritization (single event/ack register per CPU, lower IRQs =
higher priority)
- Automatic masking on ack
- Support for multiple dies
This device also represents the FIQ interrupt sources on platforms using AIC,
which do not go through a discrete interrupt controller. It also handles
FIQ-based Fast IPIs.
properties:
compatible:
items:
- const: apple,t6000-aic
- const: apple,aic2
interrupt-controller: true
'#interrupt-cells':
const: 4
description: |
The 1st cell contains the interrupt type:
- 0: Hardware IRQ
- 1: FIQ
The 2nd cell contains the die ID.
The next cell contains the interrupt number.
- HW IRQs: interrupt number
- FIQs:
- 0: physical HV timer
- 1: virtual HV timer
- 2: physical guest timer
- 3: virtual guest timer
The last cell contains the interrupt flags. This is normally
IRQ_TYPE_LEVEL_HIGH (4).
reg:
items:
- description: Address and size of the main AIC2 registers.
- description: Address and size of the AIC2 Event register.
reg-names:
items:
- const: core
- const: event
power-domains:
maxItems: 1
affinities:
type: object
additionalProperties: false
description:
FIQ affinity can be expressed as a single "affinities" node,
containing a set of sub-nodes, one per FIQ with a non-default
affinity.
patternProperties:
"^.+-affinity$":
type: object
additionalProperties: false
properties:
apple,fiq-index:
description:
The interrupt number specified as a FIQ, and for which
the affinity is not the default.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 5
cpus:
$ref: /schemas/types.yaml#/definitions/phandle-array
description:
Should be a list of phandles to CPU nodes (as described in
Documentation/devicetree/bindings/arm/cpus.yaml).
required:
- apple,fiq-index
- cpus
required:
- compatible
- '#interrupt-cells'
- interrupt-controller
- reg
- reg-names
additionalProperties: false
allOf:
- $ref: /schemas/interrupt-controller.yaml#
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
aic: interrupt-controller@28e100000 {
compatible = "apple,t6000-aic", "apple,aic2";
#interrupt-cells = <4>;
interrupt-controller;
reg = <0x2 0x8e100000 0x0 0xc000>,
<0x2 0x8e10c000 0x0 0x4>;
reg-names = "core", "event";
};
};

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Generic Interrupt Controller, version 3
maintainers:
- Marc Zyngier <maz@kernel.org>
description: |
AArch64 SMP cores are often associated with a GICv3, providing Private
Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
Software Generated Interrupts (SGI), and Locality-specific Peripheral
Interrupts (LPI).
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
compatible:
oneOf:
- items:
- enum:
- qcom,msm8996-gic-v3
- const: arm,gic-v3
- const: arm,gic-v3
interrupt-controller: true
"#address-cells":
enum: [ 0, 1, 2 ]
"#size-cells":
enum: [ 1, 2 ]
ranges: true
"#interrupt-cells":
description: |
Specifies the number of cells needed to encode an interrupt source.
Must be a single cell with a value of at least 3.
If the system requires describing PPI affinity, then the value must
be at least 4.
The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
interrupts, 2 for interrupts in the Extended SPI range, 3 for the
Extended PPI range. Other values are reserved for future use.
The 2nd cell contains the interrupt number for the interrupt type.
SPI interrupts are in the range [0-987]. PPI interrupts are in the
range [0-15]. Extented SPI interrupts are in the range [0-1023].
Extended PPI interrupts are in the range [0-127].
The 3rd cell is the flags, encoded as follows:
bits[3:0] trigger type and level flags.
1 = edge triggered
4 = level triggered
The 4th cell is a phandle to a node describing a set of CPUs this
interrupt is affine to. The interrupt must be a PPI, and the node
pointed must be a subnode of the "ppi-partitions" subnode. For
interrupt types other than PPI or PPIs that are not partitionned,
this cell must be zero. See the "ppi-partitions" node description
below.
Cells 5 and beyond are reserved for future use and must have a value
of 0 if present.
enum: [ 3, 4 ]
reg:
description: |
Specifies base physical address(s) and size of the GIC
registers, in the following order:
- GIC Distributor interface (GICD)
- GIC Redistributors (GICR), one range per redistributor region
- GIC CPU interface (GICC)
- GIC Hypervisor interface (GICH)
- GIC Virtual CPU interface (GICV)
GICC, GICH and GICV are optional, but must be described if the CPUs
support them. Examples of such CPUs are ARM's implementations of the
ARMv8.0 architecture such as Cortex-A32, A34, A35, A53, A57, A72 and
A73 (this list is not exhaustive).
minItems: 2
maxItems: 4096 # Should be enough?
interrupts:
description:
Interrupt source of the VGIC maintenance interrupt.
maxItems: 1
redistributor-stride:
description:
If using padding pages, specifies the stride of consecutive
redistributors. Must be a multiple of 64kB.
$ref: /schemas/types.yaml#/definitions/uint64
multipleOf: 0x10000
exclusiveMinimum: 0
"#redistributor-regions":
description:
The number of independent contiguous regions occupied by the
redistributors. Required if more than one such region is present.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 4096
msi-controller:
description:
Only present if the Message Based Interrupt functionnality is
being exposed by the HW, and the mbi-ranges property present.
mbi-ranges:
description:
A list of pairs <intid span>, where "intid" is the first SPI of a range
that can be used an MBI, and "span" the size of that range. Multiple
ranges can be provided.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
items:
minItems: 2
maxItems: 2
mbi-alias:
description:
Address property. Base address of an alias of the GICD region containing
only the {SET,CLR}SPI registers to be used if isolation is required,
and if supported by the HW.
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
minItems: 1
maxItems: 2
ppi-partitions:
type: object
description:
PPI affinity can be expressed as a single "ppi-partitions" node,
containing a set of sub-nodes.
patternProperties:
"^interrupt-partition-[0-9]+$":
type: object
properties:
affinity:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
maxItems: 1
description:
Should be a list of phandles to CPU nodes (as described in
Documentation/devicetree/bindings/arm/cpus.yaml).
required:
- affinity
clocks:
maxItems: 1
clock-names:
items:
- const: aclk
power-domains:
maxItems: 1
resets:
maxItems: 1
dependencies:
mbi-ranges: [ msi-controller ]
msi-controller: [ mbi-ranges ]
required:
- compatible
- reg
patternProperties:
"^gic-its@": false
"^interrupt-controller@[0-9a-f]+$": false
# msi-controller is preferred, but allow other names
"^(msi-controller|gic-its|interrupt-controller)@[0-9a-f]+$":
type: object
description:
GICv3 has one or more Interrupt Translation Services (ITS) that are
used to route Message Signalled Interrupts (MSI) to the CPUs.
properties:
compatible:
const: arm,gic-v3-its
msi-controller: true
"#msi-cells":
description:
The single msi-cell is the DeviceID of the device which will generate
the MSI.
const: 1
reg:
description:
Specifies the base physical address and size of the ITS registers.
maxItems: 1
socionext,synquacer-pre-its:
description:
(u32, u32) tuple describing the untranslated
address and size of the pre-ITS window.
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
minItems: 2
maxItems: 2
required:
- compatible
- msi-controller
- "#msi-cells"
- reg
additionalProperties: false
additionalProperties: false
examples:
- |
gic: interrupt-controller@2cf00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupt-controller;
reg = <0x2f000000 0x10000>, // GICD
<0x2f100000 0x200000>, // GICR
<0x2c000000 0x2000>, // GICC
<0x2c010000 0x2000>, // GICH
<0x2c020000 0x2000>; // GICV
interrupts = <1 9 4>;
msi-controller;
mbi-ranges = <256 128>;
msi-controller@2c200000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x2c200000 0x20000>;
};
};
- |
interrupt-controller@2c010000 {
compatible = "arm,gic-v3";
#interrupt-cells = <4>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupt-controller;
redistributor-stride = <0x0 0x40000>; // 256kB stride
#redistributor-regions = <2>;
reg = <0x2c010000 0x10000>, // GICD
<0x2d000000 0x800000>, // GICR 1: CPUs 0-31
<0x2e000000 0x800000>, // GICR 2: CPUs 32-63
<0x2c040000 0x2000>, // GICC
<0x2c060000 0x2000>, // GICH
<0x2c080000 0x2000>; // GICV
interrupts = <1 9 4 0>;
msi-controller@2c200000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x2c200000 0x20000>;
};
msi-controller@2c400000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x2c400000 0x20000>;
};
ppi-partitions {
part0: interrupt-partition-0 {
affinity = <&cpu0>, <&cpu2>;
};
part1: interrupt-partition-1 {
affinity = <&cpu1>, <&cpu3>;
};
};
};
device@0 {
reg = <0 4>;
interrupts = <1 1 4 &part0>;
};
...

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Generic Interrupt Controller v1 and v2
maintainers:
- Marc Zyngier <marc.zyngier@arm.com>
description: |+
ARM SMP cores are often associated with a GIC, providing per processor
interrupts (PPI), shared processor interrupts (SPI) and software
generated interrupts (SGI).
Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
Secondary GICs are cascaded into the upward interrupt controller and do not
have PPIs or SGIs.
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
compatible:
oneOf:
- items:
- enum:
- arm,arm11mp-gic
- arm,cortex-a15-gic
- arm,cortex-a7-gic
- arm,cortex-a5-gic
- arm,cortex-a9-gic
- arm,eb11mp-gic
- arm,gic-400
- arm,pl390
- arm,tc11mp-gic
- qcom,msm-8660-qgic
- qcom,msm-qgic2
- items:
- const: arm,gic-400
- enum:
- arm,cortex-a15-gic
- arm,cortex-a7-gic
- items:
- const: arm,arm1176jzf-devchip-gic
- const: arm,arm11mp-gic
- items:
- const: brcm,brahma-b15-gic
- const: arm,cortex-a15-gic
- oneOf:
- const: nvidia,tegra210-agic
- items:
- enum:
- nvidia,tegra186-agic
- nvidia,tegra194-agic
- nvidia,tegra234-agic
- const: nvidia,tegra210-agic
interrupt-controller: true
"#address-cells":
enum: [ 0, 1, 2 ]
"#size-cells":
enum: [ 1, 2 ]
"#interrupt-cells":
const: 3
description: |
The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
interrupts.
The 2nd cell contains the interrupt number for the interrupt type.
SPI interrupts are in the range [0-987]. PPI interrupts are in the
range [0-15].
The 3rd cell is the flags, encoded as follows:
bits[3:0] trigger type and level flags.
1 = low-to-high edge triggered
2 = high-to-low edge triggered (invalid for SPIs)
4 = active high level-sensitive
8 = active low level-sensitive (invalid for SPIs).
bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of
the 8 possible cpus attached to the GIC. A bit set to '1' indicated
the interrupt is wired to that CPU. Only valid for PPI interrupts.
Also note that the configurability of PPI interrupts is IMPLEMENTATION
DEFINED and as such not guaranteed to be present (most SoC available
in 2014 seem to ignore the setting of this flag and use the hardware
default value).
reg:
description: |
Specifies base physical address(s) and size of the GIC registers. The
first region is the GIC distributor register base and size. The 2nd region
is the GIC cpu interface register base and size.
For GICv2 with virtualization extensions, additional regions are
required for specifying the base physical address and size of the VGIC
registers. The first additional region is the GIC virtual interface
control register base and size. The 2nd additional region is the GIC
virtual cpu interface register base and size.
minItems: 2
maxItems: 4
ranges: true
interrupts:
description: Interrupt source of the parent interrupt controller on
secondary GICs, or VGIC maintenance interrupt on primary GIC (see
below).
maxItems: 1
cpu-offset:
description: per-cpu offset within the distributor and cpu interface
regions, used when the GIC doesn't have banked registers. The offset
is cpu-offset * cpu-nr.
$ref: /schemas/types.yaml#/definitions/uint32
clocks:
minItems: 1
maxItems: 2
clock-names:
description: List of names for the GIC clock input(s). Valid clock names
depend on the GIC variant.
oneOf:
- const: ic_clk # for "arm,arm11mp-gic"
- const: PERIPHCLKEN # for "arm,cortex-a15-gic"
- items: # for "arm,cortex-a9-gic"
- const: PERIPHCLK
- const: PERIPHCLKEN
- const: clk # for "arm,gic-400" and "nvidia,tegra210"
- const: gclk #for "arm,pl390"
power-domains:
maxItems: 1
resets:
maxItems: 1
required:
- compatible
- reg
patternProperties:
"^v2m@[0-9a-f]+$":
type: object
description: |
* GICv2m extension for MSI/MSI-x support (Optional)
Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).
This is enabled by specifying v2m sub-node(s).
properties:
compatible:
const: arm,gic-v2m-frame
msi-controller: true
reg:
maxItems: 1
description: GICv2m MSI interface register base and size
arm,msi-base-spi:
description: When the MSI_TYPER register contains an incorrect value,
this property should contain the SPI base of the MSI frame, overriding
the HW value.
$ref: /schemas/types.yaml#/definitions/uint32
arm,msi-num-spis:
description: When the MSI_TYPER register contains an incorrect value,
this property should contain the number of SPIs assigned to the
frame, overriding the HW value.
$ref: /schemas/types.yaml#/definitions/uint32
required:
- compatible
- msi-controller
- reg
additionalProperties: false
additionalProperties: false
examples:
- |
// GICv1
intc: interrupt-controller@fff11000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <1>;
interrupt-controller;
reg = <0xfff11000 0x1000>,
<0xfff10100 0x100>;
};
- |
// GICv2
interrupt-controller@2c001000 {
compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x2c001000 0x1000>,
<0x2c002000 0x2000>,
<0x2c004000 0x2000>,
<0x2c006000 0x2000>;
interrupts = <1 9 0xf04>;
};
- |
// GICv2m extension for MSI/MSI-x support
interrupt-controller@e1101000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
interrupts = <1 8 0xf04>;
ranges = <0 0xe1100000 0x100000>;
reg = <0xe1110000 0x01000>,
<0xe112f000 0x02000>,
<0xe1140000 0x10000>,
<0xe1160000 0x10000>;
v2m0: v2m@80000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x80000 0x1000>;
};
//...
v2mN: v2m@90000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x90000 0x1000>;
};
};
...

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* ARM Nested Vector Interrupt Controller (NVIC)
The NVIC provides an interrupt controller that is tightly coupled to
Cortex-M based processor cores. The NVIC implemented on different SoCs
vary in the number of interrupts and priority bits per interrupt.
Main node required properties:
- compatible : should be one of:
"arm,v6m-nvic"
"arm,v7m-nvic"
"arm,v8m-nvic"
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The type shall be a <u32> and the value shall be 2.
The 1st cell contains the interrupt number for the interrupt type.
The 2nd cell is the priority of the interrupt.
- reg : Specifies base physical address(s) and size of the NVIC registers.
This is at a fixed address (0xe000e100) and size (0xc00).
- arm,num-irq-priority-bits: The number of priority bits implemented by the
given SoC
Example:
intc: interrupt-controller@e000e100 {
compatible = "arm,v7m-nvic";
#interrupt-cells = <2>;
#address-cells = <1>;
interrupt-controller;
reg = <0xe000e100 0xc00>;
arm,num-irq-priority-bits = <4>;
};

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* ARM Versatile FPGA interrupt controller
One or more FPGA IRQ controllers can be synthesized in an ARM reference board
such as the Integrator or Versatile family. The output of these different
controllers are OR:ed together and fed to the CPU tile's IRQ input. Each
instance can handle up to 32 interrupts.
Required properties:
- compatible: "arm,versatile-fpga-irq" or "oxsemi,ox810se-rps-irq"
- interrupt-controller: Identifies the node as an interrupt controller
- #interrupt-cells: The number of cells to define the interrupts. Must be 1
as the FPGA IRQ controller has no configuration options for interrupt
sources. The cell is a u32 and defines the interrupt number.
- reg: The register bank for the FPGA interrupt controller.
- clear-mask: a u32 number representing the mask written to clear all IRQs
on the controller at boot for example.
- valid-mask: a u32 number representing a bit mask determining which of
the interrupts are valid. Unconnected/unused lines are set to 0, and
the system till not make it possible for devices to request these
interrupts.
Example:
pic: pic@14000000 {
compatible = "arm,versatile-fpga-irq";
#interrupt-cells = <1>;
interrupt-controller;
reg = <0x14000000 0x100>;
clear-mask = <0xffffffff>;
valid-mask = <0x003fffff>;
};
Optional properties:
- interrupts: if the FPGA IRQ controller is cascaded, i.e. if its IRQ
output is simply connected to the input of another IRQ controller,
then the parent IRQ shall be specified in this property.

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/arm,vic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Vectored Interrupt Controller
maintainers:
- Rob Herring <robh@kernel.org>
description: |+
One or more Vectored Interrupt Controllers (VIC's) can be connected in an
ARM system for interrupt routing. For multiple controllers they can either
be nested or have the outputs wire-OR'd together.
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
compatible:
enum:
- arm,pl190-vic
- arm,pl192-vic
- arm,versatile-vic
interrupt-controller: true
"#interrupt-cells":
const: 1
description:
The number of cells to define the interrupts. It must be 1 as the
VIC has no configuration options for interrupt sources. The single
cell defines the interrupt number.
reg:
maxItems: 1
interrupts:
maxItems: 1
valid-mask:
description:
A one cell big bit mask of valid interrupt sources. Each bit
represents single interrupt source, starting from source 0 at
LSb and ending at source 31 at MSb. A bit that is set means
that the source is wired and clear means otherwise. If unspecified,
defaults to all valid.
$ref: /schemas/types.yaml#/definitions/uint32
valid-wakeup-mask:
description:
A one cell big bit mask of interrupt sources that can be configured
as wake up source for the system. Order of bits is the same as for
valid-mask property. A set bit means that this interrupt source
can be configured as a wake up source for the system. If unspecied,
defaults to all interrupt sources configurable as wake up sources.
$ref: /schemas/types.yaml#/definitions/uint32
required:
- compatible
- reg
- interrupt-controller
- "#interrupt-cells"
additionalProperties: false
examples:
- |
// PL192 VIC
vic0: interrupt-controller@60000 {
compatible = "arm,pl192-vic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x60000 0x1000>;
valid-mask = <0xffffff7f>;
valid-wakeup-mask = <0x0000ff7f>;
};
...

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Device tree configuration for the I2C Interrupt Controller on the AST24XX and
AST25XX SoCs.
Required Properties:
- #address-cells : should be 1
- #size-cells : should be 1
- #interrupt-cells : should be 1
- compatible : should be "aspeed,ast2400-i2c-ic"
or "aspeed,ast2500-i2c-ic"
- reg : address start and range of controller
- interrupts : interrupt number
- interrupt-controller : denotes that the controller receives and fires
new interrupts for child busses
Example:
i2c_ic: interrupt-controller@0 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <1>;
compatible = "aspeed,ast2400-i2c-ic";
reg = <0x0 0x40>;
interrupts = <12>;
interrupt-controller;
};

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Aspeed Vectored Interrupt Controller
These bindings are for the Aspeed interrupt controller. The AST2400 and
AST2500 SoC families include a legacy register layout before a re-designed
layout, but the bindings do not prescribe the use of one or the other.
Required properties:
- compatible : "aspeed,ast2400-vic"
"aspeed,ast2500-vic"
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value shall be 1.
Example:
vic: interrupt-controller@1e6c0080 {
compatible = "aspeed,ast2400-vic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x1e6c0080 0x80>;
};

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Aspeed AST25XX and AST26XX SCU Interrupt Controller
Required Properties:
- #interrupt-cells : must be 1
- compatible : must be "aspeed,ast2500-scu-ic",
"aspeed,ast2600-scu-ic0" or
"aspeed,ast2600-scu-ic1"
- interrupts : interrupt from the parent controller
- interrupt-controller : indicates that the controller receives and
fires new interrupts for child busses
Example:
syscon@1e6e2000 {
ranges = <0 0x1e6e2000 0x1a8>;
scu_ic: interrupt-controller@18 {
#interrupt-cells = <1>;
compatible = "aspeed,ast2500-scu-ic";
interrupts = <21>;
interrupt-controller;
};
};

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* Advanced Interrupt Controller (AIC)
Required properties:
- compatible: Should be:
- "atmel,<chip>-aic" where <chip> can be "at91rm9200", "sama5d2",
"sama5d3" or "sama5d4"
- "microchip,<chip>-aic" where <chip> can be "sam9x60"
- interrupt-controller: Identifies the node as an interrupt controller.
- #interrupt-cells: The number of cells to define the interrupts. It should be 3.
The first cell is the IRQ number (aka "Peripheral IDentifier" on datasheet).
The second cell is used to specify flags:
bits[3:0] trigger type and level flags:
1 = low-to-high edge triggered.
2 = high-to-low edge triggered.
4 = active high level-sensitive.
8 = active low level-sensitive.
Valid combinations are 1, 2, 3, 4, 8.
Default flag for internal sources should be set to 4 (active high).
The third cell is used to specify the irq priority from 0 (lowest) to 7
(highest).
- reg: Should contain AIC registers location and length
- atmel,external-irqs: u32 array of external irqs.
Examples:
/*
* AIC
*/
aic: interrupt-controller@fffff000 {
compatible = "atmel,at91rm9200-aic";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0xfffff000 0x200>;
};
/*
* An interrupt generating device that is wired to an AIC.
*/
dma: dma-controller@ffffec00 {
compatible = "atmel,at91sam9g45-dma";
reg = <0xffffec00 0x200>;
interrupts = <21 4 5>;
};

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BCM2835 Top-Level ("ARMCTRL") Interrupt Controller
The BCM2835 contains a custom top-level interrupt controller, which supports
72 interrupt sources using a 2-level register scheme. The interrupt
controller, or the HW block containing it, is referred to occasionally
as "armctrl" in the SoC documentation, hence naming of this binding.
The BCM2836 contains the same interrupt controller with the same
interrupts, but the per-CPU interrupt controller is the root, and an
interrupt there indicates that the ARMCTRL has an interrupt to handle.
Required properties:
- compatible : should be "brcm,bcm2835-armctrl-ic" or
"brcm,bcm2836-armctrl-ic"
- reg : Specifies base physical address and size of the registers.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value shall be 2.
The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic
pending" register, or 1/2 respectively for interrupts in the "IRQ pending
1/2" register.
The 2nd cell contains the interrupt number within the bank. Valid values
are 0..7 for bank 0, and 0..31 for bank 1.
Additional required properties for brcm,bcm2836-armctrl-ic:
- interrupts : Specifies the interrupt on the parent for this interrupt
controller to handle.
The interrupt sources are as follows:
Bank 0:
0: ARM_TIMER
1: ARM_MAILBOX
2: ARM_DOORBELL_0
3: ARM_DOORBELL_1
4: VPU0_HALTED
5: VPU1_HALTED
6: ILLEGAL_TYPE0
7: ILLEGAL_TYPE1
Bank 1:
0: TIMER0
1: TIMER1
2: TIMER2
3: TIMER3
4: CODEC0
5: CODEC1
6: CODEC2
7: VC_JPEG
8: ISP
9: VC_USB
10: VC_3D
11: TRANSPOSER
12: MULTICORESYNC0
13: MULTICORESYNC1
14: MULTICORESYNC2
15: MULTICORESYNC3
16: DMA0
17: DMA1
18: VC_DMA2
19: VC_DMA3
20: DMA4
21: DMA5
22: DMA6
23: DMA7
24: DMA8
25: DMA9
26: DMA10
27: DMA11-14 - shared interrupt for DMA 11 to 14
28: DMAALL - triggers on all dma interrupts (including chanel 15)
29: AUX
30: ARM
31: VPUDMA
Bank 2:
0: HOSTPORT
1: VIDEOSCALER
2: CCP2TX
3: SDC
4: DSI0
5: AVE
6: CAM0
7: CAM1
8: HDMI0
9: HDMI1
10: PIXELVALVE1
11: I2CSPISLV
12: DSI1
13: PWA0
14: PWA1
15: CPR
16: SMI
17: GPIO0
18: GPIO1
19: GPIO2
20: GPIO3
21: VC_I2C
22: VC_SPI
23: VC_I2SPCM
24: VC_SDIO
25: VC_UART
26: SLIMBUS
27: VEC
28: CPG
29: RNG
30: VC_ARASANSDIO
31: AVSPMON
Example:
/* BCM2835, first level */
intc: interrupt-controller {
compatible = "brcm,bcm2835-armctrl-ic";
reg = <0x7e00b200 0x200>;
interrupt-controller;
#interrupt-cells = <2>;
};
/* BCM2836, second level */
intc: interrupt-controller {
compatible = "brcm,bcm2836-armctrl-ic";
reg = <0x7e00b200 0x200>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&local_intc>;
interrupts = <8>;
};

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BCM2836 per-CPU interrupt controller
The BCM2836 has a per-cpu interrupt controller for the timer, PMU
events, and SMP IPIs. One of the CPUs may receive interrupts for the
peripheral (GPU) events, which chain to the BCM2835-style interrupt
controller.
Required properties:
- compatible: Should be "brcm,bcm2836-l1-intc"
- reg: Specifies base physical address and size of the
registers
- interrupt-controller: Identifies the node as an interrupt controller
- #interrupt-cells: Specifies the number of cells needed to encode an
interrupt source. The value shall be 2
Please refer to interrupts.txt in this directory for details of the common
Interrupt Controllers bindings used by client devices.
The interrupt sources are as follows:
0: CNTPSIRQ
1: CNTPNSIRQ
2: CNTHPIRQ
3: CNTVIRQ
8: GPU_FAST
9: PMU_FAST
Example:
local_intc: local_intc {
compatible = "brcm,bcm2836-l1-intc";
reg = <0x40000000 0x100>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&local_intc>;
};

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Broadcom BCM6345-style Level 1 interrupt controller
This block is a first level interrupt controller that is typically connected
directly to one of the HW INT lines on each CPU.
Key elements of the hardware design include:
- 32, 64 or 128 incoming level IRQ lines
- Most onchip peripherals are wired directly to an L1 input
- A separate instance of the register set for each CPU, allowing individual
peripheral IRQs to be routed to any CPU
- Contains one or more enable/status word pairs per CPU
- No atomic set/clear operations
- No polarity/level/edge settings
- No FIFO or priority encoder logic; software is expected to read all
2-4 status words to determine which IRQs are pending
Required properties:
- compatible: should be "brcm,bcm<soc>-l1-intc", "brcm,bcm6345-l1-intc"
- reg: specifies the base physical address and size of the registers;
the number of supported IRQs is inferred from the size argument
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
source, should be 1.
- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
node; valid values depend on the type of parent interrupt controller
If multiple reg ranges and interrupt-parent entries are present on an SMP
system, the driver will allow IRQ SMP affinity to be set up through the
/proc/irq/ interface. In the simplest possible configuration, only one
reg range and one interrupt-parent is needed.
The driver operates in native CPU endian by default, there is no support for
specifying an alternative endianness.
Example:
periph_intc: interrupt-controller@10000000 {
compatible = "brcm,bcm63168-l1-intc", "brcm,bcm6345-l1-intc";
reg = <0x10000020 0x20>,
<0x10000040 0x20>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&cpu_intc>;
interrupts = <2>, <3>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7038-l1-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM7038-style Level 1 interrupt controller
description: >
This block is a first level interrupt controller that is typically connected
directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip
since BCM7038 has contained this hardware.
Key elements of the hardware design include:
- 64, 96, 128, or 160 incoming level IRQ lines
- Most onchip peripherals are wired directly to an L1 input
- A separate instance of the register set for each CPU, allowing individual
peripheral IRQs to be routed to any CPU
- Atomic mask/unmask operations
- No polarity/level/edge settings
- No FIFO or priority encoder logic; software is expected to read all
2-5 status words to determine which IRQs are pending
If multiple reg ranges and interrupt-parent entries are present on an SMP
system, the driver will allow IRQ SMP affinity to be set up through the
/proc/irq/ interface. In the simplest possible configuration, only one
reg range and one interrupt-parent is needed.
maintainers:
- Florian Fainelli <f.fainelli@gmail.com>
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
compatible:
const: brcm,bcm7038-l1-intc
reg:
description: >
Specifies the base physical address and size of the registers
the number of supported IRQs is inferred from the size argument
interrupt-controller: true
"#interrupt-cells":
const: 1
interrupts:
description: >
Specifies the interrupt line(s) in the interrupt-parent controller node;
valid values depend on the type of parent interrupt controller
brcm,irq-can-wake:
type: boolean
description: >
If present, this means the L1 controller can be used as a
wakeup source for system suspend/resume.
brcm,int-fwd-mask:
$ref: /schemas/types.yaml#/definitions/uint32-array
description:
If present, a bit mask to indicate which interrupts have already been
configured by the firmware and should be left unmanaged. This should
have one 32-bit word per status/set/clear/mask group.
required:
- compatible
- reg
- interrupt-controller
- "#interrupt-cells"
- interrupts
additionalProperties: false
examples:
- |
periph_intc: interrupt-controller@1041a400 {
compatible = "brcm,bcm7038-l1-intc";
reg = <0x1041a400 0x30>, <0x1041a600 0x30>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&cpu_intc>;
interrupts = <2>, <3>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM7120-style Level 2 and Broadcom BCM3380 Level 1 / Level 2
maintainers:
- Florian Fainelli <f.fainelli@gmail.com>
description: >
This interrupt controller hardware is a second level interrupt controller that
is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
platforms. It can be found on BCM7xxx products starting with BCM7120.
Such an interrupt controller has the following hardware design:
- outputs multiple interrupts signals towards its interrupt controller parent
- controls how some of the interrupts will be flowing, whether they will
directly output an interrupt signal towards the interrupt controller parent,
or if they will output an interrupt signal at this 2nd level interrupt
controller, in particular for UARTs
- has one 32-bit enable word and one 32-bit status word
- no atomic set/clear operations
- not all bits within the interrupt controller actually map to an interrupt
The typical hardware layout for this controller is represented below:
2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
0 -----[ MUX ] ------------|==========> GIC interrupt 75
\-----------\
|
1 -----[ MUX ] --------)---|==========> GIC interrupt 76
\------------|
|
2 -----[ MUX ] --------)---|==========> GIC interrupt 77
\------------|
|
3 ---------------------|
4 ---------------------|
5 ---------------------|
7 ---------------------|---|===========> GIC interrupt 66
9 ---------------------|
10 --------------------|
11 --------------------/
6 ------------------------\
|===========> GIC interrupt 64
8 ------------------------/
12 ........................ X
13 ........................ X (not connected)
..
31 ........................ X
The BCM3380 Level 1 / Level 2 interrrupt controller shows up in various forms
on many BCM338x/BCM63xx chipsets. It has the following properties:
- outputs a single interrupt signal to its interrupt controller parent
- contains one or more enable/status word pairs, which often appear at
different offsets in different blocks
- no atomic set/clear operations
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
compatible:
items:
- enum:
- brcm,bcm7120-l2-intc
- brcm,bcm3380-l2-intc
reg:
minItems: 1
maxItems: 4
description: >
Specifies the base physical address and size of the registers
interrupt-controller: true
"#interrupt-cells":
const: 1
interrupts:
minItems: 1
maxItems: 32
brcm,int-map-mask:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: >
32-bits bit mask describing how many and which interrupts are wired to
this 2nd level interrupt controller, and how they match their respective
interrupt parents. Should match exactly the number of interrupts
specified in the 'interrupts' property.
brcm,irq-can-wake:
type: boolean
description: >
If present, this means the L2 controller can be used as a wakeup source
for system suspend/resume.
brcm,int-fwd-mask:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
if present, a bit mask to configure the interrupts which have a mux gate,
typically UARTs. Setting these bits will make their respective interrupt
outputs bypass this 2nd level interrupt controller completely; it is
completely transparent for the interrupt controller parent. This should
have one 32-bit word per enable/status pair.
additionalProperties: false
required:
- compatible
- reg
- interrupt-controller
- "#interrupt-cells"
- interrupts
examples:
- |
irq0_intc: interrupt-controller@f0406800 {
compatible = "brcm,bcm7120-l2-intc";
interrupt-parent = <&intc>;
#interrupt-cells = <1>;
reg = <0xf0406800 0x8>;
interrupt-controller;
interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
brcm,int-map-mask = <0xeb8>, <0x140>;
brcm,int-fwd-mask = <0x7>;
};
- |
irq1_intc: interrupt-controller@10000020 {
compatible = "brcm,bcm3380-l2-intc";
reg = <0x10000024 0x4>, <0x1000002c 0x4>,
<0x10000020 0x4>, <0x10000028 0x4>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&cpu_intc>;
interrupts = <2>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/brcm,l2-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom Generic Level 2 Interrupt Controller
maintainers:
- Florian Fainelli <f.fainelli@gmail.com>
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
compatible:
oneOf:
- items:
- enum:
- brcm,hif-spi-l2-intc
- brcm,upg-aux-aon-l2-intc
- const: brcm,l2-intc
- items:
- enum:
- brcm,bcm2711-l2-intc
- const: brcm,l2-intc
- items:
- const: brcm,bcm7271-l2-intc
- items:
- const: brcm,l2-intc
reg:
maxItems: 1
description: >
Specifies the base physical address and size of the registers
interrupt-controller: true
"#interrupt-cells":
const: 1
interrupts:
maxItems: 1
interrupt-names:
maxItems: 1
brcm,irq-can-wake:
type: boolean
description: >
If present, this means the L2 controller can be used as a wakeup source
for system suspend/resume.
additionalProperties: false
required:
- compatible
- reg
- interrupt-controller
- "#interrupt-cells"
- interrupts
examples:
- |
hif_intr2_intc: interrupt-controller@f0441000 {
compatible = "brcm,l2-intc";
reg = <0xf0441000 0x30>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <0x0 0x20 0x0>;
};

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* Xtensa Interrupt Distributor and Programmable Interrupt Controller (MX)
Required properties:
- compatible: Should be "cdns,xtensa-mx".
Remaining properties have exact same meaning as in Xtensa PIC
(see cdns,xtensa-pic.txt).
Examples:
pic: pic {
compatible = "cdns,xtensa-mx";
/* one cell: internal irq number,
* two cells: second cell == 0: internal irq number
* second cell == 1: external irq number
*/
#interrupt-cells = <2>;
interrupt-controller;
};

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* Xtensa built-in Programmable Interrupt Controller (PIC)
Required properties:
- compatible: Should be "cdns,xtensa-pic".
- interrupt-controller: Identifies the node as an interrupt controller.
- #interrupt-cells: The number of cells to define the interrupts.
It may be either 1 or 2.
When it's 1, the first cell is the internal IRQ number.
When it's 2, the first cell is the IRQ number, and the second cell
specifies whether it's internal (0) or external (1).
Periferals are usually connected to a fixed external IRQ, but for different
core variants it may be mapped to different internal IRQ.
IRQ sensitivity and priority are fixed for each core variant and may not be
changed at runtime.
Examples:
pic: pic {
compatible = "cdns,xtensa-pic";
/* one cell: internal irq number,
* two cells: second cell == 0: internal irq number
* second cell == 1: external irq number
*/
#interrupt-cells = <2>;
interrupt-controller;
};

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Cirrus Logic CLPS711X Interrupt Controller
Required properties:
- compatible: Should be "cirrus,ep7209-intc".
- reg: Specifies base physical address of the registers set.
- interrupt-controller: Identifies the node as an interrupt controller.
- #interrupt-cells: Specifies the number of cells needed to encode an
interrupt source. The value shall be 1.
The interrupt sources are as follows:
ID Name Description
---------------------------
1: BLINT Battery low (FIQ)
3: MCINT Media changed (FIQ)
4: CSINT CODEC sound
5: EINT1 External 1
6: EINT2 External 2
7: EINT3 External 3
8: TC1OI TC1 under flow
9: TC2OI TC2 under flow
10: RTCMI RTC compare match
11: TINT 64Hz tick
12: UTXINT1 UART1 transmit FIFO half empty
13: URXINT1 UART1 receive FIFO half full
14: UMSINT UART1 modem status changed
15: SSEOTI SSI1 end of transfer
16: KBDINT Keyboard
17: SS2RX SSI2 receive FIFO half or greater full
18: SS2TX SSI2 transmit FIFO less than half empty
28: UTXINT2 UART2 transmit FIFO half empty
29: URXINT2 UART2 receive FIFO half full
32: DAIINT DAI interface (FIQ)
Example:
intc: interrupt-controller {
compatible = "cirrus,ep7312-intc", "cirrus,ep7209-intc";
reg = <0x80000000 0x4000>;
interrupt-controller;
#interrupt-cells = <1>;
};

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==============================
C-SKY APB Interrupt Controller
==============================
C-SKY APB Interrupt Controller is a simple soc interrupt controller
on the apb bus and we only use it as root irq controller.
- csky,apb-intc is used in a lot of csky fpgas and socs, it support 64 irq nums.
- csky,dual-apb-intc consists of 2 apb-intc and 128 irq nums supported.
- csky,gx6605s-intc is gx6605s soc internal irq interrupt controller, 64 irq nums.
=============================
intc node bindings definition
=============================
Description: Describes APB interrupt controller
PROPERTIES
- compatible
Usage: required
Value type: <string>
Definition: must be "csky,apb-intc"
"csky,dual-apb-intc"
"csky,gx6605s-intc"
- #interrupt-cells
Usage: required
Value type: <u32>
Definition: must be <1>
- reg
Usage: required
Value type: <u32 u32>
Definition: <phyaddr size> in soc from cpu view
- interrupt-controller:
Usage: required
- csky,support-pulse-signal:
Usage: select
Description: to support pulse signal flag
Examples:
---------
intc: interrupt-controller@500000 {
compatible = "csky,apb-intc";
#interrupt-cells = <1>;
reg = <0x00500000 0x400>;
interrupt-controller;
};
intc: interrupt-controller@500000 {
compatible = "csky,dual-apb-intc";
#interrupt-cells = <1>;
reg = <0x00500000 0x400>;
interrupt-controller;
};
intc: interrupt-controller@500000 {
compatible = "csky,gx6605s-intc";
#interrupt-cells = <1>;
reg = <0x00500000 0x400>;
interrupt-controller;
};

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===========================================
C-SKY Multi-processors Interrupt Controller
===========================================
C-SKY Multi-processors Interrupt Controller is designed for ck807/ck810/ck860
SMP soc, and it also could be used in non-SMP system.
Interrupt number definition:
0-15 : software irq, and we use 15 as our IPI_IRQ.
16-31 : private irq, and we use 16 as the co-processor timer.
31-1024: common irq for soc ip.
Interrupt trigger mode: (Defined in dt-bindings/interrupt-controller/irq.h)
IRQ_TYPE_LEVEL_HIGH (default)
IRQ_TYPE_LEVEL_LOW
IRQ_TYPE_EDGE_RISING
IRQ_TYPE_EDGE_FALLING
=============================
intc node bindings definition
=============================
Description: Describes SMP interrupt controller
PROPERTIES
- compatible
Usage: required
Value type: <string>
Definition: must be "csky,mpintc"
- #interrupt-cells
Usage: required
Value type: <u32>
Definition: <2>
- interrupt-controller:
Usage: required
Examples: ("interrupts = <irq_num IRQ_TYPE_XXX>")
---------
#include <dt-bindings/interrupt-controller/irq.h>
intc: interrupt-controller {
compatible = "csky,mpintc";
#interrupt-cells = <2>;
interrupt-controller;
};
device: device-example {
...
interrupts = <34 IRQ_TYPE_EDGE_RISING>;
interrupt-parent = <&intc>;
};

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Conexant Digicolor Interrupt Controller
Required properties:
- compatible : should be "cnxt,cx92755-ic"
- reg : Specifies base physical address and size of the interrupt controller
registers (IC) area
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value shall be 1.
- syscon: A phandle to the syscon node describing UC registers
Example:
intc: interrupt-controller@f0000040 {
compatible = "cnxt,cx92755-ic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xf0000040 0x40>;
syscon = <&uc_regs>;
};

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EZchip NPS Interrupt Controller
Required properties:
- compatible : should be "ezchip,nps400-ic"
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value shall be 1.
Example:
intc: interrupt-controller {
compatible = "ezchip,nps400-ic";
interrupt-controller;
#interrupt-cells = <1>;
};

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* Faraday Technologt FTINTC010 interrupt controller
This interrupt controller is a stock IP block from Faraday Technology found
in the Gemini SoCs and other designs.
Required properties:
- compatible: must be one of
"faraday,ftintc010"
"cortina,gemini-interrupt-controller" (deprecated)
- reg: The register bank for the interrupt controller.
- interrupt-controller: Identifies the node as an interrupt controller
- #interrupt-cells: The number of cells to define the interrupts.
Must be 2 as the controller can specify level or rising edge
IRQs. The bindings follows the standard binding for controllers
with two cells specified in
interrupt-controller/interrupts.txt
Example:
interrupt-controller@48000000 {
compatible = "faraday,ftintc010"
reg = <0x48000000 0x1000>;
interrupt-controller;
#interrupt-cells = <2>;
};

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/fsl,intmux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale INTMUX interrupt multiplexer
maintainers:
- Joakim Zhang <qiangqing.zhang@nxp.com>
properties:
compatible:
const: fsl,imx-intmux
reg:
maxItems: 1
interrupts:
minItems: 1
maxItems: 8
description: |
Should contain the parent interrupt lines (up to 8) used to multiplex
the input interrupts.
interrupt-controller: true
'#interrupt-cells':
const: 2
description: |
The 1st cell is hw interrupt number, the 2nd cell is channel index.
clocks:
maxItems: 1
clock-names:
const: ipg
required:
- compatible
- reg
- interrupts
- interrupt-controller
- '#interrupt-cells'
- clocks
- clock-names
additionalProperties: false
examples:
- |
interrupt-controller@37400000 {
compatible = "fsl,imx-intmux";
reg = <0x37400000 0x1000>;
interrupts = <0 16 4>,
<0 17 4>,
<0 18 4>,
<0 19 4>,
<0 20 4>,
<0 21 4>,
<0 22 4>,
<0 23 4>;
interrupt-controller;
interrupt-parent = <&gic>;
#interrupt-cells = <2>;
clocks = <&clk>;
clock-names = "ipg";
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/fsl,irqsteer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale IRQSTEER Interrupt Multiplexer
maintainers:
- Lucas Stach <l.stach@pengutronix.de>
properties:
compatible:
oneOf:
- const: fsl,imx-irqsteer
- items:
- const: fsl,imx8m-irqsteer
- const: fsl,imx-irqsteer
reg:
maxItems: 1
interrupts:
description: |
should contain the up to 8 parent interrupt lines used to multiplex
the input interrupts. They should be specified sequentially from
output 0 to 7.
items:
- description: output interrupt 0
- description: output interrupt 1
- description: output interrupt 2
- description: output interrupt 3
- description: output interrupt 4
- description: output interrupt 5
- description: output interrupt 6
- description: output interrupt 7
minItems: 1
clocks:
maxItems: 1
clock-names:
const: ipg
interrupt-controller: true
"#interrupt-cells":
const: 1
fsl,channel:
$ref: '/schemas/types.yaml#/definitions/uint32'
description: |
u32 value representing the output channel that all input IRQs should be
steered into.
fsl,num-irqs:
$ref: '/schemas/types.yaml#/definitions/uint32'
description: |
u32 value representing the number of input interrupts of this channel,
should be multiple of 32 input interrupts and up to 512 interrupts.
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- interrupt-controller
- "#interrupt-cells"
- fsl,channel
- fsl,num-irqs
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8mq-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
interrupt-controller@32e2d000 {
compatible = "fsl,imx-irqsteer";
reg = <0x32e2d000 0x1000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
clock-names = "ipg";
fsl,channel = <0>;
fsl,num-irqs = <64>;
interrupt-controller;
#interrupt-cells = <1>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-extirq.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Layerscape External Interrupt Controller
maintainers:
- Shawn Guo <shawnguo@kernel.org>
- Li Yang <leoyang.li@nxp.com>
description: |
Some Layerscape SOCs (LS1021A, LS1043A, LS1046A LS1088A, LS208xA,
LX216xA) support inverting the polarity of certain external interrupt
lines.
properties:
compatible:
oneOf:
- enum:
- fsl,ls1021a-extirq
- fsl,ls1043a-extirq
- fsl,ls1088a-extirq
- items:
- enum:
- fsl,ls1046a-extirq
- const: fsl,ls1043a-extirq
- items:
- enum:
- fsl,ls2080a-extirq
- fsl,lx2160a-extirq
- const: fsl,ls1088a-extirq
'#interrupt-cells':
const: 2
'#address-cells':
const: 0
interrupt-controller: true
reg:
maxItems: 1
description:
Specifies the Interrupt Polarity Control Register (INTPCR) in the
SCFG or the External Interrupt Control Register (IRQCR) in the ISC.
interrupt-map:
description: Specifies the mapping from external interrupts to GIC interrupts.
interrupt-map-mask: true
required:
- compatible
- '#interrupt-cells'
- '#address-cells'
- interrupt-controller
- reg
- interrupt-map
- interrupt-map-mask
allOf:
- if:
properties:
compatible:
contains:
enum:
- fsl,ls1021a-extirq
then:
properties:
interrupt-map:
minItems: 6
maxItems: 6
interrupt-map-mask:
items:
- const: 0x7
- const: 0
- if:
properties:
compatible:
contains:
enum:
- fsl,ls1043a-extirq
- fsl,ls1046a-extirq
- fsl,ls1088a-extirq
- fsl,ls2080a-extirq
- fsl,lx2160a-extirq
then:
properties:
interrupt-map:
minItems: 12
maxItems: 12
interrupt-map-mask:
items:
- const: 0xf
- const: 0
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
interrupt-controller@1ac {
compatible = "fsl,ls1021a-extirq";
#interrupt-cells = <2>;
#address-cells = <0>;
interrupt-controller;
reg = <0x1ac 4>;
interrupt-map =
<0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
<2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
<3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
<4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0x7 0x0>;
};

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* Freescale Layerscape SCFG PCIe MSI controller
Required properties:
- compatible: should be "fsl,<soc-name>-msi" to identify
Layerscape PCIe MSI controller block such as:
"fsl,ls1021a-msi"
"fsl,ls1043a-msi"
"fsl,ls1046a-msi"
"fsl,ls1043a-v1.1-msi"
"fsl,ls1012a-msi"
- msi-controller: indicates that this is a PCIe MSI controller node
- reg: physical base address of the controller and length of memory mapped.
- interrupts: an interrupt to the parent interrupt controller.
This interrupt controller hardware is a second level interrupt controller that
is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
platforms. If interrupt-parent is not provided, the default parent interrupt
controller will be used.
Each PCIe node needs to have property msi-parent that points to
MSI controller node
Examples:
msi1: msi-controller@1571000 {
compatible = "fsl,ls1043a-msi";
reg = <0x0 0x1571000 0x0 0x8>,
msi-controller;
interrupts = <0 116 0x4>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale/NXP i.MX Messaging Unit (MU) work as msi controller
maintainers:
- Frank Li <Frank.Li@nxp.com>
description: |
The Messaging Unit module enables two processors within the SoC to
communicate and coordinate by passing messages (e.g. data, status
and control) through the MU interface. The MU also provides the ability
for one processor (A side) to signal the other processor (B side) using
interrupts.
Because the MU manages the messaging between processors, the MU uses
different clocks (from each side of the different peripheral buses).
Therefore, the MU must synchronize the accesses from one side to the
other. The MU accomplishes synchronization using two sets of matching
registers (Processor A-side, Processor B-side).
MU can work as msi interrupt controller to do doorbell
allOf:
- $ref: /schemas/interrupt-controller/msi-controller.yaml#
properties:
compatible:
enum:
- fsl,imx6sx-mu-msi
- fsl,imx7ulp-mu-msi
- fsl,imx8ulp-mu-msi
- fsl,imx8ulp-mu-msi-s4
reg:
items:
- description: a side register base address
- description: b side register base address
reg-names:
items:
- const: processor-a-side
- const: processor-b-side
interrupts:
description: a side interrupt number.
maxItems: 1
clocks:
maxItems: 1
power-domains:
items:
- description: a side power domain
- description: b side power domain
power-domain-names:
items:
- const: processor-a-side
- const: processor-b-side
interrupt-controller: true
msi-controller: true
"#msi-cells":
const: 0
required:
- compatible
- reg
- interrupts
- interrupt-controller
- msi-controller
- "#msi-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/firmware/imx/rsrc.h>
msi-controller@5d270000 {
compatible = "fsl,imx6sx-mu-msi";
msi-controller;
#msi-cells = <0>;
interrupt-controller;
reg = <0x5d270000 0x10000>, /* A side */
<0x5d300000 0x10000>; /* B side */
reg-names = "processor-a-side", "processor-b-side";
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd IMX_SC_R_MU_12A>,
<&pd IMX_SC_R_MU_12B>;
power-domain-names = "processor-a-side", "processor-b-side";
};

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Android Goldfish PIC
Android Goldfish programmable interrupt device used by Android
emulator.
Required properties:
- compatible : should contain "google,goldfish-pic"
- reg : <registers mapping>
- interrupts : <interrupt mapping>
Example for mips when used in cascade mode:
cpuintc {
#interrupt-cells = <0x1>;
#address-cells = <0>;
interrupt-controller;
compatible = "mti,cpu-interrupt-controller";
};
interrupt-controller@1f000000 {
compatible = "google,goldfish-pic";
reg = <0x1f000000 0x1000>;
interrupt-controller;
#interrupt-cells = <0x1>;
interrupt-parent = <&cpuintc>;
interrupts = <0x2>;
};

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Hisilicon mbigen device tree bindings.
=======================================
Mbigen means: message based interrupt generator.
MBI is kind of msi interrupt only used on Non-PCI devices.
To reduce the wired interrupt number connected to GIC,
Hisilicon designed mbigen to collect and generate interrupt.
Non-pci devices can connect to mbigen and generate the
interrupt by writing ITS register.
The mbigen chip and devices connect to mbigen have the following properties:
Mbigen main node required properties:
-------------------------------------------
- compatible: Should be "hisilicon,mbigen-v2"
- reg: Specifies the base physical address and size of the Mbigen
registers.
Mbigen sub node required properties:
------------------------------------------
- interrupt controller: Identifies the node as an interrupt controller
- msi-parent: Specifies the MSI controller this mbigen use.
For more detail information,please refer to the generic msi-parent binding in
Documentation/devicetree/bindings/interrupt-controller/msi.txt.
- num-pins: the total number of pins implemented in this Mbigen
instance.
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value must be 2.
The 1st cell is hardware pin number of the interrupt.This number is local to
each mbigen chip and in the range from 0 to the maximum interrupts number
of the mbigen.
The 2nd cell is the interrupt trigger type.
The value of this cell should be:
1: rising edge triggered
or
4: high level triggered
Examples:
mbigen_chip_dsa {
compatible = "hisilicon,mbigen-v2";
reg = <0x0 0xc0080000 0x0 0x10000>;
mbigen_gmac:intc_gmac {
interrupt-controller;
msi-parent = <&its_dsa 0x40b1c>;
num-pins = <9>;
#interrupt-cells = <2>;
};
mbigen_i2c:intc_i2c {
interrupt-controller;
msi-parent = <&its_dsa 0x40b0e>;
num-pins = <2>;
#interrupt-cells = <2>;
};
};
Devices connect to mbigen required properties:
----------------------------------------------------
-interrupts:Specifies the interrupt source.
For the specific information of each cell in this property,please refer to
the "interrupt-cells" description mentioned above.
Examples:
gmac0: ethernet@c2080000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0xc2080000 0 0x20000>,
<0 0xc0000000 0 0x1000>;
interrupt-parent = <&mbigen_device_gmac>;
interrupts = <656 1>,
<657 1>;
};

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/idt,32434-pic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: IDT 79RC32434 Interrupt Controller
maintainers:
- Thomas Bogendoerfer <tsbogend@alpha.franken.de>
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
"#interrupt-cells":
const: 1
compatible:
const: idt,32434-pic
reg:
maxItems: 1
interrupts:
maxItems: 1
interrupt-controller: true
required:
- "#interrupt-cells"
- compatible
- reg
- interrupt-controller
- interrupts
additionalProperties: false
examples:
- |
idtpic3: interrupt-controller@3800c {
compatible = "idt,32434-pic";
reg = <0x3800c 0x0c>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&cpuintc>;
interrupts = <3>;
};
...

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* ImgTec Powerdown Controller (PDC) Interrupt Controller Binding
This binding specifies what properties must be available in the device tree
representation of a PDC IRQ controller. This has a number of input interrupt
lines which can wake the system, and are passed on through output interrupt
lines.
Required properties:
- compatible: Specifies the compatibility list for the interrupt controller.
The type shall be <string> and the value shall include "img,pdc-intc".
- reg: Specifies the base PDC physical address(s) and size(s) of the
addressable register space. The type shall be <prop-encoded-array>.
- interrupt-controller: The presence of this property identifies the node
as an interrupt controller. No property value shall be defined.
- #interrupt-cells: Specifies the number of cells needed to encode an
interrupt source. The type shall be a <u32> and the value shall be 2.
- num-perips: Number of waking peripherals.
- num-syswakes: Number of SysWake inputs.
- interrupts: List of interrupt specifiers. The first specifier shall be the
shared SysWake interrupt, and remaining specifies shall be PDC peripheral
interrupts in order.
* Interrupt Specifier Definition
Interrupt specifiers consists of 2 cells encoded as follows:
- <1st-cell>: The interrupt-number that identifies the interrupt source.
0-7: Peripheral interrupts
8-15: SysWake interrupts
- <2nd-cell>: The level-sense information, encoded using the Linux interrupt
flags as follows (only 4 valid for peripheral interrupts):
0 = none (decided by software)
1 = low-to-high edge triggered
2 = high-to-low edge triggered
3 = both edge triggered
4 = active-high level-sensitive (required for perip irqs)
8 = active-low level-sensitive
* Examples
Example 1:
/*
* TZ1090 PDC block
*/
pdc: pdc@02006000 {
// This is an interrupt controller node.
interrupt-controller;
// Three cells to encode interrupt sources.
#interrupt-cells = <2>;
// Offset address of 0x02006000 and size of 0x1000.
reg = <0x02006000 0x1000>;
// Compatible with Meta hardware trigger block.
compatible = "img,pdc-intc";
// Three peripherals are connected.
num-perips = <3>;
// Four SysWakes are connected.
num-syswakes = <4>;
interrupts = <18 4 /* level */>, /* Syswakes */
<30 4 /* level */>, /* Peripheral 0 (RTC) */
<29 4 /* level */>, /* Peripheral 1 (IR) */
<31 4 /* level */>; /* Peripheral 2 (WDT) */
};
Example 2:
/*
* An SoC peripheral that is wired through the PDC.
*/
rtc0 {
// The interrupt controller that this device is wired to.
interrupt-parent = <&pdc>;
// Interrupt source Peripheral 0
interrupts = <0 /* Peripheral 0 (RTC) */
4> /* IRQ_TYPE_LEVEL_HIGH */
};
Example 3:
/*
* An interrupt generating device that is wired to a SysWake pin.
*/
touchscreen0 {
// The interrupt controller that this device is wired to.
interrupt-parent = <&pdc>;
// Interrupt source SysWake 0 that is active-low level-sensitive
interrupts = <8 /* SysWake0 */
8 /* IRQ_TYPE_LEVEL_LOW */>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/ingenic,intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ingenic SoCs interrupt controller devicetree bindings
maintainers:
- Paul Cercueil <paul@crapouillou.net>
properties:
$nodename:
pattern: "^interrupt-controller@[0-9a-f]+$"
compatible:
oneOf:
- enum:
- ingenic,jz4740-intc
- ingenic,jz4760-intc
- ingenic,jz4780-intc
- items:
- enum:
- ingenic,jz4775-intc
- ingenic,jz4770-intc
- ingenic,jz4760b-intc
- const: ingenic,jz4760-intc
- items:
- const: ingenic,x1000-intc
- const: ingenic,jz4780-intc
- items:
- const: ingenic,jz4725b-intc
- const: ingenic,jz4740-intc
"#interrupt-cells":
const: 1
reg:
maxItems: 1
interrupts:
maxItems: 1
interrupt-controller: true
required:
- compatible
- reg
- interrupts
- "#interrupt-cells"
- interrupt-controller
additionalProperties: false
examples:
- |
intc: interrupt-controller@10001000 {
compatible = "ingenic,jz4770-intc", "ingenic,jz4760-intc";
reg = <0x10001000 0x40>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&cpuintc>;
interrupts = <2>;
};

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioapic.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Intel I/O Advanced Programmable Interrupt Controller (IO APIC)
maintainers:
- Rahul Tanwar <rtanwar@maxlinear.com>
description: |
Intel's Advanced Programmable Interrupt Controller (APIC) is a
family of interrupt controllers. The APIC is a split
architecture design, with a local component (LAPIC) integrated
into the processor itself and an external I/O APIC. Local APIC
(lapic) receives interrupts from the processor's interrupt pins,
from internal sources and from an external I/O APIC (ioapic).
And it sends these to the processor core for handling.
See [1] Chapter 8 for more details.
Many of the Intel's generic devices like hpet, ioapic, lapic have
the ce4100 name in their compatible property names because they
first appeared in CE4100 SoC.
This schema defines bindings for I/O APIC interrupt controller.
[1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf
properties:
compatible:
const: intel,ce4100-ioapic
reg:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
interrupts:
maxItems: 1
required:
- compatible
- reg
- interrupt-controller
- '#interrupt-cells'
additionalProperties: false
examples:
- |
ioapic1: interrupt-controller@fec00000 {
compatible = "intel,ce4100-ioapic";
reg = <0xfec00000 0x1000>;
interrupt-controller;
#interrupt-cells = <2>;
};

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Intel Local Advanced Programmable Interrupt Controller (LAPIC)
maintainers:
- Rahul Tanwar <rtanwar@maxlinear.com>
description: |
Intel's Advanced Programmable Interrupt Controller (APIC) is a
family of interrupt controllers. The APIC is a split
architecture design, with a local component (LAPIC) integrated
into the processor itself and an external I/O APIC. Local APIC
(lapic) receives interrupts from the processor's interrupt pins,
from internal sources and from an external I/O APIC (ioapic).
And it sends these to the processor core for handling.
See [1] Chapter 8 for more details.
Many of the Intel's generic devices like hpet, ioapic, lapic have
the ce4100 name in their compatible property names because they
first appeared in CE4100 SoC.
This schema defines bindings for local APIC interrupt controller.
[1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf
properties:
compatible:
const: intel,ce4100-lapic
reg:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
intel,virtual-wire-mode:
description: Intel defines a few possible interrupt delivery
modes. With respect to boot/init time, mainly two interrupt
delivery modes are possible.
PIC Mode - Legacy external 8259 compliant PIC interrupt controller.
Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode.
For ACPI or MPS spec compliant systems, it is figured out by some read
only bit field/s available in their respective defined data structures.
For OF based systems, it is by default set to PIC mode.
But if this optional boolean property is set, then the interrupt delivery
mode is configured to virtual wire compatibility mode.
type: boolean
required:
- compatible
- reg
- interrupt-controller
- '#interrupt-cells'
additionalProperties: false
examples:
- |
lapic0: interrupt-controller@fee00000 {
compatible = "intel,ce4100-lapic";
reg = <0xfee00000 0x1000>;
interrupt-controller;
#interrupt-cells = <2>;
intel,virtual-wire-mode;
};

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2018 Linaro Ltd.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/interrupt-controller/intel,ixp4xx-interrupt.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Intel IXP4xx XScale Networking Processors Interrupt Controller
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
description: |
This interrupt controller is found in the Intel IXP4xx processors.
Some processors have 32 interrupts, some have up to 64 interrupts.
The exact number of interrupts is determined from the compatible
string.
The distinct IXP4xx families with different interrupt controller
variations are IXP42x, IXP43x, IXP45x and IXP46x. Those four
families were the only ones to reach the developer and consumer
market.
properties:
compatible:
items:
- enum:
- intel,ixp42x-interrupt
- intel,ixp43x-interrupt
- intel,ixp45x-interrupt
- intel,ixp46x-interrupt
reg:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
required:
- compatible
- reg
- interrupt-controller
- '#interrupt-cells'
additionalProperties: false
examples:
- |
intcon: interrupt-controller@c8003000 {
compatible = "intel,ixp43x-interrupt";
reg = <0xc8003000 0x100>;
interrupt-controller;
#interrupt-cells = <2>;
};

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Specifying interrupt information for devices
============================================
1) Interrupt client nodes
-------------------------
Nodes that describe devices which generate interrupts must contain an
"interrupts" property, an "interrupts-extended" property, or both. If both are
present, the latter should take precedence; the former may be provided simply
for compatibility with software that does not recognize the latter. These
properties contain a list of interrupt specifiers, one per output interrupt. The
format of the interrupt specifier is determined by the interrupt controller to
which the interrupts are routed; see section 2 below for details.
Example:
interrupt-parent = <&intc1>;
interrupts = <5 0>, <6 0>;
The "interrupt-parent" property is used to specify the controller to which
interrupts are routed and contains a single phandle referring to the interrupt
controller node. This property is inherited, so it may be specified in an
interrupt client node or in any of its parent nodes. Interrupts listed in the
"interrupts" property are always in reference to the node's interrupt parent.
The "interrupts-extended" property is a special form; useful when a node needs
to reference multiple interrupt parents or a different interrupt parent than
the inherited one. Each entry in this property contains both the parent phandle
and the interrupt specifier.
Example:
interrupts-extended = <&intc1 5 1>, <&intc2 1 0>;
2) Interrupt controller nodes
-----------------------------
A device is marked as an interrupt controller with the "interrupt-controller"
property. This is a empty, boolean property. An additional "#interrupt-cells"
property defines the number of cells needed to specify a single interrupt.
It is the responsibility of the interrupt controller's binding to define the
length and format of the interrupt specifier. The following two variants are
commonly used:
a) one cell
-----------
The #interrupt-cells property is set to 1 and the single cell defines the
index of the interrupt within the controller.
Example:
vic: intc@10140000 {
compatible = "arm,versatile-vic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x10140000 0x1000>;
};
sic: intc@10003000 {
compatible = "arm,versatile-sic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x10003000 0x1000>;
interrupt-parent = <&vic>;
interrupts = <31>; /* Cascaded to vic */
};
b) two cells
------------
The #interrupt-cells property is set to 2 and the first cell defines the
index of the interrupt within the controller, while the second cell is used
to specify any of the following flags:
- bits[3:0] trigger type and level flags
1 = low-to-high edge triggered
2 = high-to-low edge triggered
4 = active high level-sensitive
8 = active low level-sensitive
Example:
i2c@7000c000 {
gpioext: gpio-adnp@41 {
compatible = "ad,gpio-adnp";
reg = <0x41>;
interrupt-parent = <&gpio>;
interrupts = <160 1>;
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
nr-gpios = <64>;
};
sx8634@2b {
compatible = "smtc,sx8634";
reg = <0x2b>;
interrupt-parent = <&gpioext>;
interrupts = <3 0x8>;
#address-cells = <1>;
#size-cells = <0>;
threshold = <0x40>;
sensitivity = <7>;
};
};
3) Interrupt wakeup parent
--------------------------
Some interrupt controllers in a SoC, are always powered on and have a select
interrupts routed to them, so that they can wakeup the SoC from suspend. These
interrupt controllers do not fall into the category of a parent interrupt
controller and can be specified by the "wakeup-parent" property and contain a
single phandle referring to the wakeup capable interrupt controller.
Example:
wakeup-parent = <&pdc_intc>;

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J-Core Advanced Interrupt Controller
Required properties:
- compatible: Should be "jcore,aic1" for the (obsolete) first-generation aic
with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
the "aic2" core with 64 interrupts.
- reg: Memory region(s) for configuration. For SMP, there should be one
region per cpu, indexed by the sequential, zero-based hardware cpu
number.
- interrupt-controller: Identifies the node as an interrupt controller
- #interrupt-cells: Specifies the number of cells needed to encode an
interrupt source. The value shall be 1.
Example:
aic: interrupt-controller@200 {
compatible = "jcore,aic2";
reg = < 0x200 0x30 0x500 0x30 >;
interrupt-controller;
#interrupt-cells = <1>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/kontron,sl28cpld-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Interrupt controller driver for the sl28cpld board management controller
maintainers:
- Michael Walle <michael@walle.cc>
description: |
This module is part of the sl28cpld multi-function device. For more
details see ../mfd/kontron,sl28cpld.yaml.
The following interrupts are available. All types and levels are fixed
and handled by the board management controller.
==== ============= ==================================
IRQ line/device description
==== ============= ==================================
0 RTC_INT# Interrupt line from on-board RTC
1 SMB_ALERT# Event on SMB_ALERT# line (P1)
2 ESPI_ALERT0# Event on ESPI_ALERT0# line (S43)
3 ESPI_ALERT1# Event on ESPI_ALERT1# line (S44)
4 PWR_BTN# Event on PWR_BTN# line (P128)
5 SLEEP# Event on SLEEP# line (S149)
6 watchdog Interrupt of the internal watchdog
7 n/a not used
==== ============= ==================================
properties:
compatible:
enum:
- kontron,sl28cpld-intc
reg:
maxItems: 1
interrupts:
maxItems: 1
"#interrupt-cells":
const: 2
interrupt-controller: true
required:
- compatible
- interrupts
- "#interrupt-cells"
- interrupt-controller
additionalProperties: false

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/loongarch,cpu-interrupt-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: LoongArch CPU Interrupt Controller
maintainers:
- Liu Peibao <liupeibao@loongson.cn>
properties:
compatible:
const: loongarch,cpu-interrupt-controller
'#interrupt-cells':
const: 1
interrupt-controller: true
additionalProperties: false
required:
- compatible
- '#interrupt-cells'
- interrupt-controller
examples:
- |
interrupt-controller {
compatible = "loongarch,cpu-interrupt-controller";
#interrupt-cells = <1>;
interrupt-controller;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/interrupt-controller/loongson,htpic.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Loongson-3 HyperTransport Interrupt Controller
maintainers:
- Jiaxun Yang <jiaxun.yang@flygoat.com>
allOf:
- $ref: /schemas/interrupt-controller.yaml#
description: |
This interrupt controller is found in the Loongson-3 family of chips to transmit
interrupts from PCH PIC connected on HyperTransport bus.
properties:
compatible:
const: loongson,htpic-1.0
reg:
maxItems: 1
interrupts:
minItems: 1
maxItems: 4
description: |
Four parent interrupts that receive chained interrupts.
interrupt-controller: true
'#interrupt-cells':
const: 1
required:
- compatible
- reg
- interrupts
- interrupt-controller
- '#interrupt-cells'
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
htintc: interrupt-controller@1fb000080 {
compatible = "loongson,htpic-1.0";
reg = <0xfb000080 0x40>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&liointc>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
<25 IRQ_TYPE_LEVEL_HIGH>,
<26 IRQ_TYPE_LEVEL_HIGH>,
<27 IRQ_TYPE_LEVEL_HIGH>;
};
...

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/interrupt-controller/loongson,htvec.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Loongson-3 HyperTransport Interrupt Vector Controller
maintainers:
- Jiaxun Yang <jiaxun.yang@flygoat.com>
description:
This interrupt controller is found in the Loongson-3 family of chips for
receiving vectorized interrupts from PCH's interrupt controller.
properties:
compatible:
const: loongson,htvec-1.0
reg:
maxItems: 1
interrupts:
minItems: 1
maxItems: 8
description: Eight parent interrupts that receive chained interrupts.
interrupt-controller: true
'#interrupt-cells':
const: 1
required:
- compatible
- reg
- interrupts
- interrupt-controller
- '#interrupt-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
htvec: interrupt-controller@fb000080 {
compatible = "loongson,htvec-1.0";
reg = <0xfb000080 0x40>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&liointc>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
<25 IRQ_TYPE_LEVEL_HIGH>,
<26 IRQ_TYPE_LEVEL_HIGH>,
<27 IRQ_TYPE_LEVEL_HIGH>;
};
...

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Loongson Local I/O Interrupt Controller
maintainers:
- Jiaxun Yang <jiaxun.yang@flygoat.com>
description: |
This interrupt controller is found in the Loongson-3 family of chips and
Loongson-2K1000 chip, as the primary package interrupt controller which
can route local I/O interrupt to interrupt lines of cores.
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
compatible:
enum:
- loongson,liointc-1.0
- loongson,liointc-1.0a
- loongson,liointc-2.0
reg:
minItems: 1
maxItems: 3
reg-names:
items:
- const: main
- const: isr0
- const: isr1
interrupt-controller: true
interrupts:
description:
Interrupt source of the CPU interrupts.
minItems: 1
maxItems: 4
interrupt-names:
description: List of names for the parent interrupts.
items:
- const: int0
- const: int1
- const: int2
- const: int3
minItems: 1
'#interrupt-cells':
const: 2
'loongson,parent_int_map':
description: |
This property points how the children interrupts will be mapped into CPU
interrupt lines. Each cell refers to a parent interrupt line from 0 to 3
and each bit in the cell refers to a child interrupt from 0 to 31.
If a CPU interrupt line didn't connect with liointc, then keep its
cell with zero.
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 4
maxItems: 4
required:
- compatible
- reg
- interrupts
- interrupt-controller
- '#interrupt-cells'
- 'loongson,parent_int_map'
unevaluatedProperties: false
if:
properties:
compatible:
contains:
enum:
- loongson,liointc-2.0
then:
properties:
reg:
minItems: 3
required:
- reg-names
else:
properties:
reg:
maxItems: 1
examples:
- |
iointc: interrupt-controller@3ff01400 {
compatible = "loongson,liointc-1.0";
reg = <0x3ff01400 0x64>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&cpuintc>;
interrupts = <2>, <3>;
interrupt-names = "int0", "int1";
loongson,parent_int_map = <0xf0ffffff>, /* int0 */
<0x0f000000>, /* int1 */
<0x00000000>, /* int2 */
<0x00000000>; /* int3 */
};
...

24
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Loongson ls1x Interrupt Controller
Required properties:
- compatible : should be "loongson,ls1x-intc". Valid strings are:
- reg : Specifies base physical address and size of the registers.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value shall be 2.
- interrupts : Specifies the CPU interrupt the controller is connected to.
Example:
intc: interrupt-controller@1fd01040 {
compatible = "loongson,ls1x-intc";
reg = <0x1fd01040 0x18>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&cpu_intc>;
interrupts = <2>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Loongson PCH MSI Controller
maintainers:
- Jiaxun Yang <jiaxun.yang@flygoat.com>
description:
This interrupt controller is found in the Loongson LS7A family of PCH for
transforming interrupts from PCIe MSI into HyperTransport vectorized
interrupts.
properties:
compatible:
const: loongson,pch-msi-1.0
reg:
maxItems: 1
loongson,msi-base-vec:
description:
u32 value of the base of parent HyperTransport vector allocated
to PCH MSI.
$ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 0
maximum: 255
loongson,msi-num-vecs:
description:
u32 value of the number of parent HyperTransport vectors allocated
to PCH MSI.
$ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 1
maximum: 256
msi-controller: true
required:
- compatible
- reg
- msi-controller
- loongson,msi-base-vec
- loongson,msi-num-vecs
additionalProperties: true #fixme
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
msi: msi-controller@2ff00000 {
compatible = "loongson,pch-msi-1.0";
reg = <0x2ff00000 0x4>;
msi-controller;
loongson,msi-base-vec = <64>;
loongson,msi-num-vecs = <64>;
interrupt-parent = <&htvec>;
};
...

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/interrupt-controller/loongson,pch-pic.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Loongson PCH PIC Controller
maintainers:
- Jiaxun Yang <jiaxun.yang@flygoat.com>
description:
This interrupt controller is found in the Loongson LS7A family of PCH for
transforming interrupts from on-chip devices into HyperTransport vectorized
interrupts.
properties:
compatible:
const: loongson,pch-pic-1.0
reg:
maxItems: 1
loongson,pic-base-vec:
description:
u32 value of the base of parent HyperTransport vector allocated
to PCH PIC.
$ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 0
maximum: 192
interrupt-controller: true
'#interrupt-cells':
const: 2
required:
- compatible
- reg
- loongson,pic-base-vec
- interrupt-controller
- '#interrupt-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
pic: interrupt-controller@10000000 {
compatible = "loongson,pch-pic-1.0";
reg = <0x10000000 0x400>;
interrupt-controller;
#interrupt-cells = <2>;
loongson,pic-base-vec = <64>;
interrupt-parent = <&htvec>;
};
...

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TI-NSPIRE interrupt controller
Required properties:
- compatible: Compatible property value should be "lsi,zevio-intc".
- reg: Physical base address of the controller and length of memory mapped
region.
- interrupt-controller : Identifies the node as an interrupt controller
Example:
interrupt-controller {
compatible = "lsi,zevio-intc";
interrupt-controller;
reg = <0xDC000000 0x1000>;
#interrupt-cells = <1>;
};

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Marvell Armada 370, 375, 38x, XP Interrupt Controller
-----------------------------------------------------
Required properties:
- compatible: Should be "marvell,mpic"
- interrupt-controller: Identifies the node as an interrupt controller.
- msi-controller: Identifies the node as an PCI Message Signaled
Interrupt controller.
- #interrupt-cells: The number of cells to define the interrupts. Should be 1.
The cell is the IRQ number
- reg: Should contain PMIC registers location and length. First pair
for the main interrupt registers, second pair for the per-CPU
interrupt registers. For this last pair, to be compliant with SMP
support, the "virtual" must be use (For the record, these registers
automatically map to the interrupt controller registers of the
current CPU)
Optional properties:
- interrupts: If defined, then it indicates that this MPIC is
connected as a slave to another interrupt controller. This is
typically the case on Armada 375 and Armada 38x, where the MPIC is
connected as a slave to the Cortex-A9 GIC. The provided interrupt
indicate to which GIC interrupt the MPIC output is connected.
Example:
mpic: interrupt-controller@d0020000 {
compatible = "marvell,mpic";
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
msi-controller;
reg = <0xd0020a00 0x1d0>,
<0xd0021070 0x58>;
};

25
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Marvell Armada 7K/8K PIC Interrupt controller
---------------------------------------------
This is the Device Tree binding for the PIC, a secondary interrupt
controller available on the Marvell Armada 7K/8K ARM64 SoCs, and
typically connected to the GIC as the primary interrupt controller.
Required properties:
- compatible: should be "marvell,armada-8k-pic"
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: the number of cells to define interrupts on this
controller. Should be 1
- reg: the register area for the PIC interrupt controller
- interrupts: the interrupt to the primary interrupt controller,
typically the GIC
Example:
pic: interrupt-controller@3f0100 {
compatible = "marvell,armada-8k-pic";
reg = <0x3f0100 0x10>;
#interrupt-cells = <1>;
interrupt-controller;
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};

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Marvell GICP Controller
-----------------------
GICP is a Marvell extension of the GIC that allows to trigger GIC SPI
interrupts by doing a memory transaction. It is used by the ICU
located in the Marvell CP110 to turn wired interrupts inside the CP
into GIC SPI interrupts.
Required properties:
- compatible: Must be "marvell,ap806-gicp"
- reg: Must be the address and size of the GICP SPI registers
- marvell,spi-ranges: tuples of GIC SPI interrupts ranges available
for this GICP
- msi-controller: indicates that this is an MSI controller
Example:
gicp_spi: gicp-spi@3f0040 {
compatible = "marvell,ap806-gicp";
reg = <0x3f0040 0x10>;
marvell,spi-ranges = <64 64>, <288 64>;
msi-controller;
};

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Marvell ICU Interrupt Controller
--------------------------------
The Marvell ICU (Interrupt Consolidation Unit) controller is
responsible for collecting all wired-interrupt sources in the CP and
communicating them to the GIC in the AP, the unit translates interrupt
requests on input wires to MSG memory mapped transactions to the GIC.
These messages will access a different GIC memory area depending on
their type (NSR, SR, SEI, REI, etc).
Required properties:
- compatible: Should be "marvell,cp110-icu"
- reg: Should contain ICU registers location and length.
Subnodes: Each group of interrupt is declared as a subnode of the ICU,
with their own compatible.
Required properties for the icu_nsr/icu_sei subnodes:
- compatible: Should be one of:
* "marvell,cp110-icu-nsr"
* "marvell,cp110-icu-sr"
* "marvell,cp110-icu-sei"
* "marvell,cp110-icu-rei"
- #interrupt-cells: Specifies the number of cells needed to encode an
interrupt source. The value shall be 2.
The 1st cell is the index of the interrupt in the ICU unit.
The 2nd cell is the type of the interrupt. See arm,gic.txt for
details.
- interrupt-controller: Identifies the node as an interrupt
controller.
- msi-parent: Should point to the GICP controller, the GIC extension
that allows to trigger interrupts using MSG memory mapped
transactions.
Note: each 'interrupts' property referring to any 'icu_xxx' node shall
have a different number within [0:206].
Example:
icu: interrupt-controller@1e0000 {
compatible = "marvell,cp110-icu";
reg = <0x1e0000 0x440>;
CP110_LABEL(icu_nsr): interrupt-controller@10 {
compatible = "marvell,cp110-icu-nsr";
reg = <0x10 0x20>;
#interrupt-cells = <2>;
interrupt-controller;
msi-parent = <&gicp>;
};
CP110_LABEL(icu_sei): interrupt-controller@50 {
compatible = "marvell,cp110-icu-sei";
reg = <0x50 0x10>;
#interrupt-cells = <2>;
interrupt-controller;
msi-parent = <&sei>;
};
};
node1 {
interrupt-parent = <&icu_nsr>;
interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
};
node2 {
interrupt-parent = <&icu_sei>;
interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
};
/* Would not work with the above nodes */
node3 {
interrupt-parent = <&icu_nsr>;
interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
};
The legacy bindings were different in this way:
- #interrupt-cells: The value was 3.
The 1st cell was the group type of the ICU interrupt. Possible
group types were:
ICU_GRP_NSR (0x0) : Shared peripheral interrupt, non-secure
ICU_GRP_SR (0x1) : Shared peripheral interrupt, secure
ICU_GRP_SEI (0x4) : System error interrupt
ICU_GRP_REI (0x5) : RAM error interrupt
The 2nd cell was the index of the interrupt in the ICU unit.
The 3rd cell was the type of the interrupt. See arm,gic.txt for
details.
Example:
icu: interrupt-controller@1e0000 {
compatible = "marvell,cp110-icu";
reg = <0x1e0000 0x440>;
#interrupt-cells = <3>;
interrupt-controller;
msi-parent = <&gicp>;
};
node1 {
interrupt-parent = <&icu>;
interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
};

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* Marvell ODMI for MSI support
Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller
which can be used by on-board peripheral for MSI interrupts.
Required properties:
- compatible : The value here should contain:
"marvell,ap806-odmi-controller", "marvell,odmi-controller".
- interrupt,controller : Identifies the node as an interrupt controller.
- msi-controller : Identifies the node as an MSI controller.
- marvell,odmi-frames : Number of ODMI frames available. Each frame
provides a number of events.
- reg : List of register definitions, one for each
ODMI frame.
- marvell,spi-base : List of GIC base SPI interrupts, one for each
ODMI frame. Those SPI interrupts are 0-based,
i.e marvell,spi-base = <128> will use SPI #96.
See Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
for details about the GIC Device Tree binding.
Example:
odmi: odmi@300000 {
compatible = "marvell,ap806-odmi-controller",
"marvell,odmi-controller";
interrupt-controller;
msi-controller;
marvell,odmi-frames = <4>;
reg = <0x300000 0x4000>,
<0x304000 0x4000>,
<0x308000 0x4000>,
<0x30C000 0x4000>;
marvell,spi-base = <128>, <136>, <144>, <152>;
};

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Marvell Orion SoC interrupt controllers
* Main interrupt controller
Required properties:
- compatible: shall be "marvell,orion-intc"
- reg: base address(es) of interrupt registers starting with CAUSE register
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: number of cells to encode an interrupt source, shall be 1
The interrupt sources map to the corresponding bits in the interrupt
registers, i.e.
- 0 maps to bit 0 of first base address,
- 1 maps to bit 1 of first base address,
- 32 maps to bit 0 of second base address, and so on.
Example:
intc: interrupt-controller {
compatible = "marvell,orion-intc";
interrupt-controller;
#interrupt-cells = <1>;
/* Dove has 64 first level interrupts */
reg = <0x20200 0x10>, <0x20210 0x10>;
};
* Bridge interrupt controller
Required properties:
- compatible: shall be "marvell,orion-bridge-intc"
- reg: base address of bridge interrupt registers starting with CAUSE register
- interrupts: bridge interrupt of the main interrupt controller
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: number of cells to encode an interrupt source, shall be 1
Optional properties:
- marvell,#interrupts: number of interrupts provided by bridge interrupt
controller, defaults to 32 if not set
Example:
bridge_intc: interrupt-controller {
compatible = "marvell,orion-bridge-intc";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x20110 0x8>;
interrupts = <0>;
/* Dove bridge provides 5 interrupts */
marvell,#interrupts = <5>;
};

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Marvell SEI (System Error Interrupt) Controller
-----------------------------------------------
Marvell SEI (System Error Interrupt) controller is an interrupt
aggregator. It receives interrupts from several sources and aggregates
them to a single interrupt line (an SPI) on the parent interrupt
controller.
This interrupt controller can handle up to 64 SEIs, a set comes from the
AP and is wired while a second set comes from the CPs by the mean of
MSIs.
Required properties:
- compatible: should be one of:
* "marvell,ap806-sei"
- reg: SEI registers location and length.
- interrupts: identifies the parent IRQ that will be triggered.
- #interrupt-cells: number of cells to define an SEI wired interrupt
coming from the AP, should be 1. The cell is the IRQ
number.
- interrupt-controller: identifies the node as an interrupt controller
for AP interrupts.
- msi-controller: identifies the node as an MSI controller for the CPs
interrupts.
Example:
sei: interrupt-controller@3f0200 {
compatible = "marvell,ap806-sei";
reg = <0x3f0200 0x40>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
interrupt-controller;
msi-controller;
};

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/mediatek,mtk-cirq.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek System Interrupt Controller
maintainers:
- Youlin Pei <youlin.pei@mediatek.com>
description:
In MediaTek SoCs, the CIRQ is a low power interrupt controller designed to
work outside of MCUSYS which comprises with Cortex-Ax cores, CCI and GIC.
The external interrupts (outside MCUSYS) will feed through CIRQ and connect
to GIC in MCUSYS. When CIRQ is enabled, it will record the edge-sensitive
interrupts and generate a pulse signal to parent interrupt controller when
flush command is executed. With CIRQ, MCUSYS can be completely turned off
to improve the system power consumption without losing interrupts.
properties:
compatible:
items:
- enum:
- mediatek,mt2701-cirq
- mediatek,mt8135-cirq
- mediatek,mt8173-cirq
- mediatek,mt8192-cirq
- const: mediatek,mtk-cirq
reg:
maxItems: 1
'#interrupt-cells':
const: 3
interrupt-controller: true
mediatek,ext-irq-range:
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- description: First CIRQ interrupt
- description: Last CIRQ interrupt
description:
Identifies the range of external interrupts in different SoCs
required:
- compatible
- reg
- '#interrupt-cells'
- interrupt-controller
- mediatek,ext-irq-range
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
cirq: interrupt-controller@10204000 {
compatible = "mediatek,mt2701-cirq", "mediatek,mtk-cirq";
reg = <0x10204000 0x400>;
#interrupt-cells = <3>;
interrupt-controller;
interrupt-parent = <&sysirq>;
mediatek,ext-irq-range = <32 200>;
};

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MediaTek sysirq
MediaTek SOCs sysirq support controllable irq inverter for each GIC SPI
interrupt.
Required properties:
- compatible: should be
"mediatek,mt8516-sysirq", "mediatek,mt6577-sysirq": for MT8516
"mediatek,mt8183-sysirq", "mediatek,mt6577-sysirq": for MT8183
"mediatek,mt8173-sysirq", "mediatek,mt6577-sysirq": for MT8173
"mediatek,mt8135-sysirq", "mediatek,mt6577-sysirq": for MT8135
"mediatek,mt8127-sysirq", "mediatek,mt6577-sysirq": for MT8127
"mediatek,mt7622-sysirq", "mediatek,mt6577-sysirq": for MT7622
"mediatek,mt7623-sysirq", "mediatek,mt6577-sysirq": for MT7623
"mediatek,mt7629-sysirq", "mediatek,mt6577-sysirq": for MT7629
"mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq": for MT6795
"mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq": for MT6797
"mediatek,mt6779-sysirq", "mediatek,mt6577-sysirq": for MT6779
"mediatek,mt6765-sysirq", "mediatek,mt6577-sysirq": for MT6765
"mediatek,mt6755-sysirq", "mediatek,mt6577-sysirq": for MT6755
"mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq": for MT6592
"mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq": for MT6589
"mediatek,mt6582-sysirq", "mediatek,mt6577-sysirq": for MT6582
"mediatek,mt6580-sysirq", "mediatek,mt6577-sysirq": for MT6580
"mediatek,mt6577-sysirq": for MT6577
"mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq": for MT2712
"mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
- reg: Physical base address of the intpol registers and length of memory
mapped region. Could be multiple bases here. Ex: mt6797 needs 2 reg, others
need 1.
Example:
sysirq: intpol-controller@10200620 {
compatible = "mediatek,mt6797-sysirq",
"mediatek,mt6577-sysirq";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10220620 0 0x20>,
<0 0x10220690 0 0x10>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/microchip,eic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip External Interrupt Controller
maintainers:
- Claudiu Beznea <claudiu.beznea@microchip.com>
description:
This interrupt controller is found in Microchip SoCs (SAMA7G5) and provides
support for handling up to 2 external interrupt lines.
properties:
compatible:
enum:
- microchip,sama7g5-eic
reg:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
description:
The first cell is the input IRQ number (between 0 and 1), the second cell
is the trigger type as defined in interrupt.txt present in this directory.
interrupts:
description: |
Contains the GIC SPI IRQs mapped to the external interrupt lines. They
should be specified sequentially from output 0 to output 1.
minItems: 2
maxItems: 2
clocks:
maxItems: 1
clock-names:
const: pclk
required:
- compatible
- reg
- interrupt-controller
- '#interrupt-cells'
- interrupts
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/at91.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
eic: interrupt-controller@e1628000 {
compatible = "microchip,sama7g5-eic";
reg = <0xe1628000 0x100>;
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 37>;
clock-names = "pclk";
};
...

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Microchip PIC32 Interrupt Controller
====================================
The Microchip PIC32 contains an Enhanced Vectored Interrupt Controller (EVIC).
It handles all internal and external interrupts. This controller exists outside
of the CPU and is the arbitrator of all interrupts (including interrupts from
the CPU itself) before they are presented to the CPU.
External interrupts have a software configurable edge polarity. Non external
interrupts have a type and polarity that is determined by the source of the
interrupt.
Required properties
-------------------
- compatible: Should be "microchip,pic32mzda-evic"
- reg: Specifies physical base address and size of register range.
- interrupt-controller: Identifies the node as an interrupt controller.
- #interrupt cells: Specifies the number of cells used to encode an interrupt
source connected to this controller. The value shall be 2 and interrupt
descriptor shall have the following format:
<hw_irq irq_type>
hw_irq - represents the hardware interrupt number as in the data sheet.
irq_type - is used to describe the type and polarity of an interrupt. For
internal interrupts use IRQ_TYPE_EDGE_RISING for non persistent interrupts and
IRQ_TYPE_LEVEL_HIGH for persistent interrupts. For external interrupts use
IRQ_TYPE_EDGE_RISING or IRQ_TYPE_EDGE_FALLING to select the desired polarity.
Optional properties
-------------------
- microchip,external-irqs: u32 array of external interrupts with software
polarity configuration. This array corresponds to the bits in the INTCON
SFR.
Example
-------
evic: interrupt-controller@1f810000 {
compatible = "microchip,pic32mzda-evic";
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1f810000 0x1000>;
microchip,external-irqs = <3 8 13 18 23>;
};
Each device/peripheral must request its interrupt line with the associated type
and polarity.
Internal interrupt DTS snippet
------------------------------
device@1f800000 {
...
interrupts = <113 IRQ_TYPE_LEVEL_HIGH>;
...
};
External interrupt DTS snippet
------------------------------
device@1f800000 {
...
interrupts = <3 IRQ_TYPE_EDGE_RISING>;
...
};

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# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/mrvl,intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell MMP/Orion Interrupt controller bindings
maintainers:
- Andrew Lunn <andrew@lunn.ch>
- Gregory Clement <gregory.clement@bootlin.com>
allOf:
- if:
properties:
compatible:
not:
contains:
const: marvell,orion-intc
then:
required:
- mrvl,intc-nr-irqs
- if:
properties:
compatible:
contains:
enum:
- mrvl,mmp-intc
- mrvl,mmp2-intc
then:
properties:
reg:
maxItems: 1
- if:
properties:
compatible:
contains:
enum:
- marvell,mmp3-intc
- mrvl,mmp2-mux-intc
then:
properties:
reg:
minItems: 2
- if:
properties:
compatible:
contains:
const: mrvl,mmp2-mux-intc
then:
properties:
interrupts:
maxItems: 1
reg-names:
items:
- const: 'mux status'
- const: 'mux mask'
required:
- interrupts
else:
properties:
interrupts: false
properties:
'#interrupt-cells':
const: 1
compatible:
enum:
- mrvl,mmp-intc
- mrvl,mmp2-intc
- marvell,mmp3-intc
- marvell,orion-intc
- mrvl,mmp2-mux-intc
reg:
minItems: 1
maxItems: 2
reg-names: true
interrupts: true
interrupt-controller: true
mrvl,intc-nr-irqs:
description: |
Specifies the number of interrupts in the interrupt controller.
$ref: /schemas/types.yaml#/definitions/uint32
mrvl,clr-mfp-irq:
description: |
Specifies the interrupt that needs to clear MFP edge detection first.
$ref: /schemas/types.yaml#/definitions/uint32
required:
- '#interrupt-cells'
- compatible
- reg
- interrupt-controller
additionalProperties: false
examples:
- |
interrupt-controller@d4282000 {
compatible = "mrvl,mmp2-intc";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xd4282000 0x1000>;
mrvl,intc-nr-irqs = <64>;
};
interrupt-controller@d4282150 {
compatible = "mrvl,mmp2-mux-intc";
interrupts = <4>;
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x150 0x4>, <0x168 0x4>;
reg-names = "mux status", "mux mask";
mrvl,intc-nr-irqs = <2>;
};
- |
interrupt-controller@fed20204 {
compatible = "marvell,orion-intc";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xfed20204 0x04>,
<0xfed20214 0x04>;
};
...

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Microsemi Ocelot SoC ICPU Interrupt Controller
maintainers:
- Alexandre Belloni <alexandre.belloni@bootlin.com>
allOf:
- $ref: /schemas/interrupt-controller.yaml#
description: |
the Microsemi Ocelot interrupt controller that is part of the
ICPU. It is connected directly to the MIPS core interrupt
controller.
properties:
compatible:
items:
- enum:
- mscc,jaguar2-icpu-intr
- mscc,luton-icpu-intr
- mscc,ocelot-icpu-intr
- mscc,serval-icpu-intr
'#interrupt-cells':
const: 1
'#address-cells':
const: 0
interrupt-controller: true
reg:
maxItems: 1
interrupts:
maxItems: 1
required:
- compatible
- '#interrupt-cells'
- '#address-cells'
- interrupt-controller
- reg
additionalProperties: false
examples:
- |
intc: interrupt-controller@70000070 {
compatible = "mscc,ocelot-icpu-intr";
reg = <0x70000070 0x70>;
#interrupt-cells = <1>;
#address-cells = <0>;
interrupt-controller;
interrupt-parent = <&cpuintc>;
interrupts = <2>;
};
...

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/msi-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MSI controller
maintainers:
- Marc Zyngier <maz@kernel.org>
description: |
An MSI controller signals interrupts to a CPU when a write is made
to an MMIO address by some master. An MSI controller may feature a
number of doorbells.
properties:
"#msi-cells":
description: |
The number of cells in an msi-specifier, required if not zero.
Typically this will encode information related to sideband data,
and will not encode doorbells or payloads as these can be
configured dynamically.
The meaning of the msi-specifier is defined by the device tree
binding of the specific MSI controller.
enum: [0, 1]
msi-controller:
description:
Identifies the node as an MSI controller.
$ref: /schemas/types.yaml#/definitions/flag
msi-ranges:
description:
A list of <phandle intspec span> tuples, where "phandle" is the
parent interrupt controller, "intspec" is the starting/base
interrupt specifier and "span" is the size of the
range. Multiple ranges can be provided.
$ref: /schemas/types.yaml#/definitions/phandle-array
dependencies:
"#msi-cells": [ msi-controller ]
additionalProperties: true

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This document describes the generic device tree binding for MSI controllers and
their master(s).
Message Signaled Interrupts (MSIs) are a class of interrupts generated by a
write to an MMIO address.
MSIs were originally specified by PCI (and are used with PCIe), but may also be
used with other busses, and hence a mechanism is required to relate devices on
those busses to the MSI controllers which they are capable of using,
potentially including additional information.
MSIs are distinguished by some combination of:
- The doorbell (the MMIO address written to).
Devices may be configured by software to write to arbitrary doorbells which
they can address. An MSI controller may feature a number of doorbells.
- The payload (the value written to the doorbell).
Devices may be configured to write an arbitrary payload chosen by software.
MSI controllers may have restrictions on permitted payloads.
- Sideband information accompanying the write.
Typically this is neither configurable nor probeable, and depends on the path
taken through the memory system (i.e. it is a property of the combination of
MSI controller and device rather than a property of either in isolation).
MSI controllers:
================
An MSI controller signals interrupts to a CPU when a write is made to an MMIO
address by some master. An MSI controller may feature a number of doorbells.
Required properties:
--------------------
- msi-controller: Identifies the node as an MSI controller.
Optional properties:
--------------------
- #msi-cells: The number of cells in an msi-specifier, required if not zero.
Typically this will encode information related to sideband data, and will
not encode doorbells or payloads as these can be configured dynamically.
The meaning of the msi-specifier is defined by the device tree binding of
the specific MSI controller.
MSI clients
===========
MSI clients are devices which generate MSIs. For each MSI they wish to
generate, the doorbell and payload may be configured, though sideband
information may not be configurable.
Required properties:
--------------------
- msi-parent: A list of phandle + msi-specifier pairs, one for each MSI
controller which the device is capable of using.
This property is unordered, and MSIs may be allocated from any combination of
MSI controllers listed in the msi-parent property.
If a device has restrictions on the allocation of MSIs, these restrictions
must be described with additional properties.
When #msi-cells is non-zero, busses with an msi-parent will require
additional properties to describe the relationship between devices on the bus
and the set of MSIs they can potentially generate.
Example
=======
/ {
#address-cells = <1>;
#size-cells = <1>;
msi_a: msi-controller@a {
reg = <0xa 0xf00>;
compatible = "vendor-a,some-controller";
msi-controller;
/* No sideband data, so #msi-cells omitted */
};
msi_b: msi-controller@b {
reg = <0xb 0xf00>;
compatible = "vendor-b,another-controller";
msi-controller;
/* Each device has some unique ID */
#msi-cells = <1>;
};
msi_c: msi-controller@c {
reg = <0xc 0xf00>;
compatible = "vendor-b,another-controller";
msi-controller;
/* Each device has some unique ID */
#msi-cells = <1>;
};
dev@0 {
reg = <0x0 0xf00>;
compatible = "vendor-c,some-device";
/* Can only generate MSIs to msi_a */
msi-parent = <&msi_a>;
};
dev@1 {
reg = <0x1 0xf00>;
compatible = "vendor-c,some-device";
/*
* Can generate MSIs to either A or B.
*/
msi-parent = <&msi_a>, <&msi_b 0x17>;
};
dev@2 {
reg = <0x2 0xf00>;
compatible = "vendor-c,some-device";
/*
* Has different IDs at each MSI controller.
* Can generate MSIs to all of the MSI controllers.
*/
msi-parent = <&msi_a>, <&msi_b 0x17>, <&msi_c 0x53>;
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/mstar,mst-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MStar Interrupt Controller
maintainers:
- Mark-PK Tsai <mark-pk.tsai@mediatek.com>
description: |+
MStar, SigmaStar and Mediatek TV SoCs contain multiple legacy
interrupt controllers that routes interrupts to the GIC.
The HW block exposes a number of interrupt controllers, each
can support up to 64 interrupts.
properties:
compatible:
const: mstar,mst-intc
interrupt-controller: true
"#interrupt-cells":
const: 3
description: |
Use the same format as specified by GIC in arm,gic.yaml.
reg:
maxItems: 1
mstar,irqs-map-range:
description: |
The range <start, end> of parent interrupt controller's interrupt
lines that are hardwired to mstar interrupt controller.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
items:
minItems: 2
maxItems: 2
mstar,intc-no-eoi:
description:
Mark this controller has no End Of Interrupt(EOI) implementation.
type: boolean
required:
- compatible
- reg
- mstar,irqs-map-range
additionalProperties: false
examples:
- |
mst_intc0: interrupt-controller@1f2032d0 {
compatible = "mstar,mst-intc";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0x1f2032d0 0x30>;
mstar,irqs-map-range = <0 63>;
};
...

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/mti,cpu-interrupt-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MIPS CPU Interrupt Controller
description: >
On MIPS the mips_cpu_irq_of_init() helper can be used to initialize the 8 CPU
IRQs from a devicetree file and create a irq_domain for IRQ controller.
With the irq_domain in place we can describe how the 8 IRQs are wired to the
platforms internal interrupt controller cascade.
maintainers:
- Thomas Bogendoerfer <tsbogend@alpha.franken.de>
properties:
compatible:
const: mti,cpu-interrupt-controller
'#interrupt-cells':
const: 1
'#address-cells':
const: 0
interrupt-controller: true
additionalProperties: false
required:
- compatible
- '#interrupt-cells'
- '#address-cells'
- interrupt-controller
examples:
- |
interrupt-controller {
compatible = "mti,cpu-interrupt-controller";
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};

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# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MIPS Global Interrupt Controller
maintainers:
- Paul Burton <paulburton@kernel.org>
- Thomas Bogendoerfer <tsbogend@alpha.franken.de>
description: |
The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
It also supports local (per-processor) interrupts and software-generated
interrupts which can be used as IPIs. The GIC also includes a free-running
global timer, per-CPU count/compare timers, and a watchdog.
properties:
compatible:
const: mti,gic
"#interrupt-cells":
const: 3
description: |
The 1st cell is the type of interrupt: local or shared defined in the
file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the
GIC interrupt number. The 3d cell encodes the interrupt flags setting up
the IRQ trigger modes, which are defined in the file
'dt-bindings/interrupt-controller/irq.h'.
reg:
description: |
Base address and length of the GIC registers space. If not present,
the base address reported by the hardware GCR_GIC_BASE will be used.
maxItems: 1
interrupt-controller: true
mti,reserved-cpu-vectors:
description: |
Specifies the list of CPU interrupt vectors to which the GIC may not
route interrupts. This property is ignored if the CPU is started in EIC
mode.
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 6
uniqueItems: true
items:
minimum: 2
maximum: 7
mti,reserved-ipi-vectors:
description: |
Specifies the range of GIC interrupts that are reserved for IPIs.
It accepts two values: the 1st is the starting interrupt and the 2nd is
the size of the reserved range. If not specified, the driver will
allocate the last (2 * number of VPEs in the system).
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- minimum: 0
maximum: 254
- minimum: 2
maximum: 254
timer:
type: object
description: |
MIPS GIC includes a free-running global timer, per-CPU count/compare
timers, and a watchdog. Currently only the GIC Timer is supported.
properties:
compatible:
const: mti,gic-timer
interrupts:
description: |
Interrupt for the GIC local timer, so normally it's suppose to be of
<GIC_LOCAL X IRQ_TYPE_NONE> format.
maxItems: 1
clocks:
maxItems: 1
clock-frequency: true
required:
- compatible
- interrupts
oneOf:
- required:
- clocks
- required:
- clock-frequency
additionalProperties: false
additionalProperties: false
required:
- compatible
- "#interrupt-cells"
- interrupt-controller
examples:
- |
#include <dt-bindings/interrupt-controller/mips-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
interrupt-controller@1bdc0000 {
compatible = "mti,gic";
reg = <0x1bdc0000 0x20000>;
interrupt-controller;
#interrupt-cells = <3>;
mti,reserved-cpu-vectors = <7>;
mti,reserved-ipi-vectors = <40 8>;
timer {
compatible = "mti,gic-timer";
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
clock-frequency = <50000000>;
};
};
- |
#include <dt-bindings/interrupt-controller/mips-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
interrupt-controller@1bdc0000 {
compatible = "mti,gic";
reg = <0x1bdc0000 0x20000>;
interrupt-controller;
#interrupt-cells = <3>;
timer {
compatible = "mti,gic-timer";
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
clocks = <&cpu_pll>;
};
};
- |
interrupt-controller {
compatible = "mti,gic";
interrupt-controller;
#interrupt-cells = <3>;
};
...

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/nuvoton,wpcm450-aic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Nuvoton WPCM450 Advanced Interrupt Controller bindings
maintainers:
- Jonathan Neuschäfer <j.neuschaefer@gmx.net>
properties:
'#interrupt-cells':
const: 2
compatible:
const: nuvoton,wpcm450-aic
interrupt-controller: true
reg:
maxItems: 1
additionalProperties: false
required:
- '#interrupt-cells'
- compatible
- reg
- interrupt-controller
examples:
- |
aic: interrupt-controller@b8002000 {
compatible = "nuvoton,wpcm450-aic";
reg = <0xb8002000 0x1000>;
interrupt-controller;
#interrupt-cells = <2>;
};

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NVIDIA Legacy Interrupt Controller
All Tegra SoCs contain a legacy interrupt controller that routes
interrupts to the GIC, and also serves as a wakeup source. It is also
referred to as "ictlr", hence the name of the binding.
The HW block exposes a number of interrupt controllers, each
implementing a set of 32 interrupts.
Required properties:
- compatible : should be: "nvidia,tegra<chip>-ictlr". The LIC on
subsequent SoCs remained backwards-compatible with Tegra30, so on
Tegra generations later than Tegra30 the compatible value should
include "nvidia,tegra30-ictlr".
- reg : Specifies base physical address and size of the registers.
Each controller must be described separately (Tegra20 has 4 of them,
whereas Tegra30 and later have 5).
- interrupt-controller : Identifies the node as an interrupt controller.
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value must be 3.
Notes:
- Because this HW ultimately routes interrupts to the GIC, the
interrupt specifier must be that of the GIC.
- Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs
are explicitly forbidden.
Example:
ictlr: interrupt-controller@60004000 {
compatible = "nvidia,tegra20-ictlr", "nvidia,tegra-ictlr";
reg = <0x60004000 64>,
<0x60004100 64>,
<0x60004200 64>,
<0x60004300 64>;
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&intc>;
};

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* NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers
Required properties:
- compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic".
- reg: should contain IC registers location and length.
- interrupt-controller: identifies the node as an interrupt controller.
- #interrupt-cells: the number of cells to define an interrupt, should be 2.
The first cell is the IRQ number, the second cell is used to specify
one of the supported IRQ types:
IRQ_TYPE_EDGE_RISING = low-to-high edge triggered,
IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered,
IRQ_TYPE_LEVEL_HIGH = active high level-sensitive,
IRQ_TYPE_LEVEL_LOW = active low level-sensitive.
Reset value is IRQ_TYPE_LEVEL_LOW.
Optional properties:
- interrupts: empty for MIC interrupt controller, cascaded MIC
hardware interrupts for SIC1 and SIC2
Examples:
/* LPC32xx MIC, SIC1 and SIC2 interrupt controllers */
mic: interrupt-controller@40008000 {
compatible = "nxp,lpc3220-mic";
reg = <0x40008000 0x4000>;
interrupt-controller;
#interrupt-cells = <2>;
};
sic1: interrupt-controller@4000c000 {
compatible = "nxp,lpc3220-sic";
reg = <0x4000c000 0x4000>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&mic>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
<30 IRQ_TYPE_LEVEL_LOW>;
};
sic2: interrupt-controller@40010000 {
compatible = "nxp,lpc3220-sic";
reg = <0x40010000 0x4000>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&mic>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
<31 IRQ_TYPE_LEVEL_LOW>;
};
/* ADC */
adc@40048000 {
compatible = "nxp,lpc3220-adc";
reg = <0x40048000 0x1000>;
interrupt-parent = <&sic1>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
};

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* Open PIC Binding
This binding specifies what properties must be available in the device tree
representation of an Open PIC compliant interrupt controller. This binding is
based on the binding defined for Open PIC in [1] and is a superset of that
binding.
Required properties:
NOTE: Many of these descriptions were paraphrased here from [1] to aid
readability.
- compatible: Specifies the compatibility list for the PIC. The type
shall be <string> and the value shall include "open-pic".
- reg: Specifies the base physical address(s) and size(s) of this
PIC's addressable register space. The type shall be <prop-encoded-array>.
- interrupt-controller: The presence of this property identifies the node
as an Open PIC. No property value shall be defined.
- #interrupt-cells: Specifies the number of cells needed to encode an
interrupt source. The type shall be a <u32> and the value shall be 2.
- #address-cells: Specifies the number of cells needed to encode an
address. The type shall be <u32> and the value shall be 0. As such,
'interrupt-map' nodes do not have to specify a parent unit address.
Optional properties:
- pic-no-reset: The presence of this property indicates that the PIC
shall not be reset during runtime initialization. No property value shall
be defined. The presence of this property also mandates that any
initialization related to interrupt sources shall be limited to sources
explicitly referenced in the device tree.
* Interrupt Specifier Definition
Interrupt specifiers consists of 2 cells encoded as
follows:
- <1st-cell>: The interrupt-number that identifies the interrupt source.
- <2nd-cell>: The level-sense information, encoded as follows:
0 = low-to-high edge triggered
1 = active low level-sensitive
2 = active high level-sensitive
3 = high-to-low edge triggered
* Examples
Example 1:
/*
* An Open PIC interrupt controller
*/
mpic: pic@40000 {
// This is an interrupt controller node.
interrupt-controller;
// No address cells so that 'interrupt-map' nodes which reference
// this Open PIC node do not need a parent address specifier.
#address-cells = <0>;
// Two cells to encode interrupt sources.
#interrupt-cells = <2>;
// Offset address of 0x40000 and size of 0x40000.
reg = <0x40000 0x40000>;
// Compatible with Open PIC.
compatible = "open-pic";
// The PIC shall not be reset.
pic-no-reset;
};
Example 2:
/*
* An interrupt generating device that is wired to an Open PIC.
*/
serial0: serial@4500 {
// Interrupt source '42' that is active high level-sensitive.
// Note that there are only two cells as specified in the interrupt
// parent's '#interrupt-cells' property.
interrupts = <42 2>;
// The interrupt controller that this device is wired to.
interrupt-parent = <&mpic>;
};
* References
[1] Devicetree Specification
(https://www.devicetree.org/specifications/)

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OpenRISC 1000 Programmable Interrupt Controller
Required properties:
- compatible : should be "opencores,or1k-pic-level" for variants with
level triggered interrupt lines, "opencores,or1k-pic-edge" for variants with
edge triggered interrupt lines or "opencores,or1200-pic" for machines
with the non-spec compliant or1200 type implementation.
"opencores,or1k-pic" is also provided as an alias to "opencores,or1200-pic",
but this is only for backwards compatibility.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value shall be 1.
Example:
intc: interrupt-controller {
compatible = "opencores,or1k-pic-level";
interrupt-controller;
#interrupt-cells = <1>;
};

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Open Multi-Processor Interrupt Controller
Required properties:
- compatible : This should be "openrisc,ompic"
- reg : Specifies base physical address and size of the register space. The
size is based on the number of cores the controller has been configured
to handle, this should be set to 8 bytes per cpu core.
- interrupt-controller : Identifies the node as an interrupt controller.
- #interrupt-cells : This should be set to 0 as this will not be an irq
parent.
- interrupts : Specifies the interrupt line to which the ompic is wired.
Example:
ompic: interrupt-controller@98000000 {
compatible = "openrisc,ompic";
reg = <0x98000000 16>;
interrupt-controller;
#interrupt-cells = <0>;
interrupts = <1>;
};

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Binding for Qualcomm Atheros AR7xxx/AR9XXX CPU interrupt controller
On most SoC the IRQ controller need to flush the DDR FIFO before running
the interrupt handler of some devices. This is configured using the
qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
Required Properties:
- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-cpu-intc"
as fallback
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode interrupt
source, should be 1 for intc
Please refer to interrupts.txt in this directory for details of the common
Interrupt Controllers bindings used by client devices.
Optional Properties:
- qca,ddr-wb-channel-interrupts: List of the interrupts needing a write
buffer flush
- qca,ddr-wb-channels: List of phandles to the write buffer channels for
each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt
default to the entry's index.
Example:
interrupt-controller {
compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
<&ddr_ctrl 0>, <&ddr_ctrl 1>;
};
...
ddr_ctrl: memory-controller@18000000 {
...
#qca,ddr-wb-channel-cells = <1>;
};

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Binding for Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller
The MISC interrupt controller is a secondary controller for lower priority
interrupt.
Required Properties:
- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or
"qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc"
- reg: Base address and size of the controllers memory area
- interrupts: Interrupt specifier for the controllers interrupt.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode interrupt
source, should be 1
Compatible fallback depends on the SoC. Use ar7100 for ar71xx and ar913x,
use ar7240 for all other SoCs.
Please refer to interrupts.txt in this directory for details of the common
Interrupt Controllers bindings used by client devices.
Example:
interrupt-controller@18060010 {
compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc";
reg = <0x18060010 0x4>;
interrupt-parent = <&cpuintc>;
interrupts = <6>;
interrupt-controller;
#interrupt-cells = <1>;
};
Another example:
interrupt-controller@18060010 {
compatible = "qca,ar9331-misc-intc", qca,ar7240-misc-intc";
reg = <0x18060010 0x4>;
interrupt-parent = <&cpuintc>;
interrupts = <6>;
interrupt-controller;
#interrupt-cells = <1>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/qcom,mpm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcom MPM Interrupt Controller
maintainers:
- Shawn Guo <shawn.guo@linaro.org>
description:
Qualcomm Technologies Inc. SoCs based on the RPM architecture have a
MSM Power Manager (MPM) that is in always-on domain. In addition to managing
resources during sleep, the hardware also has an interrupt controller that
monitors the interrupts when the system is asleep, wakes up the APSS when
one of these interrupts occur and replays it to GIC interrupt controller
after GIC becomes operational.
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
compatible:
items:
- const: qcom,mpm
reg:
maxItems: 1
description:
Specifies the base address and size of vMPM registers in RPM MSG RAM.
interrupts:
maxItems: 1
description:
Specify the IRQ used by RPM to wakeup APSS.
mboxes:
maxItems: 1
description:
Specify the mailbox used to notify RPM for writing vMPM registers.
interrupt-controller: true
'#interrupt-cells':
const: 2
description:
The first cell is the MPM pin number for the interrupt, and the second
is the trigger type.
qcom,mpm-pin-count:
description:
Specify the total MPM pin count that a SoC supports.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,mpm-pin-map:
description:
A set of MPM pin numbers and the corresponding GIC SPIs.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
items:
items:
- description: MPM pin number
- description: GIC SPI number for the MPM pin
required:
- compatible
- reg
- interrupts
- mboxes
- interrupt-controller
- '#interrupt-cells'
- qcom,mpm-pin-count
- qcom,mpm-pin-map
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
mpm: interrupt-controller@45f01b8 {
compatible = "qcom,mpm";
interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
reg = <0x45f01b8 0x1000>;
mboxes = <&apcs_glb 1>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
qcom,mpm-pin-count = <96>;
qcom,mpm-pin-map = <2 275>,
<5 296>,
<12 422>,
<24 79>,
<86 183>,
<90 260>,
<91 260>;
};

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/qcom,pdc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: PDC interrupt controller
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a
Power Domain Controller (PDC) that is on always-on domain. In addition to
providing power control for the power domains, the hardware also has an
interrupt controller that can be used to help detect edge low interrupts as
well detect interrupts when the GIC is non-operational.
GIC is parent interrupt controller at the highest level. Platform interrupt
controller PDC is next in hierarchy, followed by others. Drivers requiring
wakeup capabilities of their device interrupts routed through the PDC, must
specify PDC as their interrupt controller and request the PDC port associated
with the GIC interrupt. See example below.
properties:
compatible:
items:
- enum:
- qcom,sc7180-pdc
- qcom,sc7280-pdc
- qcom,sdm845-pdc
- qcom,sm6350-pdc
- qcom,sm8150-pdc
- qcom,sm8250-pdc
- qcom,sm8350-pdc
- const: qcom,pdc
reg:
minItems: 1
items:
- description: PDC base register region
- description: Edge or Level config register for SPI interrupts
'#interrupt-cells':
const: 2
interrupt-controller: true
qcom,pdc-ranges:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
minItems: 1
maxItems: 32 # no hard limit
items:
items:
- description: starting PDC port
- description: GIC hwirq number for the PDC port
- description: number of interrupts in sequence
description: |
Specifies the PDC pin offset and the number of PDC ports.
The tuples indicates the valid mapping of valid PDC ports
and their hwirq mapping.
required:
- compatible
- reg
- '#interrupt-cells'
- interrupt-controller
- qcom,pdc-ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
pdc: interrupt-controller@b220000 {
compatible = "qcom,sdm845-pdc", "qcom,pdc";
reg = <0xb220000 0x30000>;
qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupt-controller;
};
wake-device {
interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/rda,8810pl-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: RDA Micro RDA8810PL interrupt controller
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
compatible:
const: rda,8810pl-intc
reg:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
required:
- compatible
- reg
- interrupt-controller
- '#interrupt-cells'
additionalProperties: false
examples:
- |
intc: interrupt-controller@0 {
compatible = "rda,8810pl-intc";
reg = <0x0 0x1000>;
interrupt-controller;
#interrupt-cells = <2>;
};
...

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/realtek,rtl-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Realtek RTL SoC interrupt controller devicetree bindings
description:
Interrupt controller and router for Realtek MIPS SoCs, allowing each SoC
interrupt to be routed to one parent CPU (hardware) interrupt, or left
disconnected.
All connected input lines from SoC peripherals can be masked individually,
and an interrupt status register is present to indicate which interrupts are
pending.
maintainers:
- Birger Koblitz <mail@birger-koblitz.de>
- Bert Vermeulen <bert@biot.com>
- John Crispin <john@phrozen.org>
properties:
compatible:
oneOf:
- items:
- enum:
- realtek,rtl8380-intc
- const: realtek,rtl-intc
- const: realtek,rtl-intc
deprecated: true
"#interrupt-cells":
description:
SoC interrupt line index.
const: 1
reg:
maxItems: 1
interrupts:
minItems: 1
maxItems: 15
description:
List of parent interrupts, in the order that they are connected to this
interrupt router's outputs, starting at the first output.
interrupt-controller: true
interrupt-map:
deprecated: true
description: Describes mapping from SoC interrupts to CPU interrupts
required:
- compatible
- reg
- "#interrupt-cells"
- interrupt-controller
allOf:
- if:
properties:
compatible:
const: realtek,rtl-intc
then:
properties:
"#address-cells":
const: 0
required:
- "#address-cells"
- interrupt-map
else:
required:
- interrupts
additionalProperties: false
examples:
- |
interrupt-controller@3000 {
compatible = "realtek,rtl8380-intc", "realtek,rtl-intc";
#interrupt-cells = <1>;
interrupt-controller;
reg = <0x3000 0x18>;
interrupt-parent = <&cpuintc>;
interrupts = <2>, <3>, <4>, <5>, <6>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/renesas,intc-irqpin.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas Interrupt Controller (INTC) for external pins
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
properties:
compatible:
items:
- enum:
- renesas,intc-irqpin-r8a7740 # R-Mobile A1
- renesas,intc-irqpin-r8a7778 # R-Car M1A
- renesas,intc-irqpin-r8a7779 # R-Car H1
- renesas,intc-irqpin-sh73a0 # SH-Mobile AG5
- const: renesas,intc-irqpin
reg:
minItems: 5
items:
- description: Interrupt control register
- description: Interrupt priority register
- description: Interrupt source register
- description: Interrupt mask register
- description: Interrupt mask clear register
- description: Interrupt control register for ICR0 with IRLM0 bit
interrupt-controller: true
'#interrupt-cells':
const: 2
interrupts:
minItems: 1
maxItems: 8
sense-bitfield-width:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [2, 4]
default: 4
description:
Width of a single sense bitfield in the SENSE register, if different from the
default.
control-parent:
type: boolean
description:
Disable and enable interrupts on the parent interrupt controller, needed for some
broken implementations.
clocks:
maxItems: 1
power-domains:
maxItems: 1
required:
- compatible
- reg
- interrupt-controller
- '#interrupt-cells'
- interrupts
if:
properties:
compatible:
contains:
enum:
- renesas,intc-irqpin-r8a7740
- renesas,intc-irqpin-sh73a0
then:
required:
- clocks
- power-domains
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/r8a7740-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
irqpin1: interrupt-controller@e6900004 {
compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
reg = <0xe6900004 4>,
<0xe6900014 4>,
<0xe6900024 1>,
<0xe6900044 1>,
<0xe6900064 1>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
power-domains = <&pd_a4s>;
};

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/renesas,irqc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: DT bindings for the R-Mobile/R-Car/RZ/G interrupt controller
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
properties:
compatible:
items:
- enum:
- renesas,irqc-r8a73a4 # R-Mobile APE6
- renesas,irqc-r8a7742 # RZ/G1H
- renesas,irqc-r8a7743 # RZ/G1M
- renesas,irqc-r8a7744 # RZ/G1N
- renesas,irqc-r8a7745 # RZ/G1E
- renesas,irqc-r8a77470 # RZ/G1C
- renesas,irqc-r8a7790 # R-Car H2
- renesas,irqc-r8a7791 # R-Car M2-W
- renesas,irqc-r8a7792 # R-Car V2H
- renesas,irqc-r8a7793 # R-Car M2-N
- renesas,irqc-r8a7794 # R-Car E2
- renesas,intc-ex-r8a774a1 # RZ/G2M
- renesas,intc-ex-r8a774b1 # RZ/G2N
- renesas,intc-ex-r8a774c0 # RZ/G2E
- renesas,intc-ex-r8a774e1 # RZ/G2H
- renesas,intc-ex-r8a7795 # R-Car H3
- renesas,intc-ex-r8a7796 # R-Car M3-W
- renesas,intc-ex-r8a77961 # R-Car M3-W+
- renesas,intc-ex-r8a77965 # R-Car M3-N
- renesas,intc-ex-r8a77970 # R-Car V3M
- renesas,intc-ex-r8a77980 # R-Car V3H
- renesas,intc-ex-r8a77990 # R-Car E3
- renesas,intc-ex-r8a77995 # R-Car D3
- renesas,intc-ex-r8a779a0 # R-Car V3U
- renesas,intc-ex-r8a779g0 # R-Car V4H
- const: renesas,irqc
'#interrupt-cells':
# an interrupt index and flags, as defined in interrupts.txt in
# this directory
const: 2
interrupt-controller: true
reg:
maxItems: 1
interrupts:
minItems: 1
maxItems: 32
clocks:
maxItems: 1
power-domains:
maxItems: 1
resets:
maxItems: 1
required:
- compatible
- '#interrupt-cells'
- interrupt-controller
- reg
- interrupts
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/r8a7790-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
irqc0: interrupt-controller@e61c0000 {
compatible = "renesas,irqc-r8a7790", "renesas,irqc";
#interrupt-cells = <2>;
interrupt-controller;
reg = <0xe61c0000 0x200>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 407>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/renesas,rza1-irqc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/A1 Interrupt Controller
maintainers:
- Chris Brandt <chris.brandt@renesas.com>
- Geert Uytterhoeven <geert+renesas@glider.be>
description: |
The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas RZ/A1 and
RZ/A2 SoCs:
- IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI interrupts,
- NMI edge select.
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
compatible:
items:
- enum:
- renesas,r7s72100-irqc # RZ/A1H
- renesas,r7s9210-irqc # RZ/A2M
- const: renesas,rza1-irqc
'#interrupt-cells':
const: 2
'#address-cells':
const: 0
interrupt-controller: true
reg:
maxItems: 1
interrupt-map:
maxItems: 8
description: Specifies the mapping from external interrupts to GIC interrupts.
interrupt-map-mask:
items:
- const: 7
- const: 0
required:
- compatible
- '#interrupt-cells'
- '#address-cells'
- interrupt-controller
- reg
- interrupt-map
- interrupt-map-mask
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
irqc: interrupt-controller@fcfef800 {
compatible = "renesas,r7s72100-irqc", "renesas,rza1-irqc";
#interrupt-cells = <2>;
#address-cells = <0>;
interrupt-controller;
reg = <0xfcfef800 0x6>;
interrupt-map =
<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <7 0>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55)
maintainers:
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
- Geert Uytterhoeven <geert+renesas@glider.be>
description: |
IA55 performs various interrupt controls including synchronization for the external
interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral
interrupts output by each IP. And it notifies the interrupt to the GIC
- IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts
- GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts
- NMI edge select (NMI is not treated as NMI exception and supports fall edge and
stand-up edge detection interrupts)
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
compatible:
items:
- enum:
- renesas,r9a07g044-irqc # RZ/G2{L,LC}
- renesas,r9a07g054-irqc # RZ/V2L
- const: renesas,rzg2l-irqc
'#interrupt-cells':
description: The first cell should contain external interrupt number (IRQ0-7) and the
second cell is used to specify the flag.
const: 2
'#address-cells':
const: 0
interrupt-controller: true
reg:
maxItems: 1
interrupts:
maxItems: 41
clocks:
maxItems: 2
clock-names:
items:
- const: clk
- const: pclk
power-domains:
maxItems: 1
resets:
maxItems: 1
required:
- compatible
- '#interrupt-cells'
- '#address-cells'
- interrupt-controller
- reg
- interrupts
- clocks
- clock-names
- power-domains
- resets
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/r9a07g044-cpg.h>
irqc: interrupt-controller@110a0000 {
compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc";
reg = <0x110a0000 0x10000>;
#interrupt-cells = <2>;
#address-cells = <0>;
interrupt-controller;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
<&cpg CPG_MOD R9A07G044_IA55_PCLK>;
clock-names = "clk", "pclk";
power-domains = <&cpg>;
resets = <&cpg R9A07G044_IA55_RESETN>;
};

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RISC-V Hart-Level Interrupt Controller (HLIC)
---------------------------------------------
RISC-V cores include Control Status Registers (CSRs) which are local to each
CPU core (HART in RISC-V terminology) and can be read or written by software.
Some of these CSRs are used to control local interrupts connected to the core.
Every interrupt is ultimately routed through a hart's HLIC before it
interrupts that hart.
The RISC-V supervisor ISA manual specifies three interrupt sources that are
attached to every HLIC: software interrupts, the timer interrupt, and external
interrupts. Software interrupts are used to send IPIs between cores. The
timer interrupt comes from an architecturally mandated real-time timer that is
controlled via Supervisor Binary Interface (SBI) calls and CSR reads. External
interrupts connect all other device interrupts to the HLIC, which are routed
via the platform-level interrupt controller (PLIC).
All RISC-V systems that conform to the supervisor ISA specification are
required to have a HLIC with these three interrupt sources present. Since the
interrupt map is defined by the ISA it's not listed in the HLIC's device tree
entry, though external interrupt controllers (like the PLIC, for example) will
need to define how their interrupts map to the relevant HLICs. This means
a PLIC interrupt property will typically list the HLICs for all present HARTs
in the system.
Required properties:
- compatible : "riscv,cpu-intc"
- #interrupt-cells : should be <1>. The interrupt sources are defined by the
RISC-V supervisor ISA manual, with only the following three interrupts being
defined for supervisor mode:
- Source 1 is the supervisor software interrupt, which can be sent by an SBI
call and is reserved for use by software.
- Source 5 is the supervisor timer interrupt, which can be configured by
SBI calls and implements a one-shot timer.
- Source 9 is the supervisor external interrupt, which chains to all other
device interrupts.
- interrupt-controller : Identifies the node as an interrupt controller
Furthermore, this interrupt-controller MUST be embedded inside the cpu
definition of the hart whose CSRs control these local interrupts.
An example device tree entry for a HLIC is show below.
cpu1: cpu@1 {
compatible = "riscv";
...
cpu1-intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "sifive,fu540-c000-cpu-intc", "riscv,cpu-intc";
interrupt-controller;
};
};

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/samsung,exynos4210-combiner.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos SoC Interrupt Combiner Controller
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
Samsung's Exynos4 architecture includes a interrupt combiner controller which
can combine interrupt sources as a group and provide a single interrupt
request for the group. The interrupt request from each group are connected to
a parent interrupt controller, such as GIC in case of Exynos4210.
The interrupt combiner controller consists of multiple combiners. Up to eight
interrupt sources can be connected to a combiner. The combiner outputs one
combined interrupt for its eight interrupt sources. The combined interrupt is
usually connected to a parent interrupt controller.
A single node in the device tree is used to describe the interrupt combiner
controller module (which includes multiple combiners). A combiner in the
interrupt controller module shares config/control registers with other
combiners. For example, a 32-bit interrupt enable/disable config register can
accommodate up to 4 interrupt combiners (with each combiner supporting up to
8 interrupt sources).
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
compatible:
const: samsung,exynos4210-combiner
interrupt-controller: true
interrupts:
minItems: 8
maxItems: 32
"#interrupt-cells":
description: |
The meaning of the cells are:
* First Cell: Combiner Group Number.
* Second Cell: Interrupt number within the group.
const: 2
reg:
maxItems: 1
samsung,combiner-nr:
description: |
The number of interrupt combiners supported. Should match number
of interrupts set in "interrupts" property.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 8
maximum: 32
default: 16
required:
- compatible
- interrupt-controller
- interrupts
- "#interrupt-cells"
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
interrupt-controller@10440000 {
compatible = "samsung,exynos4210-combiner";
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x10440000 0x1000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
};

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Samsung S3C24XX Interrupt Controllers
The S3C24XX SoCs contain a custom set of interrupt controllers providing a
varying number of interrupt sources. The set consists of a main- and sub-
controller and on newer SoCs even a second main controller.
Required properties:
- compatible: Compatible property value should be "samsung,s3c2410-irq"
for machines before s3c2416 and "samsung,s3c2416-irq" for s3c2416 and later.
- reg: Physical base address of the controller and length of memory mapped
region.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value shall be 4 and interrupt descriptor shall
have the following format:
<ctrl_num parent_irq ctrl_irq type>
ctrl_num contains the controller to use:
- 0 ... main controller
- 1 ... sub controller
- 2 ... second main controller on s3c2416 and s3c2450
parent_irq contains the parent bit in the main controller and will be
ignored in main controllers
ctrl_irq contains the interrupt bit of the controller
type contains the trigger type to use
Example:
interrupt-controller@4a000000 {
compatible = "samsung,s3c2410-irq";
reg = <0x4a000000 0x100>;
interrupt-controller;
#interrupt-cells=<4>;
};
[...]
serial@50000000 {
compatible = "samsung,s3c2410-uart";
reg = <0x50000000 0x4000>;
interrupt-parent = <&subintc>;
interrupts = <1 28 0 4>, <1 28 1 4>;
};
rtc@57000000 {
compatible = "samsung,s3c2410-rtc";
reg = <0x57000000 0x100>;
interrupt-parent = <&intc>;
interrupts = <0 30 0 3>, <0 8 0 3>;
};

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
# Copyright (C) 2020 SiFive, Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SiFive Platform-Level Interrupt Controller (PLIC)
description:
SiFive SoCs and other RISC-V SoCs include an implementation of the
Platform-Level Interrupt Controller (PLIC) high-level specification in
the RISC-V Privileged Architecture specification. The PLIC connects all
external interrupts in the system to all hart contexts in the system, via
the external interrupt source in each hart.
A hart context is a privilege mode in a hardware execution thread. For example,
in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
privilege modes per hart; machine mode and supervisor mode.
Each interrupt can be enabled on per-context basis. Any context can claim
a pending enabled interrupt and then release it once it has been handled.
Each interrupt has a configurable priority. Higher priority interrupts are
serviced first. Each context can specify a priority threshold. Interrupts
with priority below this threshold will not cause the PLIC to raise its
interrupt line leading to the context.
The PLIC supports both edge-triggered and level-triggered interrupts. For
edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges
seen while an interrupt handler is active; the PLIC may either queue them or
ignore them. In the first case, handlers are oblivious to the trigger type, so
it is not included in the interrupt specifier. In the second case, software
needs to know the trigger type, so it can reorder the interrupt flow to avoid
missing interrupts. This special handling is needed by at least the Renesas
RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
"sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
contains a specific memory layout, which is documented in chapter 8 of the
SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
T-HEAD PLIC implementation requires setting a delegation bit to allow access
from S-mode. So add thead,c900-plic to distinguish them.
maintainers:
- Sagar Kadam <sagar.kadam@sifive.com>
- Paul Walmsley <paul.walmsley@sifive.com>
- Palmer Dabbelt <palmer@dabbelt.com>
properties:
compatible:
oneOf:
- items:
- enum:
- renesas,r9a07g043-plic
- const: andestech,nceplic100
- items:
- enum:
- sifive,fu540-c000-plic
- starfive,jh7100-plic
- canaan,k210-plic
- const: sifive,plic-1.0.0
- items:
- enum:
- allwinner,sun20i-d1-plic
- const: thead,c900-plic
- items:
- const: sifive,plic-1.0.0
- const: riscv,plic0
deprecated: true
description: For the QEMU virt machine only
reg:
maxItems: 1
'#address-cells':
const: 0
'#interrupt-cells': true
interrupt-controller: true
interrupts-extended:
minItems: 1
maxItems: 15872
description:
Specifies which contexts are connected to the PLIC, with "-1" specifying
that a context is not present. Each node pointed to should be a
riscv,cpu-intc node, which has a riscv node as parent.
riscv,ndev:
$ref: "/schemas/types.yaml#/definitions/uint32"
description:
Specifies how many external interrupts are supported by this controller.
clocks: true
power-domains: true
resets: true
required:
- compatible
- '#address-cells'
- '#interrupt-cells'
- interrupt-controller
- reg
- interrupts-extended
- riscv,ndev
allOf:
- if:
properties:
compatible:
contains:
enum:
- andestech,nceplic100
- thead,c900-plic
then:
properties:
'#interrupt-cells':
const: 2
else:
properties:
'#interrupt-cells':
const: 1
- if:
properties:
compatible:
contains:
const: renesas,r9a07g043-plic
then:
properties:
clocks:
maxItems: 1
power-domains:
maxItems: 1
resets:
maxItems: 1
required:
- clocks
- power-domains
- resets
additionalProperties: false
examples:
- |
plic: interrupt-controller@c000000 {
#address-cells = <0>;
#interrupt-cells = <1>;
compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
interrupt-controller;
interrupts-extended = <&cpu0_intc 11>,
<&cpu1_intc 11>, <&cpu1_intc 9>,
<&cpu2_intc 11>, <&cpu2_intc 9>,
<&cpu3_intc 11>, <&cpu3_intc 9>,
<&cpu4_intc 11>, <&cpu4_intc 9>;
reg = <0xc000000 0x4000000>;
riscv,ndev = <10>;
};

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bindings/interrupt-controller/snps,arc700-intc.txt Normal file
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* ARC700 incore Interrupt Controller
The core interrupt controller provides 32 prioritised interrupts (2 levels)
to ARC700 core.
Properties:
- compatible: "snps,arc700-intc"
- interrupt-controller: This is an interrupt controller.
- #interrupt-cells: Must be <1>.
Single Cell "interrupts" property of a device specifies the IRQ number
between 0 to 31
intc accessed via the special ARC AUX register interface, hence "reg" property
is not specified.
Example:
intc: interrupt-controller {
compatible = "snps,arc700-intc";
interrupt-controller;
#interrupt-cells = <1>;
};

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* ARC-HS Interrupt Distribution Unit
This optional 2nd level interrupt controller can be used in SMP configurations
for dynamic IRQ routing, load balancing of common/external IRQs towards core
intc.
Properties:
- compatible: "snps,archs-idu-intc"
- interrupt-controller: This is an interrupt controller.
- #interrupt-cells: Must be <1> or <2>.
Value of the first cell specifies the "common" IRQ from peripheral to IDU.
Number N of the particular interrupt line of IDU corresponds to the line N+24
of the core interrupt controller.
The (optional) second cell specifies any of the following flags:
- bits[3:0] trigger type and level flags
1 = low-to-high edge triggered
2 = NOT SUPPORTED (high-to-low edge triggered)
4 = active high level-sensitive <<< DEFAULT
8 = NOT SUPPORTED (active low level-sensitive)
When no second cell is specified, the interrupt is assumed to be level
sensitive.
The interrupt controller is accessed via the special ARC AUX register
interface, hence "reg" property is not specified.
Example:
core_intc: core-interrupt-controller {
compatible = "snps,archs-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
idu_intc: idu-interrupt-controller {
compatible = "snps,archs-idu-intc";
interrupt-controller;
interrupt-parent = <&core_intc>;
#interrupt-cells = <1>;
};
some_device: serial@c0fc1000 {
interrupt-parent = <&idu_intc>;
interrupts = <0>; /* upstream idu IRQ #24 */
};

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bindings/interrupt-controller/snps,archs-intc.txt Normal file
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* ARC-HS incore Interrupt Controller (Provided by cores implementing ARCv2 ISA)
Properties:
- compatible: "snps,archs-intc"
- interrupt-controller: This is an interrupt controller.
- #interrupt-cells: Must be <1>.
Single Cell "interrupts" property of a device specifies the IRQ number
between 16 to 256
intc accessed via the special ARC AUX register interface, hence "reg" property
is not specified.
Example:
intc: interrupt-controller {
compatible = "snps,archs-intc";
interrupt-controller;
#interrupt-cells = <1>;
interrupts = <16 17 18 19 20 21 22 23 24 25>;
};

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bindings/interrupt-controller/snps,dw-apb-ictl.txt Normal file
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Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
Synopsys DesignWare provides interrupt controller IP for APB known as
dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt
controller in some SoCs, e.g. Hisilicon SD5203.
Required properties:
- compatible: shall be "snps,dw-apb-ictl"
- reg: physical base address of the controller and length of memory mapped
region starting with ENABLE_LOW register
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
Additional required property when it's used as secondary interrupt controller:
- interrupts: interrupt reference to primary interrupt controller
The interrupt sources map to the corresponding bits in the interrupt
registers, i.e.
- 0 maps to bit 0 of low interrupts,
- 1 maps to bit 1 of low interrupts,
- 32 maps to bit 0 of high interrupts,
- 33 maps to bit 1 of high interrupts,
- (optional) fast interrupts start at 64.
Example:
/* dw_apb_ictl is used as secondary interrupt controller */
aic: interrupt-controller@3000 {
compatible = "snps,dw-apb-ictl";
reg = <0x3000 0xc00>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
};
/* dw_apb_ictl is used as primary interrupt controller */
vic: interrupt-controller@10130000 {
compatible = "snps,dw-apb-ictl";
reg = <0x10130000 0x1000>;
interrupt-controller;
#interrupt-cells = <1>;
};

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Socionext SynQuacer External Interrupt Unit (EXIU)
The Socionext Synquacer SoC has an external interrupt unit (EXIU)
that forwards a block of 32 configurable input lines to 32 adjacent
level-high type GICv3 SPIs.
Required properties:
- compatible : Should be "socionext,synquacer-exiu".
- reg : Specifies base physical address and size of the
control registers.
- interrupt-controller : Identifies the node as an interrupt controller.
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value must be 3.
- socionext,spi-base : The SPI number of the first SPI of the 32 adjacent
ones the EXIU forwards its interrups to.
Notes:
- Only SPIs can use the EXIU as an interrupt parent.
Example:
exiu: interrupt-controller@510c0000 {
compatible = "socionext,synquacer-exiu";
reg = <0x0 0x510c0000 0x0 0x20>;
interrupt-controller;
interrupt-parent = <&gic>;
#interrupt-cells = <3>;
socionext,spi-base = <112>;
};

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