dt-bindings: Add devicetree bindings
Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").
Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
This commit is contained in:
Melody Olvera
106
bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml
Normal file
106
bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml
Normal file
@@ -0,0 +1,106 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Device tree binding for NVIDIA Tegra NVDEC
|
||||
|
||||
description: |
|
||||
NVDEC is the hardware video decoder present on NVIDIA Tegra210
|
||||
and newer chips. It is located on the Host1x bus and typically
|
||||
programmed through Host1x channels.
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <treding@gmail.com>
|
||||
- Mikko Perttunen <mperttunen@nvidia.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^nvdec@[0-9a-f]*$"
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra210-nvdec
|
||||
- nvidia,tegra186-nvdec
|
||||
- nvidia,tegra194-nvdec
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: nvdec
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: nvdec
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
interconnects:
|
||||
items:
|
||||
- description: DMA read memory client
|
||||
- description: DMA read 2 memory client
|
||||
- description: DMA write memory client
|
||||
|
||||
interconnect-names:
|
||||
items:
|
||||
- const: dma-mem
|
||||
- const: read-1
|
||||
- const: write
|
||||
|
||||
nvidia,host1x-class:
|
||||
description: |
|
||||
Host1x class of the engine, used to specify the targeted engine
|
||||
when programming the engine through Host1x channels or when
|
||||
configuring engine-specific behavior in Host1x.
|
||||
default: 0xf0
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- reset-names
|
||||
- power-domains
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra186-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/memory/tegra186-mc.h>
|
||||
#include <dt-bindings/power/tegra186-powergate.h>
|
||||
#include <dt-bindings/reset/tegra186-reset.h>
|
||||
|
||||
nvdec@15480000 {
|
||||
compatible = "nvidia,tegra186-nvdec";
|
||||
reg = <0x15480000 0x40000>;
|
||||
clocks = <&bpmp TEGRA186_CLK_NVDEC>;
|
||||
clock-names = "nvdec";
|
||||
resets = <&bpmp TEGRA186_RESET_NVDEC>;
|
||||
reset-names = "nvdec";
|
||||
|
||||
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>;
|
||||
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>,
|
||||
<&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>,
|
||||
<&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>;
|
||||
interconnect-names = "dma-mem", "read-1", "write";
|
||||
iommus = <&smmu TEGRA186_SID_NVDEC>;
|
||||
};
|
||||
135
bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml
Normal file
135
bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml
Normal file
@@ -0,0 +1,135 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Device tree binding for NVIDIA Tegra NVENC
|
||||
|
||||
description: |
|
||||
NVENC is the hardware video encoder present on NVIDIA Tegra210
|
||||
and newer chips. It is located on the Host1x bus and typically
|
||||
programmed through Host1x channels.
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <treding@gmail.com>
|
||||
- Mikko Perttunen <mperttunen@nvidia.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^nvenc@[0-9a-f]*$"
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra210-nvenc
|
||||
- nvidia,tegra186-nvenc
|
||||
- nvidia,tegra194-nvenc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: nvenc
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: nvenc
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
interconnects:
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
interconnect-names:
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
nvidia,host1x-class:
|
||||
description: |
|
||||
Host1x class of the engine, used to specify the targeted engine
|
||||
when programming the engine through Host1x channels or when
|
||||
configuring engine-specific behavior in Host1x.
|
||||
default: 0x21
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- reset-names
|
||||
- power-domains
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra210-nvenc
|
||||
- nvidia,tegra186-nvenc
|
||||
then:
|
||||
properties:
|
||||
interconnects:
|
||||
items:
|
||||
- description: DMA read memory client
|
||||
- description: DMA write memory client
|
||||
interconnect-names:
|
||||
items:
|
||||
- const: dma-mem
|
||||
- const: write
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra194-nvenc
|
||||
then:
|
||||
properties:
|
||||
interconnects:
|
||||
items:
|
||||
- description: DMA read memory client
|
||||
- description: DMA read 2 memory client
|
||||
- description: DMA write memory client
|
||||
interconnect-names:
|
||||
items:
|
||||
- const: dma-mem
|
||||
- const: read-1
|
||||
- const: write
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra186-clock.h>
|
||||
#include <dt-bindings/memory/tegra186-mc.h>
|
||||
#include <dt-bindings/power/tegra186-powergate.h>
|
||||
#include <dt-bindings/reset/tegra186-reset.h>
|
||||
|
||||
nvenc@154c0000 {
|
||||
compatible = "nvidia,tegra186-nvenc";
|
||||
reg = <0x154c0000 0x40000>;
|
||||
clocks = <&bpmp TEGRA186_CLK_NVENC>;
|
||||
clock-names = "nvenc";
|
||||
resets = <&bpmp TEGRA186_RESET_NVENC>;
|
||||
reset-names = "nvenc";
|
||||
|
||||
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>;
|
||||
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>,
|
||||
<&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>;
|
||||
interconnect-names = "dma-mem", "write";
|
||||
iommus = <&smmu TEGRA186_SID_NVENC>;
|
||||
};
|
||||
94
bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml
Normal file
94
bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml
Normal file
@@ -0,0 +1,94 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvjpg.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Device tree binding for NVIDIA Tegra NVJPG
|
||||
|
||||
description: |
|
||||
NVJPG is the hardware JPEG decoder and encoder present on NVIDIA Tegra210
|
||||
and newer chips. It is located on the Host1x bus and typically programmed
|
||||
through Host1x channels.
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <treding@gmail.com>
|
||||
- Mikko Perttunen <mperttunen@nvidia.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^nvjpg@[0-9a-f]*$"
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra210-nvjpg
|
||||
- nvidia,tegra186-nvjpg
|
||||
- nvidia,tegra194-nvjpg
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: nvjpg
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: nvjpg
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
interconnects:
|
||||
items:
|
||||
- description: DMA read memory client
|
||||
- description: DMA write memory client
|
||||
|
||||
interconnect-names:
|
||||
items:
|
||||
- const: dma-mem
|
||||
- const: write
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- reset-names
|
||||
- power-domains
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra186-clock.h>
|
||||
#include <dt-bindings/memory/tegra186-mc.h>
|
||||
#include <dt-bindings/power/tegra186-powergate.h>
|
||||
#include <dt-bindings/reset/tegra186-reset.h>
|
||||
|
||||
nvjpg@15380000 {
|
||||
compatible = "nvidia,tegra186-nvjpg";
|
||||
reg = <0x15380000 0x40000>;
|
||||
clocks = <&bpmp TEGRA186_CLK_NVJPG>;
|
||||
clock-names = "nvjpg";
|
||||
resets = <&bpmp TEGRA186_RESET_NVJPG>;
|
||||
reset-names = "nvjpg";
|
||||
|
||||
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>;
|
||||
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>,
|
||||
<&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>;
|
||||
interconnect-names = "dma-mem", "write";
|
||||
iommus = <&smmu TEGRA186_SID_NVJPG>;
|
||||
};
|
||||
156
bindings/gpu/host1x/nvidia,tegra234-nvdec.yaml
Normal file
156
bindings/gpu/host1x/nvidia,tegra234-nvdec.yaml
Normal file
@@ -0,0 +1,156 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra234-nvdec.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Device tree binding for NVIDIA Tegra234 NVDEC
|
||||
|
||||
description: |
|
||||
NVDEC is the hardware video decoder present on NVIDIA Tegra210
|
||||
and newer chips. It is located on the Host1x bus and typically
|
||||
programmed through Host1x channels.
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <treding@gmail.com>
|
||||
- Mikko Perttunen <mperttunen@nvidia.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^nvdec@[0-9a-f]*$"
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra234-nvdec
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 3
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: nvdec
|
||||
- const: fuse
|
||||
- const: tsec_pka
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: nvdec
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
interconnects:
|
||||
items:
|
||||
- description: DMA read memory client
|
||||
- description: DMA write memory client
|
||||
|
||||
interconnect-names:
|
||||
items:
|
||||
- const: dma-mem
|
||||
- const: write
|
||||
|
||||
nvidia,memory-controller:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
phandle to the memory controller for determining information for the NVDEC
|
||||
firmware secure carveout. This carveout is configured by the bootloader and
|
||||
not accessible to CPU.
|
||||
|
||||
nvidia,bl-manifest-offset:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Offset to bootloader manifest from beginning of firmware that was configured by
|
||||
the bootloader.
|
||||
|
||||
nvidia,bl-code-offset:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Offset to bootloader code section from beginning of firmware that was configured by
|
||||
the bootloader.
|
||||
|
||||
nvidia,bl-data-offset:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Offset to bootloader data section from beginning of firmware that was configured by
|
||||
the bootloader.
|
||||
|
||||
nvidia,os-manifest-offset:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Offset to operating system manifest from beginning of firmware that was configured by
|
||||
the bootloader.
|
||||
|
||||
nvidia,os-code-offset:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Offset to operating system code section from beginning of firmware that was configured by
|
||||
the bootloader.
|
||||
|
||||
nvidia,os-data-offset:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Offset to operating system data section from beginning of firmware that was configured
|
||||
by the bootloader.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- reset-names
|
||||
- power-domains
|
||||
- nvidia,memory-controller
|
||||
- nvidia,bl-manifest-offset
|
||||
- nvidia,bl-code-offset
|
||||
- nvidia,bl-data-offset
|
||||
- nvidia,os-manifest-offset
|
||||
- nvidia,os-code-offset
|
||||
- nvidia,os-data-offset
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra234-clock.h>
|
||||
#include <dt-bindings/memory/tegra234-mc.h>
|
||||
#include <dt-bindings/power/tegra234-powergate.h>
|
||||
#include <dt-bindings/reset/tegra234-reset.h>
|
||||
|
||||
nvdec@15480000 {
|
||||
compatible = "nvidia,tegra234-nvdec";
|
||||
reg = <0x15480000 0x00040000>;
|
||||
clocks = <&bpmp TEGRA234_CLK_NVDEC>,
|
||||
<&bpmp TEGRA234_CLK_FUSE>,
|
||||
<&bpmp TEGRA234_CLK_TSEC_PKA>;
|
||||
clock-names = "nvdec", "fuse", "tsec_pka";
|
||||
resets = <&bpmp TEGRA234_RESET_NVDEC>;
|
||||
reset-names = "nvdec";
|
||||
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>;
|
||||
interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>,
|
||||
<&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>;
|
||||
interconnect-names = "dma-mem", "write";
|
||||
iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>;
|
||||
dma-coherent;
|
||||
|
||||
nvidia,memory-controller = <&mc>;
|
||||
|
||||
/* Placeholder values, to be replaced with values from overlay */
|
||||
nvidia,bl-manifest-offset = <0>;
|
||||
nvidia,bl-data-offset = <0>;
|
||||
nvidia,bl-code-offset = <0>;
|
||||
nvidia,os-manifest-offset = <0>;
|
||||
nvidia,os-data-offset = <0>;
|
||||
nvidia,os-code-offset = <0>;
|
||||
};
|
||||
Reference in New Issue
Block a user