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dt-bindings: Add devicetree bindings

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Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").

Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
This commit is contained in:
Melody Olvera
2023-04-03 14:38:11 -07:00
parent c334acf377
commit 6f18ce8026
4878 changed files with 424312 additions and 0 deletions
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237
bindings/gpu/arm,mali-bifrost.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/arm,mali-bifrost.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Mali Bifrost GPU
maintainers:
- Rob Herring <robh@kernel.org>
properties:
$nodename:
pattern: '^gpu@[a-f0-9]+$'
compatible:
oneOf:
- items:
- enum:
- amlogic,meson-g12a-mali
- mediatek,mt8183-mali
- realtek,rtd1619-mali
- renesas,r9a07g044-mali
- renesas,r9a07g054-mali
- rockchip,px30-mali
- rockchip,rk3568-mali
- const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
- items:
- enum:
- mediatek,mt8192-mali
- const: arm,mali-valhall-jm # Mali Valhall GPU model/revision is fully discoverable
reg:
maxItems: 1
interrupts:
minItems: 3
items:
- description: Job interrupt
- description: MMU interrupt
- description: GPU interrupt
- description: Event interrupt
interrupt-names:
minItems: 3
items:
- const: job
- const: mmu
- const: gpu
- const: event
clocks:
minItems: 1
maxItems: 3
clock-names: true
mali-supply: true
sram-supply: true
operating-points-v2: true
power-domains:
minItems: 1
maxItems: 3
resets:
minItems: 1
maxItems: 3
reset-names: true
"#cooling-cells":
const: 2
dynamic-power-coefficient:
$ref: '/schemas/types.yaml#/definitions/uint32'
description:
A u32 value that represents the running time dynamic
power coefficient in units of uW/MHz/V^2. The
coefficient can either be calculated from power
measurements or derived by analysis.
The dynamic power consumption of the GPU is
proportional to the square of the Voltage (V) and
the clock frequency (f). The coefficient is used to
calculate the dynamic power as below -
Pdyn = dynamic-power-coefficient * V^2 * f
where voltage is in V, frequency is in MHz.
dma-coherent: true
required:
- compatible
- reg
- interrupts
- interrupt-names
- clocks
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
const: amlogic,meson-g12a-mali
then:
required:
- resets
- if:
properties:
compatible:
contains:
enum:
- renesas,r9a07g044-mali
- renesas,r9a07g054-mali
then:
properties:
interrupts:
minItems: 4
interrupt-names:
minItems: 4
clocks:
minItems: 3
clock-names:
items:
- const: gpu
- const: bus
- const: bus_ace
resets:
minItems: 3
reset-names:
items:
- const: rst
- const: axi_rst
- const: ace_rst
required:
- clock-names
- power-domains
- resets
- reset-names
- if:
properties:
compatible:
contains:
const: mediatek,mt8183-mali
then:
properties:
power-domains:
minItems: 3
power-domain-names:
items:
- const: core0
- const: core1
- const: core2
required:
- sram-supply
- power-domains
- power-domain-names
else:
properties:
power-domains:
maxItems: 1
sram-supply: false
- if:
properties:
compatible:
contains:
const: rockchip,rk3568-mali
then:
properties:
clocks:
minItems: 2
clock-names:
items:
- const: gpu
- const: bus
required:
- clock-names
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
gpu@ffe40000 {
compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
reg = <0xffe40000 0x10000>;
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "job", "mmu", "gpu";
clocks = <&clk 1>;
mali-supply = <&vdd_gpu>;
operating-points-v2 = <&gpu_opp_table>;
resets = <&reset 0>, <&reset 1>;
};
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-533000000 {
opp-hz = /bits/ 64 <533000000>;
opp-microvolt = <1250000>;
};
opp-450000000 {
opp-hz = /bits/ 64 <450000000>;
opp-microvolt = <1150000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1125000>;
};
opp-350000000 {
opp-hz = /bits/ 64 <350000000>;
opp-microvolt = <1075000>;
};
opp-266000000 {
opp-hz = /bits/ 64 <266000000>;
opp-microvolt = <1025000>;
};
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
opp-microvolt = <925000>;
};
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-microvolt = <912500>;
};
};
...

197
bindings/gpu/arm,mali-midgard.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/arm,mali-midgard.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Mali Midgard GPU
maintainers:
- Rob Herring <robh@kernel.org>
properties:
$nodename:
pattern: '^gpu@[a-f0-9]+$'
compatible:
oneOf:
- items:
- enum:
- samsung,exynos5250-mali
- const: arm,mali-t604
- items:
- enum:
- samsung,exynos5420-mali
- const: arm,mali-t628
- items:
- enum:
- allwinner,sun50i-h6-mali
- const: arm,mali-t720
- items:
- enum:
- amlogic,meson-gxm-mali
- realtek,rtd1295-mali
- const: arm,mali-t820
- items:
- enum:
- arm,juno-mali
- const: arm,mali-t624
- items:
- enum:
- rockchip,rk3288-mali
- samsung,exynos5433-mali
- const: arm,mali-t760
- items:
- enum:
- rockchip,rk3399-mali
- const: arm,mali-t860
# "arm,mali-t830"
# "arm,mali-t880"
reg:
maxItems: 1
interrupts:
items:
- description: Job interrupt
- description: MMU interrupt
- description: GPU interrupt
interrupt-names:
items:
- const: job
- const: mmu
- const: gpu
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: core
- const: bus
mali-supply: true
opp-table:
type: object
power-domains:
maxItems: 1
resets:
minItems: 1
maxItems: 2
operating-points-v2: true
"#cooling-cells":
const: 2
dma-coherent: true
dynamic-power-coefficient:
$ref: '/schemas/types.yaml#/definitions/uint32'
description:
A u32 value that represents the running time dynamic
power coefficient in units of uW/MHz/V^2. The
coefficient can either be calculated from power
measurements or derived by analysis.
The dynamic power consumption of the GPU is
proportional to the square of the Voltage (V) and
the clock frequency (f). The coefficient is used to
calculate the dynamic power as below -
Pdyn = dynamic-power-coefficient * V^2 * f
where voltage is in V, frequency is in MHz.
required:
- compatible
- reg
- interrupts
- interrupt-names
- clocks
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
const: allwinner,sun50i-h6-mali
then:
properties:
clocks:
minItems: 2
required:
- clock-names
- resets
- if:
properties:
compatible:
contains:
const: amlogic,meson-gxm-mali
then:
properties:
resets:
minItems: 2
required:
- resets
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
gpu@ffa30000 {
compatible = "rockchip,rk3288-mali", "arm,mali-t760";
reg = <0xffa30000 0x10000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "job", "mmu", "gpu";
clocks = <&cru 0>;
mali-supply = <&vdd_gpu>;
operating-points-v2 = <&gpu_opp_table>;
power-domains = <&power 0>;
#cooling-cells = <2>;
};
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-533000000 {
opp-hz = /bits/ 64 <533000000>;
opp-microvolt = <1250000>;
};
opp-450000000 {
opp-hz = /bits/ 64 <450000000>;
opp-microvolt = <1150000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1125000>;
};
opp-350000000 {
opp-hz = /bits/ 64 <350000000>;
opp-microvolt = <1075000>;
};
opp-266000000 {
opp-hz = /bits/ 64 <266000000>;
opp-microvolt = <1025000>;
};
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
opp-microvolt = <925000>;
};
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-microvolt = <912500>;
};
};
...

180
bindings/gpu/arm,mali-utgard.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/arm,mali-utgard.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Mali Utgard GPU
maintainers:
- Rob Herring <robh@kernel.org>
- Maxime Ripard <mripard@kernel.org>
- Heiko Stuebner <heiko@sntech.de>
properties:
$nodename:
pattern: '^gpu@[a-f0-9]+$'
compatible:
oneOf:
- items:
- const: allwinner,sun8i-a23-mali
- const: allwinner,sun7i-a20-mali
- const: arm,mali-400
- items:
- enum:
- allwinner,sun4i-a10-mali
- allwinner,sun7i-a20-mali
- allwinner,sun8i-h3-mali
- allwinner,sun8i-r40-mali
- allwinner,sun50i-a64-mali
- rockchip,rk3036-mali
- rockchip,rk3066-mali
- rockchip,rk3188-mali
- rockchip,rk3228-mali
- samsung,exynos4210-mali
- stericsson,db8500-mali
- const: arm,mali-400
- items:
- enum:
- allwinner,sun50i-h5-mali
- amlogic,meson8-mali
- amlogic,meson8b-mali
- amlogic,meson-gxbb-mali
- amlogic,meson-gxl-mali
- hisilicon,hi6220-mali
- mediatek,mt7623-mali
- rockchip,rk3328-mali
- const: arm,mali-450
# "arm,mali-300"
reg:
maxItems: 1
interrupts:
minItems: 4
maxItems: 20
interrupt-names:
allOf:
- additionalItems: true
minItems: 4
maxItems: 20
items:
# At least enforce the first 2 interrupts
- const: gp
- const: gpmmu
- items:
# Not ideal as any order and combination are allowed
enum:
- gp # Geometry Processor interrupt
- gpmmu # Geometry Processor MMU interrupt
- pp # Pixel Processor broadcast interrupt (mali-450 only)
- pp0 # Pixel Processor X interrupt (X from 0 to 7)
- ppmmu0 # Pixel Processor X MMU interrupt (X from 0 to 7)
- pp1
- ppmmu1
- pp2
- ppmmu2
- pp3
- ppmmu3
- pp4
- ppmmu4
- pp5
- ppmmu5
- pp6
- ppmmu6
- pp7
- ppmmu7
- pmu # Power Management Unit interrupt (optional)
- combined # stericsson,db8500-mali only
clocks:
maxItems: 2
clock-names:
items:
- const: bus
- const: core
memory-region: true
mali-supply: true
opp-table:
type: object
power-domains:
maxItems: 1
resets:
maxItems: 1
operating-points-v2: true
"#cooling-cells":
const: 2
required:
- compatible
- reg
- interrupts
- interrupt-names
- clocks
- clock-names
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
enum:
- allwinner,sun4i-a10-mali
- allwinner,sun7i-a20-mali
- allwinner,sun8i-r40-mali
- allwinner,sun50i-a64-mali
- allwinner,sun50i-h5-mali
- amlogic,meson8-mali
- amlogic,meson8b-mali
- hisilicon,hi6220-mali
- mediatek,mt7623-mali
- rockchip,rk3036-mali
- rockchip,rk3066-mali
- rockchip,rk3188-mali
- rockchip,rk3228-mali
- rockchip,rk3328-mali
then:
required:
- resets
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
mali: gpu@1c40000 {
compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
reg = <0x01c40000 0x10000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gp",
"gpmmu",
"pp0",
"ppmmu0",
"pp1",
"ppmmu1",
"pmu";
clocks = <&ccu 1>, <&ccu 2>;
clock-names = "bus", "core";
resets = <&ccu 1>;
#cooling-cells = <2>;
};
...

41
bindings/gpu/aspeed-gfx.txt Normal file
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Device tree configuration for the GFX display device on the ASPEED SoCs
Required properties:
- compatible
* Must be one of the following:
+ aspeed,ast2500-gfx
+ aspeed,ast2400-gfx
* In addition, the ASPEED pinctrl bindings require the 'syscon' property to
be present
- reg: Physical base address and length of the GFX registers
- interrupts: interrupt number for the GFX device
- clocks: clock number used to generate the pixel clock
- resets: reset line that must be released to use the GFX device
- memory-region:
Phandle to a memory region to allocate from, as defined in
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
Example:
gfx: display@1e6e6000 {
compatible = "aspeed,ast2500-gfx", "syscon";
reg = <0x1e6e6000 0x1000>;
reg-io-width = <4>;
clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
resets = <&syscon ASPEED_RESET_CRT1>;
interrupts = <0x19>;
memory-region = <&gfx_memory>;
};
gfx_memory: framebuffer {
size = <0x01000000>;
alignment = <0x01000000>;
compatible = "shared-dma-pool";
reusable;
};

75
bindings/gpu/brcm,bcm-v3d.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/brcm,bcm-v3d.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom V3D GPU Bindings
maintainers:
- Eric Anholt <eric@anholt.net>
- Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
properties:
$nodename:
pattern: '^gpu@[a-f0-9]+$'
compatible:
enum:
- brcm,2711-v3d
- brcm,7268-v3d
- brcm,7278-v3d
reg:
items:
- description: hub register (required)
- description: core0 register (required)
- description: GCA cache controller register (if GCA controller present)
- description: bridge register (if no external reset controller)
minItems: 2
reg-names:
items:
- const: hub
- const: core0
- enum: [ bridge, gca ]
- enum: [ bridge, gca ]
minItems: 2
interrupts:
items:
- description: hub interrupt (required)
- description: core interrupts (if it doesn't share the hub's interrupt)
minItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
power-domains:
maxItems: 1
required:
- compatible
- reg
- reg-names
- interrupts
additionalProperties: false
examples:
- |
gpu@f1200000 {
compatible = "brcm,7268-v3d";
reg = <0xf1200000 0x4000>,
<0xf1208000 0x4000>,
<0xf1204000 0x100>,
<0xf1204100 0x100>;
reg-names = "hub", "core0", "bridge", "gca";
interrupts = <0 78 4>,
<0 77 4>;
};
...

106
bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Device tree binding for NVIDIA Tegra NVDEC
description: |
NVDEC is the hardware video decoder present on NVIDIA Tegra210
and newer chips. It is located on the Host1x bus and typically
programmed through Host1x channels.
maintainers:
- Thierry Reding <treding@gmail.com>
- Mikko Perttunen <mperttunen@nvidia.com>
properties:
$nodename:
pattern: "^nvdec@[0-9a-f]*$"
compatible:
enum:
- nvidia,tegra210-nvdec
- nvidia,tegra186-nvdec
- nvidia,tegra194-nvdec
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: nvdec
resets:
maxItems: 1
reset-names:
items:
- const: nvdec
power-domains:
maxItems: 1
iommus:
maxItems: 1
dma-coherent: true
interconnects:
items:
- description: DMA read memory client
- description: DMA read 2 memory client
- description: DMA write memory client
interconnect-names:
items:
- const: dma-mem
- const: read-1
- const: write
nvidia,host1x-class:
description: |
Host1x class of the engine, used to specify the targeted engine
when programming the engine through Host1x channels or when
configuring engine-specific behavior in Host1x.
default: 0xf0
$ref: /schemas/types.yaml#/definitions/uint32
required:
- compatible
- reg
- clocks
- clock-names
- resets
- reset-names
- power-domains
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/tegra186-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/memory/tegra186-mc.h>
#include <dt-bindings/power/tegra186-powergate.h>
#include <dt-bindings/reset/tegra186-reset.h>
nvdec@15480000 {
compatible = "nvidia,tegra186-nvdec";
reg = <0x15480000 0x40000>;
clocks = <&bpmp TEGRA186_CLK_NVDEC>;
clock-names = "nvdec";
resets = <&bpmp TEGRA186_RESET_NVDEC>;
reset-names = "nvdec";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>,
<&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>,
<&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>;
interconnect-names = "dma-mem", "read-1", "write";
iommus = <&smmu TEGRA186_SID_NVDEC>;
};

135
bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Device tree binding for NVIDIA Tegra NVENC
description: |
NVENC is the hardware video encoder present on NVIDIA Tegra210
and newer chips. It is located on the Host1x bus and typically
programmed through Host1x channels.
maintainers:
- Thierry Reding <treding@gmail.com>
- Mikko Perttunen <mperttunen@nvidia.com>
properties:
$nodename:
pattern: "^nvenc@[0-9a-f]*$"
compatible:
enum:
- nvidia,tegra210-nvenc
- nvidia,tegra186-nvenc
- nvidia,tegra194-nvenc
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: nvenc
resets:
maxItems: 1
reset-names:
items:
- const: nvenc
power-domains:
maxItems: 1
iommus:
maxItems: 1
dma-coherent: true
interconnects:
minItems: 2
maxItems: 3
interconnect-names:
minItems: 2
maxItems: 3
nvidia,host1x-class:
description: |
Host1x class of the engine, used to specify the targeted engine
when programming the engine through Host1x channels or when
configuring engine-specific behavior in Host1x.
default: 0x21
$ref: /schemas/types.yaml#/definitions/uint32
required:
- compatible
- reg
- clocks
- clock-names
- resets
- reset-names
- power-domains
allOf:
- if:
properties:
compatible:
enum:
- nvidia,tegra210-nvenc
- nvidia,tegra186-nvenc
then:
properties:
interconnects:
items:
- description: DMA read memory client
- description: DMA write memory client
interconnect-names:
items:
- const: dma-mem
- const: write
- if:
properties:
compatible:
enum:
- nvidia,tegra194-nvenc
then:
properties:
interconnects:
items:
- description: DMA read memory client
- description: DMA read 2 memory client
- description: DMA write memory client
interconnect-names:
items:
- const: dma-mem
- const: read-1
- const: write
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/tegra186-clock.h>
#include <dt-bindings/memory/tegra186-mc.h>
#include <dt-bindings/power/tegra186-powergate.h>
#include <dt-bindings/reset/tegra186-reset.h>
nvenc@154c0000 {
compatible = "nvidia,tegra186-nvenc";
reg = <0x154c0000 0x40000>;
clocks = <&bpmp TEGRA186_CLK_NVENC>;
clock-names = "nvenc";
resets = <&bpmp TEGRA186_RESET_NVENC>;
reset-names = "nvenc";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>,
<&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_NVENC>;
};

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvjpg.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Device tree binding for NVIDIA Tegra NVJPG
description: |
NVJPG is the hardware JPEG decoder and encoder present on NVIDIA Tegra210
and newer chips. It is located on the Host1x bus and typically programmed
through Host1x channels.
maintainers:
- Thierry Reding <treding@gmail.com>
- Mikko Perttunen <mperttunen@nvidia.com>
properties:
$nodename:
pattern: "^nvjpg@[0-9a-f]*$"
compatible:
enum:
- nvidia,tegra210-nvjpg
- nvidia,tegra186-nvjpg
- nvidia,tegra194-nvjpg
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: nvjpg
resets:
maxItems: 1
reset-names:
items:
- const: nvjpg
power-domains:
maxItems: 1
iommus:
maxItems: 1
dma-coherent: true
interconnects:
items:
- description: DMA read memory client
- description: DMA write memory client
interconnect-names:
items:
- const: dma-mem
- const: write
required:
- compatible
- reg
- clocks
- clock-names
- resets
- reset-names
- power-domains
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/tegra186-clock.h>
#include <dt-bindings/memory/tegra186-mc.h>
#include <dt-bindings/power/tegra186-powergate.h>
#include <dt-bindings/reset/tegra186-reset.h>
nvjpg@15380000 {
compatible = "nvidia,tegra186-nvjpg";
reg = <0x15380000 0x40000>;
clocks = <&bpmp TEGRA186_CLK_NVJPG>;
clock-names = "nvjpg";
resets = <&bpmp TEGRA186_RESET_NVJPG>;
reset-names = "nvjpg";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>,
<&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_NVJPG>;
};

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra234-nvdec.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Device tree binding for NVIDIA Tegra234 NVDEC
description: |
NVDEC is the hardware video decoder present on NVIDIA Tegra210
and newer chips. It is located on the Host1x bus and typically
programmed through Host1x channels.
maintainers:
- Thierry Reding <treding@gmail.com>
- Mikko Perttunen <mperttunen@nvidia.com>
properties:
$nodename:
pattern: "^nvdec@[0-9a-f]*$"
compatible:
enum:
- nvidia,tegra234-nvdec
reg:
maxItems: 1
clocks:
maxItems: 3
clock-names:
items:
- const: nvdec
- const: fuse
- const: tsec_pka
resets:
maxItems: 1
reset-names:
items:
- const: nvdec
power-domains:
maxItems: 1
iommus:
maxItems: 1
dma-coherent: true
interconnects:
items:
- description: DMA read memory client
- description: DMA write memory client
interconnect-names:
items:
- const: dma-mem
- const: write
nvidia,memory-controller:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle to the memory controller for determining information for the NVDEC
firmware secure carveout. This carveout is configured by the bootloader and
not accessible to CPU.
nvidia,bl-manifest-offset:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Offset to bootloader manifest from beginning of firmware that was configured by
the bootloader.
nvidia,bl-code-offset:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Offset to bootloader code section from beginning of firmware that was configured by
the bootloader.
nvidia,bl-data-offset:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Offset to bootloader data section from beginning of firmware that was configured by
the bootloader.
nvidia,os-manifest-offset:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Offset to operating system manifest from beginning of firmware that was configured by
the bootloader.
nvidia,os-code-offset:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Offset to operating system code section from beginning of firmware that was configured by
the bootloader.
nvidia,os-data-offset:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Offset to operating system data section from beginning of firmware that was configured
by the bootloader.
required:
- compatible
- reg
- clocks
- clock-names
- resets
- reset-names
- power-domains
- nvidia,memory-controller
- nvidia,bl-manifest-offset
- nvidia,bl-code-offset
- nvidia,bl-data-offset
- nvidia,os-manifest-offset
- nvidia,os-code-offset
- nvidia,os-data-offset
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/tegra234-clock.h>
#include <dt-bindings/memory/tegra234-mc.h>
#include <dt-bindings/power/tegra234-powergate.h>
#include <dt-bindings/reset/tegra234-reset.h>
nvdec@15480000 {
compatible = "nvidia,tegra234-nvdec";
reg = <0x15480000 0x00040000>;
clocks = <&bpmp TEGRA234_CLK_NVDEC>,
<&bpmp TEGRA234_CLK_FUSE>,
<&bpmp TEGRA234_CLK_TSEC_PKA>;
clock-names = "nvdec", "fuse", "tsec_pka";
resets = <&bpmp TEGRA234_RESET_NVDEC>;
reset-names = "nvdec";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>,
<&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>;
dma-coherent;
nvidia,memory-controller = <&mc>;
/* Placeholder values, to be replaced with values from overlay */
nvidia,bl-manifest-offset = <0>;
nvidia,bl-data-offset = <0>;
nvidia,bl-code-offset = <0>;
nvidia,os-manifest-offset = <0>;
nvidia,os-data-offset = <0>;
nvidia,os-code-offset = <0>;
};

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NVIDIA Tegra Graphics Processing Units
Required properties:
- compatible: "nvidia,<gpu>"
Currently recognized values:
- nvidia,gk20a
- nvidia,gm20b
- nvidia,gp10b
- nvidia,gv11b
- reg: Physical base address and length of the controller's registers.
Must contain two entries:
- first entry for bar0
- second entry for bar1
- interrupts: Must contain an entry for each entry in interrupt-names.
See ../interrupt-controller/interrupts.txt for details.
- interrupt-names: Must include the following entries:
- stall
- nonstall
- vdd-supply: regulator for supply voltage. Only required for GPUs not using
power domains.
- clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
- gpu
- pwr
If the compatible string is "nvidia,gm20b", then the following clock
is also required:
- ref
If the compatible string is "nvidia,gv11b", then the following clock is also
required:
- fuse
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
- gpu
- power-domains: GPUs that make use of power domains can define this property
instead of vdd-supply. Currently "nvidia,gp10b" makes use of this.
Optional properties:
- iommus: A reference to the IOMMU. See ../iommu/iommu.txt for details.
Example for GK20A:
gpu@57000000 {
compatible = "nvidia,gk20a";
reg = <0x0 0x57000000 0x0 0x01000000>,
<0x0 0x58000000 0x0 0x01000000>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "stall", "nonstall";
vdd-supply = <&vdd_gpu>;
clocks = <&tegra_car TEGRA124_CLK_GPU>,
<&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
clock-names = "gpu", "pwr";
resets = <&tegra_car 184>;
reset-names = "gpu";
iommus = <&mc TEGRA_SWGROUP_GPU>;
};
Example for GM20B:
gpu@57000000 {
compatible = "nvidia,gm20b";
reg = <0x0 0x57000000 0x0 0x01000000>,
<0x0 0x58000000 0x0 0x01000000>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "stall", "nonstall";
clocks = <&tegra_car TEGRA210_CLK_GPU>,
<&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
<&tegra_car TEGRA210_CLK_PLL_G_REF>;
clock-names = "gpu", "pwr", "ref";
resets = <&tegra_car 184>;
reset-names = "gpu";
iommus = <&mc TEGRA_SWGROUP_GPU>;
};
Example for GP10B:
gpu@17000000 {
compatible = "nvidia,gp10b";
reg = <0x0 0x17000000 0x0 0x1000000>,
<0x0 0x18000000 0x0 0x1000000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "stall", "nonstall";
clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
<&bpmp TEGRA186_CLK_GPU>;
clock-names = "gpu", "pwr";
resets = <&bpmp TEGRA186_RESET_GPU>;
reset-names = "gpu";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
iommus = <&smmu TEGRA186_SID_GPU>;
};
Example for GV11B:
gpu@17000000 {
compatible = "nvidia,gv11b";
reg = <0x17000000 0x1000000>,
<0x18000000 0x1000000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "stall", "nonstall";
clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
<&bpmp TEGRA194_CLK_GPU_PWR>,
<&bpmp TEGRA194_CLK_FUSE>;
clock-names = "gpu", "pwr", "fuse";
resets = <&bpmp TEGRA194_RESET_GPU>;
reset-names = "gpu";
dma-coherent;
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
iommus = <&smmu TEGRA194_SID_GPU>;
};

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/samsung-g2d.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung SoC 2D Graphics Accelerator
maintainers:
- Inki Dae <inki.dae@samsung.com>
properties:
compatible:
enum:
- samsung,s5pv210-g2d # in S5PV210 & Exynos4210 SoC
- samsung,exynos4212-g2d # in Exynos4x12 SoCs
- samsung,exynos5250-g2d
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks: {}
clock-names: {}
iommus: {}
power-domains: {}
if:
properties:
compatible:
contains:
const: samsung,exynos5250-g2d
then:
properties:
clocks:
items:
- description: fimg2d clock
clock-names:
items:
- const: fimg2d
else:
properties:
clocks:
items:
- description: sclk_fimg2d clock
- description: fimg2d clock
clock-names:
items:
- const: sclk_fimg2d
- const: fimg2d
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
additionalProperties: false
examples:
- |
g2d@12800000 {
compatible = "samsung,s5pv210-g2d";
reg = <0x12800000 0x1000>;
interrupts = <0 89 0>;
clocks = <&clock 177>, <&clock 277>;
clock-names = "sclk_fimg2d", "fimg2d";
};
...

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/samsung-rotator.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung SoC Image Rotator
maintainers:
- Inki Dae <inki.dae@samsung.com>
properties:
compatible:
enum:
- "samsung,s5pv210-rotator"
- "samsung,exynos4210-rotator"
- "samsung,exynos4212-rotator"
- "samsung,exynos5250-rotator"
reg:
maxItems: 1
interrupts:
maxItems: 1
iommus:
maxItems: 1
power-domains:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: rotator
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
additionalProperties: false
examples:
- |
rotator@12810000 {
compatible = "samsung,exynos4210-rotator";
reg = <0x12810000 0x1000>;
interrupts = <0 83 0>;
clocks = <&clock 278>;
clock-names = "rotator";
};

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/samsung-scaler.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos SoC Image Scaler
maintainers:
- Inki Dae <inki.dae@samsung.com>
properties:
compatible:
enum:
- samsung,exynos5420-scaler
- samsung,exynos5433-scaler
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks: {}
clock-names: {}
iommus: {}
power-domains: {}
if:
properties:
compatible:
contains:
const: samsung,exynos5420-scaler
then:
properties:
clocks:
items:
- description: mscl clock
clock-names:
items:
- const: mscl
else:
properties:
clocks:
items:
- description: pclk clock
- description: aclk clock
- description: aclk_xiu clock
clock-names:
items:
- const: pclk
- const: aclk
- const: aclk_xiu
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/exynos5420.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
scaler@12800000 {
compatible = "samsung,exynos5420-scaler";
reg = <0x12800000 0x1294>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MSCL0>;
clock-names = "mscl";
};
...

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/vivante,gc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Vivante GPU Bindings
description: Vivante GPU core devices
maintainers:
- Lucas Stach <l.stach@pengutronix.de>
properties:
compatible:
const: vivante,gc
reg:
maxItems: 1
interrupts:
maxItems: 1
'#cooling-cells':
const: 2
assigned-clock-parents: true
assigned-clock-rates: true
assigned-clocks: true
clocks:
items:
- description: AXI/master interface clock
- description: GPU core clock
- description: Shader clock (only required if GPU has feature PIPE_3D)
- description: AHB/slave interface clock (only required if GPU can gate
slave interface independently)
minItems: 1
clock-names:
items:
enum: [ bus, core, shader, reg ]
minItems: 1
maxItems: 4
resets:
maxItems: 1
power-domains:
maxItems: 1
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
gpu@130000 {
compatible = "vivante,gc";
reg = <0x00130000 0x4000>;
interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
<&clks IMX6QDL_CLK_GPU3D_CORE>,
<&clks IMX6QDL_CLK_GPU3D_SHADER>;
clock-names = "bus", "core", "shader";
power-domains = <&gpc 1>;
};
...