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dt-bindings: Add devicetree bindings

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Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").

Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
This commit is contained in:
Melody Olvera
2023-04-03 14:38:11 -07:00
parent c334acf377
commit 6f18ce8026
4878 changed files with 424312 additions and 0 deletions
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72
bindings/gpio/8xxx_gpio.txt Normal file
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GPIO controllers on MPC8xxx SoCs
This is for the non-QE/CPM/GUTs GPIO controllers as found on
8349, 8572, 8610 and compatible.
Every GPIO controller node must have #gpio-cells property defined,
this information will be used to translate gpio-specifiers.
See bindings/gpio/gpio.txt for details of how to specify GPIO
information for devices.
The GPIO module usually is connected to the SoC's internal interrupt
controller, see bindings/interrupt-controller/interrupts.txt (the
interrupt client nodes section) for details how to specify this GPIO
module's interrupt.
The GPIO module may serve as another interrupt controller (cascaded to
the SoC's internal interrupt controller). See the interrupt controller
nodes section in bindings/interrupt-controller/interrupts.txt for
details.
Required properties:
- compatible: "fsl,<chip>-gpio" followed by "fsl,mpc8349-gpio"
for 83xx, "fsl,mpc8572-gpio" for 85xx, or
"fsl,mpc8610-gpio" for 86xx.
- #gpio-cells: Should be two. The first cell is the pin number
and the second cell is used to specify optional
parameters (currently unused).
- interrupts: Interrupt mapping for GPIO IRQ.
- gpio-controller: Marks the port as GPIO controller.
Optional properties:
- interrupt-controller: Empty boolean property which marks the GPIO
module as an IRQ controller.
- #interrupt-cells: Should be two. Defines the number of integer
cells required to specify an interrupt within
this interrupt controller. The first cell
defines the pin number, the second cell
defines additional flags (trigger type,
trigger polarity). Note that the available
set of trigger conditions supported by the
GPIO module depends on the actual SoC.
Example of gpio-controller nodes for a MPC8347 SoC:
gpio1: gpio-controller@c00 {
#gpio-cells = <2>;
compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio";
reg = <0xc00 0x100>;
interrupt-parent = <&ipic>;
interrupts = <74 0x8>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio-controller@d00 {
#gpio-cells = <2>;
compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio";
reg = <0xd00 0x100>;
interrupt-parent = <&ipic>;
interrupts = <75 0x8>;
gpio-controller;
};
Example of a peripheral using the GPIO module as an IRQ controller:
funkyfpga@0 {
compatible = "funky-fpga";
...
interrupt-parent = <&gpio1>;
interrupts = <4 3>;
};

35
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* Abilis TB10x GPIO controller
Required Properties:
- compatible: Should be "abilis,tb10x-gpio"
- reg: Address and length of the register set for the device
- gpio-controller: Marks the device node as a gpio controller.
- #gpio-cells: Should be <2>. The first cell is the pin number and the
second cell is used to specify optional parameters:
- bit 0 specifies polarity (0 for normal, 1 for inverted).
- abilis,ngpio: the number of GPIO pins this driver controls.
Optional Properties:
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be <1>. Interrupts are triggered on both edges.
- interrupts: Defines the interrupt line connecting this GPIO controller to
its parent interrupt controller.
GPIO ranges are specified as described in
Documentation/devicetree/bindings/gpio/gpio.txt
Example:
gpioa: gpio@ff140000 {
compatible = "abilis,tb10x-gpio";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <27 2>;
reg = <0xFF140000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
abilis,ngpio = <3>;
gpio-ranges = <&iomux 0 0 0>;
gpio-ranges-group-names = "gpioa_pins";
};

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/airoha,en7523-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Airoha EN7523 GPIO controller
maintainers:
- John Crispin <john@phrozen.org>
description: |
Airoha's GPIO controller on their ARM EN7523 SoCs consists of two banks of 32
GPIOs.
properties:
$nodename:
pattern: "^gpio@[0-9a-f]+$"
compatible:
items:
- const: airoha,en7523-gpio
reg:
description: |
The first tuple points to the input register.
The second and third tuple point to the direction registers
The fourth tuple points to the output register
maxItems: 4
"#gpio-cells":
const: 2
gpio-controller: true
required:
- compatible
- reg
- "#gpio-cells"
- gpio-controller
additionalProperties: false
examples:
- |
gpio0: gpio@1fbf0200 {
compatible = "airoha,en7523-gpio";
reg = <0x1fbf0204 0x4>,
<0x1fbf0200 0x4>,
<0x1fbf0220 0x4>,
<0x1fbf0214 0x4>;
gpio-controller;
#gpio-cells = <2>;
};
gpio1: gpio@1fbf0270 {
compatible = "airoha,en7523-gpio";
reg = <0x1fbf0270 0x4>,
<0x1fbf0260 0x4>,
<0x1fbf0264 0x4>,
<0x1fbf0278 0x4>;
gpio-controller;
#gpio-cells = <2>;
};
...

77
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/aspeed,sgpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Aspeed SGPIO controller
maintainers:
- Andrew Jeffery <andrew@aj.id.au>
description:
This SGPIO controller is for ASPEED AST2400, AST2500 and AST2600 SoC,
AST2600 have two sgpio master one with 128 pins another one with 80 pins,
AST2500/AST2400 have one sgpio master with 80 pins. Each of the Serial
GPIO pins can be programmed to support the following options
- Support interrupt option for each input port and various interrupt
sensitivity option (level-high, level-low, edge-high, edge-low)
- Support reset tolerance option for each output port
- Directly connected to APB bus and its shift clock is from APB bus clock
divided by a programmable value.
- Co-work with external signal-chained TTL components (74LV165/74LV595)
properties:
compatible:
enum:
- aspeed,ast2400-sgpio
- aspeed,ast2500-sgpio
- aspeed,ast2600-sgpiom
reg:
maxItems: 1
gpio-controller: true
'#gpio-cells':
const: 2
interrupts:
maxItems: 1
interrupt-controller: true
clocks:
maxItems: 1
ngpios: true
bus-frequency: true
required:
- compatible
- reg
- gpio-controller
- '#gpio-cells'
- interrupts
- interrupt-controller
- ngpios
- clocks
- bus-frequency
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/aspeed-clock.h>
sgpio: sgpio@1e780200 {
#gpio-cells = <2>;
compatible = "aspeed,ast2500-sgpio";
gpio-controller;
interrupts = <40>;
reg = <0x1e780200 0x0100>;
clocks = <&syscon ASPEED_CLK_APB>;
interrupt-controller;
ngpios = <80>;
bus-frequency = <12000000>;
};

86
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/brcm,bcm6345-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM6345 GPIO controller
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
- Jonas Gorski <jonas.gorski@gmail.com>
description: |+
Bindings for Broadcom's BCM63xx memory-mapped GPIO controllers.
These bindings can be used on any BCM63xx SoC. However, BCM6338 and BCM6345
are the only ones which don't need a pinctrl driver.
BCM6338 have 8-bit data and dirout registers, where GPIO state can be read
and/or written, and the direction changed from input to output.
BCM6345 have 16-bit data and dirout registers, where GPIO state can be read
and/or written, and the direction changed from input to output.
BCM6318, BCM6328, BCM6358, BCM6362, BCM6368 and BCM63268 have 32-bit data
and dirout registers, where GPIO state can be read and/or written, and the
direction changed from input to output.
properties:
compatible:
enum:
- brcm,bcm6318-gpio
- brcm,bcm6328-gpio
- brcm,bcm6345-gpio
- brcm,bcm6358-gpio
- brcm,bcm6362-gpio
- brcm,bcm6368-gpio
- brcm,bcm63268-gpio
gpio-controller: true
"#gpio-cells":
const: 2
gpio-ranges:
maxItems: 1
native-endian: true
reg:
maxItems: 2
reg-names:
items:
- const: dirout
- const: dat
required:
- compatible
- reg
- reg-names
- gpio-controller
- '#gpio-cells'
additionalProperties: false
examples:
- |
gpio@fffe0406 {
compatible = "brcm,bcm6345-gpio";
reg-names = "dirout", "dat";
reg = <0xfffe0406 2>, <0xfffe040a 2>;
native-endian;
gpio-controller;
#gpio-cells = <2>;
};
- |
gpio@0 {
compatible = "brcm,bcm63268-gpio";
reg-names = "dirout", "dat";
reg = <0x0 0x8>, <0x8 0x8>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 52>;
#gpio-cells = <2>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom STB "UPG GIO" GPIO controller
description: >
The controller's registers are organized as sets of eight 32-bit
registers with each set controlling a bank of up to 32 pins. A single
interrupt is shared for all of the banks handled by the controller.
maintainers:
- Doug Berger <opendmb@gmail.com>
- Florian Fainelli <f.fainelli@gmail.com>
properties:
compatible:
items:
- enum:
- brcm,bcm7445-gpio
- const: brcm,brcmstb-gpio
reg:
maxItems: 1
description: >
Define the base and range of the I/O address space containing
the brcmstb GPIO controller registers
"#gpio-cells":
const: 2
description: >
The first cell is the pin number (within the controller's
pin space), and the second is used for the following:
bit[0]: polarity (0 for active-high, 1 for active-low)
gpio-controller: true
brcm,gpio-bank-widths:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: >
Number of GPIO lines for each bank. Number of elements must
correspond to number of banks suggested by the 'reg' property.
interrupts:
maxItems: 1
description: >
The interrupt shared by all GPIO lines for this controller.
"#interrupt-cells":
const: 2
description: |
The first cell is the GPIO number, the second should specify
flags. The following subset of flags is supported:
- bits[3:0] trigger type and level flags
1 = low-to-high edge triggered
2 = high-to-low edge triggered
4 = active high level-sensitive
8 = active low level-sensitive
Valid combinations are 1, 2, 3, 4, 8.
interrupt-controller: true
wakeup-source:
type: boolean
description: >
GPIOs for this controller can be used as a wakeup source
required:
- compatible
- reg
- gpio-controller
- "#gpio-cells"
- "brcm,gpio-bank-widths"
additionalProperties: false
examples:
- |
upg_gio: gpio@f040a700 {
#gpio-cells = <2>;
#interrupt-cells = <2>;
compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
gpio-controller;
interrupt-controller;
reg = <0xf040a700 0x80>;
interrupt-parent = <&irq0_intc>;
interrupts = <0x6>;
brcm,gpio-bank-widths = <32 32 32 24>;
};
upg_gio_aon: gpio@f04172c0 {
#gpio-cells = <2>;
#interrupt-cells = <2>;
compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
gpio-controller;
interrupt-controller;
reg = <0xf04172c0 0x40>;
interrupt-parent = <&irq0_aon_intc>;
interrupts = <0x6>;
wakeup-source;
brcm,gpio-bank-widths = <18 4>;
};

52
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Broadcom Kona Family GPIO
=========================
This GPIO driver is used in the following Broadcom SoCs:
BCM11130, BCM11140, BCM11351, BCM28145, BCM28155
The Broadcom GPIO Controller IP can be configured prior to synthesis to
support up to 8 banks of 32 GPIOs where each bank has its own IRQ. The
GPIO controller only supports edge, not level, triggering of interrupts.
Required properties
-------------------
- compatible: "brcm,bcm11351-gpio", "brcm,kona-gpio"
- reg: Physical base address and length of the controller's registers.
- interrupts: The interrupt outputs from the controller. There is one GPIO
interrupt per GPIO bank. The number of interrupts listed depends on the
number of GPIO banks on the SoC. The interrupts must be ordered by bank,
starting with bank 0. There is always a 1:1 mapping between banks and
IRQs.
- #gpio-cells: Should be <2>. The first cell is the pin number, the second
cell is used to specify optional parameters:
- bit 0 specifies polarity (0 for normal, 1 for inverted)
See also "gpio-specifier" in .../devicetree/bindings/gpio/gpio.txt.
- #interrupt-cells: Should be <2>. The first cell is the GPIO number. The
second cell is used to specify flags. The following subset of flags is
supported:
- trigger type (bits[1:0]):
1 = low-to-high edge triggered.
2 = high-to-low edge triggered.
3 = low-to-high or high-to-low edge triggered
Valid values are 1, 2, 3
See also .../devicetree/bindings/interrupt-controller/interrupts.txt.
- gpio-controller: Marks the device node as a GPIO controller.
- interrupt-controller: Marks the device node as an interrupt controller.
Example:
gpio: gpio@35003000 {
compatible = "brcm,bcm11351-gpio", "brcm,kona-gpio";
reg = <0x35003000 0x800>;
interrupts =
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
#interrupt-cells = <2>;
gpio-controller;
interrupt-controller;
};

70
bindings/gpio/brcm,xgs-iproc-gpio.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/brcm,xgs-iproc-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom XGS iProc GPIO controller
maintainers:
- Chris Packham <chris.packham@alliedtelesis.co.nz>
description: |
This controller is the Chip Common A GPIO present on a number of Broadcom
switch ASICs with integrated SoCs.
properties:
compatible:
const: brcm,iproc-gpio-cca
reg:
items:
- description: the I/O address containing the GPIO controller registers.
- description: the I/O address containing the Chip Common A interrupt registers.
gpio-controller: true
'#gpio-cells':
const: 2
ngpios:
minimum: 0
maximum: 32
interrupt-controller: true
'#interrupt-cells':
const: 2
interrupts:
maxItems: 1
required:
- compatible
- reg
- "#gpio-cells"
- gpio-controller
additionalProperties: false
dependencies:
interrupt-controller: [ interrupts ]
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
gpio@18000060 {
compatible = "brcm,iproc-gpio-cca";
#gpio-cells = <2>;
reg = <0x18000060 0x50>,
<0x18000000 0x50>;
ngpios = <12>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
};
...

49
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* General Purpose Input Output (GPIO) bus.
Properties:
- compatible: "cavium,octeon-3860-gpio"
Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
- reg: The base address of the GPIO unit's register bank.
- gpio-controller: This is a GPIO controller.
- #gpio-cells: Must be <2>. The first cell is the GPIO pin.
- interrupt-controller: The GPIO controller is also an interrupt
controller, many of its pins may be configured as an interrupt
source.
- #interrupt-cells: Must be <2>. The first cell is the GPIO pin
connected to the interrupt source. The second cell is the interrupt
triggering protocol and may have one of four values:
1 - edge triggered on the rising edge.
2 - edge triggered on the falling edge
4 - level triggered active high.
8 - level triggered active low.
- interrupts: Interrupt routing for each pin.
Example:
gpio-controller@1070000000800 {
#gpio-cells = <2>;
compatible = "cavium,octeon-3860-gpio";
reg = <0x10700 0x00000800 0x0 0x100>;
gpio-controller;
/* Interrupts are specified by two parts:
* 1) GPIO pin number (0..15)
* 2) Triggering (1 - edge rising
* 2 - edge falling
* 4 - level active high
* 8 - level active low)
*/
interrupt-controller;
#interrupt-cells = <2>;
/* The GPIO pin connect to 16 consecutive CUI bits */
interrupts = <0 16>, <0 17>, <0 18>, <0 19>,
<0 20>, <0 21>, <0 22>, <0 23>,
<0 24>, <0 25>, <0 26>, <0 27>,
<0 28>, <0 29>, <0 30>, <0 31>;
};

43
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Cadence GPIO controller bindings
Required properties:
- compatible: should be "cdns,gpio-r1p02".
- reg: the register base address and size.
- #gpio-cells: should be 2.
* first cell is the GPIO number.
* second cell specifies the GPIO flags, as defined in
<dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH
and GPIO_ACTIVE_LOW flags are supported.
- gpio-controller: marks the device as a GPIO controller.
- clocks: should contain one entry referencing the peripheral clock driving
the GPIO controller.
Optional properties:
- ngpios: integer number of gpio lines supported by this controller, up to 32.
- interrupts: interrupt specifier for the controllers interrupt.
- interrupt-controller: marks the device as an interrupt controller. When
defined, interrupts, interrupt-parent and #interrupt-cells
are required.
- interrupt-cells: should be 2.
* first cell is the GPIO number you want to use as an IRQ source.
* second cell specifies the IRQ type, as defined in
<dt-bindings/interrupt-controller/irq.h>.
Currently only level sensitive IRQs are supported.
Example:
gpio0: gpio-controller@fd060000 {
compatible = "cdns,gpio-r1p02";
reg =<0xfd060000 0x1000>;
clocks = <&gpio_clk>;
interrupt-parent = <&gic>;
interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};

17
bindings/gpio/cirrus,clps711x-mctrl-gpio.txt Normal file
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* ARM Cirrus Logic CLPS711X SYSFLG1 MCTRL GPIOs
Required properties:
- compatible: Should contain "cirrus,ep7209-mctrl-gpio".
- gpio-controller: Marks the device node as a gpio controller.
- #gpio-cells: Should be two. The first cell is the pin number and
the second cell is used to specify the gpio polarity:
0 = Active high,
1 = Active low.
Example:
sysgpio: sysgpio {
compatible = "cirrus,ep7312-mctrl-gpio",
"cirrus,ep7209-mctrl-gpio";
gpio-controller;
#gpio-cells = <2>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/delta,tn48m-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Delta Networks TN48M CPLD GPIO controller
maintainers:
- Robert Marko <robert.marko@sartura.hr>
description: |
This module is part of the Delta TN48M multi-function device. For more
details see ../mfd/delta,tn48m-cpld.yaml.
Delta TN48M has an onboard Lattice CPLD that is used as an GPIO expander.
It provides 12 pins in total, they are input-only or ouput-only type.
properties:
compatible:
enum:
- delta,tn48m-gpo
- delta,tn48m-gpi
reg:
maxItems: 1
"#gpio-cells":
const: 2
gpio-controller: true
required:
- compatible
- reg
- "#gpio-cells"
- gpio-controller
additionalProperties: false

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/fairchild,74hc595.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Generic 8-bit shift register
maintainers:
- Maxime Ripard <mripard@kernel.org>
properties:
compatible:
enum:
- fairchild,74hc595
- nxp,74lvc594
reg:
maxItems: 1
gpio-controller: true
'#gpio-cells':
description:
The second cell is only used to specify the GPIO polarity.
const: 2
registers-number:
$ref: /schemas/types.yaml#/definitions/uint32
description: Number of daisy-chained shift registers
enable-gpios:
description: GPIO connected to the OE (Output Enable) pin.
maxItems: 1
patternProperties:
"^(hog-[0-9]+|.+-hog(-[0-9]+)?)$":
type: object
properties:
gpio-hog: true
gpios: true
output-high: true
output-low: true
line-name: true
required:
- gpio-hog
- gpios
additionalProperties: false
required:
- compatible
- reg
- gpio-controller
- '#gpio-cells'
- registers-number
allOf:
- $ref: /schemas/spi/spi-peripheral-props.yaml#
unevaluatedProperties: false
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
gpio5: gpio5@0 {
compatible = "fairchild,74hc595";
reg = <0>;
gpio-controller;
#gpio-cells = <2>;
registers-number = <4>;
spi-max-frequency = <100000>;
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/faraday,ftgpio010.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Faraday Technology FTGPIO010 GPIO Controller
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
properties:
compatible:
oneOf:
- items:
- const: cortina,gemini-gpio
- const: faraday,ftgpio010
- items:
- const: moxa,moxart-gpio
- const: faraday,ftgpio010
- const: faraday,ftgpio010
reg:
maxItems: 1
resets:
maxItems: 1
clocks:
maxItems: 1
interrupts:
maxItems: 1
description: Should contain the interrupt line for the GPIO block
gpio-controller: true
"#gpio-cells":
const: 2
interrupt-controller: true
"#interrupt-cells":
const: 2
required:
- compatible
- reg
- interrupts
- "#gpio-cells"
- interrupt-controller
- "#interrupt-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
gpio@4d000000 {
compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
reg = <0x4d000000 0x100>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/fsl,imx8qxp-sc-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: GPIO driver over IMX SCU firmware API
maintainers:
- Shenwei Wang <shenwei.wang@nxp.com>
description: |
This module provides the standard interface to control the
resource pins in SCU domain on i.MX8 platforms.
properties:
compatible:
enum:
- fsl,imx8qxp-sc-gpio
"#gpio-cells":
const: 2
gpio-controller: true
required:
- compatible
- "#gpio-cells"
- gpio-controller
additionalProperties: false
examples:
- |
gpio0: gpio {
compatible = "fsl,imx8qxp-sc-gpio";
gpio-controller;
#gpio-cells = <2>;
};

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/fsl-imx-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX/MXC GPIO controller
maintainers:
- Anson Huang <Anson.Huang@nxp.com>
properties:
compatible:
oneOf:
- enum:
- fsl,imx1-gpio
- fsl,imx21-gpio
- fsl,imx31-gpio
- fsl,imx35-gpio
- fsl,imx7d-gpio
- items:
- const: fsl,imx35-gpio
- const: fsl,imx31-gpio
- items:
- enum:
- fsl,imx50-gpio
- fsl,imx51-gpio
- fsl,imx53-gpio
- fsl,imx6q-gpio
- fsl,imx6sl-gpio
- fsl,imx6sll-gpio
- fsl,imx6sx-gpio
- fsl,imx6ul-gpio
- fsl,imx7d-gpio
- fsl,imx8mm-gpio
- fsl,imx8mn-gpio
- fsl,imx8mp-gpio
- fsl,imx8mq-gpio
- fsl,imx8qxp-gpio
- fsl,imxrt1050-gpio
- fsl,imxrt1170-gpio
- const: fsl,imx35-gpio
reg:
maxItems: 1
interrupts:
description: |
Should be the port interrupt shared by all 32 pins, if one number.
If two numbers, the first one is the interrupt shared by low 16 pins
and the second one is for high 16 pins.
minItems: 1
maxItems: 2
interrupt-controller: true
"#interrupt-cells":
const: 2
clocks:
maxItems: 1
"#gpio-cells":
const: 2
gpio-controller: true
gpio-line-names: true
gpio-ranges: true
power-domains:
maxItems: 1
patternProperties:
"^(hog-[0-9]+|.+-hog(-[0-9]+)?)$":
type: object
properties:
gpio-hog: true
gpios: true
input: true
output-high: true
output-low: true
line-name: true
required:
- gpio-hog
- gpios
additionalProperties: false
required:
- compatible
- reg
- interrupts
- interrupt-controller
- "#interrupt-cells"
- "#gpio-cells"
- gpio-controller
additionalProperties: false
examples:
- |
gpio0: gpio@73f84000 {
compatible = "fsl,imx35-gpio";
reg = <0x73f84000 0x4000>;
interrupts = <50 51>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
...

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Fujitsu MB86S7x GPIO Controller
-------------------------------
Required properties:
- compatible: Should be "fujitsu,mb86s70-gpio"
- reg: Base address and length of register space
- clocks: Specify the clock
- gpio-controller: Marks the device node as a gpio controller.
- #gpio-cells: Should be <2>. The first cell is the pin number and the
second cell is used to specify optional parameters:
- bit 0 specifies polarity (0 for normal, 1 for inverted).
Examples:
gpio0: gpio@31000000 {
compatible = "fujitsu,mb86s70-gpio";
reg = <0 0x31000000 0x10000>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&clk 0 2 1>;
};

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Gateworks PLD GPIO controller bindings
The GPIO controller should be a child node on an I2C bus,
see: i2c/i2c.txt for details.
Required properties:
- compatible: Should be "gateworks,pld-gpio"
- reg: I2C slave address
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Should be <2>. The first cell is the gpio number and
the second cell is used to specify optional parameters.
Example:
pld@56 {
compatible = "gateworks,pld-gpio";
reg = <0x56>;
gpio-controller;
#gpio-cells = <2>;
};

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* 74XX MMIO GPIO driver
Required properties:
- compatible: Should contain one of the following:
"ti,741g125": for 741G125 (1-bit Input),
"ti,741g174": for 741G74 (1-bit Output),
"ti,742g125": for 742G125 (2-bit Input),
"ti,7474" : for 7474 (2-bit Output),
"ti,74125" : for 74125 (4-bit Input),
"ti,74175" : for 74175 (4-bit Output),
"ti,74365" : for 74365 (6-bit Input),
"ti,74174" : for 74174 (6-bit Output),
"ti,74244" : for 74244 (8-bit Input),
"ti,74273" : for 74273 (8-bit Output),
"ti,741624" : for 741624 (16-bit Input),
"ti,7416374": for 7416374 (16-bit Output).
- reg: Physical base address and length where IC resides.
- gpio-controller: Marks the device node as a gpio controller.
- #gpio-cells: Should be two. The first cell is the pin number and
the second cell is used to specify the GPIO polarity:
0 = Active High,
1 = Active Low.
Example:
ctrl: gpio@30008004 {
compatible = "ti,74174";
reg = <0x30008004 0x1>;
gpio-controller;
#gpio-cells = <2>;
};

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Avionic Design N-bit GPIO expander bindings
Required properties:
- compatible: should be "ad,gpio-adnp"
- reg: The I2C slave address for this device.
- interrupts: Interrupt specifier for the controllers interrupt.
- #gpio-cells: Should be 2. The first cell is the GPIO number and the
second cell is used to specify optional parameters:
- bit 0: polarity (0: normal, 1: inverted)
- gpio-controller: Marks the device as a GPIO controller
- nr-gpios: The number of pins supported by the controller.
The GPIO expander can optionally be used as an interrupt controller, in
which case it uses the default two cell specifier as described in
Documentation/devicetree/bindings/interrupt-controller/interrupts.txt.
Example:
gpioext: gpio-controller@41 {
compatible = "ad,gpio-adnp";
reg = <0x41>;
interrupt-parent = <&gpio>;
interrupts = <160 1>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
nr-gpios = <64>;
};

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Altera GPIO controller bindings
Required properties:
- compatible:
- "altr,pio-1.0"
- reg: Physical base address and length of the controller's registers.
- #gpio-cells : Should be 2
- The first cell is the gpio offset number.
- The second cell is reserved and is currently unused.
- gpio-controller : Marks the device node as a GPIO controller.
- interrupt-controller: Mark the device node as an interrupt controller
- #interrupt-cells : Should be 2. The interrupt type is fixed in the hardware.
- The first cell is the GPIO offset number within the GPIO controller.
- The second cell is the interrupt trigger type and level flags.
- interrupts: Specify the interrupt.
- altr,interrupt-type: Specifies the interrupt trigger type the GPIO
hardware is synthesized. This field is required if the Altera GPIO controller
used has IRQ enabled as the interrupt type is not software controlled,
but hardware synthesized. Required if GPIO is used as an interrupt
controller. The value is defined in <dt-bindings/interrupt-controller/irq.h>
Only the following flags are supported:
IRQ_TYPE_EDGE_RISING
IRQ_TYPE_EDGE_FALLING
IRQ_TYPE_EDGE_BOTH
IRQ_TYPE_LEVEL_HIGH
Optional properties:
- altr,ngpio: Width of the GPIO bank. This defines how many pins the
GPIO device has. Ranges between 1-32. Optional and defaults to 32 if not
specified.
Example:
gpio_altr: gpio@ff200000 {
compatible = "altr,pio-1.0";
reg = <0xff200000 0x10>;
interrupts = <0 45 4>;
altr,ngpio = <32>;
altr,interrupt-type = <IRQ_TYPE_EDGE_RISING>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
};

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Aspeed GPIO controller Device Tree Bindings
-------------------------------------------
Required properties:
- compatible : Either "aspeed,ast2400-gpio", "aspeed,ast2500-gpio",
or "aspeed,ast2600-gpio".
- #gpio-cells : Should be two
- First cell is the GPIO line number
- Second cell is used to specify optional
parameters (unused)
- reg : Address and length of the register set for the device
- gpio-controller : Marks the device node as a GPIO controller.
- interrupts : Interrupt specifier (see interrupt bindings for
details)
- interrupt-controller : Mark the GPIO controller as an interrupt-controller
Optional properties:
- clocks : A phandle to the clock to use for debounce timings
- ngpios : Number of GPIOs controlled by this controller. Should be set
when there are multiple GPIO controllers on a SoC (ast2600).
The gpio and interrupt properties are further described in their respective
bindings documentation:
- Documentation/devicetree/bindings/gpio/gpio.txt
- Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
Example:
gpio@1e780000 {
#gpio-cells = <2>;
compatible = "aspeed,ast2400-gpio";
gpio-controller;
interrupts = <20>;
reg = <0x1e780000 0x1000>;
interrupt-controller;
};

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Binding for Qualcomm Atheros AR7xxx/AR9xxx GPIO controller
Required properties:
- compatible: has to be "qca,<soctype>-gpio" and one of the following
fallbacks:
- "qca,ar7100-gpio"
- "qca,ar9340-gpio"
- reg: Base address and size of the controllers memory area
- gpio-controller : Marks the device node as a GPIO controller.
- #gpio-cells : Should be two. The first cell is the pin number and the
second cell is used to specify optional parameters.
- ngpios: Should be set to the number of GPIOs available on the SoC.
Optional properties:
- interrupts: Interrupt specifier for the controllers interrupt.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode interrupt
source, should be 2
Please refer to interrupts.txt in this directory for details of the common
Interrupt Controllers bindings used by client devices.
Example:
gpio@18040000 {
compatible = "qca,ar9132-gpio", "qca,ar7100-gpio";
reg = <0x18040000 0x30>;
interrupts = <2>;
ngpios = <22>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};

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Cirrus Logic CLPS711X GPIO controller
Required properties:
- compatible: Should be "cirrus,ep7209-gpio"
- reg: Physical base GPIO controller registers location and length.
There should be two registers, first is DATA register, the second
is DIRECTION.
- gpio-controller: Marks the device node as a gpio controller.
- #gpio-cells: Should be two. The first cell is the pin number and
the second cell is used to specify the gpio polarity:
0 = active high
1 = active low
Note: Each GPIO port should have an alias correctly numbered in "aliases"
node.
Example:
aliases {
gpio0 = &porta;
};
porta: gpio@80000000 {
compatible = "cirrus,ep7312-gpio","cirrus,ep7209-gpio";
reg = <0x80000000 0x1>, <0x80000040 0x1>;
gpio-controller;
#gpio-cells = <2>;
};

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/gpio-consumer-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Common GPIO lines
maintainers:
- Bartosz Golaszewski <brgl@bgdev.pl>
- Linus Walleij <linus.walleij@linaro.org>
description:
Pay attention to using proper GPIO flag (e.g. GPIO_ACTIVE_LOW) for the GPIOs
using inverted signal (e.g. RESETN).
select: true
properties:
enable-gpios:
maxItems: 1
description:
GPIO connected to the enable control pin.
reset-gpios:
description:
GPIO (or GPIOs for power sequence) connected to the device reset pin
(e.g. RESET or RESETN).
powerdown-gpios:
maxItems: 1
description:
GPIO connected to the power down pin (hardware power down or power cut,
e.g. PD or PWDN).
pwdn-gpios:
maxItems: 1
description: Use powerdown-gpios
deprecated: true
wakeup-gpios:
maxItems: 1
description:
GPIO connected to the pin waking up the device from suspend or other
power-saving modes.
allOf:
- if:
properties:
compatible:
contains:
enum:
- mmc-pwrseq-simple
then:
properties:
reset-gpios:
minItems: 1
maxItems: 32
else:
properties:
reset-gpios:
maxItems: 1
additionalProperties: true

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/gpio-davinci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: GPIO controller for Davinci and keystone devices
maintainers:
- Keerthy <j-keerthy@ti.com>
properties:
compatible:
oneOf:
- items:
- enum:
- ti,k2g-gpio
- ti,am654-gpio
- ti,j721e-gpio
- ti,am64-gpio
- const: ti,keystone-gpio
- items:
- enum:
- ti,dm6441-gpio
- ti,keystone-gpio
reg:
maxItems: 1
gpio-controller: true
gpio-ranges: true
gpio-line-names:
description: strings describing the names of each gpio line.
minItems: 1
maxItems: 100
"#gpio-cells":
const: 2
description:
first cell is the pin number and second cell is used to specify optional parameters (unused).
interrupts:
description:
The interrupts are specified as per the interrupt parent. Only banked
or unbanked IRQs are supported at a time. If the interrupts are
banked then provide list of interrupts corresponding to each bank, else
provide the list of interrupts for each gpio.
minItems: 1
maxItems: 100
ti,ngpio:
$ref: /schemas/types.yaml#/definitions/uint32
description: The number of GPIO pins supported consecutively.
minimum: 1
ti,davinci-gpio-unbanked:
$ref: /schemas/types.yaml#/definitions/uint32
description: The number of GPIOs that have an individual interrupt line to processor.
minimum: 0
clocks:
maxItems: 1
clock-names:
const: gpio
interrupt-controller: true
power-domains:
maxItems: 1
"#interrupt-cells":
const: 2
patternProperties:
"^(.+-hog(-[0-9]+)?)$":
type: object
required:
- gpio-hog
required:
- compatible
- reg
- gpio-controller
- "#gpio-cells"
- interrupts
- ti,ngpio
- ti,davinci-gpio-unbanked
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include<dt-bindings/interrupt-controller/arm-gic.h>
gpio0: gpio@2603000 {
compatible = "ti,k2g-gpio", "ti,keystone-gpio";
reg = <0x02603000 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 434 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 435 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 437 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 438 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 439 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 440 IRQ_TYPE_EDGE_RISING>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <144>;
ti,davinci-gpio-unbanked = <0>;
clocks = <&k2g_clks 0x001b 0x0>;
clock-names = "gpio";
};
- |
#include<dt-bindings/interrupt-controller/arm-gic.h>
gpio1: gpio@260bf00 {
compatible = "ti,keystone-gpio";
reg = <0x0260bf00 0x100>;
gpio-controller;
#gpio-cells = <2>;
/* HW Interrupts mapped to GPIO pins */
interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkgpio>;
clock-names = "gpio";
ti,ngpio = <32>;
ti,davinci-gpio-unbanked = <32>;
};
- |
wkup_gpio0: gpio0@42110000 {
compatible = "ti,am654-gpio", "ti,keystone-gpio";
reg = <0x42110000 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&intr_wkup_gpio>;
interrupts = <60>, <61>, <62>, <63>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <56>;
ti,davinci-gpio-unbanked = <0>;
clocks = <&k3_clks 59 0>;
clock-names = "gpio";
};

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Keystone 2 DSP GPIO controller bindings
HOST OS userland running on ARM can send interrupts to DSP cores using
the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core.
This is one of the component used by the IPC mechanism used on Keystone SOCs.
For example TCI6638K2K SoC has 8 DSP GPIO controllers:
- 8 for C66x CorePacx CPUs 0-7
Keystone 2 DSP GPIO controller has specific features:
- each GPIO can be configured only as output pin;
- setting GPIO value to 1 causes IRQ generation on target DSP core;
- reading pin value returns 0 - if IRQ was handled or 1 - IRQ is still
pending.
Required Properties:
- compatible: should be "ti,keystone-dsp-gpio"
- ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
access device state control registers and the offset of device's specific
registers within device state control registers range.
- gpio-controller: Marks the device node as a gpio controller.
- #gpio-cells: Should be 2.
Please refer to gpio.txt in this directory for details of the common GPIO
bindings used by client devices.
Example:
dspgpio0: keystone_dsp_gpio@2620240 {
compatible = "ti,keystone-dsp-gpio";
ti,syscon-dev = <&devctrl 0x240>;
gpio-controller;
#gpio-cells = <2>;
};
dsp0: dsp0 {
compatible = "linux,rproc-user";
...
kick-gpio = <&dspgpio0 27>;
};

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Spreadtrum EIC controller bindings
The EIC is the abbreviation of external interrupt controller, which can
be used only in input mode. The Spreadtrum platform has 2 EIC controllers,
one is in digital chip, and another one is in PMIC. The digital chip EIC
controller contains 4 sub-modules: EIC-debounce, EIC-latch, EIC-async and
EIC-sync. But the PMIC EIC controller contains only one EIC-debounce sub-
module.
The EIC-debounce sub-module provides up to 8 source input signal
connections. A debounce mechanism is used to capture the input signals'
stable status (millisecond resolution) and a single-trigger mechanism
is introduced into this sub-module to enhance the input event detection
reliability. In addition, this sub-module's clock can be shut off
automatically to reduce power dissipation. Moreover the debounce range
is from 1ms to 4s with a step size of 1ms. The input signal will be
ignored if it is asserted for less than 1 ms.
The EIC-latch sub-module is used to latch some special power down signals
and generate interrupts, since the EIC-latch does not depend on the APB
clock to capture signals.
The EIC-async sub-module uses a 32kHz clock to capture the short signals
(microsecond resolution) to generate interrupts by level or edge trigger.
The EIC-sync is similar with GPIO's input function, which is a synchronized
signal input register. It can generate interrupts by level or edge trigger
when detecting input signals.
Required properties:
- compatible: Should be one of the following:
"sprd,sc9860-eic-debounce",
"sprd,sc9860-eic-latch",
"sprd,sc9860-eic-async",
"sprd,sc9860-eic-sync",
"sprd,sc2731-eic".
- reg: Define the base and range of the I/O address space containing
the GPIO controller registers.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Should be <2>. The first cell is the gpio number and
the second cell is used to specify optional parameters.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be <2>. Specifies the number of cells needed
to encode interrupt source.
- interrupts: Should be the port interrupt shared by all the gpios.
Example:
eic_debounce: gpio@40210000 {
compatible = "sprd,sc9860-eic-debounce";
reg = <0 0x40210000 0 0x80>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
};
eic_latch: gpio@40210080 {
compatible = "sprd,sc9860-eic-latch";
reg = <0 0x40210080 0 0x20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
};
eic_async: gpio@402100a0 {
compatible = "sprd,sc9860-eic-async";
reg = <0 0x402100a0 0 0x20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
};
eic_sync: gpio@402100c0 {
compatible = "sprd,sc9860-eic-sync";
reg = <0 0x402100c0 0 0x20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
};
pmic_eic: gpio@300 {
compatible = "sprd,sc2731-eic";
reg = <0x300>;
interrupt-parent = <&sc2731_pmic>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};

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Exportable MPIO interface of Exar UART chips
Required properties of the device:
- exar,first-pin: first exportable pins (0..15)
- ngpios: number of exportable pins (1..16)

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Aeroflex Gaisler GRGPIO General Purpose I/O cores.
The GRGPIO GPIO core is available in the GRLIB VHDL IP core library.
Note: In the ordinary environment for the GRGPIO core, a Leon SPARC system,
these properties are built from information in the AMBA plug&play.
Required properties:
- name : Should be "GAISLER_GPIO" or "01_01a"
- reg : Address and length of the register set for the device
- interrupts : Interrupt numbers for this device
Optional properties:
- nbits : The number of gpio lines. If not present driver assumes 32 lines.
- irqmap : An array with an index for each gpio line. An index is either a valid
index into the interrupts property array, or 0xffffffff that indicates
no irq for that line. Driver provides no interrupt support if not
present.
For further information look in the documentation for the GLIB IP core library:
http://www.gaisler.com/products/grlib/grip.pdf

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TI/National Semiconductor LP3943 GPIO controller
Required properties:
- compatible: "ti,lp3943-gpio"
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Should be 2. See gpio.txt in this directory for a
description of the cells format.
Example:
Simple LED controls with LP3943 GPIO controller
&i2c4 {
lp3943@60 {
compatible = "ti,lp3943";
reg = <0x60>;
gpioex: gpio {
compatible = "ti,lp3943-gpio";
gpio-controller;
#gpio-cells = <2>;
};
};
};
leds {
compatible = "gpio-leds";
indicator1 {
label = "indi1";
gpios = <&gpioex 9 GPIO_ACTIVE_LOW>;
};
indicator2 {
label = "indi2";
gpios = <&gpioex 10 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};

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GPIO driver for Maxim MAX3191x industrial serializer
Required properties:
- compatible: Must be one of:
"maxim,max31910"
"maxim,max31911"
"maxim,max31912"
"maxim,max31913"
"maxim,max31953"
"maxim,max31963"
- reg: Chip select number.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Should be two. For consumer use see gpio.txt.
Optional properties:
- #daisy-chained-devices:
Number of chips in the daisy-chain (default is 1).
- maxim,modesel-gpios: GPIO pins to configure modesel of each chip.
The number of GPIOs must equal "#daisy-chained-devices"
(if each chip is driven by a separate pin) or 1
(if all chips are wired to the same pin).
- maxim,fault-gpios: GPIO pins to read fault of each chip.
The number of GPIOs must equal "#daisy-chained-devices"
or 1.
- maxim,db0-gpios: GPIO pins to configure debounce of each chip.
The number of GPIOs must equal "#daisy-chained-devices"
or 1.
- maxim,db1-gpios: GPIO pins to configure debounce of each chip.
The number of GPIOs must equal "maxim,db0-gpios".
- maxim,modesel-8bit: Boolean whether the modesel pin of the chips is
pulled high (8-bit mode). Use this if the modesel pin
is hardwired and consequently "maxim,modesel-gpios"
cannot be specified. By default if neither this nor
"maxim,modesel-gpios" is given, the driver assumes
that modesel is pulled low (16-bit mode).
- maxim,ignore-undervoltage:
Boolean whether to ignore undervoltage alarms signaled
by the "maxim,fault-gpios" or by the status byte
(in 16-bit mode). Use this if the chips are powered
through 5VOUT instead of VCC24V, in which case they
will constantly signal undervoltage.
For other required and optional properties of SPI slave nodes please refer to
../spi/spi-bus.txt.
Example:
gpio@0 {
compatible = "maxim,max31913";
reg = <0>;
gpio-controller;
#gpio-cells = <2>;
maxim,modesel-gpios = <&gpio2 23>;
maxim,fault-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
maxim,db0-gpios = <&gpio2 25>;
maxim,db1-gpios = <&gpio2 26>;
spi-max-frequency = <25000000>;
};

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GPIO driver for MAX77620 Power management IC from Maxim Semiconductor.
Device has 8 GPIO pins which can be configured as GPIO as well as the
special IO functions.
Required properties:
-------------------
- gpio-controller : Marks the device node as a gpio controller.
- #gpio-cells : Should be two. The first cell is the pin number and
the second cell is used to specify the gpio polarity:
0 = active high
1 = active low
For more details, please refer generic GPIO DT binding document
<devicetree/bindings/gpio/gpio.txt>.
Example:
--------
#include <dt-bindings/mfd/max77620.h>
...
max77620@3c {
compatible = "maxim,max77620";
gpio-controller;
#gpio-cells = <2>;
};

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Lantiq SoC External Bus memory mapped GPIO controller
By attaching hardware latches to the EBU it is possible to create output
only gpios. This driver configures a special memory address, which when
written to outputs 16 bit to the latches.
The node describing the memory mapped GPIOs needs to be a child of the node
describing the "lantiq,localbus".
Required properties:
- compatible : Should be "lantiq,gpio-mm-lantiq"
- reg : Address and length of the register set for the device
- #gpio-cells : Should be two. The first cell is the pin number and
the second cell is used to specify optional parameters (currently
unused).
- gpio-controller : Marks the device node as a gpio controller.
Optional properties:
- lantiq,shadow : The default value that we shall assume as already set on the
shift register cascade.
Example:
localbus@0 {
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x0 0x3ffffff /* addrsel0 */
1 0 0x4000000 0x4000010>; /* addsel1 */
compatible = "lantiq,localbus", "simple-bus";
gpio_mm0: gpio@4000000 {
compatible = "lantiq,gpio-mm";
reg = <1 0x0 0x10>;
gpio-controller;
#gpio-cells = <2>;
lantiq,shadow = <0x77f>
};
}

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Turris Mox Moxtet GPIO expander via Moxtet bus
Required properties:
- compatible : Should be "cznic,moxtet-gpio".
- gpio-controller : Marks the device node as a GPIO controller.
- #gpio-cells : Should be two. For consumer use see gpio.txt.
Other properties are required for a Moxtet bus device, please refer to
Documentation/devicetree/bindings/bus/moxtet.txt.
Example:
moxtet_sfp: gpio@0 {
compatible = "cznic,moxtet-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0>;
}

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* Freescale MPC512x/MPC8xxx/QorIQ/Layerscape GPIO controller
Required properties:
- compatible : Should be "fsl,<soc>-gpio"
The following <soc>s are known to be supported:
mpc5121, mpc5125, mpc8349, mpc8572, mpc8610, pq3, qoriq,
ls1021a, ls1043a, ls2080a, ls1028a, ls1088a.
- reg : Address and length of the register set for the device
- interrupts : Should be the port interrupt shared by all 32 pins.
- #gpio-cells : Should be two. The first cell is the pin number and
the second cell is used to specify the gpio polarity:
0 = active high
1 = active low
Optional properties:
- little-endian : GPIO registers are used as little endian. If not
present registers are used as big endian by default.
Example of gpio-controller node for a mpc5125 SoC:
gpio0: gpio@1100 {
compatible = "fsl,mpc5125-gpio";
#gpio-cells = <2>;
reg = <0x1100 0x080>;
interrupts = <78 0x8>;
};
Example of gpio-controller node for a ls2080a SoC:
gpio0: gpio@2300000 {
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
interrupts = <0 36 0x4>; /* Level high type */
gpio-controller;
little-endian;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
Example of gpio-controller node for a ls1028a/ls1088a SoC:
gpio1: gpio@2300000 {
compatible = "fsl,ls1028a-gpio", "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
little-endian;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/gpio-mvebu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell EBU GPIO controller
maintainers:
- Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- Andrew Lunn <andrew@lunn.ch>
properties:
compatible:
oneOf:
- enum:
- marvell,armada-8k-gpio
- marvell,orion-gpio
- items:
- enum:
- marvell,mv78200-gpio
- marvell,armada-370-gpio
- const: marvell,orion-gpio
- description: Deprecated binding
items:
- const: marvell,armadaxp-gpio
- const: marvell,orion-gpio
deprecated: true
reg:
description: |
Address and length of the register set for the device. Not used for
marvell,armada-8k-gpio.
A second entry can be provided, for the PWM function using the GPIO Blink
Counter on/off registers.
minItems: 1
maxItems: 2
reg-names:
items:
- const: gpio
- const: pwm
minItems: 1
offset:
$ref: /schemas/types.yaml#/definitions/uint32
description: Offset in the register map for the gpio registers (in bytes)
interrupts:
description: |
The list of interrupts that are used for all the pins managed by this
GPIO bank. There can be more than one interrupt (example: 1 interrupt
per 8 pins on Armada XP, which means 4 interrupts per bank of 32
GPIOs).
minItems: 1
maxItems: 4
interrupt-controller: true
"#interrupt-cells":
const: 2
gpio-controller: true
ngpios:
minimum: 1
maximum: 32
"#gpio-cells":
const: 2
marvell,pwm-offset:
$ref: /schemas/types.yaml#/definitions/uint32
description: Offset in the register map for the pwm registers (in bytes)
"#pwm-cells":
description:
The first cell is the GPIO line number. The second cell is the period
in nanoseconds.
const: 2
clocks:
description:
Clock(s) used for PWM function.
items:
- description: Core clock
- description: AXI bus clock
minItems: 1
clock-names:
items:
- const: core
- const: axi
minItems: 1
required:
- compatible
- gpio-controller
- ngpios
- "#gpio-cells"
allOf:
- if:
properties:
compatible:
contains:
const: marvell,armada-8k-gpio
then:
required:
- offset
else:
required:
- reg
unevaluatedProperties: true
examples:
- |
gpio@d0018100 {
compatible = "marvell,armadaxp-gpio", "marvell,orion-gpio";
reg = <0xd0018100 0x40>, <0xd0018800 0x30>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <16>, <17>, <18>, <19>;
};
- |
gpio@18140 {
compatible = "marvell,armada-370-gpio", "marvell,orion-gpio";
reg = <0x18140 0x40>, <0x181c8 0x08>;
reg-names = "gpio", "pwm";
ngpios = <17>;
gpio-controller;
#gpio-cells = <2>;
#pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <87>, <88>, <89>;
clocks = <&coreclk 0>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/gpio-mxs.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale MXS GPIO controller
maintainers:
- Shawn Guo <shawnguo@kernel.org>
- Anson Huang <Anson.Huang@nxp.com>
description: |
The Freescale MXS GPIO controller is part of MXS PIN controller.
The GPIOs are organized in port/bank, each port consists of 32 GPIOs.
As the GPIO controller is embedded in the PIN controller and all the
GPIO ports share the same IO space with PIN controller, the GPIO node
will be represented as sub-nodes of MXS pinctrl node.
properties:
compatible:
enum:
- fsl,imx23-pinctrl
- fsl,imx28-pinctrl
'#address-cells':
const: 1
'#size-cells':
const: 0
reg:
maxItems: 1
patternProperties:
"gpio@[0-9]+$":
type: object
properties:
compatible:
enum:
- fsl,imx23-gpio
- fsl,imx28-gpio
reg:
maxItems: 1
interrupts:
description: Should be the port interrupt shared by all 32 pins.
maxItems: 1
interrupt-controller: true
"#interrupt-cells":
const: 2
"#gpio-cells":
const: 2
gpio-controller: true
required:
- compatible
- reg
- interrupts
- interrupt-controller
- "#interrupt-cells"
- "#gpio-cells"
- gpio-controller
additionalProperties: false
required:
- compatible
- reg
- '#address-cells'
- '#size-cells'
additionalProperties: false
examples:
- |
pinctrl@80018000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx28-pinctrl";
reg = <0x80018000 0x2000>;
gpio@0 {
compatible = "fsl,imx28-gpio";
reg = <0>;
interrupts = <127>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio@1 {
compatible = "fsl,imx28-gpio";
reg = <1>;
interrupts = <126>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio@2 {
compatible = "fsl,imx28-gpio";
reg = <2>;
interrupts = <125>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio@3 {
compatible = "fsl,imx28-gpio";
reg = <3>;
interrupts = <124>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio@4 {
compatible = "fsl,imx28-gpio";
reg = <4>;
interrupts = <123>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};

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Nomadik GPIO controller
Required properties:
- compatible : Should be "st,nomadik-gpio".
- reg : Physical base address and length of the controller's registers.
- interrupts : The interrupt outputs from the controller.
- #gpio-cells : Should be two:
The first cell is the pin number.
The second cell is used to specify optional parameters:
- bits[3:0] trigger type and level flags:
1 = low-to-high edge triggered.
2 = high-to-low edge triggered.
4 = active high level-sensitive.
8 = active low level-sensitive.
- gpio-controller : Marks the device node as a GPIO controller.
- interrupt-controller : Marks the device node as an interrupt controller.
- gpio-bank : Specifies which bank a controller owns.
- st,supports-sleepmode : Specifies whether controller can sleep or not
Example:
gpio1: gpio@8012e080 {
compatible = "st,nomadik-gpio";
reg = <0x8012e080 0x80>;
interrupts = <0 120 0x4>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
st,supports-sleepmode;
gpio-bank = <1>;
};

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Palmas GPIO controller bindings
Required properties:
- compatible:
- "ti,palams-gpio" for palma series of the GPIO controller
- "ti,tps80036-gpio" for Palma series device TPS80036.
- "ti,tps65913-gpio" for palma series device TPS65913.
- "ti,tps65914-gpio" for palma series device TPS65914.
- #gpio-cells : Should be two.
- first cell is the gpio pin number
- second cell is used to specify the gpio polarity:
0 = active high
1 = active low
- gpio-controller : Marks the device node as a GPIO controller.
Note: This gpio node will be sub node of palmas node.
Example:
palmas: tps65913@58 {
:::::::::::
palmas_gpio: palmas_gpio {
compatible = "ti,palmas-gpio";
gpio-controller;
#gpio-cells = <2>;
};
:::::::::::
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/gpio-pca9570.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: PCA9570 I2C GPO expander
maintainers:
- Sungbo Eo <mans0n@gorani.run>
properties:
compatible:
enum:
- nxp,pca9570
- nxp,pca9571
reg:
maxItems: 1
gpio-controller: true
'#gpio-cells':
const: 2
required:
- compatible
- reg
- gpio-controller
- "#gpio-cells"
additionalProperties: false
examples:
- |
i2c0 {
#address-cells = <1>;
#size-cells = <0>;
gpio@24 {
compatible = "nxp,pca9570";
reg = <0x24>;
gpio-controller;
#gpio-cells = <2>;
};
};
...

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/gpio-pca95xx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP PCA95xx I2C GPIO multiplexer
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
description: |+
Bindings for the family of I2C GPIO multiplexers/expanders: NXP PCA95xx,
Maxim MAX73xx
properties:
compatible:
oneOf:
- items:
- const: diodes,pi4ioe5v6534q
- const: nxp,pcal6534
- items:
- enum:
- exar,xra1202
- maxim,max7310
- maxim,max7312
- maxim,max7313
- maxim,max7315
- maxim,max7319
- maxim,max7320
- maxim,max7321
- maxim,max7322
- maxim,max7323
- maxim,max7324
- maxim,max7325
- maxim,max7326
- maxim,max7327
- nxp,pca6408
- nxp,pca6416
- nxp,pca9505
- nxp,pca9506
- nxp,pca9534
- nxp,pca9535
- nxp,pca9536
- nxp,pca9537
- nxp,pca9538
- nxp,pca9539
- nxp,pca9554
- nxp,pca9555
- nxp,pca9556
- nxp,pca9557
- nxp,pca9574
- nxp,pca9575
- nxp,pca9698
- nxp,pcal6408
- nxp,pcal6416
- nxp,pcal6524
- nxp,pcal6534
- nxp,pcal9535
- nxp,pcal9554b
- nxp,pcal9555a
- onnn,cat9554
- onnn,pca9654
- ti,pca6107
- ti,pca9536
- ti,tca6408
- ti,tca6416
- ti,tca6424
- ti,tca9539
- ti,tca9554
reg:
maxItems: 1
gpio-controller: true
'#gpio-cells':
const: 2
gpio-line-names:
minItems: 1
maxItems: 40
interrupts:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
reset-gpios:
maxItems: 1
description:
GPIO specification for the RESET input. This is an active low signal to
the PCA953x. Not valid for Maxim MAX732x devices.
vcc-supply:
description:
Optional power supply. Not valid for Maxim MAX732x devices.
wakeup-source:
$ref: /schemas/types.yaml#/definitions/flag
patternProperties:
"^(hog-[0-9]+|.+-hog(-[0-9]+)?)$":
type: object
properties:
gpio-hog: true
gpios: true
input: true
output-high: true
output-low: true
line-name: true
required:
- gpio-hog
- gpios
additionalProperties: false
required:
- compatible
- reg
- gpio-controller
- "#gpio-cells"
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
enum:
- maxim,max7320
- maxim,max7321
- maxim,max7322
- maxim,max7323
- maxim,max7324
- maxim,max7325
- maxim,max7326
- maxim,max7327
then:
properties:
reset-gpios: false
vcc-supply: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c0 {
#address-cells = <1>;
#size-cells = <0>;
gpio@20 {
compatible = "nxp,pca9505";
reg = <0x20>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pca9505>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio3>;
interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
usb3-sata-sel-hog {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "usb3_sata_sel";
};
};
};
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c1 {
#address-cells = <1>;
#size-cells = <0>;
gpio99: gpio@22 {
compatible = "nxp,pcal6524";
reg = <0x22>;
interrupt-parent = <&gpio6>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>; /* gpio6_161 */
interrupt-controller;
#interrupt-cells = <2>;
vcc-supply = <&vdds_1v8_main>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "hdmi-ct-hpd", "hdmi.ls-oe", "p02", "p03",
"vibra", "fault2", "p06", "p07", "en-usb",
"en-host1", "en-host2", "chg-int", "p14", "p15",
"mic-int", "en-modem", "shdn-hs-amp",
"chg-status+red", "green", "blue", "en-esata",
"fault1", "p26", "p27";
};
};
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c2 {
#address-cells = <1>;
#size-cells = <0>;
/* MAX7325 with interrupt support enabled */
gpio@6d {
compatible = "maxim,max7325";
reg = <0x6d>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gpio4>;
interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
};
};
- |
i2c3 {
#address-cells = <1>;
#size-cells = <0>;
/* MAX7325 with interrupt support disabled */
gpio@6e {
compatible = "maxim,max7325";
reg = <0x6e>;
gpio-controller;
#gpio-cells = <2>;
};
};

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Generic Parallel-in/Serial-out Shift Register GPIO Driver
This binding describes generic parallel-in/serial-out shift register
devices that can be used for GPI (General Purpose Input). This includes
SN74165 serial-out shift registers and the SN65HVS88x series of
industrial serializers.
Required properties:
- compatible : Should be "pisosr-gpio".
- gpio-controller : Marks the device node as a GPIO controller.
- #gpio-cells : Should be two. For consumer use see gpio.txt.
Optional properties:
- ngpios : Number of used GPIO lines (0..n-1), default is 8.
- load-gpios : GPIO pin specifier attached to load enable, this
pin is pulsed before reading from the device to
load input pin values into the device.
For other required and optional properties of SPI slave
nodes please refer to ../spi/spi-bus.txt.
Example:
gpio@0 {
compatible = "ti,sn65hvs882", "pisosr-gpio";
gpio-controller;
#gpio-cells = <2>;
load-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
reg = <0>;
spi-max-frequency = <1000000>;
spi-cpol;
};

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/gpio-rda.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: RDA Micro GPIO controller
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
properties:
compatible:
const: rda,8810pl-gpio
reg:
maxItems: 1
gpio-controller: true
"#gpio-cells":
const: 2
ngpios:
description:
Number of available gpios in a bank.
minimum: 1
maximum: 32
interrupt-controller: true
"#interrupt-cells":
const: 2
interrupts:
maxItems: 1
required:
- compatible
- reg
- gpio-controller
- "#gpio-cells"
- ngpios
- interrupt-controller
- "#interrupt-cells"
- interrupts
additionalProperties: false
...

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Spreadtrum GPIO controller bindings
The controller's registers are organized as sets of sixteen 16-bit
registers with each set controlling a bank of up to 16 pins. A single
interrupt is shared for all of the banks handled by the controller.
Required properties:
- compatible: Should be "sprd,sc9860-gpio".
- reg: Define the base and range of the I/O address space containing
the GPIO controller registers.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Should be <2>. The first cell is the gpio number and
the second cell is used to specify optional parameters.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be <2>. Specifies the number of cells needed
to encode interrupt source.
- interrupts: Should be the port interrupt shared by all the gpios.
Example:
ap_gpio: gpio@40280000 {
compatible = "sprd,sc9860-gpio";
reg = <0 0x40280000 0 0x1000>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
};

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STMPE gpio
----------
Required properties:
- compatible: "st,stmpe-gpio"
Optional properties:
- st,norequest-mask: bitmask specifying which GPIOs should _not_ be requestable
due to different usage (e.g. touch, keypad)
Node should be child node of stmpe node to which it belongs.
Example:
stmpe_gpio {
compatible = "st,stmpe-gpio";
st,norequest-mask = <0x20>; //gpio 5 can't be used
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/gpio-stp-xway.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Lantiq SoC Serial To Parallel (STP) GPIO controller
description: |
The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a
peripheral controller used to drive external shift register cascades. At most
3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem
and Ethernet PHYs to drive some bytes of the cascade automatically.
maintainers:
- John Crispin <john@phrozen.org>
properties:
$nodename:
pattern: "^gpio@[0-9a-f]+$"
compatible:
const: lantiq,gpio-stp-xway
reg:
maxItems: 1
gpio-controller: true
"#gpio-cells":
description:
The first cell is the pin number and the second cell is used to specify
consumer flags.
const: 2
lantiq,shadow:
description:
The default value that we shall assume as already set on the
shift register cascade.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0x000000
maximum: 0xffffff
lantiq,groups:
description:
Set the 3 bit mask to select which of the 3 groups are enabled
in the shift register cascade.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0x0
maximum: 0x7
lantiq,dsl:
description:
The dsl core can control the 2 LSBs of the gpio cascade. This 2 bit
property can enable this feature.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0x0
maximum: 0x3
lantiq,rising:
description:
Use rising instead of falling edge for the shift register.
type: boolean
patternProperties:
"^lantiq,phy[1-4]$":
description:
The gphy core can control 3 bits of the gpio cascade. In the xRX200 family
phy[1-2] are available, in xRX330 phy[1-3] and in XRX330 phy[1-4].
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0x0
maximum: 0x7
required:
- compatible
- reg
- gpio-controller
- "#gpio-cells"
additionalProperties: false
examples:
- |
gpio@e100bb0 {
compatible = "lantiq,gpio-stp-xway";
reg = <0xE100BB0 0x40>;
#gpio-cells = <2>;
gpio-controller;
pinctrl-0 = <&stp_pins>;
pinctrl-names = "default";
lantiq,shadow = <0xffffff>;
lantiq,groups = <0x7>;
lantiq,dsl = <0x3>;
lantiq,phy1 = <0x7>;
lantiq,phy2 = <0x7>;
};
...

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Cavium ThunderX/OCTEON-TX GPIO controller bindings
Required Properties:
- reg: The controller bus address.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Must be 2.
- First cell is the GPIO pin number relative to the controller.
- Second cell is a standard generic flag bitfield as described in gpio.txt.
Optional Properties:
- compatible: "cavium,thunder-8890-gpio", unused as PCI driver binding is used.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Must be present and have value of 2 if
"interrupt-controller" is present.
- First cell is the GPIO pin number relative to the controller.
- Second cell is triggering flags as defined in interrupts.txt.
Example:
gpio_6_0: gpio@6,0 {
compatible = "cavium,thunder-8890-gpio";
reg = <0x3000 0 0 0 0>; /* DEVFN = 0x30 (6:0) */
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/gpio-tpic2810.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TPIC2810 GPIO controller bindings
maintainers:
- Aswath Govindraju <a-govindraju@ti.com>
properties:
compatible:
enum:
- ti,tpic2810
reg:
maxItems: 1
gpio-controller: true
"#gpio-cells":
const: 2
gpio-line-names:
minItems: 1
maxItems: 32
required:
- compatible
- reg
- gpio-controller
- "#gpio-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
gpio@60 {
compatible = "ti,tpic2810";
reg = <0x60>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "LED A", "LED B", "LED C";
};
};

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* TS-4800 FPGA's GPIO controller bindings
Required properties:
- compatible: Must be "technologic,ts4800-gpio".
- #gpio-cells: Should be two. The first cell is the pin number.
- reg: Physical base address of the controller and length
of memory mapped region.
Optional property:
- ngpios: See "gpio.txt"
Example:
gpio1: gpio {
compatible = "technologic,ts4800-gpio";
reg = <0x10020 0x6>;
ngpios = <8>;
gpio-controller;
#gpio-cells = <2>;
};

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* Technologic Systems I2C-FPGA's GPIO controller bindings
This bindings describes the GPIO controller for Technologic's FPGA core.
TS-4900's FPGA encodes the GPIO state on 3 bits, whereas the TS-7970's FPGA
uses 2 bits: it doesn't use a dedicated input bit.
Required properties:
- compatible: Should be one of the following
"technologic,ts4900-gpio"
"technologic,ts7970-gpio"
- reg: Physical base address of the controller and length
of memory mapped region.
- #gpio-cells: Should be two. The first cell is the pin number.
- gpio-controller: Marks the device node as a gpio controller.
Optional property:
- ngpios: Number of GPIOs this controller is instantiated with,
the default is 32. See gpio.txt for more details.
Example:
&i2c2 {
gpio8: gpio@28 {
compatible = "technologic,ts4900-gpio";
reg = <0x28>;
#gpio-cells = <2>;
gpio-controller;
ngpios = <32>;
};
};

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twl4030 GPIO controller bindings
Required properties:
- compatible:
- "ti,twl4030-gpio" for twl4030 GPIO controller
- #gpio-cells : Should be two.
- first cell is the pin number
- second cell is used to specify optional parameters (unused)
- gpio-controller : Marks the device node as a GPIO controller.
- #interrupt-cells : Should be 2.
- interrupt-controller: Mark the device node as an interrupt controller
The first cell is the GPIO number.
The second cell is not used.
- ti,use-leds : Enables LEDA and LEDB outputs if set
- ti,debounce : if n-th bit is set, debounces GPIO-n
- ti,mmc-cd : if n-th bit is set, GPIO-n controls VMMC(n+1)
- ti,pullups : if n-th bit is set, set a pullup on GPIO-n
- ti,pulldowns : if n-th bit is set, set a pulldown on GPIO-n
Example:
twl_gpio: gpio {
compatible = "ti,twl4030-gpio";
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
ti,use-leds;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/gpio-vf610.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale VF610 PORT/GPIO module
maintainers:
- Stefan Agner <stefan@agner.ch>
description: |
The Freescale PORT/GPIO modules are two adjacent modules providing GPIO
functionality. Each pair serves 32 GPIOs. The VF610 has 5 instances of
each, and each PORT module has its own interrupt.
Note: Each GPIO port should have an alias correctly numbered in "aliases"
node.
properties:
compatible:
oneOf:
- const: fsl,vf610-gpio
- items:
- const: fsl,imx7ulp-gpio
- const: fsl,vf610-gpio
- items:
- enum:
- fsl,imx93-gpio
- fsl,imx8ulp-gpio
- const: fsl,imx7ulp-gpio
reg:
description: The first reg tuple represents the PORT module, the second tuple
represents the GPIO module.
maxItems: 2
interrupts:
maxItems: 1
interrupt-controller: true
"#interrupt-cells":
const: 2
"#gpio-cells":
const: 2
gpio-controller: true
clocks:
items:
- description: SoC GPIO clock
- description: SoC PORT clock
clock-names:
items:
- const: gpio
- const: port
gpio-ranges:
maxItems: 1
required:
- compatible
- reg
- interrupts
- interrupt-controller
- "#interrupt-cells"
- "#gpio-cells"
- gpio-controller
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
gpio1: gpio@40049000 {
compatible = "fsl,vf610-gpio";
reg = <0x40049000 0x1000>, <0x400ff000 0x40>;
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 0 32>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/gpio-virtio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Virtio GPIO controller
maintainers:
- Viresh Kumar <viresh.kumar@linaro.org>
allOf:
- $ref: /schemas/virtio/virtio-device.yaml#
description:
Virtio GPIO controller, see /schemas/virtio/virtio-device.yaml for more
details.
properties:
$nodename:
const: gpio
compatible:
const: virtio,device29
gpio-controller: true
"#gpio-cells":
const: 2
interrupt-controller: true
"#interrupt-cells":
const: 2
required:
- compatible
- gpio-controller
- "#gpio-cells"
unevaluatedProperties: false
examples:
- |
virtio@3000 {
compatible = "virtio,mmio";
reg = <0x3000 0x100>;
interrupts = <41>;
gpio {
compatible = "virtio,device29";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
...

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APM X-Gene Standby GPIO controller bindings
This is a gpio controller in the standby domain. It also supports interrupt in
some particular pins which are sourced to its parent interrupt controller
as diagram below:
+-----------------+
| X-Gene standby |
| GPIO controller +------ GPIO_0
+------------+ | | ...
| Parent IRQ | EXT_INT_0 | +------ GPIO_8/EXT_INT_0
| controller | (SPI40) | | ...
| (GICv2) +--------------+ +------ GPIO_[N+8]/EXT_INT_N
| | ... | |
| | EXT_INT_N | +------ GPIO_[N+9]
| | (SPI[40 + N])| | ...
| +--------------+ +------ GPIO_MAX
+------------+ +-----------------+
Required properties:
- compatible: "apm,xgene-gpio-sb" for the X-Gene Standby GPIO controller
- reg: Physical base address and size of the controller's registers
- #gpio-cells: Should be two.
- first cell is the pin number
- second cell is used to specify the gpio polarity:
0 = active high
1 = active low
- gpio-controller: Marks the device node as a GPIO controller.
- interrupts: The EXT_INT_0 parent interrupt resource must be listed first.
- interrupt-cells: Should be two.
- first cell is 0-N coresponding for EXT_INT_0 to EXT_INT_N.
- second cell is used to specify flags.
- interrupt-controller: Marks the device node as an interrupt controller.
- apm,nr-gpios: Optional, specify number of gpios pin.
- apm,nr-irqs: Optional, specify number of interrupt pins.
- apm,irq-start: Optional, specify lowest gpio pin support interrupt.
Example:
sbgpio: gpio@17001000{
compatible = "apm,xgene-gpio-sb";
reg = <0x0 0x17001000 0x0 0x400>;
#gpio-cells = <2>;
gpio-controller;
interrupts = <0x0 0x28 0x1>,
<0x0 0x29 0x1>,
<0x0 0x2a 0x1>,
<0x0 0x2b 0x1>,
<0x0 0x2c 0x1>,
<0x0 0x2d 0x1>;
interrupt-parent = <&gic>;
#interrupt-cells = <2>;
interrupt-controller;
apm,nr-gpios = <22>;
apm,nr-irqs = <6>;
apm,irq-start = <8>;
};
testuser {
compatible = "example,testuser";
/* Use the GPIO_13/EXT_INT_5 line as an active high triggered
* level interrupt
*/
interrupts = <5 4>;
interrupt-parent = <&sbgpio>;
};

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APM X-Gene SoC GPIO controller bindings
This is a gpio controller that is part of the flash controller.
This gpio controller controls a total of 48 gpios.
Required properties:
- compatible: "apm,xgene-gpio" for X-Gene GPIO controller
- reg: Physical base address and size of the controller's registers
- #gpio-cells: Should be two.
- first cell is the pin number
- second cell is used to specify the gpio polarity:
0 = active high
1 = active low
- gpio-controller: Marks the device node as a GPIO controller.
Example:
gpio0: gpio0@1701c000 {
compatible = "apm,xgene-gpio";
reg = <0x0 0x1701c000 0x0 0x40>;
gpio-controller;
#gpio-cells = <2>;
};

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GPIO Driver for XRA1403 16-BIT GPIO Expander With Reset Input from EXAR
The XRA1403 is an 16-bit GPIO expander with an SPI interface. Features available:
- Individually programmable inputs:
- Internal pull-up resistors
- Polarity inversion
- Individual interrupt enable
- Rising edge and/or Falling edge interrupt
- Input filter
- Individually programmable outputs
- Output Level Control
- Output Three-State Control
Properties
----------
Check documentation for SPI and GPIO controllers regarding properties needed to configure the node.
- compatible = "exar,xra1403".
- reg - SPI id of the device.
- gpio-controller - marks the node as gpio.
- #gpio-cells - should be two where the first cell is the pin number
and the second one is used for optional parameters.
Optional properties:
-------------------
- reset-gpios: in case available used to control the device reset line.
- interrupt-controller - marks the node as interrupt controller.
- #interrupt-cells - should be two and represents the number of cells
needed to encode interrupt source.
Example
--------
gpioxra0: gpio@2 {
compatible = "exar,xra1403";
reg = <2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reset-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
spi-max-frequency = <1000000>;
};

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Zevio GPIO controller
Required properties:
- compatible: Should be "lsi,zevio-gpio"
- reg: Address and length of the register set for the device
- #gpio-cells: Should be two. The first cell is the pin number and the
second cell is used to specify optional parameters (currently unused).
- gpio-controller: Marks the device node as a GPIO controller.
Example:
gpio: gpio@90000000 {
compatible = "lsi,zevio-gpio";
reg = <0x90000000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
};

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/gpio-zynq.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq GPIO controller
maintainers:
- Michal Simek <michal.simek@xilinx.com>
properties:
compatible:
enum:
- xlnx,zynq-gpio-1.0
- xlnx,zynqmp-gpio-1.0
- xlnx,versal-gpio-1.0
- xlnx,pmc-gpio-1.0
reg:
maxItems: 1
"#gpio-cells":
const: 2
interrupts:
maxItems: 1
gpio-controller: true
gpio-line-names:
description: strings describing the names of each gpio line
minItems: 58
maxItems: 174
interrupt-controller: true
"#interrupt-cells":
const: 2
clocks:
maxItems: 1
power-domains:
maxItems: 1
allOf:
- if:
properties:
compatible:
enum:
- xlnx,zynqmp-gpio-1.0
then:
properties:
gpio-line-names:
minItems: 174
maxItems: 174
- if:
properties:
compatible:
enum:
- xlnx,zynq-gpio-1.0
then:
properties:
gpio-line-names:
minItems: 118
maxItems: 118
- if:
properties:
compatible:
enum:
- xlnx,versal-gpio-1.0
then:
properties:
gpio-line-names:
minItems: 58
maxItems: 58
- if:
properties:
compatible:
enum:
- xlnx,pmc-gpio-1.0
then:
properties:
gpio-line-names:
minItems: 116
maxItems: 116
required:
- compatible
- reg
- "#gpio-cells"
- interrupts
- gpio-controller
- interrupt-controller
- "#interrupt-cells"
- clocks
additionalProperties: false
examples:
- |
gpio@e000a000 {
#gpio-cells = <2>;
compatible = "xlnx,zynq-gpio-1.0";
clocks = <&clkc 42>;
gpio-controller;
interrupt-parent = <&intc>;
interrupts = <0 20 4>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0xe000a000 0x1000>;
};

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Specifying GPIO information for devices
=======================================
1) gpios property
-----------------
GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
of this GPIO for the device. While a non-existent <name> is considered valid
for compatibility reasons (resolving to the "gpios" property), it is not allowed
for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
bindings use it, but are only supported for compatibility reasons and should not
be used for newer bindings since it has been deprecated.
GPIO properties can contain one or more GPIO phandles, but only in exceptional
cases should they contain more than one. If your device uses several GPIOs with
distinct functions, reference each of them under its own property, giving it a
meaningful name. The only case where an array of GPIOs is accepted is when
several GPIOs serve the same function (e.g. a parallel data line).
The exact purpose of each gpios property must be documented in the device tree
binding of the device.
The following example could be used to describe GPIO pins used as device enable
and bit-banged data signals:
gpio1: gpio1 {
gpio-controller;
#gpio-cells = <2>;
};
[...]
data-gpios = <&gpio1 12 0>,
<&gpio1 13 0>,
<&gpio1 14 0>,
<&gpio1 15 0>;
In the above example, &gpio1 uses 2 cells to specify a gpio. The first cell is
a local offset to the GPIO line and the second cell represent consumer flags,
such as if the consumer desire the line to be active low (inverted) or open
drain. This is the recommended practice.
The exact meaning of each specifier cell is controller specific, and must be
documented in the device tree binding for the device, but it is strongly
recommended to use the two-cell approach.
Most controllers are specifying a generic flag bitfield in the last cell, so
for these, use the macros defined in
include/dt-bindings/gpio/gpio.h whenever possible:
Example of a node using GPIOs:
node {
enable-gpios = <&qe_pio_e 18 GPIO_ACTIVE_HIGH>;
};
GPIO_ACTIVE_HIGH is 0, so in this example gpio-specifier is "18 0" and encodes
GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller.
Optional standard bitfield specifiers for the last cell:
- Bit 0: 0 means active high, 1 means active low
- Bit 1: 0 mean push-pull wiring, see:
https://en.wikipedia.org/wiki/Push-pull_output
1 means single-ended wiring, see:
https://en.wikipedia.org/wiki/Single-ended_triode
- Bit 2: 0 means open-source, 1 means open drain, see:
https://en.wikipedia.org/wiki/Open_collector
- Bit 3: 0 means the output should be maintained during sleep/low-power mode
1 means the output state can be lost during sleep/low-power mode
- Bit 4: 0 means no pull-up resistor should be enabled
1 means a pull-up resistor should be enabled
This setting only applies to hardware with a simple on/off
control for pull-up configuration. If the hardware has more
elaborate pull-up configuration, it should be represented
using a pin control binding.
- Bit 5: 0 means no pull-down resistor should be enabled
1 means a pull-down resistor should be enabled
This setting only applies to hardware with a simple on/off
control for pull-down configuration. If the hardware has more
elaborate pull-down configuration, it should be represented
using a pin control binding.
1.1) GPIO specifier best practices
----------------------------------
A gpio-specifier should contain a flag indicating the GPIO polarity; active-
high or active-low. If it does, the following best practices should be
followed:
The gpio-specifier's polarity flag should represent the physical level at the
GPIO controller that achieves (or represents, for inputs) a logically asserted
value at the device. The exact definition of logically asserted should be
defined by the binding for the device. If the board inverts the signal between
the GPIO controller and the device, then the gpio-specifier will represent the
opposite physical level than the signal at the device's pin.
When the device's signal polarity is configurable, the binding for the
device must either:
a) Define a single static polarity for the signal, with the expectation that
any software using that binding would statically program the device to use
that signal polarity.
The static choice of polarity may be either:
a1) (Preferred) Dictated by a binding-specific DT property.
or:
a2) Defined statically by the DT binding itself.
In particular, the polarity cannot be derived from the gpio-specifier, since
that would prevent the DT from separately representing the two orthogonal
concepts of configurable signal polarity in the device, and possible board-
level signal inversion.
or:
b) Pick a single option for device signal polarity, and document this choice
in the binding. The gpio-specifier should represent the polarity of the signal
(at the GPIO controller) assuming that the device is configured for this
particular signal polarity choice. If software chooses to program the device
to generate or receive a signal of the opposite polarity, software will be
responsible for correctly interpreting (inverting) the GPIO signal at the GPIO
controller.
2) gpio-controller nodes
------------------------
Every GPIO controller node must contain both an empty "gpio-controller"
property, and a #gpio-cells integer property, which indicates the number of
cells in a gpio-specifier.
Some system-on-chips (SoCs) use the concept of GPIO banks. A GPIO bank is an
instance of a hardware IP core on a silicon die, usually exposed to the
programmer as a coherent range of I/O addresses. Usually each such bank is
exposed in the device tree as an individual gpio-controller node, reflecting
the fact that the hardware was synthesized by reusing the same IP block a
few times over.
Optionally, a GPIO controller may have a "ngpios" property. This property
indicates the number of in-use slots of available slots for GPIOs. The
typical example is something like this: the hardware register is 32 bits
wide, but only 18 of the bits have a physical counterpart. The driver is
generally written so that all 32 bits can be used, but the IP block is reused
in a lot of designs, some using all 32 bits, some using 18 and some using
12. In this case, setting "ngpios = <18>;" informs the driver that only the
first 18 GPIOs, at local offset 0 .. 17, are in use.
If these GPIOs do not happen to be the first N GPIOs at offset 0...N-1, an
additional set of tuples is needed to specify which GPIOs are unusable, with
the gpio-reserved-ranges binding. This property indicates the start and size
of the GPIOs that can't be used.
Optionally, a GPIO controller may have a "gpio-line-names" property. This is
an array of strings defining the names of the GPIO lines going out of the
GPIO controller. This name should be the most meaningful producer name
for the system, such as a rail name indicating the usage. Package names
such as pin name are discouraged: such lines have opaque names (since they
are by definition generic purpose) and such names are usually not very
helpful. For example "MMC-CD", "Red LED Vdd" and "ethernet reset" are
reasonable line names as they describe what the line is used for. "GPIO0"
is not a good name to give to a GPIO line. Placeholders are discouraged:
rather use the "" (blank string) if the use of the GPIO line is undefined
in your design. The names are assigned starting from line offset 0 from
left to right from the passed array. An incomplete array (where the number
of passed named are less than ngpios) will still be used up until the last
provided valid line index.
Example:
gpio-controller@00000000 {
compatible = "foo";
reg = <0x00000000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <18>;
gpio-reserved-ranges = <0 4>, <12 2>;
gpio-line-names = "MMC-CD", "MMC-WP", "VDD eth", "RST eth", "LED R",
"LED G", "LED B", "Col A", "Col B", "Col C", "Col D",
"Row A", "Row B", "Row C", "Row D", "NMI button",
"poweroff", "reset";
}
The GPIO chip may contain GPIO hog definitions. GPIO hogging is a mechanism
providing automatic GPIO request and configuration as part of the
gpio-controller's driver probe function.
Each GPIO hog definition is represented as a child node of the GPIO controller.
Required properties:
- gpio-hog: A property specifying that this child node represents a GPIO hog.
- gpios: Store the GPIO information (id, flags, ...) for each GPIO to
affect. Shall contain an integer multiple of the number of cells
specified in its parent node (GPIO controller node).
Only one of the following properties scanned in the order shown below.
This means that when multiple properties are present they will be searched
in the order presented below and the first match is taken as the intended
configuration.
- input: A property specifying to set the GPIO direction as input.
- output-low A property specifying to set the GPIO direction as output with
the value low.
- output-high A property specifying to set the GPIO direction as output with
the value high.
Optional properties:
- line-name: The GPIO label name. If not present the node name is used.
Example of two SOC GPIO banks defined as gpio-controller nodes:
qe_pio_a: gpio-controller@1400 {
compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank";
reg = <0x1400 0x18>;
gpio-controller;
#gpio-cells = <2>;
line_b-hog {
gpio-hog;
gpios = <6 0>;
output-low;
line-name = "foo-bar-gpio";
};
};
qe_pio_e: gpio-controller@1460 {
compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
reg = <0x1460 0x18>;
gpio-controller;
#gpio-cells = <2>;
};
2.1) gpio- and pin-controller interaction
-----------------------------------------
Some or all of the GPIOs provided by a GPIO controller may be routed to pins
on the package via a pin controller. This allows muxing those pins between
GPIO and other functions. It is a fairly common practice among silicon
engineers.
2.2) Ordinary (numerical) GPIO ranges
-------------------------------------
It is useful to represent which GPIOs correspond to which pins on which pin
controllers. The gpio-ranges property described below represents this with
a discrete set of ranges mapping pins from the pin controller local number space
to pins in the GPIO controller local number space.
The format is: <[pin controller phandle], [GPIO controller offset],
[pin controller offset], [number of pins]>;
The GPIO controller offset pertains to the GPIO controller node containing the
range definition.
The pin controller node referenced by the phandle must conform to the bindings
described in pinctrl/pinctrl-bindings.txt.
Each offset runs from 0 to N. It is perfectly fine to pile any number of
ranges with just one pin-to-GPIO line mapping if the ranges are concocted, but
in practice these ranges are often lumped in discrete sets.
Example:
gpio-ranges = <&foo 0 20 10>, <&bar 10 50 20>;
This means:
- pins 20..29 on pin controller "foo" is mapped to GPIO line 0..9 and
- pins 50..69 on pin controller "bar" is mapped to GPIO line 10..29
Verbose example:
qe_pio_e: gpio-controller@1460 {
#gpio-cells = <2>;
compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
reg = <0x1460 0x18>;
gpio-controller;
gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>;
};
Here, a single GPIO controller has GPIOs 0..9 routed to pin controller
pinctrl1's pins 20..29, and GPIOs 10..29 routed to pin controller pinctrl2's
pins 50..69.
2.3) GPIO ranges from named pin groups
--------------------------------------
It is also possible to use pin groups for gpio ranges when pin groups are the
easiest and most convenient mapping.
Both both <pinctrl-base> and <count> must set to 0 when using named pin groups
names.
The property gpio-ranges-group-names must contain exactly one string for each
range.
Elements of gpio-ranges-group-names must contain the name of a pin group
defined in the respective pin controller. The number of pins/GPIO lines in the
range is the number of pins in that pin group. The number of pins of that
group is defined int the implementation and not in the device tree.
If numerical and named pin groups are mixed, the string corresponding to a
numerical pin range in gpio-ranges-group-names must be empty.
Example:
gpio_pio_i: gpio-controller@14b0 {
#gpio-cells = <2>;
compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
reg = <0x1480 0x18>;
gpio-controller;
gpio-ranges = <&pinctrl1 0 20 10>,
<&pinctrl2 10 0 0>,
<&pinctrl1 15 0 10>,
<&pinctrl2 25 0 0>;
gpio-ranges-group-names = "",
"foo",
"",
"bar";
};
Here, three GPIO ranges are defined referring to two pin controllers.
pinctrl1 GPIO ranges are defined using pin numbers whereas the GPIO ranges
in pinctrl2 are defined using the pin groups named "foo" and "bar".
Previous versions of this binding required all pin controller nodes that
were referenced by any gpio-ranges property to contain a property named
#gpio-range-cells with value <3>. This requirement is now deprecated.
However, that property may still exist in older device trees for
compatibility reasons, and would still be required even in new device
trees that need to be compatible with older software.

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* Atmel GPIO controller (PIO)
Required properties:
- compatible: "atmel,<chip>-gpio", where <chip> is at91rm9200 or at91sam9x5.
- reg: Should contain GPIO controller registers location and length
- interrupts: Should be the port interrupt shared by all the pins.
- #gpio-cells: Should be two. The first cell is the pin number and
the second cell is used to specify optional parameters to declare if the GPIO
is active high or low. See gpio.txt.
- gpio-controller: Marks the device node as a GPIO controller.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be two. The first cell is the pin number and the
second cell is used to specify irq type flags, see the two cell description
in interrupt-controller/interrupts.txt for details.
optional properties:
- #gpio-lines: Number of gpio if absent 32.
Example:
pioA: gpio@fffff200 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff200 0x100>;
interrupts = <2 4>;
#gpio-cells = <2>;
gpio-controller;
#gpio-lines = <19>;
interrupt-controller;
#interrupt-cells = <2>;
};

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NXP LPC32xx SoC GPIO controller
Required properties:
- compatible: must be "nxp,lpc3220-gpio"
- reg: Physical base address and length of the controller's registers.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Should be 3:
1) bank:
0: GPIO P0
1: GPIO P1
2: GPIO P2
3: GPIO P3
4: GPI P3
5: GPO P3
2) pin number
3) optional parameters:
- bit 0 specifies polarity (0 for normal, 1 for inverted)
- reg: Index of the GPIO group
Example:
gpio: gpio@40028000 {
compatible = "nxp,lpc3220-gpio";
reg = <0x40028000 0x1000>;
gpio-controller;
#gpio-cells = <3>; /* bank, pin, flags */
};
leds {
compatible = "gpio-leds";
led0 {
gpios = <&gpio 5 1 1>; /* GPO_P3 1, active low */
linux,default-trigger = "heartbeat";
default-state = "off";
};
led1 {
gpios = <&gpio 5 14 1>; /* GPO_P3 14, active low */
linux,default-trigger = "timer";
default-state = "off";
};
};

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* Oxford Semiconductor OXNAS SoC GPIO Controller
Please refer to gpio.txt for generic information regarding GPIO bindings.
Required properties:
- compatible: "oxsemi,ox810se-gpio" or "oxsemi,ox820-gpio"
- reg: Base address and length for the device.
- interrupts: The port interrupt shared by all pins.
- gpio-controller: Marks the port as GPIO controller.
- #gpio-cells: Two. The first cell is the pin number and
the second cell is used to specify the gpio polarity as defined in
defined in <dt-bindings/gpio/gpio.h>:
0 = GPIO_ACTIVE_HIGH
1 = GPIO_ACTIVE_LOW
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Two. The first cell is the GPIO number and second cell
is used to specify the trigger type as defined in
<dt-bindings/interrupt-controller/irq.h>:
IRQ_TYPE_EDGE_RISING
IRQ_TYPE_EDGE_FALLING
IRQ_TYPE_EDGE_BOTH
- gpio-ranges: Interaction with the PINCTRL subsystem, it also specifies the
gpio base and count, should be in the format of numeric-gpio-range as
specified in the gpio.txt file.
Example:
gpio0: gpio@0 {
compatible = "oxsemi,ox810se-gpio";
reg = <0x000000 0x100000>;
interrupts = <21>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&pinctrl 0 0 32>;
};
keys {
...
button-esc {
label = "ESC";
linux,code = <1>;
gpios = <&gpio0 12 0>;
};
};

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* IBM/AMCC/APM GPIO Controller for PowerPC 4XX series and compatible SoCs
All GPIOs are pin-shared with other functions. DCRs control whether a
particular pin that has GPIO capabilities acts as a GPIO or is used for
another purpose. GPIO outputs are separately programmable to emulate
an open-drain driver.
Required properties:
- compatible: must be "ibm,ppc4xx-gpio"
- reg: address and length of the register set for the device
- #gpio-cells: must be set to 2. The first cell is the pin number
and the second cell is used to specify the gpio polarity:
0 = active high
1 = active low
- gpio-controller: marks the device node as a gpio controller.
Example:
GPIO0: gpio@ef600b00 {
compatible = "ibm,ppc4xx-gpio";
reg = <0xef600b00 0x00000048>;
#gpio-cells = <2>;
gpio-controller;
};

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/idt,32434-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: IDT 79RC32434 GPIO controller
maintainers:
- Thomas Bogendoerfer <tsbogend@alpha.franken.de>
properties:
compatible:
const: idt,32434-gpio
reg:
maxItems: 2
reg-names:
items:
- const: gpio
- const: pic
gpio-controller: true
"#gpio-cells":
const: 2
ngpios:
minimum: 1
maximum: 32
interrupt-controller: true
"#interrupt-cells":
const: 2
interrupts:
maxItems: 1
required:
- compatible
- reg
- reg-names
- gpio-controller
- "#gpio-cells"
additionalProperties: false
examples:
- |
gpio0: gpio@50004 {
compatible = "idt,32434-gpio";
reg = <0x50004 0x10>, <0x38030 0x0c>;
reg-names = "gpio", "pic";
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&cpuintc>;
interrupts = <6>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <14>;
};

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Intel IXP4xx XScale Networking Processors GPIO
This GPIO controller is found in the Intel IXP4xx processors.
It supports 16 GPIO lines.
The interrupt portions of the GPIO controller is hierarchical:
the synchronous edge detector is part of the GPIO block, but the
actual enabling/disabling of the interrupt line is done in the
main IXP4xx interrupt controller which has a 1:1 mapping for
the first 12 GPIO lines to 12 system interrupts.
The remaining 4 GPIO lines can not be used for receiving
interrupts.
The interrupt parent of this GPIO controller must be the
IXP4xx interrupt controller.
Required properties:
- compatible : Should be
"intel,ixp4xx-gpio"
- reg : Should contain registers location and length
- gpio-controller : marks this as a GPIO controller
- #gpio-cells : Should be 2, see gpio/gpio.txt
- interrupt-controller : marks this as an interrupt controller
- #interrupt-cells : a standard two-cell interrupt, see
interrupt-controller/interrupts.txt
Example:
gpio0: gpio@c8004000 {
compatible = "intel,ixp4xx-gpio";
reg = <0xc8004000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/kontron,sl28cpld-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: GPIO driver for the sl28cpld board management controller
maintainers:
- Michael Walle <michael@walle.cc>
description: |
This module is part of the sl28cpld multi-function device. For more
details see ../mfd/kontron,sl28cpld.yaml.
There are three flavors of the GPIO controller, one full featured
input/output with interrupt support (kontron,sl28cpld-gpio), one
output-only (kontron,sl28-gpo) and one input-only (kontron,sl28-gpi).
Each controller supports 8 GPIO lines.
properties:
compatible:
enum:
- kontron,sl28cpld-gpio
- kontron,sl28cpld-gpi
- kontron,sl28cpld-gpo
reg:
maxItems: 1
interrupts:
maxItems: 1
"#interrupt-cells":
const: 2
interrupt-controller: true
"#gpio-cells":
const: 2
gpio-controller: true
gpio-line-names:
minItems: 1
maxItems: 8
required:
- compatible
- "#gpio-cells"
- gpio-controller
additionalProperties: false

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/mediatek,mt7621-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek MT7621 SoC GPIO controller
maintainers:
- Sergio Paracuellos <sergio.paracuellos@gmail.com>
description: |
The IP core used inside these SoCs has 3 banks of 32 GPIOs each.
The registers of all the banks are interwoven inside one single IO range.
We load one GPIO controller instance per bank. Also the GPIO controller can receive
interrupts on any of the GPIOs, either edge or level. It then interrupts the CPU
using GIC INT12.
properties:
$nodename:
pattern: "^gpio@[0-9a-f]+$"
compatible:
const: mediatek,mt7621-gpio
reg:
maxItems: 1
"#gpio-cells":
const: 2
gpio-controller: true
gpio-ranges: true
interrupt-controller: true
"#interrupt-cells":
const: 2
interrupts:
maxItems: 1
required:
- compatible
- reg
- "#gpio-cells"
- gpio-controller
- gpio-ranges
- interrupt-controller
- "#interrupt-cells"
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/mips-gic.h>
gpio@600 {
compatible = "mediatek,mt7621-gpio";
reg = <0x600 0x100>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 95>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
};
...

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/microchip,mpfs-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip MPFS GPIO Controller
maintainers:
- Conor Dooley <conor.dooley@microchip.com>
properties:
compatible:
items:
- enum:
- microchip,mpfs-gpio
reg:
maxItems: 1
interrupts:
description:
Interrupt mapping, one per GPIO. Maximum 32 GPIOs.
minItems: 1
maxItems: 32
interrupt-controller: true
clocks:
maxItems: 1
"#gpio-cells":
const: 2
"#interrupt-cells":
const: 1
ngpios:
description:
The number of GPIOs available.
minimum: 1
maximum: 32
default: 32
gpio-controller: true
patternProperties:
"^.+-hog(-[0-9]+)?$":
type: object
additionalProperties: false
properties:
gpio-hog: true
gpios: true
input: true
output-high: true
output-low: true
line-name: true
required:
- gpio-hog
- gpios
required:
- compatible
- reg
- interrupts
- "#interrupt-cells"
- interrupt-controller
- "#gpio-cells"
- gpio-controller
- clocks
additionalProperties: false
examples:
- |
gpio@20122000 {
compatible = "microchip,mpfs-gpio";
reg = <0x20122000 0x1000>;
clocks = <&clkcfg 25>;
interrupt-parent = <&plic>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
interrupts = <53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>;
};
...

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* Microchip PIC32 GPIO devices (PIO).
Required properties:
- compatible: "microchip,pic32mzda-gpio"
- reg: Base address and length for the device.
- interrupts: The port interrupt shared by all pins.
- gpio-controller: Marks the port as GPIO controller.
- #gpio-cells: Two. The first cell is the pin number and
the second cell is used to specify the gpio polarity as defined in
defined in <dt-bindings/gpio/gpio.h>:
0 = GPIO_ACTIVE_HIGH
1 = GPIO_ACTIVE_LOW
2 = GPIO_OPEN_DRAIN
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Two. The first cell is the GPIO number and second cell
is used to specify the trigger type as defined in
<dt-bindings/interrupt-controller/irq.h>:
IRQ_TYPE_EDGE_RISING
IRQ_TYPE_EDGE_FALLING
IRQ_TYPE_EDGE_BOTH
- clocks: Clock specifier (see clock bindings for details).
- microchip,gpio-bank: Specifies which bank a controller owns.
- gpio-ranges: Interaction with the PINCTRL subsystem.
Example:
/* PORTA */
gpio0: gpio0@1f860000 {
compatible = "microchip,pic32mzda-gpio";
reg = <0x1f860000 0x100>;
interrupts = <118 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&rootclk PB4CLK>;
microchip,gpio-bank = <0>;
gpio-ranges = <&pic32_pinctrl 0 0 16>;
};
keys {
...
button@sw1 {
label = "ESC";
linux,code = <1>;
gpios = <&gpio0 12 0>;
};
};

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# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/mrvl-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell PXA GPIO controller
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
- Bartosz Golaszewski <bgolaszewski@baylibre.com>
- Rob Herring <robh+dt@kernel.org>
allOf:
- if:
properties:
compatible:
contains:
enum:
- intel,pxa25x-gpio
- intel,pxa26x-gpio
- intel,pxa27x-gpio
- intel,pxa3xx-gpio
then:
properties:
interrupts:
minItems: 3
maxItems: 3
interrupt-names:
items:
- const: gpio0
- const: gpio1
- const: gpio_mux
- if:
properties:
compatible:
contains:
enum:
- marvell,mmp-gpio
- marvell,mmp2-gpio
then:
properties:
interrupts:
maxItems: 1
interrupt-names:
items:
- const: gpio_mux
properties:
$nodename:
pattern: '^gpio@[0-9a-f]+$'
compatible:
enum:
- intel,pxa25x-gpio
- intel,pxa26x-gpio
- intel,pxa27x-gpio
- intel,pxa3xx-gpio
- marvell,mmp-gpio
- marvell,mmp2-gpio
- marvell,pxa93x-gpio
reg:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
ranges: true
'#address-cells':
const: 1
'#size-cells':
const: 1
gpio-controller: true
'#gpio-cells':
const: 2
gpio-ranges: true
interrupts: true
interrupt-names: true
interrupt-controller: true
'#interrupt-cells':
const: 2
patternProperties:
'^gpio@[0-9a-f]*$':
type: object
properties:
reg:
maxItems: 1
required:
- reg
additionalProperties: false
required:
- compatible
- '#address-cells'
- '#size-cells'
- reg
- gpio-controller
- '#gpio-cells'
- interrupts
- interrupt-names
- interrupt-controller
- '#interrupt-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/pxa-clock.h>
gpio@40e00000 {
compatible = "intel,pxa3xx-gpio";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x40e00000 0x10000>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <8>, <9>, <10>;
interrupt-names = "gpio0", "gpio1", "gpio_mux";
clocks = <&clks CLK_GPIO>;
interrupt-controller;
#interrupt-cells = <2>;
};
- |
#include <dt-bindings/clock/marvell,pxa910.h>
gpio@d4019000 {
compatible = "marvell,mmp-gpio";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xd4019000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <49>;
interrupt-names = "gpio_mux";
clocks = <&soc_clocks PXA910_CLK_GPIO>;
resets = <&soc_clocks PXA910_CLK_GPIO>;
interrupt-controller;
#interrupt-cells = <2>;
ranges;
gpio@d4019000 {
reg = <0xd4019000 0x4>;
};
gpio@d4019004 {
reg = <0xd4019004 0x4>;
};
gpio@d4019008 {
reg = <0xd4019008 0x4>;
};
gpio@d4019100 {
reg = <0xd4019100 0x4>;
};
};
...

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/mstar,msc313-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MStar/SigmaStar GPIO controller
maintainers:
- Daniel Palmer <daniel@thingy.jp>
properties:
$nodename:
pattern: "^gpio@[0-9a-f]+$"
compatible:
enum:
- mstar,msc313-gpio
- sstar,ssd20xd-gpio
reg:
maxItems: 1
gpio-controller: true
"#gpio-cells":
const: 2
gpio-ranges: true
interrupt-controller: true
"#interrupt-cells":
const: 2
required:
- compatible
- reg
- gpio-controller
- "#gpio-cells"
- interrupt-controller
- "#interrupt-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/msc313-gpio.h>
gpio: gpio@207800 {
compatible = "mstar,msc313-gpio";
#gpio-cells = <2>;
reg = <0x207800 0x200>;
gpio-controller;
gpio-ranges = <&pinctrl 0 36 22>,
<&pinctrl 22 63 4>,
<&pinctrl 26 68 6>;
#interrupt-cells = <2>;
interrupt-controller;
interrupt-parent = <&intc_fiq>;
};

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Binding for the GPIO extension bus found on some LaCie/Seagate boards
(Example: 2Big/5Big Network v2, 2Big NAS).
Required properties:
- compatible: "lacie,netxbig-gpio-ext".
- addr-gpios: GPIOs representing the address register (LSB -> MSB).
- data-gpios: GPIOs representing the data register (LSB -> MSB).
- enable-gpio: latches the new configuration (address, data) on raising edge.
Example:
netxbig_gpio_ext: netxbig-gpio-ext {
compatible = "lacie,netxbig-gpio-ext";
addr-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH
&gpio1 16 GPIO_ACTIVE_HIGH
&gpio1 17 GPIO_ACTIVE_HIGH>;
data-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH
&gpio1 13 GPIO_ACTIVE_HIGH
&gpio1 14 GPIO_ACTIVE_HIGH>;
enable-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>;
};

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Bindings for the National Instruments 169445 GPIO NAND controller
The 169445 GPIO NAND controller has two memory mapped GPIO registers, one
for input (the ready signal) and one for output (control signals). It is
intended to be used with the GPIO NAND driver.
Required properties:
- compatible: should be "ni,169445-nand-gpio"
- reg-names: must contain
"dat" - data register
- reg: address + size pairs describing the GPIO register sets;
order must correspond with the order of entries in reg-names
- #gpio-cells: must be set to 2. The first cell is the pin number and
the second cell is used to specify the gpio polarity:
0 = active high
1 = active low
- gpio-controller: Marks the device node as a gpio controller.
Optional properties:
- no-output: disables driving output on the pins
Examples:
gpio1: nand-gpio-out@1f300010 {
compatible = "ni,169445-nand-gpio";
reg = <0x1f300010 0x4>;
reg-names = "dat";
gpio-controller;
#gpio-cells = <2>;
};
gpio2: nand-gpio-in@1f300014 {
compatible = "ni,169445-nand-gpio";
reg = <0x1f300014 0x4>;
reg-names = "dat";
gpio-controller;
#gpio-cells = <2>;
no-output;
};

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Nintendo Wii (Hollywood) GPIO controller
Required properties:
- compatible: "nintendo,hollywood-gpio"
- reg: Physical base address and length of the controller's registers.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Should be <2>. The first cell is the pin number and the
second cell is used to specify optional parameters:
- bit 0 specifies polarity (0 for normal, 1 for inverted).
Optional properties:
- ngpios: see Documentation/devicetree/bindings/gpio/gpio.txt
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be two.
- interrupts: Interrupt specifier for the controller's Broadway (PowerPC)
interrupt.
Example:
GPIO: gpio@d8000c0 {
#gpio-cells = <2>;
compatible = "nintendo,hollywood-gpio";
reg = <0x0d8000c0 0x40>;
gpio-controller;
ngpios = <24>;
}

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra GPIO Controller (Tegra186 and later)
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
description: |
Tegra186 contains two GPIO controllers; a main controller and an "AON"
controller. This binding document applies to both controllers. The register
layouts for the controllers share many similarities, but also some
significant differences. Hence, this document describes closely related but
different bindings and compatible values.
The Tegra186 GPIO controller allows software to set the IO direction of,
and read/write the value of, numerous GPIO signals. Routing of GPIO signals
to package balls is under the control of a separate pin controller hardware
block. Two major sets of registers exist:
a) Security registers, which allow configuration of allowed access to the
GPIO register set. These registers exist in a single contiguous block
of physical address space. The size of this block, and the security
features available, varies between the different GPIO controllers.
Access to this set of registers is not necessary in all circumstances.
Code that wishes to configure access to the GPIO registers needs access
to these registers to do so. Code which simply wishes to read or write
GPIO data does not need access to these registers.
b) GPIO registers, which allow manipulation of the GPIO signals. In some
GPIO controllers, these registers are exposed via multiple "physical
aliases" in address space, each of which access the same underlying
state. See the hardware documentation for rationale. Any particular
GPIO client is expected to access just one of these physical aliases.
Tegra HW documentation describes a unified naming convention for all GPIOs
implemented by the SoC. Each GPIO is assigned to a port, and a port may
control a number of GPIOs. Thus, each GPIO is named according to an
alphabetical port name and an integer GPIO name within the port. For
example, GPIO_PA0, GPIO_PN6, or GPIO_PCC3.
The number of ports implemented by each GPIO controller varies. The number
of implemented GPIOs within each port varies. GPIO registers within a
controller are grouped and laid out according to the port they affect.
The mapping from port name to the GPIO controller that implements that
port, and the mapping from port name to register offset within a
controller, are both extremely non-linear. The header file
<dt-bindings/gpio/tegra186-gpio.h> describes the port-level mapping. In
that file, the naming convention for ports matches the HW documentation.
The values chosen for the names are alphabetically sorted within a
particular controller. Drivers need to map between the DT GPIO IDs and HW
register offsets using a lookup table.
Each GPIO controller can generate a number of interrupt signals. Each
signal represents the aggregate status for all GPIOs within a set of
ports. Thus, the number of interrupt signals generated by a controller
varies as a rough function of the number of ports it implements. Note
that the HW documentation refers to both the overall controller HW
module and the sets-of-ports as "controllers".
Each GPIO controller in fact generates multiple interrupts signals for
each set of ports. Each GPIO may be configured to feed into a specific
one of the interrupt signals generated by a set-of-ports. The intent is
for each generated signal to be routed to a different CPU, thus allowing
different CPUs to each handle subsets of the interrupts within a port.
The status of each of these per-port-set signals is reported via a
separate register. Thus, a driver needs to know which status register to
observe. This binding currently defines no configuration mechanism for
this. By default, drivers should use register
GPIO_${port}_INTERRUPT_STATUS_G1_0. Future revisions to the binding could
define a property to configure this.
properties:
compatible:
enum:
- nvidia,tegra186-gpio
- nvidia,tegra186-gpio-aon
- nvidia,tegra194-gpio
- nvidia,tegra194-gpio-aon
- nvidia,tegra234-gpio
- nvidia,tegra234-gpio-aon
reg-names:
items:
- const: security
- const: gpio
minItems: 1
reg:
items:
- description: Security configuration registers.
- description: |
GPIO control registers. This may cover either:
a) The single physical alias that this OS should use.
b) All physical aliases that exist in the controller. This is
appropriate when the OS is responsible for managing assignment
of the physical aliases.
minItems: 1
interrupts:
description: The interrupt outputs from the HW block, one per set of
ports, in the order the HW manual describes them. The number of entries
required varies depending on compatible value.
gpio-controller: true
"#gpio-cells":
description: |
Indicates how many cells are used in a consumer's GPIO specifier. In the
specifier:
- The first cell is the pin number.
See <dt-bindings/gpio/tegra186-gpio.h>.
- The second cell contains flags:
- Bit 0 specifies polarity
- 0: Active-high (normal).
- 1: Active-low (inverted).
const: 2
interrupt-controller: true
"#interrupt-cells":
description: |
Indicates how many cells are used in a consumer's interrupt specifier.
In the specifier:
- The first cell is the GPIO number.
See <dt-bindings/gpio/tegra186-gpio.h>.
- The second cell is contains flags:
- Bits [3:0] indicate trigger type and level:
- 1: Low-to-high edge triggered.
- 2: High-to-low edge triggered.
- 4: Active high level-sensitive.
- 8: Active low level-sensitive.
Valid combinations are 1, 2, 3, 4, 8.
const: 2
allOf:
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra186-gpio
- nvidia,tegra194-gpio
- nvidia,tegra234-gpio
then:
properties:
interrupts:
minItems: 6
maxItems: 48
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra186-gpio-aon
- nvidia,tegra194-gpio-aon
- nvidia,tegra234-gpio-aon
then:
properties:
interrupts:
minItems: 1
maxItems: 4
required:
- compatible
- reg
- reg-names
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
gpio@2200000 {
compatible = "nvidia,tegra186-gpio";
reg-names = "security", "gpio";
reg = <0x2200000 0x10000>,
<0x2210000 0x10000>;
interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>,
<0 50 IRQ_TYPE_LEVEL_HIGH>,
<0 53 IRQ_TYPE_LEVEL_HIGH>,
<0 56 IRQ_TYPE_LEVEL_HIGH>,
<0 59 IRQ_TYPE_LEVEL_HIGH>,
<0 180 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio@c2f0000 {
compatible = "nvidia,tegra186-gpio-aon";
reg-names = "security", "gpio";
reg = <0xc2f0000 0x1000>,
<0xc2f1000 0x1000>;
interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/nvidia,tegra20-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra GPIO Controller (Tegra20 - Tegra210)
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
compatible:
oneOf:
- enum:
- nvidia,tegra20-gpio
- nvidia,tegra30-gpio
- items:
- enum:
- nvidia,tegra114-gpio
- nvidia,tegra124-gpio
- nvidia,tegra210-gpio
- const: nvidia,tegra30-gpio
reg:
maxItems: 1
interrupts:
description: The interrupt outputs from the controller. For Tegra20,
there should be 7 interrupts specified, and for Tegra30, there should
be 8 interrupts specified.
"#gpio-cells":
description: The first cell is the pin number and the second cell is used
to specify the GPIO polarity (0 = active high, 1 = active low).
const: 2
gpio-controller: true
gpio-ranges:
maxItems: 1
"#interrupt-cells":
description: |
Should be 2. The first cell is the GPIO number. The second cell is
used to specify flags:
bits[3:0] trigger type and level flags:
1 = low-to-high edge triggered.
2 = high-to-low edge triggered.
4 = active high level-sensitive.
8 = active low level-sensitive.
Valid combinations are 1, 2, 3, 4, 8.
const: 2
interrupt-controller: true
allOf:
- if:
properties:
compatible:
contains:
const: nvidia,tegra30-gpio
then:
properties:
interrupts:
minItems: 8
maxItems: 8
else:
properties:
interrupts:
minItems: 7
maxItems: 7
required:
- compatible
- reg
- interrupts
- "#gpio-cells"
- gpio-controller
- "#interrupt-cells"
- interrupt-controller
additionalProperties:
type: object
required:
- gpio-hog
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
gpio: gpio@6000d000 {
compatible = "nvidia,tegra20-gpio";
reg = <0x6000d000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
};

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NXP LPC18xx/43xx GPIO controller Device Tree Bindings
-----------------------------------------------------
Required properties:
- compatible : Should be "nxp,lpc1850-gpio"
- reg : List of addresses and lengths of the GPIO controller
register sets
- reg-names : Should be "gpio", "gpio-pin-ic", "gpio-group0-ic" and
"gpio-gpoup1-ic"
- clocks : Phandle and clock specifier pair for GPIO controller
- resets : Phandle and reset specifier pair for GPIO controller
- gpio-controller : Marks the device node as a GPIO controller
- #gpio-cells : Should be two:
- The first cell is the GPIO line number
- The second cell is used to specify polarity
- interrupt-controller : Marks the device node as an interrupt controller
- #interrupt-cells : Should be two:
- The first cell is an interrupt number within
0..9 range, for GPIO pin interrupts it is equal
to 'nxp,gpio-pin-interrupt' property value of
GPIO pin configuration, 8 is for GPIO GROUP0
interrupt, 9 is for GPIO GROUP1 interrupt
- The second cell is used to specify interrupt type
Optional properties:
- gpio-ranges : Mapping between GPIO and pinctrl
Example:
#define LPC_GPIO(port, pin) (port * 32 + pin)
#define LPC_PIN(port, pin) (0x##port * 32 + pin)
gpio: gpio@400f4000 {
compatible = "nxp,lpc1850-gpio";
reg = <0x400f4000 0x4000>, <0x40087000 0x1000>,
<0x40088000 0x1000>, <0x40089000 0x1000>;
reg-names = "gpio", "gpio-pin-ic",
"gpio-group0-ic", "gpio-gpoup1-ic";
clocks = <&ccu1 CLK_CPU_GPIO>;
resets = <&rgu 28>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>,
...
<&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>;
};
gpio_joystick {
compatible = "gpio-keys";
...
button0 {
...
interrupt-parent = <&gpio>;
interrupts = <1 IRQ_TYPE_EDGE_BOTH>;
gpios = <&gpio LPC_GPIO(4,8) GPIO_ACTIVE_LOW>;
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/nxp,pcf8575.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: PCF857x-compatible I/O expanders
maintainers:
- Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
description:
The PCF857x-compatible chips have "quasi-bidirectional" I/O lines that can be
driven high by a pull-up current source or driven low to ground. This
combines the direction and output level into a single bit per line, which
can't be read back. We can't actually know at initialization time whether a
line is configured (a) as output and driving the signal low/high, or (b) as
input and reporting a low/high value, without knowing the last value written
since the chip came out of reset (if any). The only reliable solution for
setting up line direction is thus to do it explicitly.
properties:
compatible:
enum:
- maxim,max7328
- maxim,max7329
- nxp,pca8574
- nxp,pca8575
- nxp,pca9670
- nxp,pca9671
- nxp,pca9672
- nxp,pca9673
- nxp,pca9674
- nxp,pca9675
- nxp,pcf8574
- nxp,pcf8574a
- nxp,pcf8575
reg:
maxItems: 1
gpio-controller: true
'#gpio-cells':
const: 2
description:
The first cell is the GPIO number and the second cell specifies GPIO
flags, as defined in <dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH
and GPIO_ACTIVE_LOW flags are supported.
lines-initial-states:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Bitmask that specifies the initial state of each line.
When a bit is set to zero, the corresponding line will be initialized to
the input (pulled-up) state.
When the bit is set to one, the line will be initialized to the
low-level output state.
If the property is not specified all lines will be initialized to the
input state.
interrupts:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
wakeup-source: true
patternProperties:
"^(.+-hog(-[0-9]+)?)$":
type: object
required:
- gpio-hog
required:
- compatible
- reg
- gpio-controller
- '#gpio-cells'
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
pcf8575: gpio@20 {
compatible = "nxp,pcf8575";
reg = <0x20>;
interrupt-parent = <&irqpin2>;
interrupts = <3 0>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/pl061-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM PL061 GPIO controller
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
- Rob Herring <robh@kernel.org>
# We need a select here so we don't match all nodes with 'arm,primecell'
select:
properties:
compatible:
contains:
const: arm,pl061
required:
- compatible
properties:
$nodename:
pattern: "^gpio@[0-9a-f]+$"
compatible:
items:
- const: arm,pl061
- const: arm,primecell
reg:
maxItems: 1
interrupts:
oneOf:
- maxItems: 1
- maxItems: 8
interrupt-controller: true
"#interrupt-cells":
const: 2
clocks:
maxItems: 1
clock-names: true
"#gpio-cells":
const: 2
gpio-controller: true
gpio-line-names: true
gpio-ranges:
minItems: 1
maxItems: 8
required:
- compatible
- reg
- interrupts
- interrupt-controller
- "#interrupt-cells"
- clocks
- "#gpio-cells"
- gpio-controller
additionalProperties: false
...

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/qcom,wcd934x-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: WCD9340/WCD9341 GPIO controller
maintainers:
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
description: |
Qualcomm Technologies Inc WCD9340/WCD9341 Audio Codec has integrated
gpio controller to control 5 gpios on the chip.
properties:
compatible:
enum:
- qcom,wcd9340-gpio
- qcom,wcd9341-gpio
reg:
maxItems: 1
gpio-controller: true
'#gpio-cells':
const: 2
required:
- compatible
- reg
- gpio-controller
- "#gpio-cells"
additionalProperties: false
examples:
- |
wcdgpio: gpio@42 {
compatible = "qcom,wcd9340-gpio";
reg = <0x042 0x2>;
gpio-controller;
#gpio-cells = <2>;
};
...

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Raspberry Pi GPIO expander
The Raspberry Pi 3 GPIO expander is controlled by the VC4 firmware. The
firmware exposes a mailbox interface that allows the ARM core to control the
GPIO lines on the expander.
The Raspberry Pi GPIO expander node must be a child node of the Raspberry Pi
firmware node.
Required properties:
- compatible : Should be "raspberrypi,firmware-gpio"
- gpio-controller : Marks the device node as a gpio controller
- #gpio-cells : Should be two. The first cell is the pin number, and
the second cell is used to specify the gpio polarity:
0 = active high
1 = active low
Example:
firmware: firmware-rpi {
compatible = "raspberrypi,bcm2835-firmware";
mboxes = <&mailbox>;
expgpio: gpio {
compatible = "raspberrypi,firmware-gpio";
gpio-controller;
#gpio-cells = <2>;
};
};

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/realtek,otto-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Realtek Otto GPIO controller
maintainers:
- Sander Vanheule <sander@svanheule.net>
- Bert Vermeulen <bert@biot.com>
description: |
Realtek's GPIO controller on their MIPS switch SoCs (Otto platform) consists
of two banks of 32 GPIOs. These GPIOs can generate edge-triggered interrupts.
Each bank's interrupts are cascased into one interrupt line on the parent
interrupt controller, if provided.
This binding allows defining a single bank in the devicetree. The interrupt
controller is not supported on the fallback compatible name, which only
allows for GPIO port use.
properties:
$nodename:
pattern: "^gpio@[0-9a-f]+$"
compatible:
items:
- enum:
- realtek,rtl8380-gpio
- realtek,rtl8390-gpio
- realtek,rtl9300-gpio
- realtek,rtl9310-gpio
- const: realtek,otto-gpio
reg: true
"#gpio-cells":
const: 2
gpio-controller: true
ngpios:
minimum: 1
maximum: 32
interrupt-controller: true
"#interrupt-cells":
const: 2
interrupts:
maxItems: 1
if:
properties:
compatible:
contains:
const: realtek,rtl9300-gpio
then:
properties:
reg:
items:
- description: GPIO and interrupt control
- description: interrupt CPU map
else:
properties:
reg:
items:
- description: GPIO and interrupt control
required:
- compatible
- reg
- "#gpio-cells"
- gpio-controller
additionalProperties: false
dependencies:
interrupt-controller: [ interrupts ]
examples:
- |
gpio@3500 {
compatible = "realtek,rtl8380-gpio", "realtek,otto-gpio";
reg = <0x3500 0x1c>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <24>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&rtlintc>;
interrupts = <23>;
};
- |
gpio@3300 {
compatible = "realtek,rtl9300-gpio", "realtek,otto-gpio";
reg = <0x3300 0x1c>, <0x3338 0x8>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <24>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&rtlintc>;
interrupts = <13>;
};
...

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/renesas,em-gio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas EMMA Mobile General Purpose I/O Interface
maintainers:
- Magnus Damm <magnus.damm@gmail.com>
properties:
compatible:
const: renesas,em-gio
reg:
items:
- description: First set of contiguous registers
- description: Second set of contiguous registers
interrupts:
items:
- description: Interrupt for the first set of 16 GPIO ports
- description: Interrupt for the second set of 16 GPIO ports
gpio-controller: true
'#gpio-cells':
const: 2
gpio-ranges:
maxItems: 1
ngpios:
minimum: 1
maximum: 32
interrupt-controller: true
'#interrupt-cells':
const: 2
required:
- compatible
- reg
- interrupts
- gpio-controller
- '#gpio-cells'
- gpio-ranges
- ngpios
- interrupt-controller
- '#interrupt-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
gpio0: gpio@e0050000 {
compatible = "renesas,em-gio";
reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pfc 0 0 32>;
ngpios = <32>;
interrupt-controller;
#interrupt-cells = <2>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/renesas,rcar-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas R-Car General-Purpose Input/Output Ports (GPIO)
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
properties:
compatible:
oneOf:
- items:
- enum:
- renesas,gpio-r8a7778 # R-Car M1
- renesas,gpio-r8a7779 # R-Car H1
- const: renesas,rcar-gen1-gpio # R-Car Gen1
- items:
- enum:
- renesas,gpio-r8a7742 # RZ/G1H
- renesas,gpio-r8a7743 # RZ/G1M
- renesas,gpio-r8a7744 # RZ/G1N
- renesas,gpio-r8a7745 # RZ/G1E
- renesas,gpio-r8a77470 # RZ/G1C
- renesas,gpio-r8a7790 # R-Car H2
- renesas,gpio-r8a7791 # R-Car M2-W
- renesas,gpio-r8a7792 # R-Car V2H
- renesas,gpio-r8a7793 # R-Car M2-N
- renesas,gpio-r8a7794 # R-Car E2
- const: renesas,rcar-gen2-gpio # R-Car Gen2 or RZ/G1
- items:
- enum:
- renesas,gpio-r8a774a1 # RZ/G2M
- renesas,gpio-r8a774b1 # RZ/G2N
- renesas,gpio-r8a774c0 # RZ/G2E
- renesas,gpio-r8a774e1 # RZ/G2H
- renesas,gpio-r8a7795 # R-Car H3
- renesas,gpio-r8a7796 # R-Car M3-W
- renesas,gpio-r8a77961 # R-Car M3-W+
- renesas,gpio-r8a77965 # R-Car M3-N
- renesas,gpio-r8a77970 # R-Car V3M
- renesas,gpio-r8a77980 # R-Car V3H
- renesas,gpio-r8a77990 # R-Car E3
- renesas,gpio-r8a77995 # R-Car D3
- const: renesas,rcar-gen3-gpio # R-Car Gen3 or RZ/G2
- items:
- enum:
- renesas,gpio-r8a779a0 # R-Car V3U
- renesas,gpio-r8a779f0 # R-Car S4-8
- renesas,gpio-r8a779g0 # R-Car V4H
- const: renesas,rcar-gen4-gpio # R-Car Gen4
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
power-domains:
maxItems: 1
resets:
maxItems: 1
gpio-controller: true
'#gpio-cells':
const: 2
interrupt-controller: true
'#interrupt-cells':
const: 2
gpio-ranges:
maxItems: 1
gpio-reserved-ranges:
minItems: 1
maxItems: 8
patternProperties:
"^.*$":
if:
type: object
then:
properties:
gpio-hog: true
gpios: true
input: true
output-high: true
output-low: true
line-name: true
required:
- gpio-hog
- gpios
additionalProperties: false
required:
- compatible
- reg
- interrupts
- gpio-controller
- '#gpio-cells'
- gpio-ranges
- interrupt-controller
- '#interrupt-cells'
if:
not:
properties:
compatible:
contains:
enum:
- renesas,rcar-gen1-gpio
then:
required:
- clocks
- power-domains
- resets
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/r8a77470-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a77470-sysc.h>
gpio3: gpio@e6053000 {
compatible = "renesas,gpio-r8a77470", "renesas,rcar-gen2-gpio";
reg = <0xe6053000 0x50>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 909>;
power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
resets = <&cpg 909>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pfc 0 96 30>;
gpio-reserved-ranges = <17 10>;
interrupt-controller;
#interrupt-cells = <2>;
};

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/rockchip,gpio-bank.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip GPIO bank
maintainers:
- Heiko Stuebner <heiko@sntech.de>
properties:
compatible:
enum:
- rockchip,gpio-bank
- rockchip,rk3188-gpio-bank0
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 1
items:
- description: APB interface clock source
- description: GPIO debounce reference clock source
gpio-ranges: true
gpio-controller: true
gpio-line-names: true
"#gpio-cells":
const: 2
interrupt-controller: true
"#interrupt-cells":
const: 2
required:
- compatible
- reg
- interrupts
- clocks
- gpio-controller
- "#gpio-cells"
- interrupt-controller
- "#interrupt-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl: pinctrl {
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio0: gpio@2000a000 {
compatible = "rockchip,rk3188-gpio-bank0";
reg = <0x2000a000 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates8 9>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@2003c000 {
compatible = "rockchip,gpio-bank";
reg = <0x2003c000 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates8 10>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};

50
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/rockchip,rk3328-grf-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip RK3328 General Register Files GPIO controller
description:
The Rockchip RK3328 General Register File (GRF) outputs only the
GPIO_MUTE pin, originally for codec mute control, but it can also be used
for general purpose. It is manipulated by the GRF_SOC_CON10 register.
If needed in the future support for the HDMI pins can also be added.
The GPIO node should be declared as the child of the GRF node.
The GPIO_MUTE pin is referred to in the format
<&grf_gpio 0 GPIO_ACTIVE_LOW>
The first cell is the pin number and
the second cell is used to specify the GPIO polarity
0 = Active high
1 = Active low
maintainers:
- Heiko Stuebner <heiko@sntech.de>
properties:
compatible:
const: rockchip,rk3328-grf-gpio
gpio-controller: true
"#gpio-cells":
const: 2
required:
- compatible
- gpio-controller
- "#gpio-cells"
additionalProperties: false
examples:
- |
grf_gpio: gpio {
compatible = "rockchip,rk3328-grf-gpio";
gpio-controller;
#gpio-cells = <2>;
};

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/sifive,gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SiFive GPIO controller
maintainers:
- Paul Walmsley <paul.walmsley@sifive.com>
properties:
compatible:
items:
- enum:
- sifive,fu540-c000-gpio
- sifive,fu740-c000-gpio
- canaan,k210-gpiohs
- const: sifive,gpio0
reg:
maxItems: 1
interrupts:
description:
Interrupt mapping, one per GPIO. Maximum 32 GPIOs.
minItems: 1
maxItems: 32
interrupt-controller: true
"#interrupt-cells":
const: 2
clocks:
maxItems: 1
"#gpio-cells":
const: 2
ngpios:
description:
The number of GPIOs available on the controller implementation.
It is 16 for the SiFive SoCs and 32 for the Canaan K210.
minimum: 1
maximum: 32
default: 16
gpio-line-names:
minItems: 1
maxItems: 32
gpio-controller: true
required:
- compatible
- reg
- interrupts
- interrupt-controller
- "#interrupt-cells"
- "#gpio-cells"
- gpio-controller
if:
properties:
compatible:
contains:
enum:
- sifive,fu540-c000-gpio
- sifive,fu740-c000-gpio
then:
required:
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/sifive-fu540-prci.h>
gpio@10060000 {
compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
interrupt-parent = <&plic>;
interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>,
<17>, <18>, <19>, <20>, <21>, <22>;
reg = <0x10060000 0x1000>;
clocks = <&tlclk FU540_PRCI_CLK_TLCLK>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
...

21
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Synopsys GPIO via CREG (Control REGisters) driver
Required properties:
- compatible : "snps,creg-gpio-hsdk" or "snps,creg-gpio-axs10x".
- reg : Exactly one register range with length 0x4.
- #gpio-cells : Since the generic GPIO binding is used, the
amount of cells must be specified as 2. The first cell is the
pin number, the second cell is used to specify optional parameters:
See "gpio-specifier" in .../devicetree/bindings/gpio/gpio.txt.
- gpio-controller : Marks the device node as a GPIO controller.
- ngpios: Number of GPIO pins.
Example:
gpio: gpio@f00014b0 {
compatible = "snps,creg-gpio-hsdk";
reg = <0xf00014b0 0x4>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <2>;
};

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/snps,dw-apb-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Synopsys DesignWare APB GPIO controller
description: |
Synopsys DesignWare GPIO controllers have a configurable number of ports,
each of which are intended to be represented as child nodes with the generic
GPIO-controller properties as desribed in this bindings file.
maintainers:
- Hoan Tran <hoan@os.amperecomputing.com>
- Serge Semin <fancer.lancer@gmail.com>
properties:
$nodename:
pattern: "^gpio@[0-9a-f]+$"
compatible:
const: snps,dw-apb-gpio
"#address-cells":
const: 1
"#size-cells":
const: 0
reg:
maxItems: 1
clocks:
minItems: 1
items:
- description: APB interface clock source
- description: DW GPIO debounce reference clock source
clock-names:
minItems: 1
items:
- const: bus
- const: db
resets:
maxItems: 1
patternProperties:
"^gpio-(port|controller)@[0-9a-f]+$":
type: object
properties:
compatible:
const: snps,dw-apb-gpio-port
reg:
maxItems: 1
gpio-controller: true
'#gpio-cells':
const: 2
ngpios:
default: 32
minimum: 1
maximum: 32
snps,nr-gpios:
description: The number of GPIO pins exported by the port.
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
default: 32
minimum: 1
maximum: 32
interrupts:
description: |
The interrupts to the parent controller raised when GPIOs generate
the interrupts. If the controller provides one combined interrupt
for all GPIOs, specify a single interrupt. If the controller provides
one interrupt for each GPIO, provide a list of interrupts that
correspond to each of the GPIO pins.
minItems: 1
maxItems: 32
interrupt-controller: true
'#interrupt-cells':
const: 2
required:
- compatible
- reg
- gpio-controller
- '#gpio-cells'
dependencies:
interrupt-controller: [ interrupts ]
additionalProperties: false
additionalProperties: false
required:
- compatible
- reg
- "#address-cells"
- "#size-cells"
examples:
- |
gpio: gpio@20000 {
compatible = "snps,dw-apb-gpio";
reg = <0x20000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
porta: gpio-port@0 {
compatible = "snps,dw-apb-gpio-port";
reg = <0>;
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <8>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&vic1>;
interrupts = <0>;
};
portb: gpio-port@1 {
compatible = "snps,dw-apb-gpio-port";
reg = <1>;
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <8>;
};
};
...

112
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/socionext,uniphier-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: UniPhier GPIO controller
maintainers:
- Masahiro Yamada <yamada.masahiro@socionext.com>
properties:
$nodename:
pattern: "^gpio@[0-9a-f]+$"
compatible:
const: socionext,uniphier-gpio
reg:
maxItems: 1
gpio-controller: true
"#gpio-cells":
const: 2
interrupt-controller: true
"#interrupt-cells":
description: |
The first cell defines the interrupt number.
The second cell bits[3:0] is used to specify trigger type as follows:
1 = low-to-high edge triggered
2 = high-to-low edge triggered
4 = active high level-sensitive
8 = active low level-sensitive
Valid combinations are 1, 2, 3, 4, 8.
const: 2
ngpios:
minimum: 0
maximum: 512
gpio-ranges: true
gpio-ranges-group-names: true
socionext,interrupt-ranges:
description: |
Specifies an interrupt number mapping between this GPIO controller and
its interrupt parent, in the form of arbitrary number of
<child-interrupt-base parent-interrupt-base length> triplets.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
patternProperties:
"^.+-hog(-[0-9]+)?$":
type: object
properties:
gpio-hog: true
gpios: true
input: true
output-high: true
output-low: true
line-name: true
required:
- gpio-hog
- gpios
additionalProperties: false
required:
- compatible
- reg
- gpio-controller
- "#gpio-cells"
- interrupt-controller
- "#interrupt-cells"
- ngpios
- gpio-ranges
- socionext,interrupt-ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/uniphier-gpio.h>
gpio: gpio@55000000 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000000 0x200>;
interrupt-parent = <&aidet>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 0>;
gpio-ranges-group-names = "gpio_range";
ngpios = <248>;
socionext,interrupt-ranges = <0 48 16>, <16 154 5>, <21 217 3>;
};
// Consumer:
// Please note UNIPHIER_GPIO_PORT(29, 4) represents PORT294 in the SoC
// document. Unfortunately, only the one's place is octal in the port
// numbering. (That is, PORT 8, 9, 18, 19, 28, 29, ... do not exist.)
// UNIPHIER_GPIO_PORT() is a helper macro to calculate 29 * 8 + 4.
sdhci0_pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio UNIPHIER_GPIO_PORT(29, 4) GPIO_ACTIVE_LOW>;
};

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GPIO controller on CE4100 / Sodaville SoCs
==========================================
The bindings for CE4100's GPIO controller match the generic description
which is covered by the gpio.txt file in this folder.
The only additional property is the intel,muxctl property which holds the
value which is written into the MUXCNTL register.
There is no compatible property for now because the driver is probed via
PCI id (vendor 0x8086 device 0x2e67).
The interrupt specifier consists of two cells encoded as follows:
- <1st cell>: The interrupt-number that identifies the interrupt source.
- <2nd cell>: The level-sense information, encoded as follows:
4 - active high level-sensitive
8 - active low level-sensitive
Example of the GPIO device and one user:
pcigpio: gpio@b,1 {
/* two cells for GPIO and interrupt */
#gpio-cells = <2>;
#interrupt-cells = <2>;
compatible = "pci8086,2e67.2",
"pci8086,2e67",
"pciclassff0000",
"pciclassff00";
reg = <0x15900 0x0 0x0 0x0 0x0>;
/* Interrupt line of the gpio device */
interrupts = <15 1>;
/* It is an interrupt and GPIO controller itself */
interrupt-controller;
gpio-controller;
intel,muxctl = <0>;
};
testuser@20 {
compatible = "example,testuser";
/* User the 11th GPIO line as an active high triggered
* level interrupt
*/
interrupts = <11 8>;
interrupt-parent = <&pcigpio>;
/* Use this GPIO also with the gpio functions */
gpios = <&pcigpio 11 0>;
};

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=== ST Microelectronics SPEAr SPI CS Driver ===
SPEAr platform provides a provision to control chipselects of ARM PL022 Prime
Cell spi controller through its system registers, which otherwise remains under
PL022 control. If chipselect remain under PL022 control then they would be
released as soon as transfer is over and TxFIFO becomes empty. This is not
desired by some of the device protocols above spi which expect (multiple)
transfers without releasing their chipselects.
Chipselects can be controlled by software by turning them as GPIOs. SPEAr
provides another interface through system registers through which software can
directly control each PL022 chipselect. Hence, it is natural for SPEAr to export
the control of this interface as gpio.
Required properties:
* compatible: should be defined as "st,spear-spics-gpio"
* reg: mentioning address range of spics controller
* st-spics,peripcfg-reg: peripheral configuration register offset
* st-spics,sw-enable-bit: bit offset to enable sw control
* st-spics,cs-value-bit: bit offset to drive chipselect low or high
* st-spics,cs-enable-mask: chip select number bit mask
* st-spics,cs-enable-shift: chip select number program offset
* gpio-controller: Marks the device node as gpio controller
* #gpio-cells: should be 1 and will mention chip select number
All the above bit offsets are within peripcfg register.
Example:
-------
spics: spics@e0700000{
compatible = "st,spear-spics-gpio";
reg = <0xe0700000 0x1000>;
st-spics,peripcfg-reg = <0x3b0>;
st-spics,sw-enable-bit = <12>;
st-spics,cs-value-bit = <11>;
st-spics,cs-enable-mask = <3>;
st-spics,cs-enable-shift = <8>;
gpio-controller;
#gpio-cells = <2>;
};
spi0: spi@e0100000 {
num-cs = <3>;
cs-gpios = <&gpio1 7 0>, <&spics 0>,
<&spics 1>;
...
}

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/ti,omap-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: OMAP GPIO controller bindings
maintainers:
- Grygorii Strashko <grygorii.strashko@ti.com>
description: |
The general-purpose interface combines general-purpose input/output (GPIO) banks.
Each GPIO banks provides up to 32 dedicated general-purpose pins with input
and output capabilities; interrupt generation in active mode and wake-up
request generation in idle mode upon the detection of external events.
properties:
compatible:
oneOf:
- enum:
- ti,omap2-gpio
- ti,omap3-gpio
- ti,omap4-gpio
- items:
- const: ti,am4372-gpio
- const: ti,omap4-gpio
reg:
maxItems: 1
gpio-controller: true
'#gpio-cells':
const: 2
interrupt-controller: true
'#interrupt-cells':
const: 2
interrupts:
maxItems: 1
gpio-ranges: true
gpio-line-names:
minItems: 1
maxItems: 32
ti,gpio-always-on:
$ref: /schemas/types.yaml#/definitions/flag
description:
Indicates if a GPIO bank is always powered and will never lose its logic state.
ti,hwmods:
$ref: /schemas/types.yaml#/definitions/string
deprecated: true
description:
Name of the hwmod associated with the GPIO. Needed on some legacy OMAP
SoCs which have not been converted to the ti,sysc interconnect hierarachy.
ti,no-reset-on-init:
$ref: /schemas/types.yaml#/definitions/flag
deprecated: true
description:
Do not reset on init. Used with ti,hwmods on some legacy OMAP SoCs which
have not been converted to the ti,sysc interconnect hierarachy.
patternProperties:
"^(.+-hog(-[0-9]+)?)$":
type: object
required:
- gpio-hog
required:
- compatible
- reg
- gpio-controller
- "#gpio-cells"
- interrupt-controller
- "#interrupt-cells"
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
gpio0: gpio@0 {
compatible = "ti,omap4-gpio";
reg = <0x0 0x1000>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <96>;
ti,gpio-always-on;
ls-buf-en-hog {
gpio-hog;
gpios = <10 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "LS_BUF_EN";
};
};

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bindings/gpio/toshiba,gpio-visconti.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/toshiba,gpio-visconti.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Toshiba Visconti ARM SoCs GPIO controller
maintainers:
- Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
properties:
compatible:
items:
- const: toshiba,gpio-tmpv7708
reg:
maxItems: 1
"#gpio-cells":
const: 2
gpio-ranges: true
gpio-controller: true
interrupt-controller: true
"#interrupt-cells":
const: 2
interrupts:
description:
interrupt mapping one per GPIO.
minItems: 16
maxItems: 16
required:
- compatible
- reg
- "#gpio-cells"
- gpio-ranges
- gpio-controller
- interrupt-controller
- "#interrupt-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
gpio: gpio@28020000 {
compatible = "toshiba,gpio-tmpv7708";
reg = <0 0x28020000 0 0x1000>;
#gpio-cells = <0x2>;
gpio-ranges = <&pmux 0 0 32>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
};
};
...

38
bindings/gpio/wd,mbl-gpio.txt Normal file
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Bindings for the Western Digital's MyBook Live memory-mapped GPIO controllers.
The Western Digital MyBook Live has two memory-mapped GPIO controllers.
Both GPIO controller only have a single 8-bit data register, where GPIO
state can be read and/or written.
Required properties:
- compatible: should be "wd,mbl-gpio"
- reg-names: must contain
"dat" - data register
- reg: address + size pairs describing the GPIO register sets;
order must correspond with the order of entries in reg-names
- #gpio-cells: must be set to 2. The first cell is the pin number and
the second cell is used to specify the gpio polarity:
0 = active high
1 = active low
- gpio-controller: Marks the device node as a gpio controller.
Optional properties:
- no-output: GPIOs are read-only.
Examples:
gpio0: gpio0@e0000000 {
compatible = "wd,mbl-gpio";
reg-names = "dat";
reg = <0xe0000000 0x1>;
#gpio-cells = <2>;
gpio-controller;
};
gpio1: gpio1@e0100000 {
compatible = "wd,mbl-gpio";
reg-names = "dat";
reg = <0xe0100000 0x1>;
#gpio-cells = <2>;
gpio-controller;
no-output;
};

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bindings/gpio/x-powers,axp209-gpio.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: "http://devicetree.org/schemas/gpio/x-powers,axp209-gpio.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: X-Powers AXP209 GPIO
maintainers:
- Chen-Yu Tsai <wens@csie.org>
properties:
"#gpio-cells":
const: 2
description: >
The first cell is the pin number and the second is the GPIO flags.
compatible:
oneOf:
- enum:
- x-powers,axp209-gpio
- x-powers,axp221-gpio
- x-powers,axp813-gpio
- items:
- enum:
- x-powers,axp223-gpio
- x-powers,axp809-gpio
- const: x-powers,axp221-gpio
- items:
- const: x-powers,axp803-gpio
- const: x-powers,axp813-gpio
gpio-controller: true
patternProperties:
"^.*-pins?$":
$ref: /schemas/pinctrl/pinmux-node.yaml#
properties:
pins:
items:
enum:
- GPIO0
- GPIO1
- GPIO2
function:
enum:
- adc
- ldo
- gpio_in
- gpio_out
required:
- compatible
- "#gpio-cells"
- gpio-controller
additionalProperties: false
...

154
bindings/gpio/xlnx,gpio-xilinx.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/xlnx,gpio-xilinx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx AXI GPIO controller
maintainers:
- Neeli Srinivas <srinivas.neeli@xilinx.com>
description:
The AXI GPIO design provides a general purpose input/output interface
to an AXI4-Lite interface. The AXI GPIO can be configured as either
a single or a dual-channel device. The width of each channel is
independently configurable. The channels can be configured to
generate an interrupt when a transition on any of their inputs occurs.
properties:
compatible:
enum:
- xlnx,xps-gpio-1.00.a
reg:
maxItems: 1
"#gpio-cells":
const: 2
interrupts:
maxItems: 1
gpio-controller: true
gpio-line-names:
description: strings describing the names of each gpio line
minItems: 1
maxItems: 64
interrupt-controller: true
"#interrupt-cells":
const: 2
clocks:
maxItems: 1
interrupt-names: true
xlnx,all-inputs:
$ref: /schemas/types.yaml#/definitions/uint32
description: This option sets this GPIO channel1 bits in input mode.
xlnx,all-inputs-2:
$ref: /schemas/types.yaml#/definitions/uint32
description: This option sets this GPIO channel2 bits in input mode.
xlnx,all-outputs:
$ref: /schemas/types.yaml#/definitions/uint32
description: This option sets this GPIO channel1 bits in output mode.
xlnx,all-outputs-2:
$ref: /schemas/types.yaml#/definitions/uint32
description: This option sets this GPIO channel2 bits in output mode.
xlnx,dout-default:
$ref: /schemas/types.yaml#/definitions/uint32
description: Sets the default value of all the enabled bits of
channel1.
default: 0
xlnx,dout-default-2:
$ref: /schemas/types.yaml#/definitions/uint32
description: Sets the default value of all the enabled bits of
channel2.
default: 0
xlnx,gpio-width:
$ref: /schemas/types.yaml#/definitions/uint32
description: The value defines the bit width of the GPIO channel1.
minimum: 1
maximum: 32
default: 32
xlnx,gpio2-width:
$ref: /schemas/types.yaml#/definitions/uint32
description: The value defines the bit width of the GPIO channel2.
minimum: 1
maximum: 32
default: 32
xlnx,interrupt-present:
$ref: /schemas/types.yaml#/definitions/uint32
description: This parameter enables interrupt control logic
and interrupt registers in GPIO module.
minimum: 0
maximum: 1
default: 0
xlnx,is-dual:
$ref: /schemas/types.yaml#/definitions/uint32
description: This parameter enables a second GPIO channel (GPIO2).
minimum: 0
maximum: 1
default: 0
xlnx,tri-default:
$ref: /schemas/types.yaml#/definitions/uint32
description: This value configures the input or output mode
of each bit of GPIO channel1.
xlnx,tri-default-2:
$ref: /schemas/types.yaml#/definitions/uint32
description: This value configures the input or output mode
of each bit of GPIO channel2.
required:
- reg
- compatible
- gpio-controller
- "#gpio-cells"
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
gpio@e000a000 {
compatible = "xlnx,xps-gpio-1.00.a";
reg = <0xa0020000 0x10000>;
#gpio-cells = <2>;
#interrupt-cells = <0x2>;
clocks = <&zynqmp_clk 71>;
gpio-controller;
interrupt-controller;
interrupt-names = "ip2intc_irpt";
interrupt-parent = <&gic>;
interrupts = <0 89 4>;
xlnx,all-inputs = <0x0>;
xlnx,all-inputs-2 = <0x0>;
xlnx,all-outputs = <0x0>;
xlnx,all-outputs-2 = <0x0>;
xlnx,dout-default = <0x0>;
xlnx,dout-default-2 = <0x0>;
xlnx,gpio-width = <0x20>;
xlnx,gpio2-width = <0x20>;
xlnx,interrupt-present = <0x1>;
xlnx,is-dual = <0x1>;
xlnx,tri-default = <0xFFFFFFFF>;
xlnx,tri-default-2 = <0xFFFFFFFF>;
};
...

43
bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: ZynqMP Mode Pin GPIO controller
description:
PS_MODE is 4-bits boot mode pins sampled on POR deassertion. Mode Pin
GPIO controller with configurable from numbers of pins (from 0 to 3 per
PS_MODE). Every pin can be configured as input/output.
maintainers:
- Piyush Mehta <piyush.mehta@xilinx.com>
properties:
compatible:
const: xlnx,zynqmp-gpio-modepin
gpio-controller: true
"#gpio-cells":
const: 2
required:
- compatible
- gpio-controller
- "#gpio-cells"
additionalProperties: false
examples:
- |
zynqmp-firmware {
gpio {
compatible = "xlnx,zynqmp-gpio-modepin";
gpio-controller;
#gpio-cells = <2>;
};
};
...

71
bindings/gpio/xylon,logicvc-gpio.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 Bootlin
%YAML 1.2
---
$id: "http://devicetree.org/schemas/gpio/xylon,logicvc-gpio.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Xylon LogiCVC GPIO controller
maintainers:
- Paul Kocialkowski <paul.kocialkowski@bootlin.com>
description: |
The LogiCVC GPIO describes the GPIO block included in the LogiCVC display
controller. These are meant to be used for controlling display-related
signals.
The controller exposes GPIOs from the display and power control registers,
which are mapped by the driver as follows:
- GPIO[4:0] (display control) mapped to index 0-4
- EN_BLIGHT (power control) mapped to index 5
- EN_VDD (power control) mapped to index 6
- EN_VEE (power control) mapped to index 7
- V_EN (power control) mapped to index 8
properties:
$nodename:
pattern: "^gpio@[0-9a-f]+$"
compatible:
enum:
- xylon,logicvc-3.02.a-gpio
reg:
maxItems: 1
"#gpio-cells":
const: 2
gpio-controller: true
gpio-line-names:
minItems: 1
maxItems: 9
required:
- compatible
- reg
- "#gpio-cells"
- gpio-controller
additionalProperties: false
examples:
- |
logicvc: logicvc@43c00000 {
compatible = "xylon,logicvc-3.02.a", "syscon", "simple-mfd";
reg = <0x43c00000 0x6000>;
#address-cells = <1>;
#size-cells = <1>;
logicvc_gpio: gpio@40 {
compatible = "xylon,logicvc-3.02.a-gpio";
reg = <0x40 0x40>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "GPIO0", "GPIO1", "GPIO2", "GPIO3", "GPIO4",
"EN_BLIGHT", "EN_VDD", "EN_VEE", "V_EN";
};
};