dt-bindings: Add devicetree bindings
Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").
Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
This commit is contained in:
Melody Olvera
66
bindings/edac/amazon,al-mc-edac.yaml
Normal file
66
bindings/edac/amazon,al-mc-edac.yaml
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@@ -0,0 +1,66 @@
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/edac/amazon,al-mc-edac.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Amazon's Annapurna Labs Memory Controller EDAC
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maintainers:
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- Talel Shenhar <talel@amazon.com>
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- Talel Shenhar <talelshenhar@gmail.com>
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description: |
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EDAC node is defined to describe on-chip error detection and correction for
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Amazon's Annapurna Labs Memory Controller.
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properties:
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compatible:
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const: amazon,al-mc-edac
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reg:
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maxItems: 1
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"#address-cells":
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const: 2
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"#size-cells":
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const: 2
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interrupts:
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minItems: 1
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items:
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- description: uncorrectable error interrupt
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- description: correctable error interrupt
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interrupt-names:
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minItems: 1
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items:
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- const: ue
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- const: ce
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required:
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- compatible
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- reg
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- "#address-cells"
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- "#size-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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edac@f0080000 {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "amazon,al-mc-edac";
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reg = <0x0 0xf0080000 0x0 0x00010000>;
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interrupt-parent = <&amazon_al_system_fabric>;
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interrupt-names = "ue";
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interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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112
bindings/edac/apm-xgene-edac.txt
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112
bindings/edac/apm-xgene-edac.txt
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@@ -0,0 +1,112 @@
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* APM X-Gene SoC EDAC node
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EDAC node is defined to describe on-chip error detection and correction.
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The follow error types are supported:
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memory controller - Memory controller
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PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache
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L3 - L3 cache controller
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SoC - SoC IP's such as Ethernet, SATA, and etc
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The following section describes the EDAC DT node binding.
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Required properties:
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- compatible : Shall be "apm,xgene-edac".
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- regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
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- regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
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- regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
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- regmap-efuse : Regmap of the PMD efuse resource.
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- regmap-rb : Regmap of the register bus resource. This property
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is optional only for compatibility. If the RB
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error conditions are not cleared, it will
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continuously generate interrupt.
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- reg : First resource shall be the CPU bus (PCP) resource.
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- interrupts : Interrupt-specifier for MCU, PMD, L3, or SoC error
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IRQ(s).
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Required properties for memory controller subnode:
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- compatible : Shall be "apm,xgene-edac-mc".
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- reg : First resource shall be the memory controller unit
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(MCU) resource.
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- memory-controller : Instance number of the memory controller.
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Required properties for PMD subnode:
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- compatible : Shall be "apm,xgene-edac-pmd" or
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"apm,xgene-edac-pmd-v2".
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- reg : First resource shall be the PMD resource.
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- pmd-controller : Instance number of the PMD controller.
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Required properties for L3 subnode:
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- compatible : Shall be "apm,xgene-edac-l3" or
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"apm,xgene-edac-l3-v2".
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- reg : First resource shall be the L3 EDAC resource.
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Required properties for SoC subnode:
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- compatible : Shall be "apm,xgene-edac-soc-v1" for revision 1 or
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"apm,xgene-edac-l3-soc" for general value reporting
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only.
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- reg : First resource shall be the SoC EDAC resource.
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Example:
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csw: csw@7e200000 {
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compatible = "apm,xgene-csw", "syscon";
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reg = <0x0 0x7e200000 0x0 0x1000>;
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};
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mcba: mcba@7e700000 {
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compatible = "apm,xgene-mcb", "syscon";
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reg = <0x0 0x7e700000 0x0 0x1000>;
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};
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mcbb: mcbb@7e720000 {
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compatible = "apm,xgene-mcb", "syscon";
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reg = <0x0 0x7e720000 0x0 0x1000>;
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};
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efuse: efuse@1054a000 {
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compatible = "apm,xgene-efuse", "syscon";
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reg = <0x0 0x1054a000 0x0 0x20>;
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};
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rb: rb@7e000000 {
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compatible = "apm,xgene-rb", "syscon";
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reg = <0x0 0x7e000000 0x0 0x10>;
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};
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edac@78800000 {
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compatible = "apm,xgene-edac";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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regmap-csw = <&csw>;
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regmap-mcba = <&mcba>;
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regmap-mcbb = <&mcbb>;
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regmap-efuse = <&efuse>;
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regmap-rb = <&rb>;
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reg = <0x0 0x78800000 0x0 0x100>;
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interrupts = <0x0 0x20 0x4>,
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<0x0 0x21 0x4>,
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<0x0 0x27 0x4>;
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edacmc@7e800000 {
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compatible = "apm,xgene-edac-mc";
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reg = <0x0 0x7e800000 0x0 0x1000>;
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memory-controller = <0>;
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};
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edacpmd@7c000000 {
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compatible = "apm,xgene-edac-pmd";
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reg = <0x0 0x7c000000 0x0 0x200000>;
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pmd-controller = <0>;
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};
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edacl3@7e600000 {
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compatible = "apm,xgene-edac-l3";
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reg = <0x0 0x7e600000 0x0 0x1000>;
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};
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edacsoc@7e930000 {
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compatible = "apm,xgene-edac-soc-v1";
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reg = <0x0 0x7e930000 0x0 0x1000>;
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};
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};
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28
bindings/edac/aspeed-sdram-edac.txt
Normal file
28
bindings/edac/aspeed-sdram-edac.txt
Normal file
@@ -0,0 +1,28 @@
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Aspeed BMC SoC EDAC node
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The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
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correction check).
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The memory controller supports SECDED (single bit error correction, double bit
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error detection) and single bit error auto scrubbing by reserving 8 bits for
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every 64 bit word (effectively reducing available memory to 8/9).
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Note, the bootloader must configure ECC mode in the memory controller.
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Required properties:
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- compatible: should be one of
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- "aspeed,ast2400-sdram-edac"
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- "aspeed,ast2500-sdram-edac"
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- "aspeed,ast2600-sdram-edac"
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- reg: sdram controller register set should be <0x1e6e0000 0x174>
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- interrupts: should be AVIC interrupt #0
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Example:
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edac: sdram@1e6e0000 {
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compatible = "aspeed,ast2500-sdram-edac";
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reg = <0x1e6e0000 0x174>;
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interrupts = <0>;
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};
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61
bindings/edac/dmc-520.yaml
Normal file
61
bindings/edac/dmc-520.yaml
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@@ -0,0 +1,61 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/edac/dmc-520.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM DMC-520 EDAC bindings
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maintainers:
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- Lei Wang <lewan@microsoft.com>
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description: |+
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DMC-520 node is defined to describe DRAM error detection and correction.
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https://static.docs.arm.com/100000/0200/corelink_dmc520_trm_100000_0200_01_en.pdf
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properties:
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compatible:
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items:
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- const: brcm,dmc-520
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- const: arm,dmc-520
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reg:
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maxItems: 1
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interrupts:
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minItems: 1
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maxItems: 10
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interrupt-names:
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minItems: 1
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maxItems: 10
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items:
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enum:
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- ram_ecc_errc
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- ram_ecc_errd
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- dram_ecc_errc
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- dram_ecc_errd
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- failed_access
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- failed_prog
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- link_err
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- temperature_event
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- arch_fsm
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- phy_request
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-names
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additionalProperties: false
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examples:
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- |
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dmc0: dmc@200000 {
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compatible = "brcm,dmc-520", "arm,dmc-520";
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reg = <0x200000 0x80000>;
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interrupts = <0x0 0x349 0x4>, <0x0 0x34B 0x4>;
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interrupt-names = "dram_ecc_errc", "dram_ecc_errd";
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};
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383
bindings/edac/socfpga-eccmgr.txt
Normal file
383
bindings/edac/socfpga-eccmgr.txt
Normal file
@@ -0,0 +1,383 @@
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Altera SoCFPGA ECC Manager
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This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.
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The ECC Manager counts and corrects single bit errors and counts/handles
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double bit errors which are uncorrectable.
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Cyclone5 and Arria5 ECC Manager
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Required Properties:
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- compatible : Should be "altr,socfpga-ecc-manager"
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- #address-cells: must be 1
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- #size-cells: must be 1
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- ranges : standard definition, should translate from local addresses
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Subcomponents:
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L2 Cache ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-l2-ecc"
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- reg : Address and size for ECC error interrupt clear registers.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt. Note the rising edge type.
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On Chip RAM ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-ocram-ecc"
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- reg : Address and size for ECC error interrupt clear registers.
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- iram : phandle to On-Chip RAM definition.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt. Note the rising edge type.
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Example:
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eccmgr: eccmgr@ffd08140 {
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compatible = "altr,socfpga-ecc-manager";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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l2-ecc@ffd08140 {
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compatible = "altr,socfpga-l2-ecc";
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reg = <0xffd08140 0x4>;
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interrupts = <0 36 1>, <0 37 1>;
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};
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ocram-ecc@ffd08144 {
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compatible = "altr,socfpga-ocram-ecc";
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reg = <0xffd08144 0x4>;
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iram = <&ocram>;
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interrupts = <0 178 1>, <0 179 1>;
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};
|
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};
|
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|
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Arria10 SoCFPGA ECC Manager
|
||||
The Arria10 SoC ECC Manager handles the IRQs for each peripheral
|
||||
in a shared register instead of individual IRQs like the Cyclone5
|
||||
and Arria5. Therefore the device tree is different as well.
|
||||
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,socfpga-a10-ecc-manager"
|
||||
- altr,sysgr-syscon : phandle to Arria10 System Manager Block
|
||||
containing the ECC manager registers.
|
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- #address-cells: must be 1
|
||||
- #size-cells: must be 1
|
||||
- interrupts : Should be single bit error interrupt, then double bit error
|
||||
interrupt.
|
||||
- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
|
||||
- #interrupt-cells : must be set to 2.
|
||||
- ranges : standard definition, should translate from local addresses
|
||||
|
||||
Subcomponents:
|
||||
|
||||
L2 Cache ECC
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,socfpga-a10-l2-ecc"
|
||||
- reg : Address and size for ECC error interrupt clear registers.
|
||||
- interrupts : Should be single bit error interrupt, then double bit error
|
||||
interrupt, in this order.
|
||||
|
||||
On-Chip RAM ECC
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,socfpga-a10-ocram-ecc"
|
||||
- reg : Address and size for ECC block registers.
|
||||
- interrupts : Should be single bit error interrupt, then double bit error
|
||||
interrupt, in this order.
|
||||
|
||||
Ethernet FIFO ECC
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,socfpga-eth-mac-ecc"
|
||||
- reg : Address and size for ECC block registers.
|
||||
- altr,ecc-parent : phandle to parent Ethernet node.
|
||||
- interrupts : Should be single bit error interrupt, then double bit error
|
||||
interrupt, in this order.
|
||||
|
||||
NAND FIFO ECC
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,socfpga-nand-ecc"
|
||||
- reg : Address and size for ECC block registers.
|
||||
- altr,ecc-parent : phandle to parent NAND node.
|
||||
- interrupts : Should be single bit error interrupt, then double bit error
|
||||
interrupt, in this order.
|
||||
|
||||
DMA FIFO ECC
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,socfpga-dma-ecc"
|
||||
- reg : Address and size for ECC block registers.
|
||||
- altr,ecc-parent : phandle to parent DMA node.
|
||||
- interrupts : Should be single bit error interrupt, then double bit error
|
||||
interrupt, in this order.
|
||||
|
||||
USB FIFO ECC
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,socfpga-usb-ecc"
|
||||
- reg : Address and size for ECC block registers.
|
||||
- altr,ecc-parent : phandle to parent USB node.
|
||||
- interrupts : Should be single bit error interrupt, then double bit error
|
||||
interrupt, in this order.
|
||||
|
||||
QSPI FIFO ECC
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,socfpga-qspi-ecc"
|
||||
- reg : Address and size for ECC block registers.
|
||||
- altr,ecc-parent : phandle to parent QSPI node.
|
||||
- interrupts : Should be single bit error interrupt, then double bit error
|
||||
interrupt, in this order.
|
||||
|
||||
SDMMC FIFO ECC
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,socfpga-sdmmc-ecc"
|
||||
- reg : Address and size for ECC block registers.
|
||||
- altr,ecc-parent : phandle to parent SD/MMC node.
|
||||
- interrupts : Should be single bit error interrupt, then double bit error
|
||||
interrupt, in this order for port A, and then single bit error interrupt,
|
||||
then double bit error interrupt in this order for port B.
|
||||
|
||||
Example:
|
||||
|
||||
eccmgr: eccmgr@ffd06000 {
|
||||
compatible = "altr,socfpga-a10-ecc-manager";
|
||||
altr,sysmgr-syscon = <&sysmgr>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ranges;
|
||||
|
||||
l2-ecc@ffd06010 {
|
||||
compatible = "altr,socfpga-a10-l2-ecc";
|
||||
reg = <0xffd06010 0x4>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
ocram-ecc@ff8c3000 {
|
||||
compatible = "altr,socfpga-a10-ocram-ecc";
|
||||
reg = <0xff8c3000 0x90>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<33 IRQ_TYPE_LEVEL_HIGH> ;
|
||||
};
|
||||
|
||||
emac0-rx-ecc@ff8c0800 {
|
||||
compatible = "altr,socfpga-eth-mac-ecc";
|
||||
reg = <0xff8c0800 0x400>;
|
||||
altr,ecc-parent = <&gmac0>;
|
||||
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
emac0-tx-ecc@ff8c0c00 {
|
||||
compatible = "altr,socfpga-eth-mac-ecc";
|
||||
reg = <0xff8c0c00 0x400>;
|
||||
altr,ecc-parent = <&gmac0>;
|
||||
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
nand-buf-ecc@ff8c2000 {
|
||||
compatible = "altr,socfpga-nand-ecc";
|
||||
reg = <0xff8c2000 0x400>;
|
||||
altr,ecc-parent = <&nand>;
|
||||
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
nand-rd-ecc@ff8c2400 {
|
||||
compatible = "altr,socfpga-nand-ecc";
|
||||
reg = <0xff8c2400 0x400>;
|
||||
altr,ecc-parent = <&nand>;
|
||||
interrupts = <13 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
nand-wr-ecc@ff8c2800 {
|
||||
compatible = "altr,socfpga-nand-ecc";
|
||||
reg = <0xff8c2800 0x400>;
|
||||
altr,ecc-parent = <&nand>;
|
||||
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
dma-ecc@ff8c8000 {
|
||||
compatible = "altr,socfpga-dma-ecc";
|
||||
reg = <0xff8c8000 0x400>;
|
||||
altr,ecc-parent = <&pdma>;
|
||||
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
usb0-ecc@ff8c8800 {
|
||||
compatible = "altr,socfpga-usb-ecc";
|
||||
reg = <0xff8c8800 0x400>;
|
||||
altr,ecc-parent = <&usb0>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
qspi-ecc@ff8c8400 {
|
||||
compatible = "altr,socfpga-qspi-ecc";
|
||||
reg = <0xff8c8400 0x400>;
|
||||
altr,ecc-parent = <&qspi>;
|
||||
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sdmmc-ecc@ff8c2c00 {
|
||||
compatible = "altr,socfpga-sdmmc-ecc";
|
||||
reg = <0xff8c2c00 0x400>;
|
||||
altr,ecc-parent = <&mmc>;
|
||||
interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<47 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<16 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
Stratix10 SoCFPGA ECC Manager (ARM64)
|
||||
The Stratix10 SoC ECC Manager handles the IRQs for each peripheral
|
||||
in a shared register similar to the Arria10. However, Stratix10 ECC
|
||||
requires access to registers that can only be read from Secure Monitor
|
||||
with SMC calls. Therefore the device tree is slightly different. Note
|
||||
that only 1 interrupt is sent in Stratix10 because the double bit errors
|
||||
are treated as SErrors in ARM64 instead of IRQs in ARM32.
|
||||
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,socfpga-s10-ecc-manager"
|
||||
- altr,sysgr-syscon : phandle to Stratix10 System Manager Block
|
||||
containing the ECC manager registers.
|
||||
- interrupts : Should be single bit error interrupt.
|
||||
- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
|
||||
- #interrupt-cells : must be set to 2.
|
||||
- #address-cells: must be 1
|
||||
- #size-cells: must be 1
|
||||
- ranges : standard definition, should translate from local addresses
|
||||
|
||||
Subcomponents:
|
||||
|
||||
SDRAM ECC
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,sdram-edac-s10"
|
||||
- interrupts : Should be single bit error interrupt.
|
||||
|
||||
On-Chip RAM ECC
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,socfpga-s10-ocram-ecc"
|
||||
- reg : Address and size for ECC block registers.
|
||||
- altr,ecc-parent : phandle to parent OCRAM node.
|
||||
- interrupts : Should be single bit error interrupt.
|
||||
|
||||
Ethernet FIFO ECC
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,socfpga-s10-eth-mac-ecc"
|
||||
- reg : Address and size for ECC block registers.
|
||||
- altr,ecc-parent : phandle to parent Ethernet node.
|
||||
- interrupts : Should be single bit error interrupt.
|
||||
|
||||
NAND FIFO ECC
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,socfpga-s10-nand-ecc"
|
||||
- reg : Address and size for ECC block registers.
|
||||
- altr,ecc-parent : phandle to parent NAND node.
|
||||
- interrupts : Should be single bit error interrupt.
|
||||
|
||||
DMA FIFO ECC
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,socfpga-s10-dma-ecc"
|
||||
- reg : Address and size for ECC block registers.
|
||||
- altr,ecc-parent : phandle to parent DMA node.
|
||||
- interrupts : Should be single bit error interrupt.
|
||||
|
||||
USB FIFO ECC
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,socfpga-s10-usb-ecc"
|
||||
- reg : Address and size for ECC block registers.
|
||||
- altr,ecc-parent : phandle to parent USB node.
|
||||
- interrupts : Should be single bit error interrupt.
|
||||
|
||||
SDMMC FIFO ECC
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,socfpga-s10-sdmmc-ecc"
|
||||
- reg : Address and size for ECC block registers.
|
||||
- altr,ecc-parent : phandle to parent SD/MMC node.
|
||||
- interrupts : Should be single bit error interrupt for port A
|
||||
and then single bit error interrupt for port B.
|
||||
|
||||
Example:
|
||||
|
||||
eccmgr {
|
||||
compatible = "altr,socfpga-s10-ecc-manager";
|
||||
altr,sysmgr-syscon = <&sysmgr>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <0 15 4>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ranges;
|
||||
|
||||
sdramedac {
|
||||
compatible = "altr,sdram-edac-s10";
|
||||
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
ocram-ecc@ff8cc000 {
|
||||
compatible = "altr,socfpga-s10-ocram-ecc";
|
||||
reg = <ff8cc000 0x100>;
|
||||
altr,ecc-parent = <&ocram>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
emac0-rx-ecc@ff8c0000 {
|
||||
compatible = "altr,socfpga-s10-eth-mac-ecc";
|
||||
reg = <0xff8c0000 0x100>;
|
||||
altr,ecc-parent = <&gmac0>;
|
||||
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
emac0-tx-ecc@ff8c0400 {
|
||||
compatible = "altr,socfpga-s10-eth-mac-ecc";
|
||||
reg = <0xff8c0400 0x100>;
|
||||
altr,ecc-parent = <&gmac0>;
|
||||
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>'
|
||||
};
|
||||
|
||||
nand-buf-ecc@ff8c8000 {
|
||||
compatible = "altr,socfpga-s10-nand-ecc";
|
||||
reg = <0xff8c8000 0x100>;
|
||||
altr,ecc-parent = <&nand>;
|
||||
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
nand-rd-ecc@ff8c8400 {
|
||||
compatible = "altr,socfpga-s10-nand-ecc";
|
||||
reg = <0xff8c8400 0x100>;
|
||||
altr,ecc-parent = <&nand>;
|
||||
interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
nand-wr-ecc@ff8c8800 {
|
||||
compatible = "altr,socfpga-s10-nand-ecc";
|
||||
reg = <0xff8c8800 0x100>;
|
||||
altr,ecc-parent = <&nand>;
|
||||
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
dma-ecc@ff8c9000 {
|
||||
compatible = "altr,socfpga-s10-dma-ecc";
|
||||
reg = <0xff8c9000 0x100>;
|
||||
altr,ecc-parent = <&pdma>;
|
||||
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
usb0-ecc@ff8c4000 {
|
||||
compatible = "altr,socfpga-s10-usb-ecc";
|
||||
reg = <0xff8c4000 0x100>;
|
||||
altr,ecc-parent = <&usb0>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sdmmc-ecc@ff8c8c00 {
|
||||
compatible = "altr,socfpga-s10-sdmmc-ecc";
|
||||
reg = <0xff8c8c00 0x100>;
|
||||
altr,ecc-parent = <&mmc>;
|
||||
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
Reference in New Issue
Block a user