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dt-bindings: Add devicetree bindings

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Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").

Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
This commit is contained in:
Melody Olvera
2023-04-03 14:38:11 -07:00
parent c334acf377
commit 6f18ce8026
4878 changed files with 424312 additions and 0 deletions
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205
bindings/dsp/fsl,dsp.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dsp/fsl,dsp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX8 DSP core
maintainers:
- Daniel Baluta <daniel.baluta@nxp.com>
- Shengjiu Wang <shengjiu.wang@nxp.com>
description: |
Some boards from i.MX8 family contain a DSP core used for
advanced pre- and post- audio processing.
properties:
compatible:
enum:
- fsl,imx8qxp-dsp
- fsl,imx8qm-dsp
- fsl,imx8mp-dsp
- fsl,imx8ulp-dsp
- fsl,imx8qxp-hifi4
- fsl,imx8qm-hifi4
- fsl,imx8mp-hifi4
- fsl,imx8ulp-hifi4
reg:
maxItems: 1
clocks:
items:
- description: ipg clock
- description: ocram clock
- description: core clock
- description: debug interface clock
- description: message unit clock
minItems: 3
clock-names:
items:
- const: ipg
- const: ocram
- const: core
- const: debug
- const: mu
minItems: 3
power-domains:
description:
List of phandle and PM domain specifier as documented in
Documentation/devicetree/bindings/power/power_domain.txt
minItems: 1
maxItems: 4
mboxes:
description:
List of <&phandle type channel> - 2 channels for TXDB, 2 channels for RXDB
or - 1 channel for TX, 1 channel for RX, 1 channel for RXDB
(see mailbox/fsl,mu.txt)
minItems: 3
maxItems: 4
mbox-names:
minItems: 3
maxItems: 4
memory-region:
description:
phandle to a node describing reserved memory (System RAM memory)
used by DSP (see bindings/reserved-memory/reserved-memory.txt)
minItems: 1
maxItems: 4
firmware-name:
description: |
Default name of the firmware to load to the remote processor.
fsl,dsp-ctrl:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to syscon block which provide access for processor enablement
required:
- compatible
- reg
- clocks
- clock-names
- power-domains
- mboxes
- mbox-names
- memory-region
allOf:
- if:
properties:
compatible:
contains:
enum:
- fsl,imx8qxp-dsp
- fsl,imx8qm-dsp
- fsl,imx8qxp-hifi4
- fsl,imx8qm-hifi4
then:
properties:
power-domains:
minItems: 4
else:
properties:
power-domains:
maxItems: 1
- if:
properties:
compatible:
contains:
enum:
- fsl,imx8qxp-hifi4
- fsl,imx8qm-hifi4
- fsl,imx8mp-hifi4
- fsl,imx8ulp-hifi4
then:
properties:
memory-region:
minItems: 4
mboxes:
maxItems: 3
mbox-names:
items:
- const: tx
- const: rx
- const: rxdb
else:
properties:
memory-region:
maxItems: 1
mboxes:
minItems: 4
mbox-names:
items:
- const: txdb0
- const: txdb1
- const: rxdb0
- const: rxdb1
additionalProperties: false
examples:
- |
#include <dt-bindings/firmware/imx/rsrc.h>
#include <dt-bindings/clock/imx8-clock.h>
dsp@596e8000 {
compatible = "fsl,imx8qxp-dsp";
reg = <0x596e8000 0x88000>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>,
<&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,
<&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;
clock-names = "ipg", "ocram", "core";
power-domains = <&pd IMX_SC_R_MU_13A>,
<&pd IMX_SC_R_MU_13B>,
<&pd IMX_SC_R_DSP>,
<&pd IMX_SC_R_DSP_RAM>;
mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1";
mboxes = <&lsio_mu13 2 0>, <&lsio_mu13 2 1>, <&lsio_mu13 3 0>, <&lsio_mu13 3 1>;
memory-region = <&dsp_reserved>;
};
- |
#include <dt-bindings/clock/imx8mp-clock.h>
dsp_reserved: dsp@92400000 {
reg = <0x92400000 0x1000000>;
no-map;
};
dsp_vdev0vring0: vdev0vring0@942f0000 {
reg = <0x942f0000 0x8000>;
no-map;
};
dsp_vdev0vring1: vdev0vring1@942f8000 {
reg = <0x942f8000 0x8000>;
no-map;
};
dsp_vdev0buffer: vdev0buffer@94300000 {
compatible = "shared-dma-pool";
reg = <0x94300000 0x100000>;
no-map;
};
dsp: dsp@3b6e8000 {
compatible = "fsl,imx8mp-hifi4";
reg = <0x3b6e8000 0x88000>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT>;
clock-names = "ipg", "ocram", "core", "debug";
firmware-name = "imx/dsp/hifi4.bin";
power-domains = <&audiomix_pd>;
mbox-names = "tx", "rx", "rxdb";
mboxes = <&mu2 0 0>,
<&mu2 1 0>,
<&mu2 3 0>;
memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>,
<&dsp_vdev0vring1>, <&dsp_reserved>;
fsl,dsp-ctrl = <&audio_blk_ctrl>;
};

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bindings/dsp/mediatek,mt8186-dsp.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dsp/mediatek,mt8186-dsp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek mt8186 DSP core
maintainers:
- Tinghan Shen <tinghan.shen@mediatek.com>
description: |
MediaTek mt8186 SoC contains a DSP core used for
advanced pre- and post- audio processing.
properties:
compatible:
const: mediatek,mt8186-dsp
reg:
items:
- description: Address and size of the DSP config registers
- description: Address and size of the DSP SRAM
- description: Address and size of the DSP secure registers
- description: Address and size of the DSP bus registers
reg-names:
items:
- const: cfg
- const: sram
- const: sec
- const: bus
clocks:
items:
- description: mux for audio dsp clock
- description: mux for audio dsp local bus
clock-names:
items:
- const: audiodsp
- const: adsp_bus
power-domains:
maxItems: 1
mboxes:
items:
- description: mailbox for receiving audio DSP requests.
- description: mailbox for transmitting requests to audio DSP.
mbox-names:
items:
- const: rx
- const: tx
memory-region:
items:
- description: dma buffer between host and DSP.
- description: DSP system memory.
required:
- compatible
- reg
- reg-names
- clocks
- clock-names
- power-domains
- mbox-names
- mboxes
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mt8186-clk.h>
dsp@10680000 {
compatible = "mediatek,mt8186-dsp";
reg = <0x10680000 0x2000>,
<0x10800000 0x100000>,
<0x1068b000 0x100>,
<0x1068f000 0x1000>;
reg-names = "cfg", "sram", "sec", "bus";
clocks = <&topckgen CLK_TOP_AUDIODSP>,
<&topckgen CLK_TOP_ADSP_BUS>;
clock-names = "audiodsp",
"adsp_bus";
power-domains = <&spm 6>;
mbox-names = "rx", "tx";
mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
};

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bindings/dsp/mediatek,mt8195-dsp.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dsp/mediatek,mt8195-dsp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek mt8195 DSP core
maintainers:
- YC Hung <yc.hung@mediatek.com>
description: |
Some boards from mt8195 contain a DSP core used for
advanced pre- and post- audio processing.
properties:
compatible:
const: mediatek,mt8195-dsp
reg:
items:
- description: Address and size of the DSP Cfg registers
- description: Address and size of the DSP SRAM
reg-names:
items:
- const: cfg
- const: sram
clocks:
items:
- description: mux for audio dsp clock
- description: 26M clock
- description: mux for audio dsp local bus
- description: default audio dsp local bus clock source
- description: clock gate for audio dsp clock
- description: mux for audio dsp access external bus
clock-names:
items:
- const: adsp_sel
- const: clk26m_ck
- const: audio_local_bus
- const: mainpll_d7_d2
- const: scp_adsp_audiodsp
- const: audio_h
power-domains:
maxItems: 1
mboxes:
items:
- description: mailbox for receiving audio DSP requests.
- description: mailbox for transmitting requests to audio DSP.
mbox-names:
items:
- const: rx
- const: tx
memory-region:
items:
- description: dma buffer between host and DSP.
- description: DSP system memory.
required:
- compatible
- reg
- reg-names
- clocks
- clock-names
- memory-region
- power-domains
- mbox-names
- mboxes
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
dsp@10803000 {
compatible = "mediatek,mt8195-dsp";
reg = <0x10803000 0x1000>,
<0x10840000 0x40000>;
reg-names = "cfg", "sram";
clocks = <&topckgen 10>, //CLK_TOP_ADSP
<&clk26m>,
<&topckgen 107>, //CLK_TOP_AUDIO_LOCAL_BUS
<&topckgen 136>, //CLK_TOP_MAINPLL_D7_D2
<&scp_adsp 0>, //CLK_SCP_ADSP_AUDIODSP
<&topckgen 34>; //CLK_TOP_AUDIO_H
clock-names = "adsp_sel",
"clk26m_ck",
"audio_local_bus",
"mainpll_d7_d2",
"scp_adsp_audiodsp",
"audio_h";
memory-region = <&adsp_dma_mem_reserved>,
<&adsp_mem_reserved>;
power-domains = <&spm 6>; //MT8195_POWER_DOMAIN_ADSP
mbox-names = "rx", "tx";
mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
};