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dt-bindings: Add devicetree bindings

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Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").

Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
This commit is contained in:
Melody Olvera
2023-04-03 14:38:11 -07:00
parent c334acf377
commit 6f18ce8026
4878 changed files with 424312 additions and 0 deletions
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41
bindings/display/samsung/samsung,exynos-hdmi-ddc.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/samsung/samsung,exynos-hdmi-ddc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos SoC HDMI DDC
maintainers:
- Inki Dae <inki.dae@samsung.com>
- Seung-Woo Kim <sw0312.kim@samsung.com>
- Kyungmin Park <kyungmin.park@samsung.com>
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:
oneOf:
- const: samsung,exynos4210-hdmiddc
- const: samsung,exynos5-hdmiddc
deprecated: true
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
ddc@50 {
compatible = "samsung,exynos4210-hdmiddc";
reg = <0x50>;
};
};

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bindings/display/samsung/samsung,exynos-hdmi.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/samsung/samsung,exynos-hdmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos SoC HDMI
maintainers:
- Inki Dae <inki.dae@samsung.com>
- Seung-Woo Kim <sw0312.kim@samsung.com>
- Kyungmin Park <kyungmin.park@samsung.com>
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:
enum:
- samsung,exynos4210-hdmi
- samsung,exynos4212-hdmi
- samsung,exynos5420-hdmi
- samsung,exynos5433-hdmi
clocks:
minItems: 5
maxItems: 10
clock-names:
minItems: 5
maxItems: 10
ddc:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to the HDMI DDC node.
hdmi-en-supply:
description:
Provides voltage source for DCC lines available on HDMI connector. When
there is no power provided for DDC epprom, some TV-sets do not pulls up
HPD (hot plug detect) line, what causes HDMI block to stay turned off.
When provided, the regulator allows TV-set correctly signal HPD event.
hpd-gpios:
maxItems: 1
description:
A GPIO line connected to HPD
interrupts:
maxItems: 1
phy:
$ref: /schemas/types.yaml#/definitions/phandle
description: Phandle to the HDMI PHY node.
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Contains a port which is connected to mic node.
power-domains:
maxItems: 1
reg:
maxItems: 1
samsung,syscon-phandle:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to the PMU system controller node.
samsung,sysreg-phandle:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to DISP system controller interface.
'#sound-dai-cells':
const: 0
vdd-supply:
description:
VDD 1.0V HDMI TX.
vdd_osc-supply:
description:
VDD 1.8V HDMI OSC.
vdd_pll-supply:
description:
VDD 1.0V HDMI PLL.
required:
- compatible
- clocks
- clock-names
- ddc
- hpd-gpios
- interrupts
- phy
- reg
- samsung,syscon-phandle
- '#sound-dai-cells'
- vdd-supply
- vdd_osc-supply
- vdd_pll-supply
allOf:
- if:
properties:
compatible:
contains:
const: samsung,exynos5433-hdmi
then:
properties:
clocks:
items:
- description: Gate of HDMI IP APB bus.
- description: Gate of HDMI-PHY IP APB bus.
- description: Gate of HDMI TMDS clock.
- description: Gate of HDMI pixel clock.
- description: TMDS clock generated by HDMI-PHY.
- description: MUX used to switch between oscclk and tmds_clko,
respectively if HDMI-PHY is off and operational.
- description: Pixel clock generated by HDMI-PHY.
- description: MUX used to switch between oscclk and pixel_clko,
respectively if HDMI-PHY is off and operational.
- description: Oscillator clock, used as parent of following *_user
clocks in case HDMI-PHY is not operational.
- description: Gate of HDMI SPDIF clock.
clock-names:
items:
- const: hdmi_pclk
- const: hdmi_i_pclk
- const: i_tmds_clk
- const: i_pixel_clk
- const: tmds_clko
- const: tmds_clko_user
- const: pixel_clko
- const: pixel_clko_user
- const: oscclk
- const: i_spdif_clk
required:
- samsung,sysreg-phandle
else:
properties:
clocks:
items:
- description: Gate of HDMI IP bus clock.
- description: Gate of HDMI special clock.
- description: Pixel special clock, one of the two possible inputs
of HDMI clock mux.
- description: HDMI PHY clock output, one of two possible inputs of
HDMI clock mux.
- description: It is required by the driver to switch between the 2
parents i.e. sclk_pixel and sclk_hdmiphy. If hdmiphy is stable
after configuration, parent is set to sclk_hdmiphy else
sclk_pixel.
clock-names:
items:
- const: hdmi
- const: sclk_hdmi
- const: sclk_pixel
- const: sclk_hdmiphy
- const: mout_hdmi
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/exynos5433.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
hdmi@13970000 {
compatible = "samsung,exynos5433-hdmi";
reg = <0x13970000 0x70000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_disp CLK_PCLK_HDMI>,
<&cmu_disp CLK_PCLK_HDMIPHY>,
<&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>,
<&cmu_disp CLK_PHYCLK_HDMI_PIXEL>,
<&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>,
<&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>,
<&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>,
<&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>,
<&xxti>,
<&cmu_disp CLK_SCLK_HDMI_SPDIF>;
clock-names = "hdmi_pclk",
"hdmi_i_pclk",
"i_tmds_clk",
"i_pixel_clk",
"tmds_clko",
"tmds_clko_user",
"pixel_clko",
"pixel_clko_user",
"oscclk",
"i_spdif_clk";
phy = <&hdmiphy>;
ddc = <&hsi2c_11>;
samsung,syscon-phandle = <&pmu_system_controller>;
samsung,sysreg-phandle = <&syscon_disp>;
#sound-dai-cells = <0>;
hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH>;
vdd-supply = <&ldo6_reg>;
vdd_osc-supply = <&ldo7_reg>;
vdd_pll-supply = <&ldo6_reg>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hdmi_to_tv: endpoint {
remote-endpoint = <&tv_to_hdmi>;
};
};
port@1 {
reg = <1>;
hdmi_to_mhl: endpoint {
remote-endpoint = <&mhl_to_hdmi>;
};
};
};
};

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bindings/display/samsung/samsung,exynos-mixer.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/samsung/samsung,exynos-mixer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos SoC Mixer
maintainers:
- Inki Dae <inki.dae@samsung.com>
- Seung-Woo Kim <sw0312.kim@samsung.com>
- Kyungmin Park <kyungmin.park@samsung.com>
- Krzysztof Kozlowski <krzk@kernel.org>
description:
Samsung Exynos SoC Mixer is responsible for mixing and blending multiple data
inputs before passing it to an output device. The output is passed to HDMI.
properties:
compatible:
oneOf:
- enum:
- samsung,exynos4210-mixer
- samsung,exynos4212-mixer
- samsung,exynos5250-mixer
- samsung,exynos5420-mixer
- const: samsung,exynos5-mixer
deprecated: true
clocks:
minItems: 3
items:
- description: Gate of Mixer IP bus clock.
- description: Gate of HDMI IP bus clock, needed together with sclk_hdmi.
- description: HDMI Special clock, one of the two possible inputs of
mixer mux.
- description: Video Processor clock.
- description: Mixer mux clock.
- description: Mixer Special clock.
clock-names:
minItems: 3
items:
- const: mixer
- const: hdmi
- const: sclk_hdmi
- const: vp
- const: mout_mixer
- const: sclk_mixer
interconnects:
maxItems: 1
interrupts:
maxItems: 1
iommus:
maxItems: 1
power-domains:
maxItems: 1
reg:
minItems: 1
items:
- description: Mixer memory region.
- description: Video Processor memory region.
required:
- compatible
- clocks
- clock-names
- interrupts
- reg
allOf:
- if:
properties:
compatible:
contains:
const: samsung,exynos4210-mixer
- samsung,exynos4212-mixer
then:
properties:
clocks:
minItems: 6
maxItems: 6
regs:
minItems: 2
maxItems: 2
- if:
properties:
compatible:
contains:
const: samsung,exynos4212-mixer
then:
properties:
clocks:
minItems: 4
maxItems: 4
regs:
minItems: 2
maxItems: 2
- if:
properties:
compatible:
contains:
enum:
- samsung,exynos5-mixer
- samsung,exynos5250-mixer
- samsung,exynos5420-mixer
then:
properties:
clocks:
minItems: 3
maxItems: 3
regs:
minItems: 1
maxItems: 1
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/exynos5250.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
mixer@14450000 {
compatible = "samsung,exynos5250-mixer";
reg = <0x14450000 0x10000>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MIXER>,
<&clock CLK_HDMI>,
<&clock CLK_SCLK_HDMI>;
clock-names = "mixer",
"hdmi",
"sclk_hdmi";
iommus = <&sysmmu_tv>;
power-domains = <&pd_disp1>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/samsung/samsung,exynos5433-decon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos5433 SoC Display and Enhancement Controller (DECON)
maintainers:
- Inki Dae <inki.dae@samsung.com>
- Seung-Woo Kim <sw0312.kim@samsung.com>
- Kyungmin Park <kyungmin.park@samsung.com>
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
DECON (Display and Enhancement Controller) is the Display Controller for the
Exynos5433 series of SoCs which transfers the image data from a video memory
buffer to an external LCD interface.
properties:
compatible:
enum:
- samsung,exynos5433-decon
- samsung,exynos5433-decon-tv
clocks:
maxItems: 11
clock-names:
items:
- const: pclk
- const: aclk_decon
- const: aclk_smmu_decon0x
- const: aclk_xiu_decon0x
- const: pclk_smmu_decon0x
- const: aclk_smmu_decon1x
- const: aclk_xiu_decon1x
- const: pclk_smmu_decon1x
- const: sclk_decon_vclk
- const: sclk_decon_eclk
- const: dsd
interrupts:
minItems: 3
maxItems: 4
description: |
Interrupts depend on mode of work:
- video mode: vsync
- command mode: lcd_sys
- command mode with software trigger: lcd_sys, te
interrupt-names:
minItems: 3
items:
- const: fifo
- const: vsync
- const: lcd_sys
- const: te
iommus:
maxItems: 2
iommu-names:
items:
- const: m0
- const: m1
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Contains a port which is connected to mic node.
power-domains:
maxItems: 1
reg:
maxItems: 1
samsung,disp-sysreg:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to DISP system controller interface.
required:
- compatible
- clocks
- clock-names
- interrupts
- interrupt-names
- ports
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/exynos5433.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
display-controller@13800000 {
compatible = "samsung,exynos5433-decon";
reg = <0x13800000 0x2104>;
clocks = <&cmu_disp CLK_PCLK_DECON>,
<&cmu_disp CLK_ACLK_DECON>,
<&cmu_disp CLK_ACLK_SMMU_DECON0X>,
<&cmu_disp CLK_ACLK_XIU_DECON0X>,
<&cmu_disp CLK_PCLK_SMMU_DECON0X>,
<&cmu_disp CLK_ACLK_SMMU_DECON1X>,
<&cmu_disp CLK_ACLK_XIU_DECON1X>,
<&cmu_disp CLK_PCLK_SMMU_DECON1X>,
<&cmu_disp CLK_SCLK_DECON_VCLK>,
<&cmu_disp CLK_SCLK_DECON_ECLK>,
<&cmu_disp CLK_SCLK_DSD>;
clock-names = "pclk",
"aclk_decon",
"aclk_smmu_decon0x",
"aclk_xiu_decon0x",
"pclk_smmu_decon0x",
"aclk_smmu_decon1x",
"aclk_xiu_decon1x",
"pclk_smmu_decon1x",
"sclk_decon_vclk",
"sclk_decon_eclk",
"dsd";
power-domains = <&pd_disp>;
interrupt-names = "fifo", "vsync", "lcd_sys";
interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
samsung,disp-sysreg = <&syscon_disp>;
iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>;
iommu-names = "m0", "m1";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
decon_to_mic: endpoint {
remote-endpoint = <&mic_to_decon>;
};
};
};
};

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bindings/display/samsung/samsung,exynos5433-mic.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/samsung/samsung,exynos5433-mic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos5433 SoC Mobile Image Compressor (MIC)
maintainers:
- Inki Dae <inki.dae@samsung.com>
- Seung-Woo Kim <sw0312.kim@samsung.com>
- Kyungmin Park <kyungmin.park@samsung.com>
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
MIC (Mobile Image Compressor) resides between DECON and MIPI DSI. MIPI DSI is
not capable of transferring high resoltuion frame data as DECON can send. MIC
solves this problem by compressing the frame data by 1/2 before it is
transferred through MIPI DSI. The compressed frame data must be uncompressed
in the panel PCB.
properties:
compatible:
const: samsung,exynos5433-mic
clocks:
maxItems: 2
clock-names:
items:
- const: pclk_mic0
- const: sclk_rgb_vclk_to_mic0
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Contains a port which is connected to mic node.
power-domains:
maxItems: 1
reg:
maxItems: 1
samsung,disp-syscon:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to DISP system controller interface.
required:
- compatible
- clocks
- clock-names
- ports
- reg
- samsung,disp-syscon
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/exynos5433.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
image-processor@13930000 {
compatible = "samsung,exynos5433-mic";
reg = <0x13930000 0x48>;
clocks = <&cmu_disp CLK_PCLK_MIC0>,
<&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>;
clock-names = "pclk_mic0",
"sclk_rgb_vclk_to_mic0";
power-domains = <&pd_disp>;
samsung,disp-syscon = <&syscon_disp>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mic_to_decon: endpoint {
remote-endpoint = <&decon_to_mic>;
};
};
port@1 {
reg = <1>;
mic_to_dsi: endpoint {
remote-endpoint = <&dsi_to_mic>;
};
};
};
};

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bindings/display/samsung/samsung,exynos7-decon.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/samsung/samsung,exynos7-decon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos7 SoC Display and Enhancement Controller (DECON)
maintainers:
- Inki Dae <inki.dae@samsung.com>
- Seung-Woo Kim <sw0312.kim@samsung.com>
- Kyungmin Park <kyungmin.park@samsung.com>
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
DECON (Display and Enhancement Controller) is the Display Controller for the
Exynos7 series of SoCs which transfers the image data from a video memory
buffer to an external LCD interface.
properties:
compatible:
const: samsung,exynos7-decon
clocks:
maxItems: 4
clock-names:
items:
- const: pclk_decon0
- const: aclk_decon0
- const: decon0_eclk
- const: decon0_vclk
display-timings:
$ref: ../panel/display-timings.yaml#
i80-if-timings:
type: object
additionalProperties: false
description: timing configuration for lcd i80 interface support
properties:
cs-setup:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Clock cycles for the active period of address signal is enabled until
chip select is enabled.
default: 0
wr-active:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Clock cycles for the active period of CS is enabled.
default: 1
wr-hold:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Clock cycles for the active period of CS is disabled until write
signal is disabled.
default: 0
wr-setup:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Clock cycles for the active period of CS signal is enabled until
write signal is enabled.
default: 0
interrupts:
items:
- description: FIFO level
- description: VSYNC
- description: LCD system
interrupt-names:
items:
- const: fifo
- const: vsync
- const: lcd_sys
power-domains:
maxItems: 1
reg:
maxItems: 1
required:
- compatible
- clocks
- clock-names
- interrupts
- interrupt-names
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/exynos7-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
display-controller@13930000 {
compatible = "samsung,exynos7-decon";
reg = <0x13930000 0x1000>;
interrupt-names = "fifo", "vsync", "lcd_sys";
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_disp 100>, /* PCLK_DECON_INT */
<&clock_disp 101>, /* ACLK_DECON_INT */
<&clock_disp 102>, /* SCLK_DECON_INT_ECLK */
<&clock_disp 103>; /* SCLK_DECON_INT_EXTCLKPLL */
clock-names = "pclk_decon0",
"aclk_decon0",
"decon0_eclk",
"decon0_vclk";
pinctrl-0 = <&lcd_clk &pwm1_out>;
pinctrl-names = "default";
};

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# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/samsung/samsung,fimd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung S3C/S5P/Exynos SoC Fully Interactive Mobile Display (FIMD)
maintainers:
- Inki Dae <inki.dae@samsung.com>
- Seung-Woo Kim <sw0312.kim@samsung.com>
- Kyungmin Park <kyungmin.park@samsung.com>
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:
enum:
- samsung,s3c2443-fimd
- samsung,s3c6400-fimd
- samsung,s5pv210-fimd
- samsung,exynos3250-fimd
- samsung,exynos4210-fimd
- samsung,exynos5250-fimd
- samsung,exynos5420-fimd
'#address-cells':
const: 1
clocks:
maxItems: 2
clock-names:
items:
- const: sclk_fimd
- const: fimd
display-timings:
$ref: ../panel/display-timings.yaml#
i80-if-timings:
type: object
additionalProperties: false
description: |
Timing configuration for lcd i80 interface support.
The parameters are defined as::
VCLK(internal) __|??????|_____|??????|_____|??????|_____|??????|_____|??
: : : : :
Address Output --:<XXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XX
| cs-setup+1 | : : :
|<---------->| : : :
Chip Select ???????????????|____________:____________:____________|??
| wr-setup+1 | | wr-hold+1 |
|<---------->| |<---------->|
Write Enable ????????????????????????????|____________|???????????????
| wr-active+1|
|<---------->|
Video Data ----------------------------<XXXXXXXXXXXXXXXXXXXXXXXXX>--
properties:
cs-setup:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Clock cycles for the active period of address signal is enabled until
chip select is enabled.
default: 0
wr-active:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Clock cycles for the active period of CS is enabled.
default: 1
wr-hold:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Clock cycles for the active period of CS is disabled until write
signal is disabled.
default: 0
wr-setup:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Clock cycles for the active period of CS signal is enabled until
write signal is enabled.
default: 0
iommus:
minItems: 1
maxItems: 2
iommu-names:
items:
- const: m0
- const: m1
interrupts:
items:
- description: FIFO level
- description: VSYNC
- description: LCD system
interrupt-names:
items:
- const: fifo
- const: vsync
- const: lcd_sys
power-domains:
maxItems: 1
reg:
maxItems: 1
samsung,invert-vden:
type: boolean
description:
Video enable signal is inverted.
samsung,invert-vclk:
type: boolean
description:
Video clock signal is inverted.
samsung,sysreg:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to System Register syscon.
'#size-cells':
const: 0
patternProperties:
"^port@[0-4]+$":
$ref: /schemas/graph.yaml#/properties/port
description: |
Contains ports with port with index::
0 - for CAMIF0 input,
1 - for CAMIF1 input,
2 - for CAMIF2 input,
3 - for parallel output,
4 - for write-back interface
required:
- compatible
- clocks
- clock-names
- interrupts
- interrupt-names
- reg
allOf:
- if:
properties:
compatible:
contains:
const: samsung,exynos5420-fimd
then:
properties:
iommus:
minItems: 2
maxItems: 2
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/exynos4.h>
fimd@11c00000 {
compatible = "samsung,exynos4210-fimd";
interrupt-parent = <&combiner>;
reg = <0x11c00000 0x20000>;
interrupt-names = "fifo", "vsync", "lcd_sys";
interrupts = <11 0>, <11 1>, <11 2>;
clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
clock-names = "sclk_fimd", "fimd";
power-domains = <&pd_lcd0>;
iommus = <&sysmmu_fimd0>;
samsung,sysreg = <&sys_reg>;
#address-cells = <1>;
#size-cells = <0>;
samsung,invert-vden;
samsung,invert-vclk;
pinctrl-0 = <&lcd_clk>, <&lcd_data24>;
pinctrl-names = "default";
port@3 {
reg = <3>;
fimd_dpi_ep: endpoint {
remote-endpoint = <&lcd_ep>;
};
};
};