dt-bindings: Add devicetree bindings
Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").
Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
This commit is contained in:
Melody Olvera
95
bindings/crypto/allwinner,sun4i-a10-crypto.yaml
Normal file
95
bindings/crypto/allwinner,sun4i-a10-crypto.yaml
Normal file
@@ -0,0 +1,95 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/crypto/allwinner,sun4i-a10-crypto.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Allwinner A10 Security System
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maintainers:
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- Chen-Yu Tsai <wens@csie.org>
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- Maxime Ripard <mripard@kernel.org>
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properties:
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compatible:
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oneOf:
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- const: allwinner,sun4i-a10-crypto
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- items:
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- const: allwinner,sun5i-a13-crypto
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- const: allwinner,sun4i-a10-crypto
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- items:
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- const: allwinner,sun6i-a31-crypto
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- const: allwinner,sun4i-a10-crypto
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- items:
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- const: allwinner,sun7i-a20-crypto
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- const: allwinner,sun4i-a10-crypto
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- const: allwinner,sun8i-a33-crypto
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- items:
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- const: allwinner,sun8i-v3s-crypto
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- const: allwinner,sun8i-a33-crypto
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: Bus Clock
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- description: Module Clock
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clock-names:
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items:
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- const: ahb
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- const: mod
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dmas:
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items:
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- description: RX DMA Channel
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- description: TX DMA Channel
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dma-names:
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items:
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- const: rx
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- const: tx
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resets:
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maxItems: 1
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reset-names:
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const: ahb
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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if:
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properties:
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compatible:
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contains:
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enum:
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- allwinner,sun6i-a31-crypto
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- allwinner,sun8i-a33-crypto
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then:
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required:
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- resets
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- reset-names
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additionalProperties: false
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examples:
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- |
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crypto: crypto-engine@1c15000 {
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compatible = "allwinner,sun4i-a10-crypto";
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reg = <0x01c15000 0x1000>;
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interrupts = <86>;
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clocks = <&ahb_gates 5>, <&ss_clk>;
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clock-names = "ahb", "mod";
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};
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...
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84
bindings/crypto/allwinner,sun8i-ce.yaml
Normal file
84
bindings/crypto/allwinner,sun8i-ce.yaml
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@@ -0,0 +1,84 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/crypto/allwinner,sun8i-ce.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Allwinner Crypto Engine driver
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maintainers:
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- Corentin Labbe <clabbe.montjoie@gmail.com>
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properties:
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compatible:
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enum:
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- allwinner,sun8i-h3-crypto
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- allwinner,sun8i-r40-crypto
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- allwinner,sun50i-a64-crypto
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- allwinner,sun50i-h5-crypto
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- allwinner,sun50i-h6-crypto
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: Bus clock
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- description: Module clock
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- description: MBus clock
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minItems: 2
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clock-names:
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items:
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- const: bus
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- const: mod
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- const: ram
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minItems: 2
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resets:
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maxItems: 1
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if:
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properties:
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compatible:
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const: allwinner,sun50i-h6-crypto
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then:
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properties:
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clocks:
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minItems: 3
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clock-names:
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minItems: 3
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else:
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properties:
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clocks:
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maxItems: 2
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clock-names:
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maxItems: 2
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- resets
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/sun50i-a64-ccu.h>
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#include <dt-bindings/reset/sun50i-a64-ccu.h>
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crypto: crypto@1c15000 {
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compatible = "allwinner,sun8i-h3-crypto";
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reg = <0x01c15000 0x1000>;
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interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
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clock-names = "bus", "mod";
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resets = <&ccu RST_BUS_CE>;
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};
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60
bindings/crypto/allwinner,sun8i-ss.yaml
Normal file
60
bindings/crypto/allwinner,sun8i-ss.yaml
Normal file
@@ -0,0 +1,60 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/crypto/allwinner,sun8i-ss.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Allwinner Security System v2 driver
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maintainers:
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- Corentin Labbe <corentin.labbe@gmail.com>
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properties:
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compatible:
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enum:
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- allwinner,sun8i-a83t-crypto
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- allwinner,sun9i-a80-crypto
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: Bus clock
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- description: Module clock
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clock-names:
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items:
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- const: bus
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- const: mod
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resets:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- resets
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/sun8i-a83t-ccu.h>
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#include <dt-bindings/reset/sun8i-a83t-ccu.h>
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crypto: crypto@1c15000 {
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compatible = "allwinner,sun8i-a83t-crypto";
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reg = <0x01c15000 0x1000>;
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interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&ccu RST_BUS_SS>;
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clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
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clock-names = "bus", "mod";
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};
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17
bindings/crypto/amd-ccp.txt
Normal file
17
bindings/crypto/amd-ccp.txt
Normal file
@@ -0,0 +1,17 @@
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* AMD Cryptographic Coprocessor driver (ccp)
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Required properties:
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- compatible: Should be "amd,ccp-seattle-v1a"
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- reg: Address and length of the register set for the device
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- interrupts: Should contain the CCP interrupt
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Optional properties:
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- dma-coherent: Present if dma operations are coherent
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Example:
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ccp@e0100000 {
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compatible = "amd,ccp-seattle-v1a";
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reg = <0 0xe0100000 0 0x10000>;
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interrupt-parent = <&gic>;
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interrupts = <0 3 4>;
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};
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52
bindings/crypto/amlogic,gxl-crypto.yaml
Normal file
52
bindings/crypto/amlogic,gxl-crypto.yaml
Normal file
@@ -0,0 +1,52 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/crypto/amlogic,gxl-crypto.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Amlogic GXL Cryptographic Offloader
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maintainers:
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- Corentin Labbe <clabbe@baylibre.com>
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properties:
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compatible:
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items:
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- const: amlogic,gxl-crypto
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reg:
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maxItems: 1
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interrupts:
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items:
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- description: "Interrupt for flow 0"
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- description: "Interrupt for flow 1"
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clocks:
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maxItems: 1
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clock-names:
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const: blkmv
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/gxbb-clkc.h>
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crypto: crypto-engine@c883e000 {
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compatible = "amlogic,gxl-crypto";
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reg = <0xc883e000 0x36>;
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interrupts = <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
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clocks = <&clkc CLKID_BLKMV>;
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clock-names = "blkmv";
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};
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53
bindings/crypto/arm,cryptocell.yaml
Normal file
53
bindings/crypto/arm,cryptocell.yaml
Normal file
@@ -0,0 +1,53 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/crypto/arm,cryptocell.yaml#
|
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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|
||||
title: Arm TrustZone CryptoCell cryptographic engine
|
||||
|
||||
maintainers:
|
||||
- Gilad Ben-Yossef <gilad@benyossef.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- arm,cryptocell-713-ree
|
||||
- arm,cryptocell-703-ree
|
||||
- arm,cryptocell-712-ree
|
||||
- arm,cryptocell-710-ree
|
||||
- arm,cryptocell-630p-ree
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
arm_cc712: crypto@80000000 {
|
||||
compatible = "arm,cryptocell-712-ree";
|
||||
reg = <0x80000000 0x10000>;
|
||||
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
16
bindings/crypto/artpec6-crypto.txt
Normal file
16
bindings/crypto/artpec6-crypto.txt
Normal file
@@ -0,0 +1,16 @@
|
||||
Axis crypto engine with PDMA interface.
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be one of the following strings:
|
||||
"axis,artpec6-crypto" for the version in the Axis ARTPEC-6 SoC
|
||||
"axis,artpec7-crypto" for the version in the Axis ARTPEC-7 SoC.
|
||||
- reg: Base address and size for the PDMA register area.
|
||||
- interrupts: Interrupt handle for the PDMA interrupt line.
|
||||
|
||||
Example:
|
||||
|
||||
crypto@f4264000 {
|
||||
compatible = "axis,artpec6-crypto";
|
||||
reg = <0xf4264000 0x1000>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
53
bindings/crypto/aspeed,ast2500-hace.yaml
Normal file
53
bindings/crypto/aspeed,ast2500-hace.yaml
Normal file
@@ -0,0 +1,53 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/aspeed,ast2500-hace.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ASPEED HACE hash and crypto Hardware Accelerator Engines
|
||||
|
||||
maintainers:
|
||||
- Neal Liu <neal_liu@aspeedtech.com>
|
||||
|
||||
description: |
|
||||
The Hash and Crypto Engine (HACE) is designed to accelerate the throughput
|
||||
of hash data digest, encryption, and decryption. Basically, HACE can be
|
||||
divided into two independently engines - Hash Engine and Crypto Engine.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- aspeed,ast2500-hace
|
||||
- aspeed,ast2600-hace
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- interrupts
|
||||
- resets
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/ast2600-clock.h>
|
||||
hace: crypto@1e6d0000 {
|
||||
compatible = "aspeed,ast2600-hace";
|
||||
reg = <0x1e6d0000 0x200>;
|
||||
interrupts = <4>;
|
||||
clocks = <&syscon ASPEED_CLK_GATE_YCLK>;
|
||||
resets = <&syscon ASPEED_RESET_HACE>;
|
||||
};
|
||||
66
bindings/crypto/atmel,at91sam9g46-aes.yaml
Normal file
66
bindings/crypto/atmel,at91sam9g46-aes.yaml
Normal file
@@ -0,0 +1,66 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/atmel,at91sam9g46-aes.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Atmel Advanced Encryption Standard (AES) HW cryptographic accelerator
|
||||
|
||||
maintainers:
|
||||
- Tudor Ambarus <tudor.ambarus@microchip.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: atmel,at91sam9g46-aes
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: aes_clk
|
||||
|
||||
dmas:
|
||||
items:
|
||||
- description: TX DMA Channel
|
||||
- description: RX DMA Channel
|
||||
|
||||
dma-names:
|
||||
items:
|
||||
- const: tx
|
||||
- const: rx
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- dmas
|
||||
- dma-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/at91.h>
|
||||
#include <dt-bindings/dma/at91.h>
|
||||
|
||||
aes: crypto@e1810000 {
|
||||
compatible = "atmel,at91sam9g46-aes";
|
||||
reg = <0xe1810000 0x100>;
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
|
||||
clock-names = "aes_clk";
|
||||
dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>,
|
||||
<&dma0 AT91_XDMAC_DT_PERID(2)>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
60
bindings/crypto/atmel,at91sam9g46-sha.yaml
Normal file
60
bindings/crypto/atmel,at91sam9g46-sha.yaml
Normal file
@@ -0,0 +1,60 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/atmel,at91sam9g46-sha.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Atmel Secure Hash Algorithm (SHA) HW cryptographic accelerator
|
||||
|
||||
maintainers:
|
||||
- Tudor Ambarus <tudor.ambarus@microchip.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: atmel,at91sam9g46-sha
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: sha_clk
|
||||
|
||||
dmas:
|
||||
maxItems: 1
|
||||
description: TX DMA Channel
|
||||
|
||||
dma-names:
|
||||
const: tx
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/at91.h>
|
||||
#include <dt-bindings/dma/at91.h>
|
||||
|
||||
sha: crypto@e1814000 {
|
||||
compatible = "atmel,at91sam9g46-sha";
|
||||
reg = <0xe1814000 0x100>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 83>;
|
||||
clock-names = "sha_clk";
|
||||
dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>;
|
||||
dma-names = "tx";
|
||||
};
|
||||
64
bindings/crypto/atmel,at91sam9g46-tdes.yaml
Normal file
64
bindings/crypto/atmel,at91sam9g46-tdes.yaml
Normal file
@@ -0,0 +1,64 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/atmel,at91sam9g46-tdes.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Atmel Triple Data Encryption Standard (TDES) HW cryptographic accelerator
|
||||
|
||||
maintainers:
|
||||
- Tudor Ambarus <tudor.ambarus@microchip.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: atmel,at91sam9g46-tdes
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: tdes_clk
|
||||
|
||||
dmas:
|
||||
items:
|
||||
- description: TX DMA Channel
|
||||
- description: RX DMA Channel
|
||||
|
||||
dma-names:
|
||||
items:
|
||||
- const: tx
|
||||
- const: rx
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/at91.h>
|
||||
#include <dt-bindings/dma/at91.h>
|
||||
|
||||
tdes: crypto@e2014000 {
|
||||
compatible = "atmel,at91sam9g46-tdes";
|
||||
reg = <0xe2014000 0x100>;
|
||||
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 96>;
|
||||
clock-names = "tdes_clk";
|
||||
dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>,
|
||||
<&dma0 AT91_XDMAC_DT_PERID(53)>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
22
bindings/crypto/brcm,spu-crypto.txt
Normal file
22
bindings/crypto/brcm,spu-crypto.txt
Normal file
@@ -0,0 +1,22 @@
|
||||
The Broadcom Secure Processing Unit (SPU) hardware supports symmetric
|
||||
cryptographic offload for Broadcom SoCs. A SoC may have multiple SPU hardware
|
||||
blocks.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be one of the following:
|
||||
brcm,spum-crypto - for devices with SPU-M hardware
|
||||
brcm,spu2-crypto - for devices with SPU2 hardware
|
||||
brcm,spu2-v2-crypto - for devices with enhanced SPU2 hardware features like SHA3
|
||||
and Rabin Fingerprint support
|
||||
brcm,spum-nsp-crypto - for the Northstar Plus variant of the SPU-M hardware
|
||||
|
||||
- reg: Should contain SPU registers location and length.
|
||||
- mboxes: The mailbox channel to be used to communicate with the SPU.
|
||||
Mailbox channels correspond to DMA rings on the device.
|
||||
|
||||
Example:
|
||||
crypto@612d0000 {
|
||||
compatible = "brcm,spum-crypto";
|
||||
reg = <0 0x612d0000 0 0x900>;
|
||||
mboxes = <&pdc0 0>;
|
||||
};
|
||||
50
bindings/crypto/cortina,sl3516-crypto.yaml
Normal file
50
bindings/crypto/cortina,sl3516-crypto.yaml
Normal file
@@ -0,0 +1,50 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/cortina,sl3516-crypto.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: SL3516 cryptographic offloader driver
|
||||
|
||||
maintainers:
|
||||
- Corentin Labbe <clabbe@baylibre.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- cortina,sl3516-crypto
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- resets
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/clock/cortina,gemini-clock.h>
|
||||
#include <dt-bindings/reset/cortina,gemini-reset.h>
|
||||
|
||||
crypto@62000000 {
|
||||
compatible = "cortina,sl3516-crypto";
|
||||
reg = <0x62000000 0x10000>;
|
||||
interrupts = <7 IRQ_TYPE_EDGE_RISING>;
|
||||
resets = <&syscon GEMINI_RESET_SECURITY>;
|
||||
clocks = <&syscon GEMINI_CLK_GATE_SECURITY>;
|
||||
};
|
||||
50
bindings/crypto/fsl-dcp.yaml
Normal file
50
bindings/crypto/fsl-dcp.yaml
Normal file
@@ -0,0 +1,50 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/fsl-dcp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale DCP (Data Co-Processor) found on i.MX23/i.MX28
|
||||
|
||||
maintainers:
|
||||
- Marek Vasut <marex@denx.de>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- fsl,imx23-dcp
|
||||
- fsl,imx28-dcp
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
description: Should contain MXS DCP interrupt numbers, VMI IRQ and DCP IRQ
|
||||
must be supplied, optionally Secure IRQ can be present, but is currently
|
||||
not implemented and not used.
|
||||
items:
|
||||
- description: MXS DCP VMI interrupt
|
||||
- description: MXS DCP DCP interrupt
|
||||
- description: MXS DCP secure interrupt
|
||||
minItems: 2
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: dcp
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
crypto@80028000 {
|
||||
compatible = "fsl,imx23-dcp";
|
||||
reg = <0x80028000 0x2000>;
|
||||
interrupts = <53>, <54>;
|
||||
};
|
||||
37
bindings/crypto/fsl-imx-sahara.yaml
Normal file
37
bindings/crypto/fsl-imx-sahara.yaml
Normal file
@@ -0,0 +1,37 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/fsl-imx-sahara.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale SAHARA Cryptographic Accelerator included in some i.MX chips
|
||||
|
||||
maintainers:
|
||||
- Steffen Trumtrar <s.trumtrar@pengutronix.de>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- fsl,imx27-sahara
|
||||
- fsl,imx53-sahara
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
crypto@10025000 {
|
||||
compatible = "fsl,imx27-sahara";
|
||||
reg = < 0x10025000 0x800>;
|
||||
interrupts = <75>;
|
||||
};
|
||||
54
bindings/crypto/fsl-imx-scc.yaml
Normal file
54
bindings/crypto/fsl-imx-scc.yaml
Normal file
@@ -0,0 +1,54 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/fsl-imx-scc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale Security Controller (SCC)
|
||||
|
||||
maintainers:
|
||||
- Steffen Trumtrar <s.trumtrar@pengutronix.de>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx25-scc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: SCC SCM interrupt
|
||||
- description: SCC SMN interrupt
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: scm
|
||||
- const: smn
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: ipg
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
crypto@53fac000 {
|
||||
compatible = "fsl,imx25-scc";
|
||||
reg = <0x53fac000 0x4000>;
|
||||
clocks = <&clks 111>;
|
||||
clock-names = "ipg";
|
||||
interrupts = <49>, <50>;
|
||||
interrupt-names = "scm", "smn";
|
||||
};
|
||||
65
bindings/crypto/fsl-sec2.txt
Normal file
65
bindings/crypto/fsl-sec2.txt
Normal file
@@ -0,0 +1,65 @@
|
||||
Freescale SoC SEC Security Engines versions 1.x-2.x-3.x
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : Should contain entries for this and backward compatible
|
||||
SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0" (SEC2/3)
|
||||
e.g., "fsl,sec1.2", "fsl,sec1.0" (SEC1)
|
||||
warning: SEC1 and SEC2 are mutually exclusive
|
||||
- reg : Offset and length of the register set for the device
|
||||
- interrupts : the SEC's interrupt number
|
||||
- fsl,num-channels : An integer representing the number of channels
|
||||
available.
|
||||
- fsl,channel-fifo-len : An integer representing the number of
|
||||
descriptor pointers each channel fetch fifo can hold.
|
||||
- fsl,exec-units-mask : The bitmask representing what execution units
|
||||
(EUs) are available. It's a single 32-bit cell. EU information
|
||||
should be encoded following the SEC's Descriptor Header Dword
|
||||
EU_SEL0 field documentation, i.e. as follows:
|
||||
|
||||
bit 0 = reserved - should be 0
|
||||
bit 1 = set if SEC has the ARC4 EU (AFEU)
|
||||
bit 2 = set if SEC has the DES/3DES EU (DEU)
|
||||
bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A)
|
||||
bit 4 = set if SEC has the random number generator EU (RNG)
|
||||
bit 5 = set if SEC has the public key EU (PKEU)
|
||||
bit 6 = set if SEC has the AES EU (AESU)
|
||||
bit 7 = set if SEC has the Kasumi EU (KEU)
|
||||
bit 8 = set if SEC has the CRC EU (CRCU)
|
||||
bit 11 = set if SEC has the message digest EU extended alg set (MDEU-B)
|
||||
|
||||
remaining bits are reserved for future SEC EUs.
|
||||
|
||||
- fsl,descriptor-types-mask : The bitmask representing what descriptors
|
||||
are available. It's a single 32-bit cell. Descriptor type information
|
||||
should be encoded following the SEC's Descriptor Header Dword DESC_TYPE
|
||||
field documentation, i.e. as follows:
|
||||
|
||||
bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type
|
||||
bit 1 = set if SEC supports the ipsec_esp descriptor type
|
||||
bit 2 = set if SEC supports the common_nonsnoop desc. type
|
||||
bit 3 = set if SEC supports the 802.11i AES ccmp desc. type
|
||||
bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type
|
||||
bit 5 = set if SEC supports the srtp descriptor type
|
||||
bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type
|
||||
bit 7 = set if SEC supports the pkeu_assemble descriptor type
|
||||
bit 8 = set if SEC supports the aesu_key_expand_output desc.type
|
||||
bit 9 = set if SEC supports the pkeu_ptmul descriptor type
|
||||
bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type
|
||||
bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type
|
||||
|
||||
..and so on and so forth.
|
||||
|
||||
Example:
|
||||
|
||||
/* MPC8548E */
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <29 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0xfe>;
|
||||
fsl,descriptor-types-mask = <0x12b0ebf>;
|
||||
};
|
||||
553
bindings/crypto/fsl-sec4.txt
Normal file
553
bindings/crypto/fsl-sec4.txt
Normal file
@@ -0,0 +1,553 @@
|
||||
=====================================================================
|
||||
SEC 4 Device Tree Binding
|
||||
Copyright (C) 2008-2011 Freescale Semiconductor Inc.
|
||||
|
||||
CONTENTS
|
||||
-Overview
|
||||
-SEC 4 Node
|
||||
-Job Ring Node
|
||||
-Run Time Integrity Check (RTIC) Node
|
||||
-Run Time Integrity Check (RTIC) Memory Node
|
||||
-Secure Non-Volatile Storage (SNVS) Node
|
||||
-Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
|
||||
-Full Example
|
||||
|
||||
NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
|
||||
Accelerator and Assurance Module (CAAM).
|
||||
|
||||
=====================================================================
|
||||
Overview
|
||||
|
||||
DESCRIPTION
|
||||
|
||||
SEC 4 h/w can process requests from 2 types of sources.
|
||||
1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
|
||||
2. Job Rings (HW interface between cores & SEC 4 registers).
|
||||
|
||||
High Speed Data Path Configuration:
|
||||
|
||||
HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
|
||||
such as the P4080. The number of simultaneous dequeues the QI can make is
|
||||
equal to the number of Descriptor Controller (DECO) engines in a particular
|
||||
SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
|
||||
dequeue from 5 subportals simultaneously.
|
||||
|
||||
Job Ring Data Path Configuration:
|
||||
|
||||
Each JR is located on a separate 4k page, they may (or may not) be made visible
|
||||
in the memory partition devoted to a particular core. The P4080 has 4 JRs, so
|
||||
up to 4 JRs can be configured; and all 4 JRs process requests in parallel.
|
||||
|
||||
=====================================================================
|
||||
SEC 4 Node
|
||||
|
||||
Description
|
||||
|
||||
Node defines the base address of the SEC 4 block.
|
||||
This block specifies the address range of all global
|
||||
configuration registers for the SEC 4 block. It
|
||||
also receives interrupts from the Run Time Integrity Check
|
||||
(RTIC) function within the SEC 4 block.
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Must include "fsl,sec-v4.0"
|
||||
|
||||
- fsl,sec-era
|
||||
Usage: optional
|
||||
Value type: <u32>
|
||||
Definition: A standard property. Define the 'ERA' of the SEC
|
||||
device.
|
||||
|
||||
- #address-cells
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: A standard property. Defines the number of cells
|
||||
for representing physical addresses in child nodes.
|
||||
|
||||
- #size-cells
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: A standard property. Defines the number of cells
|
||||
for representing the size of physical addresses in
|
||||
child nodes.
|
||||
|
||||
- reg
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: A standard property. Specifies the physical
|
||||
address and length of the SEC4 configuration registers.
|
||||
registers
|
||||
|
||||
- ranges
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: A standard property. Specifies the physical address
|
||||
range of the SEC 4.0 register space (-SNVS not included). A
|
||||
triplet that includes the child address, parent address, &
|
||||
length.
|
||||
|
||||
- interrupts
|
||||
Usage: required
|
||||
Value type: <prop_encoded-array>
|
||||
Definition: Specifies the interrupts generated by this
|
||||
device. The value of the interrupts property
|
||||
consists of one interrupt specifier. The format
|
||||
of the specifier is defined by the binding document
|
||||
describing the node's interrupt parent.
|
||||
|
||||
- clocks
|
||||
Usage: required if SEC 4.0 requires explicit enablement of clocks
|
||||
Value type: <prop_encoded-array>
|
||||
Definition: A list of phandle and clock specifier pairs describing
|
||||
the clocks required for enabling and disabling SEC 4.0.
|
||||
|
||||
- clock-names
|
||||
Usage: required if SEC 4.0 requires explicit enablement of clocks
|
||||
Value type: <string>
|
||||
Definition: A list of clock name strings in the same order as the
|
||||
clocks property.
|
||||
|
||||
Note: All other standard properties (see the Devicetree Specification)
|
||||
are allowed but are optional.
|
||||
|
||||
|
||||
EXAMPLE
|
||||
|
||||
iMX6QDL/SX requires four clocks
|
||||
|
||||
crypto@300000 {
|
||||
compatible = "fsl,sec-v4.0";
|
||||
fsl,sec-era = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x300000 0x10000>;
|
||||
ranges = <0 0x300000 0x10000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <92 2>;
|
||||
clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
|
||||
<&clks IMX6QDL_CLK_CAAM_ACLK>,
|
||||
<&clks IMX6QDL_CLK_CAAM_IPG>,
|
||||
<&clks IMX6QDL_CLK_EIM_SLOW>;
|
||||
clock-names = "mem", "aclk", "ipg", "emi_slow";
|
||||
};
|
||||
|
||||
|
||||
iMX6UL does only require three clocks
|
||||
|
||||
crypto: crypto@2140000 {
|
||||
compatible = "fsl,sec-v4.0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x2140000 0x3c000>;
|
||||
ranges = <0 0x2140000 0x3c000>;
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&clks IMX6UL_CLK_CAAM_MEM>,
|
||||
<&clks IMX6UL_CLK_CAAM_ACLK>,
|
||||
<&clks IMX6UL_CLK_CAAM_IPG>;
|
||||
clock-names = "mem", "aclk", "ipg";
|
||||
};
|
||||
|
||||
=====================================================================
|
||||
Job Ring (JR) Node
|
||||
|
||||
Child of the crypto node defines data processing interface to SEC 4
|
||||
across the peripheral bus for purposes of processing
|
||||
cryptographic descriptors. The specified address
|
||||
range can be made visible to one (or more) cores.
|
||||
The interrupt defined for this node is controlled within
|
||||
the address range of this node.
|
||||
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Must include "fsl,sec-v4.0-job-ring"
|
||||
|
||||
- reg
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: Specifies a two JR parameters: an offset from
|
||||
the parent physical address and the length the JR registers.
|
||||
|
||||
- fsl,liodn
|
||||
Usage: optional-but-recommended
|
||||
Value type: <prop-encoded-array>
|
||||
Definition:
|
||||
Specifies the LIODN to be used in conjunction with
|
||||
the ppid-to-liodn table that specifies the PPID to LIODN mapping.
|
||||
Needed if the PAMU is used. Value is a 12 bit value
|
||||
where value is a LIODN ID for this JR. This property is
|
||||
normally set by boot firmware.
|
||||
|
||||
- interrupts
|
||||
Usage: required
|
||||
Value type: <prop_encoded-array>
|
||||
Definition: Specifies the interrupts generated by this
|
||||
device. The value of the interrupts property
|
||||
consists of one interrupt specifier. The format
|
||||
of the specifier is defined by the binding document
|
||||
describing the node's interrupt parent.
|
||||
|
||||
EXAMPLE
|
||||
jr@1000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x1000 0x1000>;
|
||||
fsl,liodn = <0x081>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <88 2>;
|
||||
};
|
||||
|
||||
|
||||
=====================================================================
|
||||
Run Time Integrity Check (RTIC) Node
|
||||
|
||||
Child node of the crypto node. Defines a register space that
|
||||
contains up to 5 sets of addresses and their lengths (sizes) that
|
||||
will be checked at run time. After an initial hash result is
|
||||
calculated, these addresses are checked by HW to monitor any
|
||||
change. If any memory is modified, a Security Violation is
|
||||
triggered (see SNVS definition).
|
||||
|
||||
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Must include "fsl,sec-v4.0-rtic".
|
||||
|
||||
- #address-cells
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: A standard property. Defines the number of cells
|
||||
for representing physical addresses in child nodes. Must
|
||||
have a value of 1.
|
||||
|
||||
- #size-cells
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: A standard property. Defines the number of cells
|
||||
for representing the size of physical addresses in
|
||||
child nodes. Must have a value of 1.
|
||||
|
||||
- reg
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: A standard property. Specifies a two parameters:
|
||||
an offset from the parent physical address and the length
|
||||
the SEC4 registers.
|
||||
|
||||
- ranges
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: A standard property. Specifies the physical address
|
||||
range of the SEC 4 register space (-SNVS not included). A
|
||||
triplet that includes the child address, parent address, &
|
||||
length.
|
||||
|
||||
EXAMPLE
|
||||
rtic@6000 {
|
||||
compatible = "fsl,sec-v4.0-rtic";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x6000 0x100>;
|
||||
ranges = <0x0 0x6100 0xe00>;
|
||||
};
|
||||
|
||||
=====================================================================
|
||||
Run Time Integrity Check (RTIC) Memory Node
|
||||
A child node that defines individual RTIC memory regions that are used to
|
||||
perform run-time integrity check of memory areas that should not modified.
|
||||
The node defines a register that contains the memory address &
|
||||
length (combined) and a second register that contains the hash result
|
||||
in big endian format.
|
||||
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Must include "fsl,sec-v4.0-rtic-memory".
|
||||
|
||||
- reg
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: A standard property. Specifies two parameters:
|
||||
an offset from the parent physical address and the length:
|
||||
|
||||
1. The location of the RTIC memory address & length registers.
|
||||
2. The location RTIC hash result.
|
||||
|
||||
- fsl,rtic-region
|
||||
Usage: optional-but-recommended
|
||||
Value type: <prop-encoded-array>
|
||||
Definition:
|
||||
Specifies the HW address (36 bit address) for this region
|
||||
followed by the length of the HW partition to be checked;
|
||||
the address is represented as a 64 bit quantity followed
|
||||
by a 32 bit length.
|
||||
|
||||
- fsl,liodn
|
||||
Usage: optional-but-recommended
|
||||
Value type: <prop-encoded-array>
|
||||
Definition:
|
||||
Specifies the LIODN to be used in conjunction with
|
||||
the ppid-to-liodn table that specifies the PPID to LIODN
|
||||
mapping. Needed if the PAMU is used. Value is a 12 bit value
|
||||
where value is a LIODN ID for this RTIC memory region. This
|
||||
property is normally set by boot firmware.
|
||||
|
||||
EXAMPLE
|
||||
rtic-a@0 {
|
||||
compatible = "fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x00 0x20 0x100 0x80>;
|
||||
fsl,liodn = <0x03c>;
|
||||
fsl,rtic-region = <0x12345678 0x12345678 0x12345678>;
|
||||
};
|
||||
|
||||
=====================================================================
|
||||
Secure Non-Volatile Storage (SNVS) Node
|
||||
|
||||
Node defines address range and the associated
|
||||
interrupt for the SNVS function. This function
|
||||
monitors security state information & reports
|
||||
security violations. This also included rtc,
|
||||
system power off and ON/OFF key.
|
||||
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Must include "fsl,sec-v4.0-mon" and "syscon".
|
||||
|
||||
- reg
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: A standard property. Specifies the physical
|
||||
address and length of the SEC4 configuration
|
||||
registers.
|
||||
|
||||
- #address-cells
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: A standard property. Defines the number of cells
|
||||
for representing physical addresses in child nodes. Must
|
||||
have a value of 1.
|
||||
|
||||
- #size-cells
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: A standard property. Defines the number of cells
|
||||
for representing the size of physical addresses in
|
||||
child nodes. Must have a value of 1.
|
||||
|
||||
- ranges
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: A standard property. Specifies the physical address
|
||||
range of the SNVS register space. A triplet that includes
|
||||
the child address, parent address, & length.
|
||||
|
||||
- interrupts
|
||||
Usage: optional
|
||||
Value type: <prop_encoded-array>
|
||||
Definition: Specifies the interrupts generated by this
|
||||
device. The value of the interrupts property
|
||||
consists of one interrupt specifier. The format
|
||||
of the specifier is defined by the binding document
|
||||
describing the node's interrupt parent.
|
||||
|
||||
EXAMPLE
|
||||
sec_mon@314000 {
|
||||
compatible = "fsl,sec-v4.0-mon", "syscon";
|
||||
reg = <0x314000 0x1000>;
|
||||
ranges = <0 0x314000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <93 2>;
|
||||
};
|
||||
|
||||
=====================================================================
|
||||
Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
|
||||
|
||||
A SNVS child node that defines SNVS LP RTC.
|
||||
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Must include "fsl,sec-v4.0-mon-rtc-lp".
|
||||
|
||||
- interrupts
|
||||
Usage: required
|
||||
Value type: <prop_encoded-array>
|
||||
Definition: Specifies the interrupts generated by this
|
||||
device. The value of the interrupts property
|
||||
consists of one interrupt specifier. The format
|
||||
of the specifier is defined by the binding document
|
||||
describing the node's interrupt parent.
|
||||
|
||||
- regmap
|
||||
Usage: required
|
||||
Value type: <phandle>
|
||||
Definition: this is phandle to the register map node.
|
||||
|
||||
- offset
|
||||
Usage: option
|
||||
value type: <u32>
|
||||
Definition: LP register offset. default it is 0x34.
|
||||
|
||||
- clocks
|
||||
Usage: optional, required if SNVS LP RTC requires explicit
|
||||
enablement of clocks
|
||||
Value type: <prop_encoded-array>
|
||||
Definition: a clock specifier describing the clock required for
|
||||
enabling and disabling SNVS LP RTC.
|
||||
|
||||
- clock-names
|
||||
Usage: optional, required if SNVS LP RTC requires explicit
|
||||
enablement of clocks
|
||||
Value type: <string>
|
||||
Definition: clock name string should be "snvs-rtc".
|
||||
|
||||
EXAMPLE
|
||||
sec_mon_rtc_lp@1 {
|
||||
compatible = "fsl,sec-v4.0-mon-rtc-lp";
|
||||
interrupts = <93 2>;
|
||||
regmap = <&snvs>;
|
||||
offset = <0x34>;
|
||||
clocks = <&clks IMX7D_SNVS_CLK>;
|
||||
clock-names = "snvs-rtc";
|
||||
};
|
||||
|
||||
=====================================================================
|
||||
System ON/OFF key driver
|
||||
|
||||
The snvs-pwrkey is designed to enable POWER key function which controlled
|
||||
by SNVS ONOFF, the driver can report the status of POWER key and wakeup
|
||||
system if pressed after system suspend.
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Mush include "fsl,sec-v4.0-pwrkey".
|
||||
|
||||
- interrupts:
|
||||
Usage: required
|
||||
Value type: <prop_encoded-array>
|
||||
Definition: The SNVS ON/OFF interrupt number to the CPU(s).
|
||||
|
||||
- linux,keycode:
|
||||
Usage: option
|
||||
Value type: <int>
|
||||
Definition: Keycode to emit, KEY_POWER by default.
|
||||
|
||||
- wakeup-source:
|
||||
Usage: option
|
||||
Value type: <boo>
|
||||
Definition: Button can wake-up the system.
|
||||
|
||||
- regmap:
|
||||
Usage: required:
|
||||
Value type: <phandle>
|
||||
Definition: this is phandle to the register map node.
|
||||
|
||||
EXAMPLE:
|
||||
snvs-pwrkey@020cc000 {
|
||||
compatible = "fsl,sec-v4.0-pwrkey";
|
||||
regmap = <&snvs>;
|
||||
interrupts = <0 4 0x4>
|
||||
linux,keycode = <116>; /* KEY_POWER */
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
=====================================================================
|
||||
FULL EXAMPLE
|
||||
|
||||
crypto: crypto@300000 {
|
||||
compatible = "fsl,sec-v4.0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x300000 0x10000>;
|
||||
ranges = <0 0x300000 0x10000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <92 2>;
|
||||
|
||||
sec_jr0: jr@1000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <88 2>;
|
||||
};
|
||||
|
||||
sec_jr1: jr@2000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <89 2>;
|
||||
};
|
||||
|
||||
sec_jr2: jr@3000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x3000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <90 2>;
|
||||
};
|
||||
|
||||
sec_jr3: jr@4000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x4000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <91 2>;
|
||||
};
|
||||
|
||||
rtic@6000 {
|
||||
compatible = "fsl,sec-v4.0-rtic";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x6000 0x100>;
|
||||
ranges = <0x0 0x6100 0xe00>;
|
||||
|
||||
rtic_a: rtic-a@0 {
|
||||
compatible = "fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x00 0x20 0x100 0x80>;
|
||||
};
|
||||
|
||||
rtic_b: rtic-b@20 {
|
||||
compatible = "fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x20 0x20 0x200 0x80>;
|
||||
};
|
||||
|
||||
rtic_c: rtic-c@40 {
|
||||
compatible = "fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x40 0x20 0x300 0x80>;
|
||||
};
|
||||
|
||||
rtic_d: rtic-d@60 {
|
||||
compatible = "fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x60 0x20 0x500 0x80>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sec_mon: sec_mon@314000 {
|
||||
compatible = "fsl,sec-v4.0-mon";
|
||||
reg = <0x314000 0x1000>;
|
||||
ranges = <0 0x314000 0x1000>;
|
||||
|
||||
sec_mon_rtc_lp@34 {
|
||||
compatible = "fsl,sec-v4.0-mon-rtc-lp";
|
||||
regmap = <&sec_mon>;
|
||||
offset = <0x34>;
|
||||
interrupts = <93 2>;
|
||||
clocks = <&clks IMX7D_SNVS_CLK>;
|
||||
clock-names = "snvs-rtc";
|
||||
};
|
||||
|
||||
snvs-pwrkey@020cc000 {
|
||||
compatible = "fsl,sec-v4.0-pwrkey";
|
||||
regmap = <&sec_mon>;
|
||||
interrupts = <0 4 0x4>;
|
||||
linux,keycode = <116>; /* KEY_POWER */
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
=====================================================================
|
||||
157
bindings/crypto/fsl-sec6.txt
Normal file
157
bindings/crypto/fsl-sec6.txt
Normal file
@@ -0,0 +1,157 @@
|
||||
SEC 6 is as Freescale's Cryptographic Accelerator and Assurance Module (CAAM).
|
||||
Currently Freescale powerpc chip C29X is embedded with SEC 6.
|
||||
SEC 6 device tree binding include:
|
||||
-SEC 6 Node
|
||||
-Job Ring Node
|
||||
-Full Example
|
||||
|
||||
=====================================================================
|
||||
SEC 6 Node
|
||||
|
||||
Description
|
||||
|
||||
Node defines the base address of the SEC 6 block.
|
||||
This block specifies the address range of all global
|
||||
configuration registers for the SEC 6 block.
|
||||
For example, In C293, we could see three SEC 6 node.
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Must include "fsl,sec-v6.0".
|
||||
|
||||
- fsl,sec-era
|
||||
Usage: optional
|
||||
Value type: <u32>
|
||||
Definition: A standard property. Define the 'ERA' of the SEC
|
||||
device.
|
||||
|
||||
- #address-cells
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: A standard property. Defines the number of cells
|
||||
for representing physical addresses in child nodes.
|
||||
|
||||
- #size-cells
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: A standard property. Defines the number of cells
|
||||
for representing the size of physical addresses in
|
||||
child nodes.
|
||||
|
||||
- reg
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: A standard property. Specifies the physical
|
||||
address and length of the SEC 6 configuration registers.
|
||||
|
||||
- ranges
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: A standard property. Specifies the physical address
|
||||
range of the SEC 6.0 register space (-SNVS not included). A
|
||||
triplet that includes the child address, parent address, &
|
||||
length.
|
||||
|
||||
Note: All other standard properties (see the Devicetree Specification)
|
||||
are allowed but are optional.
|
||||
|
||||
EXAMPLE
|
||||
crypto@a0000 {
|
||||
compatible = "fsl,sec-v6.0";
|
||||
fsl,sec-era = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xa0000 0x20000>;
|
||||
ranges = <0 0xa0000 0x20000>;
|
||||
};
|
||||
|
||||
=====================================================================
|
||||
Job Ring (JR) Node
|
||||
|
||||
Child of the crypto node defines data processing interface to SEC 6
|
||||
across the peripheral bus for purposes of processing
|
||||
cryptographic descriptors. The specified address
|
||||
range can be made visible to one (or more) cores.
|
||||
The interrupt defined for this node is controlled within
|
||||
the address range of this node.
|
||||
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Must include "fsl,sec-v6.0-job-ring".
|
||||
|
||||
- reg
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: Specifies a two JR parameters: an offset from
|
||||
the parent physical address and the length the JR registers.
|
||||
|
||||
- interrupts
|
||||
Usage: required
|
||||
Value type: <prop_encoded-array>
|
||||
Definition: Specifies the interrupts generated by this
|
||||
device. The value of the interrupts property
|
||||
consists of one interrupt specifier. The format
|
||||
of the specifier is defined by the binding document
|
||||
describing the node's interrupt parent.
|
||||
|
||||
EXAMPLE
|
||||
jr@1000 {
|
||||
compatible = "fsl,sec-v6.0-job-ring";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <49 2 0 0>;
|
||||
};
|
||||
|
||||
===================================================================
|
||||
Full Example
|
||||
|
||||
Since some chips may contain more than one SEC, the dtsi contains
|
||||
only the node contents, not the node itself. A chip using the SEC
|
||||
should include the dtsi inside each SEC node. Example:
|
||||
|
||||
In qoriq-sec6.0.dtsi:
|
||||
|
||||
compatible = "fsl,sec-v6.0";
|
||||
fsl,sec-era = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
jr@1000 {
|
||||
compatible = "fsl,sec-v6.0-job-ring",
|
||||
"fsl,sec-v5.2-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.4-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x1000 0x1000>;
|
||||
};
|
||||
|
||||
jr@2000 {
|
||||
compatible = "fsl,sec-v6.0-job-ring",
|
||||
"fsl,sec-v5.2-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.4-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x2000 0x1000>;
|
||||
};
|
||||
|
||||
In the C293 device tree, we add the include of public property:
|
||||
|
||||
crypto@a0000 {
|
||||
/include/ "qoriq-sec6.0.dtsi"
|
||||
}
|
||||
|
||||
crypto@a0000 {
|
||||
reg = <0xa0000 0x20000>;
|
||||
ranges = <0 0xa0000 0x20000>;
|
||||
|
||||
jr@1000 {
|
||||
interrupts = <49 2 0 0>;
|
||||
};
|
||||
|
||||
jr@2000 {
|
||||
interrupts = <50 2 0 0>;
|
||||
};
|
||||
};
|
||||
67
bindings/crypto/hisilicon,hip07-sec.txt
Normal file
67
bindings/crypto/hisilicon,hip07-sec.txt
Normal file
@@ -0,0 +1,67 @@
|
||||
* Hisilicon hip07 Security Accelerator (SEC)
|
||||
|
||||
Required properties:
|
||||
- compatible: Must contain one of
|
||||
- "hisilicon,hip06-sec"
|
||||
- "hisilicon,hip07-sec"
|
||||
- reg: Memory addresses and lengths of the memory regions through which
|
||||
this device is controlled.
|
||||
Region 0 has registers to control the backend processing engines.
|
||||
Region 1 has registers for functionality common to all queues.
|
||||
Regions 2-18 have registers for the 16 individual queues which are isolated
|
||||
both in hardware and within the driver.
|
||||
- interrupts: Interrupt specifiers.
|
||||
Refer to interrupt-controller/interrupts.txt for generic interrupt client node
|
||||
bindings.
|
||||
Interrupt 0 is for the SEC unit error queue.
|
||||
Interrupt 2N + 1 is the completion interrupt for queue N.
|
||||
Interrupt 2N + 2 is the error interrupt for queue N.
|
||||
- dma-coherent: The driver assumes coherent dma is possible.
|
||||
|
||||
Optional properties:
|
||||
- iommus: The SEC units are behind smmu-v3 iommus.
|
||||
Refer to iommu/arm,smmu-v3.txt for more information.
|
||||
|
||||
Example:
|
||||
|
||||
p1_sec_a: crypto@400d2000000 {
|
||||
compatible = "hisilicon,hip07-sec";
|
||||
reg = <0x400 0xd0000000 0x0 0x10000
|
||||
0x400 0xd2000000 0x0 0x10000
|
||||
0x400 0xd2010000 0x0 0x10000
|
||||
0x400 0xd2020000 0x0 0x10000
|
||||
0x400 0xd2030000 0x0 0x10000
|
||||
0x400 0xd2040000 0x0 0x10000
|
||||
0x400 0xd2050000 0x0 0x10000
|
||||
0x400 0xd2060000 0x0 0x10000
|
||||
0x400 0xd2070000 0x0 0x10000
|
||||
0x400 0xd2080000 0x0 0x10000
|
||||
0x400 0xd2090000 0x0 0x10000
|
||||
0x400 0xd20a0000 0x0 0x10000
|
||||
0x400 0xd20b0000 0x0 0x10000
|
||||
0x400 0xd20c0000 0x0 0x10000
|
||||
0x400 0xd20d0000 0x0 0x10000
|
||||
0x400 0xd20e0000 0x0 0x10000
|
||||
0x400 0xd20f0000 0x0 0x10000
|
||||
0x400 0xd2100000 0x0 0x10000>;
|
||||
interrupt-parent = <&p1_mbigen_sec_a>;
|
||||
iommus = <&p1_smmu_alg_a 0x600>;
|
||||
dma-coherent;
|
||||
interrupts = <576 4>,
|
||||
<577 1>, <578 4>,
|
||||
<579 1>, <580 4>,
|
||||
<581 1>, <582 4>,
|
||||
<583 1>, <584 4>,
|
||||
<585 1>, <586 4>,
|
||||
<587 1>, <588 4>,
|
||||
<589 1>, <590 4>,
|
||||
<591 1>, <592 4>,
|
||||
<593 1>, <594 4>,
|
||||
<595 1>, <596 4>,
|
||||
<597 1>, <598 4>,
|
||||
<599 1>, <600 4>,
|
||||
<601 1>, <602 4>,
|
||||
<603 1>, <604 4>,
|
||||
<605 1>, <606 4>,
|
||||
<607 1>, <608 4>;
|
||||
};
|
||||
27
bindings/crypto/img-hash.txt
Normal file
27
bindings/crypto/img-hash.txt
Normal file
@@ -0,0 +1,27 @@
|
||||
Imagination Technologies hardware hash accelerator
|
||||
|
||||
The hash accelerator provides hardware hashing acceleration for
|
||||
SHA1, SHA224, SHA256 and MD5 hashes
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : "img,hash-accelerator"
|
||||
- reg : Offset and length of the register set for the module, and the DMA port
|
||||
- interrupts : The designated IRQ line for the hashing module.
|
||||
- dmas : DMA specifier as per Documentation/devicetree/bindings/dma/dma.txt
|
||||
- dma-names : Should be "tx"
|
||||
- clocks : Clock specifiers
|
||||
- clock-names : "sys" Used to clock the hash block registers
|
||||
"hash" Used to clock data through the accelerator
|
||||
|
||||
Example:
|
||||
|
||||
hash: hash@18149600 {
|
||||
compatible = "img,hash-accelerator";
|
||||
reg = <0x18149600 0x100>, <0x18101100 0x4>;
|
||||
interrupts = <GIC_SHARED 59 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&dma 8 0xffffffff 0>;
|
||||
dma-names = "tx";
|
||||
clocks = <&cr_periph SYS_CLK_HASH>, <&clk_periph PERIPH_CLK_ROM>;
|
||||
clock-names = "sys", "hash";
|
||||
};
|
||||
40
bindings/crypto/inside-secure-safexcel.txt
Normal file
40
bindings/crypto/inside-secure-safexcel.txt
Normal file
@@ -0,0 +1,40 @@
|
||||
Inside Secure SafeXcel cryptographic engine
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "inside-secure,safexcel-eip197b",
|
||||
"inside-secure,safexcel-eip197d" or
|
||||
"inside-secure,safexcel-eip97ies".
|
||||
- reg: Base physical address of the engine and length of memory mapped region.
|
||||
- interrupts: Interrupt numbers for the rings and engine.
|
||||
- interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem".
|
||||
|
||||
Optional properties:
|
||||
- clocks: Reference to the crypto engine clocks, the second clock is
|
||||
needed for the Armada 7K/8K SoCs.
|
||||
- clock-names: mandatory if there is a second clock, in this case the
|
||||
name must be "core" for the first clock and "reg" for
|
||||
the second one.
|
||||
|
||||
Backward compatibility:
|
||||
Two compatibles are kept for backward compatibility, but shouldn't be used for
|
||||
new submissions:
|
||||
- "inside-secure,safexcel-eip197" is equivalent to
|
||||
"inside-secure,safexcel-eip197b".
|
||||
- "inside-secure,safexcel-eip97" is equivalent to
|
||||
"inside-secure,safexcel-eip97ies".
|
||||
|
||||
Example:
|
||||
|
||||
crypto: crypto@800000 {
|
||||
compatible = "inside-secure,safexcel-eip197b";
|
||||
reg = <0x800000 0x200000>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3",
|
||||
"eip";
|
||||
clocks = <&cpm_syscon0 1 26>;
|
||||
};
|
||||
56
bindings/crypto/intel,ixp4xx-crypto.yaml
Normal file
56
bindings/crypto/intel,ixp4xx-crypto.yaml
Normal file
@@ -0,0 +1,56 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
# Copyright 2018 Linaro Ltd.
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Intel IXP4xx cryptographic engine
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
description: |
|
||||
The Intel IXP4xx cryptographic engine makes use of the IXP4xx NPE
|
||||
(Network Processing Engine). Since it is not a device on its own
|
||||
it is defined as a subnode of the NPE, if crypto support is
|
||||
available on the platform.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: intel,ixp4xx-crypto
|
||||
|
||||
intel,npe-handle:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle-array'
|
||||
items:
|
||||
- items:
|
||||
- description: phandle to the NPE this crypto engine
|
||||
- description: the NPE instance number
|
||||
description: phandle to the NPE this crypto engine is using, the cell
|
||||
describing the NPE instance to be used.
|
||||
|
||||
queue-rx:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
- items:
|
||||
- description: phandle to the RX queue on the NPE
|
||||
- description: the queue instance number
|
||||
description: phandle to the RX queue on the NPE, the cell describing
|
||||
the queue instance to be used.
|
||||
|
||||
queue-txready:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
- items:
|
||||
- description: phandle to the TX READY queue on the NPE
|
||||
- description: the queue instance number
|
||||
description: phandle to the TX READY queue on the NPE, the cell describing
|
||||
the queue instance to be used.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- intel,npe-handle
|
||||
- queue-rx
|
||||
- queue-txready
|
||||
|
||||
additionalProperties: false
|
||||
45
bindings/crypto/intel,keembay-ocs-aes.yaml
Normal file
45
bindings/crypto/intel,keembay-ocs-aes.yaml
Normal file
@@ -0,0 +1,45 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-aes.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Intel Keem Bay OCS AES
|
||||
|
||||
maintainers:
|
||||
- Daniele Alessandrelli <daniele.alessandrelli@intel.com>
|
||||
|
||||
description:
|
||||
The Intel Keem Bay Offload and Crypto Subsystem (OCS) AES engine provides
|
||||
hardware-accelerated AES/SM4 encryption/decryption.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: intel,keembay-ocs-aes
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
crypto@30008000 {
|
||||
compatible = "intel,keembay-ocs-aes";
|
||||
reg = <0x30008000 0x1000>;
|
||||
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&scmi_clk 95>;
|
||||
};
|
||||
47
bindings/crypto/intel,keembay-ocs-ecc.yaml
Normal file
47
bindings/crypto/intel,keembay-ocs-ecc.yaml
Normal file
@@ -0,0 +1,47 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-ecc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Intel Keem Bay OCS ECC
|
||||
|
||||
maintainers:
|
||||
- Daniele Alessandrelli <daniele.alessandrelli@intel.com>
|
||||
- Prabhjot Khurana <prabhjot.khurana@intel.com>
|
||||
|
||||
description:
|
||||
The Intel Keem Bay Offload and Crypto Subsystem (OCS) Elliptic Curve
|
||||
Cryptography (ECC) device provides hardware acceleration for elliptic curve
|
||||
cryptography using the NIST P-256 and NIST P-384 elliptic curves.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: intel,keembay-ocs-ecc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
crypto@30001000 {
|
||||
compatible = "intel,keembay-ocs-ecc";
|
||||
reg = <0x30001000 0x1000>;
|
||||
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&scmi_clk 95>;
|
||||
};
|
||||
46
bindings/crypto/intel,keembay-ocs-hcu.yaml
Normal file
46
bindings/crypto/intel,keembay-ocs-hcu.yaml
Normal file
@@ -0,0 +1,46 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-hcu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Intel Keem Bay OCS HCU
|
||||
|
||||
maintainers:
|
||||
- Declan Murphy <declan.murphy@intel.com>
|
||||
- Daniele Alessandrelli <daniele.alessandrelli@intel.com>
|
||||
|
||||
description:
|
||||
The Intel Keem Bay Offload and Crypto Subsystem (OCS) Hash Control Unit (HCU)
|
||||
provides hardware-accelerated hashing and HMAC.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: intel,keembay-ocs-hcu
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
crypto@3000b000 {
|
||||
compatible = "intel,keembay-ocs-hcu";
|
||||
reg = <0x3000b000 0x1000>;
|
||||
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&scmi_clk 94>;
|
||||
};
|
||||
44
bindings/crypto/marvell-cesa.txt
Normal file
44
bindings/crypto/marvell-cesa.txt
Normal file
@@ -0,0 +1,44 @@
|
||||
Marvell Cryptographic Engines And Security Accelerator
|
||||
|
||||
Required properties:
|
||||
- compatible: should be one of the following string
|
||||
"marvell,orion-crypto"
|
||||
"marvell,kirkwood-crypto"
|
||||
"marvell,dove-crypto"
|
||||
"marvell,armada-370-crypto"
|
||||
"marvell,armada-xp-crypto"
|
||||
"marvell,armada-375-crypto"
|
||||
"marvell,armada-38x-crypto"
|
||||
- reg: base physical address of the engine and length of memory mapped
|
||||
region. Can also contain an entry for the SRAM attached to the CESA,
|
||||
but this representation is deprecated and marvell,crypto-srams should
|
||||
be used instead
|
||||
- reg-names: "regs". Can contain an "sram" entry, but this representation
|
||||
is deprecated and marvell,crypto-srams should be used instead
|
||||
- interrupts: interrupt number
|
||||
- clocks: reference to the crypto engines clocks. This property is not
|
||||
required for orion and kirkwood platforms
|
||||
- clock-names: "cesaX" and "cesazX", X should be replaced by the crypto engine
|
||||
id.
|
||||
This property is not required for the orion and kirkwoord
|
||||
platforms.
|
||||
"cesazX" clocks are not required on armada-370 platforms
|
||||
- marvell,crypto-srams: phandle to crypto SRAM definitions
|
||||
|
||||
Optional properties:
|
||||
- marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not
|
||||
specified the whole SRAM is used (2KB)
|
||||
|
||||
|
||||
Examples:
|
||||
|
||||
crypto@90000 {
|
||||
compatible = "marvell,armada-xp-crypto";
|
||||
reg = <0x90000 0x10000>;
|
||||
reg-names = "regs";
|
||||
interrupts = <48>, <49>;
|
||||
clocks = <&gateclk 23>, <&gateclk 23>;
|
||||
clock-names = "cesa0", "cesa1";
|
||||
marvell,crypto-srams = <&crypto_sram0>, <&crypto_sram1>;
|
||||
marvell,crypto-sram-size = <0x600>;
|
||||
};
|
||||
25
bindings/crypto/mediatek-crypto.txt
Normal file
25
bindings/crypto/mediatek-crypto.txt
Normal file
@@ -0,0 +1,25 @@
|
||||
MediaTek cryptographic accelerators
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "mediatek,eip97-crypto"
|
||||
- reg: Address and length of the register set for the device
|
||||
- interrupts: Should contain the five crypto engines interrupts in numeric
|
||||
order. These are global system and four descriptor rings.
|
||||
- clocks: the clock used by the core
|
||||
- clock-names: Must contain "cryp".
|
||||
- power-domains: Must contain a reference to the PM domain.
|
||||
|
||||
|
||||
Example:
|
||||
crypto: crypto@1b240000 {
|
||||
compatible = "mediatek,eip97-crypto";
|
||||
reg = <0 0x1b240000 0 0x20000>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <ðsys CLK_ETHSYS_CRYPTO>;
|
||||
clock-names = "cryp";
|
||||
power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
|
||||
};
|
||||
32
bindings/crypto/mv_cesa.txt
Normal file
32
bindings/crypto/mv_cesa.txt
Normal file
@@ -0,0 +1,32 @@
|
||||
Marvell Cryptographic Engines And Security Accelerator
|
||||
|
||||
Required properties:
|
||||
- compatible: should be one of the following string
|
||||
"marvell,orion-crypto"
|
||||
"marvell,kirkwood-crypto"
|
||||
"marvell,dove-crypto"
|
||||
- reg: base physical address of the engine and length of memory mapped
|
||||
region. Can also contain an entry for the SRAM attached to the CESA,
|
||||
but this representation is deprecated and marvell,crypto-srams should
|
||||
be used instead
|
||||
- reg-names: "regs". Can contain an "sram" entry, but this representation
|
||||
is deprecated and marvell,crypto-srams should be used instead
|
||||
- interrupts: interrupt number
|
||||
- clocks: reference to the crypto engines clocks. This property is only
|
||||
required for Dove platforms
|
||||
- marvell,crypto-srams: phandle to crypto SRAM definitions
|
||||
|
||||
Optional properties:
|
||||
- marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not
|
||||
specified the whole SRAM is used (2KB)
|
||||
|
||||
Examples:
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "marvell,orion-crypto";
|
||||
reg = <0x30000 0x10000>;
|
||||
reg-names = "regs";
|
||||
interrupts = <22>;
|
||||
marvell,crypto-srams = <&crypto_sram>;
|
||||
marvell,crypto-sram-size = <0x600>;
|
||||
};
|
||||
31
bindings/crypto/omap-aes.txt
Normal file
31
bindings/crypto/omap-aes.txt
Normal file
@@ -0,0 +1,31 @@
|
||||
OMAP SoC AES crypto Module
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : Should contain entries for this and backward compatible
|
||||
AES versions:
|
||||
- "ti,omap2-aes" for OMAP2.
|
||||
- "ti,omap3-aes" for OMAP3.
|
||||
- "ti,omap4-aes" for OMAP4 and AM33XX.
|
||||
Note that the OMAP2 and 3 versions are compatible (OMAP3 supports
|
||||
more algorithms) but they are incompatible with OMAP4.
|
||||
- ti,hwmods: Name of the hwmod associated with the AES module
|
||||
- reg : Offset and length of the register set for the module
|
||||
- interrupts : the interrupt-specifier for the AES module.
|
||||
|
||||
Optional properties:
|
||||
- dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
|
||||
Documentation/devicetree/bindings/dma/dma.txt
|
||||
- dma-names: DMA request names should include "tx" and "rx" if present.
|
||||
|
||||
Example:
|
||||
/* AM335x */
|
||||
aes: aes@53500000 {
|
||||
compatible = "ti,omap4-aes";
|
||||
ti,hwmods = "aes";
|
||||
reg = <0x53500000 0xa0>;
|
||||
interrupts = <102>;
|
||||
dmas = <&edma 6>,
|
||||
<&edma 5>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
30
bindings/crypto/omap-des.txt
Normal file
30
bindings/crypto/omap-des.txt
Normal file
@@ -0,0 +1,30 @@
|
||||
OMAP SoC DES crypto Module
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : Should contain "ti,omap4-des"
|
||||
- ti,hwmods: Name of the hwmod associated with the DES module
|
||||
- reg : Offset and length of the register set for the module
|
||||
- interrupts : the interrupt-specifier for the DES module
|
||||
- clocks : A phandle to the functional clock node of the DES module
|
||||
corresponding to each entry in clock-names
|
||||
- clock-names : Name of the functional clock, should be "fck"
|
||||
|
||||
Optional properties:
|
||||
- dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
|
||||
Documentation/devicetree/bindings/dma/dma.txt
|
||||
Each entry corresponds to an entry in dma-names
|
||||
- dma-names: DMA request names should include "tx" and "rx" if present
|
||||
|
||||
Example:
|
||||
/* DRA7xx SoC */
|
||||
des: des@480a5000 {
|
||||
compatible = "ti,omap4-des";
|
||||
ti,hwmods = "des";
|
||||
reg = <0x480a5000 0xa0>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&sdma 117>, <&sdma 116>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&l3_iclk_div>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
28
bindings/crypto/omap-sham.txt
Normal file
28
bindings/crypto/omap-sham.txt
Normal file
@@ -0,0 +1,28 @@
|
||||
OMAP SoC SHA crypto Module
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : Should contain entries for this and backward compatible
|
||||
SHAM versions:
|
||||
- "ti,omap2-sham" for OMAP2 & OMAP3.
|
||||
- "ti,omap4-sham" for OMAP4 and AM33XX.
|
||||
- "ti,omap5-sham" for OMAP5, DRA7 and AM43XX.
|
||||
- ti,hwmods: Name of the hwmod associated with the SHAM module
|
||||
- reg : Offset and length of the register set for the module
|
||||
- interrupts : the interrupt-specifier for the SHAM module.
|
||||
|
||||
Optional properties:
|
||||
- dmas: DMA specifiers for the rx dma. See the DMA client binding,
|
||||
Documentation/devicetree/bindings/dma/dma.txt
|
||||
- dma-names: DMA request name. Should be "rx" if a dma is present.
|
||||
|
||||
Example:
|
||||
/* AM335x */
|
||||
sham: sham@53100000 {
|
||||
compatible = "ti,omap4-sham";
|
||||
ti,hwmods = "sham";
|
||||
reg = <0x53100000 0x200>;
|
||||
interrupts = <109>;
|
||||
dmas = <&edma 36>;
|
||||
dma-names = "rx";
|
||||
};
|
||||
43
bindings/crypto/qcom,prng.yaml
Normal file
43
bindings/crypto/qcom,prng.yaml
Normal file
@@ -0,0 +1,43 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/qcom,prng.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Pseudo Random Number Generator
|
||||
|
||||
maintainers:
|
||||
- Vinod Koul <vkoul@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,prng # 8916 etc.
|
||||
- qcom,prng-ee # 8996 and later using EE
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: core
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
rng@f9bff000 {
|
||||
compatible = "qcom,prng";
|
||||
reg = <0xf9bff000 0x200>;
|
||||
clocks = <&clk 125>;
|
||||
clock-names = "core";
|
||||
};
|
||||
25
bindings/crypto/qcom-qce.txt
Normal file
25
bindings/crypto/qcom-qce.txt
Normal file
@@ -0,0 +1,25 @@
|
||||
Qualcomm crypto engine driver
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "qcom,crypto-v5.1"
|
||||
- reg : specifies base physical address and size of the registers map
|
||||
- clocks : phandle to clock-controller plus clock-specifier pair
|
||||
- clock-names : "iface" clocks register interface
|
||||
"bus" clocks data transfer interface
|
||||
"core" clocks rest of the crypto block
|
||||
- dmas : DMA specifiers for tx and rx dma channels. For more see
|
||||
Documentation/devicetree/bindings/dma/dma.txt
|
||||
- dma-names : DMA request names should be "rx" and "tx"
|
||||
|
||||
Example:
|
||||
crypto@fd45a000 {
|
||||
compatible = "qcom,crypto-v5.1";
|
||||
reg = <0xfd45a000 0x6000>;
|
||||
clocks = <&gcc GCC_CE2_AHB_CLK>,
|
||||
<&gcc GCC_CE2_AXI_CLK>,
|
||||
<&gcc GCC_CE2_CLK>;
|
||||
clock-names = "iface", "bus", "core";
|
||||
dmas = <&cryptobam 2>, <&cryptobam 3>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
28
bindings/crypto/rockchip-crypto.txt
Normal file
28
bindings/crypto/rockchip-crypto.txt
Normal file
@@ -0,0 +1,28 @@
|
||||
Rockchip Electronics And Security Accelerator
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "rockchip,rk3288-crypto"
|
||||
- reg: Base physical address of the engine and length of memory mapped
|
||||
region
|
||||
- interrupts: Interrupt number
|
||||
- clocks: Reference to the clocks about crypto
|
||||
- clock-names: "aclk" used to clock data
|
||||
"hclk" used to clock data
|
||||
"sclk" used to clock crypto accelerator
|
||||
"apb_pclk" used to clock dma
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the name "crypto-rst".
|
||||
|
||||
Examples:
|
||||
|
||||
crypto: cypto-controller@ff8a0000 {
|
||||
compatible = "rockchip,rk3288-crypto";
|
||||
reg = <0xff8a0000 0x4000>;
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
|
||||
<&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
|
||||
clock-names = "aclk", "hclk", "sclk", "apb_pclk";
|
||||
resets = <&cru SRST_CRYPTO>;
|
||||
reset-names = "crypto-rst";
|
||||
};
|
||||
45
bindings/crypto/samsung-slimsss.yaml
Normal file
45
bindings/crypto/samsung-slimsss.yaml
Normal file
@@ -0,0 +1,45 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/samsung-slimsss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos SoC SlimSSS (Slim Security SubSystem) module
|
||||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
description: |+
|
||||
The SlimSSS module in Exynos5433 SoC supports the following:
|
||||
-- Feeder (FeedCtrl)
|
||||
-- Advanced Encryption Standard (AES) with ECB,CBC,CTR,XTS and (CBC/XTS)/CTS
|
||||
-- SHA-1/SHA-256 and (SHA-1/SHA-256)/HMAC
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: samsung,exynos5433-slim-sss
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pclk
|
||||
- const: aclk
|
||||
|
||||
interrupts:
|
||||
description: One feed control interrupt.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clock-names
|
||||
- clocks
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
57
bindings/crypto/samsung-sss.yaml
Normal file
57
bindings/crypto/samsung-sss.yaml
Normal file
@@ -0,0 +1,57 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/samsung-sss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos SoC SSS (Security SubSystem) module
|
||||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
description: |+
|
||||
The SSS module in S5PV210 SoC supports the following:
|
||||
-- Feeder (FeedCtrl)
|
||||
-- Advanced Encryption Standard (AES)
|
||||
-- Data Encryption Standard (DES)/3DES
|
||||
-- Public Key Accelerator (PKA)
|
||||
-- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
|
||||
-- PRNG: Pseudo Random Number Generator
|
||||
|
||||
The SSS module in Exynos4 (Exynos4210) and Exynos5 (Exynos5420 and Exynos5250)
|
||||
SoCs supports the following also:
|
||||
-- ARCFOUR (ARC4)
|
||||
-- True Random Number Generator (TRNG)
|
||||
-- Secure Key Manager
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- samsung,s5pv210-secss # for S5PV210
|
||||
- samsung,exynos4210-secss # for Exynos4210, Exynos4212,
|
||||
# Exynos4412, Exynos5250,
|
||||
# Exynos5260 and Exynos5420
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: secss
|
||||
|
||||
interrupts:
|
||||
description: One feed control interrupt.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clock-names
|
||||
- clocks
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
38
bindings/crypto/st,stm32-crc.yaml
Normal file
38
bindings/crypto/st,stm32-crc.yaml
Normal file
@@ -0,0 +1,38 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/st,stm32-crc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: STMicroelectronics STM32 CRC bindings
|
||||
|
||||
maintainers:
|
||||
- Lionel Debieve <lionel.debieve@foss.st.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: st,stm32f7-crc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/stm32mp1-clks.h>
|
||||
crc@40023000 {
|
||||
compatible = "st,stm32f7-crc";
|
||||
reg = <0x40023000 0x400>;
|
||||
clocks = <&rcc 0 12>;
|
||||
};
|
||||
|
||||
...
|
||||
51
bindings/crypto/st,stm32-cryp.yaml
Normal file
51
bindings/crypto/st,stm32-cryp.yaml
Normal file
@@ -0,0 +1,51 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/st,stm32-cryp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: STMicroelectronics STM32 CRYP bindings
|
||||
|
||||
maintainers:
|
||||
- Lionel Debieve <lionel.debieve@foss.st.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- st,stm32f756-cryp
|
||||
- st,stm32mp1-cryp
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/stm32mp1-clks.h>
|
||||
#include <dt-bindings/reset/stm32mp1-resets.h>
|
||||
cryp@54001000 {
|
||||
compatible = "st,stm32mp1-cryp";
|
||||
reg = <0x54001000 0x400>;
|
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc CRYP1>;
|
||||
resets = <&rcc CRYP1_R>;
|
||||
};
|
||||
|
||||
...
|
||||
68
bindings/crypto/st,stm32-hash.yaml
Normal file
68
bindings/crypto/st,stm32-hash.yaml
Normal file
@@ -0,0 +1,68 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/st,stm32-hash.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: STMicroelectronics STM32 HASH bindings
|
||||
|
||||
maintainers:
|
||||
- Lionel Debieve <lionel.debieve@foss.st.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- st,stm32f456-hash
|
||||
- st,stm32f756-hash
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
dmas:
|
||||
maxItems: 1
|
||||
|
||||
dma-names:
|
||||
items:
|
||||
- const: in
|
||||
|
||||
dma-maxburst:
|
||||
description: Set number of maximum dma burst supported
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 2
|
||||
default: 0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/stm32mp1-clks.h>
|
||||
#include <dt-bindings/reset/stm32mp1-resets.h>
|
||||
hash@54002000 {
|
||||
compatible = "st,stm32f756-hash";
|
||||
reg = <0x54002000 0x400>;
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc HASH1>;
|
||||
resets = <&rcc HASH1_R>;
|
||||
dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
|
||||
dma-names = "in";
|
||||
dma-maxburst = <2>;
|
||||
};
|
||||
|
||||
...
|
||||
86
bindings/crypto/ti,sa2ul.yaml
Normal file
86
bindings/crypto/ti,sa2ul.yaml
Normal file
@@ -0,0 +1,86 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/ti,sa2ul.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: K3 SoC SA2UL crypto module
|
||||
|
||||
maintainers:
|
||||
- Tero Kristo <t-kristo@ti.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- ti,j721e-sa2ul
|
||||
- ti,am654-sa2ul
|
||||
- ti,am64-sa2ul
|
||||
- ti,am62-sa3ul
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
dmas:
|
||||
items:
|
||||
- description: TX DMA Channel
|
||||
- description: RX DMA Channel #1
|
||||
- description: RX DMA Channel #2
|
||||
|
||||
dma-names:
|
||||
items:
|
||||
- const: tx
|
||||
- const: rx1
|
||||
- const: rx2
|
||||
|
||||
"#address-cells":
|
||||
const: 2
|
||||
|
||||
"#size-cells":
|
||||
const: 2
|
||||
|
||||
ranges:
|
||||
description:
|
||||
Address translation for the possible RNG child node for SA2UL
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Clock used by PKA
|
||||
- description: Main Input Clock
|
||||
- description: Clock used by rng
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pka_in_clk
|
||||
- const: x1_clk
|
||||
- const: x2_clk
|
||||
|
||||
patternProperties:
|
||||
"^rng@[a-f0-9]+$":
|
||||
type: object
|
||||
description:
|
||||
Child RNG node for SA2UL
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- power-domains
|
||||
- dmas
|
||||
- dma-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/soc/ti,sci_pm_domain.h>
|
||||
|
||||
main_crypto: crypto@4e00000 {
|
||||
compatible = "ti,j721e-sa2ul";
|
||||
reg = <0x4e00000 0x1200>;
|
||||
power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
|
||||
dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
|
||||
<&main_udmap 0x4001>;
|
||||
dma-names = "tx", "rx1", "rx2";
|
||||
};
|
||||
37
bindings/crypto/xlnx,zynqmp-aes.yaml
Normal file
37
bindings/crypto/xlnx,zynqmp-aes.yaml
Normal file
@@ -0,0 +1,37 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/xlnx,zynqmp-aes.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Xilinx ZynqMP AES-GCM Hardware Accelerator
|
||||
|
||||
maintainers:
|
||||
- Kalyani Akula <kalyani.akula@xilinx.com>
|
||||
- Michal Simek <michal.simek@xilinx.com>
|
||||
|
||||
description: |
|
||||
The ZynqMP AES-GCM hardened cryptographic accelerator is used to
|
||||
encrypt or decrypt the data with provided key and initialization vector.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: xlnx,zynqmp-aes
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
firmware {
|
||||
zynqmp_firmware: zynqmp-firmware {
|
||||
compatible = "xlnx,zynqmp-firmware";
|
||||
method = "smc";
|
||||
xlnx_aes: zynqmp-aes {
|
||||
compatible = "xlnx,zynqmp-aes";
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
Reference in New Issue
Block a user