dt-bindings: Add devicetree bindings
Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").
Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
This commit is contained in:
Melody Olvera
93
bindings/clock/ti/davinci/da8xx-cfgchip.txt
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93
bindings/clock/ti/davinci/da8xx-cfgchip.txt
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Binding for TI DA8XX/OMAP-L13X/AM17XX/AM18XX CFGCHIP clocks
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TI DA8XX/OMAP-L13X/AM17XX/AM18XX SoCs contain a general purpose set of
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registers call CFGCHIPn. Some of these registers function as clock
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gates. This document describes the bindings for those clocks.
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All of the clock nodes described below must be child nodes of a CFGCHIP node
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(compatible = "ti,da830-cfgchip").
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USB PHY clocks
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--------------
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Required properties:
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- compatible: shall be "ti,da830-usb-phy-clocks".
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- #clock-cells: from common clock binding; shall be set to 1.
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- clocks: phandles to the parent clocks corresponding to clock-names
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- clock-names: shall be "fck", "usb_refclkin", "auxclk"
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This node provides two clocks. The clock at index 0 is the USB 2.0 PHY 48MHz
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clock and the clock at index 1 is the USB 1.1 PHY 48MHz clock.
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eHRPWM Time Base Clock (TBCLK)
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------------------------------
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Required properties:
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- compatible: shall be "ti,da830-tbclksync".
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- #clock-cells: from common clock binding; shall be set to 0.
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- clocks: phandle to the parent clock
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- clock-names: shall be "fck"
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PLL DIV4.5 divider
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------------------
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Required properties:
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- compatible: shall be "ti,da830-div4p5ena".
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- #clock-cells: from common clock binding; shall be set to 0.
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- clocks: phandle to the parent clock
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- clock-names: shall be "pll0_pllout"
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EMIFA clock source (ASYNC1)
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---------------------------
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Required properties:
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- compatible: shall be "ti,da850-async1-clksrc".
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- #clock-cells: from common clock binding; shall be set to 0.
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- clocks: phandles to the parent clocks corresponding to clock-names
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- clock-names: shall be "pll0_sysclk3", "div4.5"
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ASYNC3 clock source
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-------------------
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Required properties:
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- compatible: shall be "ti,da850-async3-clksrc".
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- #clock-cells: from common clock binding; shall be set to 0.
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- clocks: phandles to the parent clocks corresponding to clock-names
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- clock-names: shall be "pll0_sysclk2", "pll1_sysclk2"
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Examples:
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cfgchip: syscon@1417c {
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compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";
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reg = <0x1417c 0x14>;
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usb_phy_clk: usb-phy-clocks {
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compatible = "ti,da830-usb-phy-clocks";
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#clock-cells = <1>;
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clocks = <&psc1 1>, <&usb_refclkin>, <&pll0_auxclk>;
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clock-names = "fck", "usb_refclkin", "auxclk";
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};
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ehrpwm_tbclk: ehrpwm_tbclk {
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compatible = "ti,da830-tbclksync";
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#clock-cells = <0>;
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clocks = <&psc1 17>;
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clock-names = "fck";
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};
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div4p5_clk: div4.5 {
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compatible = "ti,da830-div4p5ena";
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#clock-cells = <0>;
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clocks = <&pll0_pllout>;
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clock-names = "pll0_pllout";
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};
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async1_clk: async1 {
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compatible = "ti,da850-async1-clksrc";
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#clock-cells = <0>;
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clocks = <&pll0_sysclk 3>, <&div4p5_clk>;
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clock-names = "pll0_sysclk3", "div4.5";
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};
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async3_clk: async3 {
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compatible = "ti,da850-async3-clksrc";
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#clock-cells = <0>;
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clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>;
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clock-names = "pll0_sysclk2", "pll1_sysclk2";
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};
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};
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Also see:
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- Documentation/devicetree/bindings/clock/clock-bindings.txt
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96
bindings/clock/ti/davinci/pll.txt
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96
bindings/clock/ti/davinci/pll.txt
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Binding for TI DaVinci PLL Controllers
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The PLL provides clocks to most of the components on the SoC. In addition
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to the PLL itself, this controller also contains bypasses, gates, dividers,
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an multiplexers for various clock signals.
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Required properties:
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- compatible: shall be one of:
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- "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
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- "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
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- reg: physical base address and size of the controller's register area.
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- clocks: phandles corresponding to the clock names
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- clock-names: names of the clock sources - depends on compatible string
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- for "ti,da850-pll0", shall be "clksrc", "extclksrc"
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- for "ti,da850-pll1", shall be "clksrc"
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Optional properties:
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- ti,clkmode-square-wave: Indicates that the board is supplying a square
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wave input on the OSCIN pin instead of using a crystal oscillator.
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This property is only valid when compatible = "ti,da850-pll0".
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Optional child nodes:
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pllout
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Describes the main PLL clock output (before POSTDIV). The node name must
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be "pllout".
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Required properties:
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- #clock-cells: shall be 0
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sysclk
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Describes the PLLDIVn divider clocks that provide the SYSCLKn clock
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domains. The node name must be "sysclk". Consumers of this node should
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use "n" in "SYSCLKn" as the index parameter for the clock cell.
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Required properties:
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- #clock-cells: shall be 1
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auxclk
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Describes the AUXCLK output of the PLL. The node name must be "auxclk".
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This child node is only valid when compatible = "ti,da850-pll0".
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Required properties:
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- #clock-cells: shall be 0
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obsclk
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Describes the OBSCLK output of the PLL. The node name must be "obsclk".
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Required properties:
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- #clock-cells: shall be 0
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Examples:
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pll0: clock-controller@11000 {
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compatible = "ti,da850-pll0";
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reg = <0x11000 0x1000>;
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clocks = <&ref_clk>, <&pll1_sysclk 3>;
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clock-names = "clksrc", "extclksrc";
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ti,clkmode-square-wave;
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pll0_pllout: pllout {
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#clock-cells = <0>;
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};
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pll0_sysclk: sysclk {
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#clock-cells = <1>;
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};
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pll0_auxclk: auxclk {
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#clock-cells = <0>;
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};
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pll0_obsclk: obsclk {
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#clock-cells = <0>;
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};
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};
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pll1: clock-controller@21a000 {
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compatible = "ti,da850-pll1";
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reg = <0x21a000 0x1000>;
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clocks = <&ref_clk>;
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clock-names = "clksrc";
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pll0_sysclk: sysclk {
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#clock-cells = <1>;
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};
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pll0_obsclk: obsclk {
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#clock-cells = <0>;
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};
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};
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Also see:
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- Documentation/devicetree/bindings/clock/clock-bindings.txt
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71
bindings/clock/ti/davinci/psc.txt
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71
bindings/clock/ti/davinci/psc.txt
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@@ -0,0 +1,71 @@
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Binding for TI DaVinci Power Sleep Controller (PSC)
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The PSC provides power management, clock gating and reset functionality. It is
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primarily used for clocking.
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Required properties:
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- compatible: shall be one of:
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- "ti,da850-psc0" for PSC0 on DA850/OMAP-L138/AM18XX
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- "ti,da850-psc1" for PSC1 on DA850/OMAP-L138/AM18XX
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- reg: physical base address and size of the controller's register area
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- #clock-cells: from common clock binding; shall be set to 1
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- #power-domain-cells: from generic power domain binding; shall be set to 1.
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- clocks: phandles to clocks corresponding to the clock-names property
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- clock-names: list of parent clock names - depends on compatible value
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- for "ti,da850-psc0", shall be "pll0_sysclk1", "pll0_sysclk2",
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"pll0_sysclk4", "pll0_sysclk6", "async1"
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- for "ti,da850-psc1", shall be "pll0_sysclk2", "pll0_sysclk4", "async3"
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Optional properties:
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- #reset-cells: from reset binding; shall be set to 1 - only applicable when
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at least one local domain provides a local reset.
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Consumers:
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Clock, power domain and reset consumers shall use the local power domain
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module ID (LPSC) as the index corresponding to the clock cell. Refer to
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the device-specific datasheet to find these numbers. NB: Most local
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domains only provide a clock/power domain and not a reset.
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Examples:
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psc0: clock-controller@10000 {
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compatible = "ti,da850-psc0";
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reg = <0x10000 0x1000>;
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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#reset-cells = <1>;
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clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>,
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<&pll0_sysclk 4>, <&pll0_sysclk 6>, <&async1_clk>;
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clock_names = "pll0_sysclk1", "pll0_sysclk2",
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"pll0_sysclk4", "pll0_sysclk6", "async1";
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};
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psc1: clock-controller@227000 {
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compatible = "ti,da850-psc1";
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reg = <0x227000 0x1000>;
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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clocks = <&pll0_sysclk 2>, <&pll0_sysclk 4>, <&async3_clk>;
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clock_names = "pll0_sysclk2", "pll0_sysclk4", "async3";
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};
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/* consumer */
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dsp: dsp@11800000 {
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compatible = "ti,da850-dsp";
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reg = <0x11800000 0x40000>,
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<0x11e00000 0x8000>,
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<0x11f00000 0x8000>,
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<0x01c14044 0x4>,
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<0x01c14174 0x8>;
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reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig";
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interrupt-parent = <&intc>;
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interrupts = <28>;
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clocks = <&psc0 15>;
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power-domains = <&psc0 15>;
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resets = <&psc0 15>;
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};
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Also see:
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- Documentation/devicetree/bindings/clock/clock-bindings.txt
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- Documentation/devicetree/bindings/power/power-domain.yaml
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- Documentation/devicetree/bindings/reset/reset.txt
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