dt-bindings: Add devicetree bindings
Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").
Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
This commit is contained in:
Melody Olvera
32
bindings/clock/st/st,clkgen-mux.txt
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32
bindings/clock/st/st,clkgen-mux.txt
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Binding for a ST multiplexed clock driver.
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This binding supports only simple indexed multiplexers, it does not
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support table based parent index to hardware value translations.
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be:
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"st,stih407-clkgen-a9-mux"
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- #clock-cells : from common clock binding; shall be set to 0.
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- reg : A Base address and length of the register set.
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- clocks : from common clock binding
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Example:
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clk_m_a9: clk-m-a9@92b0000 {
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#clock-cells = <0>;
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compatible = "st,stih407-clkgen-a9-mux";
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reg = <0x92b0000 0x10000>;
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clocks = <&clockgen_a9_pll 0>,
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<&clockgen_a9_pll 0>,
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<&clk_s_c0_flexgen 13>,
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<&clk_m_a9_ext2f_div2>;
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};
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40
bindings/clock/st/st,clkgen-pll.txt
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40
bindings/clock/st/st,clkgen-pll.txt
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Binding for a ST pll clock driver.
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This binding uses the common clock binding[1].
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Base address is located to the parent node. See clock binding[2]
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
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Required properties:
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- compatible : shall be:
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"st,clkgen-pll0"
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"st,clkgen-pll0-a0"
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"st,clkgen-pll0-c0"
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"st,clkgen-pll1"
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"st,clkgen-pll1-c0"
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"st,stih407-clkgen-plla9"
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"st,stih418-clkgen-plla9"
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- #clock-cells : From common clock binding; shall be set to 1.
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- clocks : From common clock binding
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- clock-output-names : From common clock binding.
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Example:
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clockgen-a9@92b0000 {
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compatible = "st,clkgen-c32";
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reg = <0x92b0000 0xffff>;
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clockgen_a9_pll: clockgen-a9-pll {
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#clock-cells = <1>;
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compatible = "st,stih407-clkgen-plla9";
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clocks = <&clk_sysin>;
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clock-output-names = "clockgen-a9-pll-odf";
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};
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};
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68
bindings/clock/st/st,clkgen.txt
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68
bindings/clock/st/st,clkgen.txt
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Binding for a Clockgen hardware block found on
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certain STMicroelectronics consumer electronics SoC devices.
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A Clockgen node can contain pll, diviser or multiplexer nodes.
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We will find only the base address of the Clockgen, this base
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address is common of all subnode.
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clockgen_node {
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reg = <>;
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pll_node {
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...
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};
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quadfs_node {
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...
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};
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mux_node {
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...
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};
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flexgen_node {
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...
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};
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...
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};
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This binding uses the common clock binding[1].
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Each subnode should use the binding described in [2]..[7]
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[3] Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
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[4] Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
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[7] Documentation/devicetree/bindings/clock/st/st,quadfs.txt
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[8] Documentation/devicetree/bindings/clock/st/st,flexgen.txt
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Required properties:
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- reg : A Base address and length of the register set.
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Example:
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clockgen-a@90ff000 {
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compatible = "st,clkgen-c32";
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reg = <0x90ff000 0x1000>;
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clk_s_a0_pll: clk-s-a0-pll {
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#clock-cells = <1>;
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compatible = "st,clkgen-pll0";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-a0-pll-ofd-0";
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};
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clk_s_a0_flexgen: clk-s-a0-flexgen {
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compatible = "st,flexgen";
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#clock-cells = <1>;
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clocks = <&clk_s_a0_pll 0>,
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<&clk_sysin>;
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clock-output-names = "clk-ic-lmi0";
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};
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};
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133
bindings/clock/st/st,flexgen.txt
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133
bindings/clock/st/st,flexgen.txt
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Binding for a type of flexgen structure found on certain
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STMicroelectronics consumer electronics SoC devices
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This structure includes:
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- a clock cross bar (represented by a mux element)
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- a pre and final dividers (represented by a divider and gate elements)
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Flexgen structure is a part of Clockgen[1].
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Please find an example below:
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Clockgen block diagram
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-------------------------------------------------------------------
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| Flexgen structure |
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| --------------------------------------------- |
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| | ------- -------- -------- | |
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clk_sysin | | | | | | | | |
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---|-----------------|-->| | | | | | | |
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| | | | | | | | | | |
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| | ------- | | | |Pre | |Final | | |
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| | |PLL0 | | | | |Dividers| |Dividers| | |
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| |->| | | | | | x32 | | x32 | | |
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| | | odf_0|----|-->| | | | | | | |
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| | | | | | | | | | | | |
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| | | | | | | | | | | | |
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| | | | | | | | | | | | |
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| | | | | | | | | | | | |
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| | ------- | | | | | | | | |
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| | | | | | | | | | |
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| | ------- | | Clock | | | | | | |
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| | |PLL1 | | | | | | | | | |
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| |->| | | | Cross | | | | | | |
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| | | odf_0|----|-->| | | | | | CLK_DIV[31:0]
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| | | | | | Bar |====>| |====>| |===|=========>
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| | | | | | | | | | | | |
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| | | | | | | | | | | | |
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| | | | | | | | | | | | |
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| | ------- | | | | | | | | |
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| | | | | | | | | | |
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| | ------- | | | | | | | | |
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| | |QUADFS | | | | | | | | | |
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| |->| ch0|----|-->| | | | | | | |
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| | | | | | | | | | | |
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| | ch1|----|-->| | | | | | | |
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| | | | | | | | | | | |
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| | ch2|----|-->| | | DIV | | DIV | | |
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| | | | | | | 1 to | | 1 to | | |
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| | ch3|----|-->| | | 1024 | | 64 | | |
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| ------- | | | | | | | | |
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| | ------- -------- -------- | |
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| -------------------------------------------- |
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| |
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-------------------------------------------------------------------
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This binding uses the common clock binding[2].
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[1] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
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[2] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be:
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"st,flexgen"
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"st,flexgen-audio", "st,flexgen" (enable clock propagation on parent for
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audio use case)
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"st,flexgen-video", "st,flexgen" (enable clock propagation on parent
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and activate synchronous mode)
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"st,flexgen-stih407-a0"
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"st,flexgen-stih410-a0"
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"st,flexgen-stih407-c0"
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"st,flexgen-stih410-c0"
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"st,flexgen-stih418-c0"
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"st,flexgen-stih407-d0"
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"st,flexgen-stih410-d0"
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"st,flexgen-stih407-d2"
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"st,flexgen-stih418-d2"
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"st,flexgen-stih407-d3"
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- #clock-cells : from common clock binding; shall be set to 1 (multiple clock
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outputs).
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- clocks : must be set to the parent's phandle. it could be output clocks of
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a quadsfs or/and a pll or/and clk_sysin (up to 7 clocks)
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- clock-output-names : List of strings used to name the clock outputs.
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Example:
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clk_s_c0_flexgen: clk-s-c0-flexgen {
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#clock-cells = <1>;
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compatible = "st,flexgen";
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clocks = <&clk_s_c0_pll0 0>,
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<&clk_s_c0_pll1 0>,
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<&clk_s_c0_quadfs 0>,
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<&clk_s_c0_quadfs 1>,
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<&clk_s_c0_quadfs 2>,
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<&clk_s_c0_quadfs 3>,
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<&clk_sysin>;
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clock-output-names = "clk-icn-gpu",
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"clk-fdma",
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"clk-nand",
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"clk-hva",
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"clk-proc-stfe",
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"clk-proc-tp",
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"clk-rx-icn-dmu",
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"clk-rx-icn-hva",
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"clk-icn-cpu",
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"clk-tx-icn-dmu",
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"clk-mmc-0",
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"clk-mmc-1",
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"clk-jpegdec",
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"clk-ext2fa9",
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"clk-ic-bdisp-0",
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"clk-ic-bdisp-1",
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"clk-pp-dmu",
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"clk-vid-dmu",
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"clk-dss-lpc",
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"clk-st231-aud-0",
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"clk-st231-gp-1",
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"clk-st231-dmu",
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"clk-icn-lmi",
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"clk-tx-icn-disp-1",
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"clk-icn-sbc",
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"clk-stfe-frc2",
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"clk-eth-phy",
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"clk-eth-ref-phyclk",
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"clk-flash-promip",
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"clk-main-disp",
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"clk-aux-disp",
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"clk-compo-dvp";
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};
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48
bindings/clock/st/st,quadfs.txt
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48
bindings/clock/st/st,quadfs.txt
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@@ -0,0 +1,48 @@
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Binding for a type of quad channel digital frequency synthesizer found on
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certain STMicroelectronics consumer electronics SoC devices.
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This version contains a programmable PLL which can generate up to 216, 432
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or 660MHz (from a 30MHz oscillator input) as the input to the digital
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synthesizers.
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be:
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"st,quadfs"
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"st,quadfs-d0"
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"st,quadfs-d2"
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"st,quadfs-d3"
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"st,quadfs-pll"
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- #clock-cells : from common clock binding; shall be set to 1.
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- reg : A Base address and length of the register set.
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- clocks : from common clock binding
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- clock-output-names : From common clock binding. The block has 4
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clock outputs but not all of them in a specific instance
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have to be used in the SoC. If a clock name is left as
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an empty string then no clock will be created for the
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output associated with that string index. If fewer than
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4 strings are provided then no clocks will be created
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for the remaining outputs.
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Example:
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clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
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#clock-cells = <1>;
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compatible = "st,quadfs-pll";
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reg = <0x9103000 0x1000>;
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-c0-fs0-ch0",
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"clk-s-c0-fs0-ch1",
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"clk-s-c0-fs0-ch2",
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"clk-s-c0-fs0-ch3";
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};
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