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dt-bindings: Add devicetree bindings

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Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").

Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
This commit is contained in:
Melody Olvera
2023-04-03 14:38:11 -07:00
parent c334acf377
commit 6f18ce8026
4878 changed files with 424312 additions and 0 deletions
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52
bindings/clock/actions,owl-cmu.txt Normal file
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* Actions Semi Owl Clock Management Unit (CMU)
The Actions Semi Owl Clock Management Unit generates and supplies clock
to various controllers within the SoC. The clock binding described here is
applicable to S900, S700 and S500 SoC's.
Required Properties:
- compatible: should be one of the following,
"actions,s900-cmu"
"actions,s700-cmu"
"actions,s500-cmu"
- reg: physical base address of the controller and length of memory mapped
region.
- clocks: Reference to the parent clocks ("hosc", "losc")
- #clock-cells: should be 1.
- #reset-cells: should be 1.
Each clock is assigned an identifier, and client nodes can use this identifier
to specify the clock which they consume.
All available clocks are defined as preprocessor macros in corresponding
dt-bindings/clock/actions,s900-cmu.h or actions,s700-cmu.h or
actions,s500-cmu.h header and can be used in device tree sources.
External clocks:
The hosc clock used as input for the plls is generated outside the SoC. It is
expected that it is defined using standard clock bindings as "hosc".
Actions Semi S900 CMU also requires one more clock:
- "losc" - internal low frequency oscillator
Example: Clock Management Unit node:
cmu: clock-controller@e0160000 {
compatible = "actions,s900-cmu";
reg = <0x0 0xe0160000 0x0 0x1000>;
clocks = <&hosc>, <&losc>;
#clock-cells = <1>;
#reset-cells = <1>;
};
Example: UART controller node that consumes clock generated by the clock
management unit:
uart: serial@e012a000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe012a000 0x0 0x2000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_UART5>;
};

54
bindings/clock/adi,axi-clkgen.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/adi,axi-clkgen.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Binding for Analog Devices AXI clkgen pcore clock generator
maintainers:
- Lars-Peter Clausen <lars@metafoo.de>
- Michael Hennerich <michael.hennerich@analog.com>
description: |
The axi_clkgen IP core is a software programmable clock generator,
that can be synthesized on various FPGA platforms.
Link: https://wiki.analog.com/resources/fpga/docs/axi_clkgen
properties:
compatible:
enum:
- adi,axi-clkgen-2.00.a
- adi,zynqmp-axi-clkgen-2.00.a
clocks:
description:
Specifies the reference clock(s) from which the output frequency is
derived. This must either reference one clock if only the first clock
input is connected or two if both clock inputs are connected.
minItems: 1
maxItems: 2
'#clock-cells':
const: 0
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@ff000000 {
compatible = "adi,axi-clkgen-2.00.a";
#clock-cells = <0>;
reg = <0xff000000 0x1000>;
clocks = <&osc 1>;
};

58
bindings/clock/airoha,en7523-scu.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/airoha,en7523-scu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: EN7523 Clock
maintainers:
- Felix Fietkau <nbd@nbd.name>
- John Crispin <nbd@nbd.name>
description: |
This node defines the System Control Unit of the EN7523 SoC,
a collection of registers configuring many different aspects of the SoC.
The clock driver uses it to read and configure settings of the
PLL controller, which provides clocks for the CPU, the bus and
other SoC internal peripherals.
Each clock is assigned an identifier and client nodes use this identifier
to specify which clock they consume.
All these identifiers can be found in:
[1]: <include/dt-bindings/clock/en7523-clk.h>.
The clocks are provided inside a system controller node.
properties:
compatible:
items:
- const: airoha,en7523-scu
reg:
maxItems: 2
"#clock-cells":
description:
The first cell indicates the clock number, see [1] for available
clocks.
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/en7523-clk.h>
scu: system-controller@1fa20000 {
compatible = "airoha,en7523-scu";
reg = <0x1fa20000 0x400>,
<0x1fb00000 0x1000>;
#clock-cells = <1>;
};

108
bindings/clock/allwinner,sun4i-a10-ahb-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ahb-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 AHB Clock
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
deprecated: true
properties:
"#clock-cells":
const: 0
compatible:
enum:
- allwinner,sun4i-a10-ahb-clk
- allwinner,sun6i-a31-ahb1-clk
- allwinner,sun8i-h3-ahb2-clk
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 4
description: >
The parent order must match the hardware programming order.
clock-output-names:
maxItems: 1
required:
- "#clock-cells"
- compatible
- reg
- clocks
- clock-output-names
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
const: allwinner,sun4i-a10-ahb-clk
then:
properties:
clocks:
maxItems: 1
- if:
properties:
compatible:
contains:
const: allwinner,sun6i-a31-ahb1-clk
then:
properties:
clocks:
maxItems: 4
- if:
properties:
compatible:
contains:
const: allwinner,sun8i-h3-ahb2-clk
then:
properties:
clocks:
maxItems: 2
examples:
- |
ahb@1c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-ahb-clk";
reg = <0x01c20054 0x4>;
clocks = <&axi>;
clock-output-names = "ahb";
};
- |
ahb1@1c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun6i-a31-ahb1-clk";
reg = <0x01c20054 0x4>;
clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
clock-output-names = "ahb1";
};
- |
ahb2_clk@1c2005c {
#clock-cells = <0>;
compatible = "allwinner,sun8i-h3-ahb2-clk";
reg = <0x01c2005c 0x4>;
clocks = <&ahb1>, <&pll6d2>;
clock-output-names = "ahb2";
};
...

50
bindings/clock/allwinner,sun4i-a10-apb0-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-apb0-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 APB0 Bus Clock
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
deprecated: true
properties:
"#clock-cells":
const: 0
compatible:
const: allwinner,sun4i-a10-apb0-clk
reg:
maxItems: 1
clocks:
maxItems: 1
clock-output-names:
maxItems: 1
required:
- "#clock-cells"
- compatible
- reg
- clocks
- clock-output-names
additionalProperties: false
examples:
- |
apb0@1c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-apb0-clk";
reg = <0x01c20054 0x4>;
clocks = <&ahb>;
clock-output-names = "apb0";
};
...

52
bindings/clock/allwinner,sun4i-a10-apb1-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-apb1-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 APB1 Bus Clock
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
deprecated: true
properties:
"#clock-cells":
const: 0
compatible:
const: allwinner,sun4i-a10-apb1-clk
reg:
maxItems: 1
clocks:
maxItems: 3
description: >
The parent order must match the hardware programming order.
clock-output-names:
maxItems: 1
required:
- "#clock-cells"
- compatible
- reg
- clocks
- clock-output-names
additionalProperties: false
examples:
- |
clk@1c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-apb1-clk";
reg = <0x01c20058 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
clock-output-names = "apb1";
};
...

61
bindings/clock/allwinner,sun4i-a10-axi-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-axi-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 AXI Clock
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
deprecated: true
properties:
"#clock-cells":
const: 0
compatible:
enum:
- allwinner,sun4i-a10-axi-clk
- allwinner,sun8i-a23-axi-clk
reg:
maxItems: 1
clocks:
maxItems: 1
clock-output-names:
maxItems: 1
required:
- "#clock-cells"
- compatible
- reg
- clocks
- clock-output-names
additionalProperties: false
examples:
- |
axi@1c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-axi-clk";
reg = <0x01c20054 0x4>;
clocks = <&cpu>;
clock-output-names = "axi";
};
- |
axi_clk@1c20050 {
#clock-cells = <0>;
compatible = "allwinner,sun8i-a23-axi-clk";
reg = <0x01c20050 0x4>;
clocks = <&cpu>;
clock-output-names = "axi";
};
...

153
bindings/clock/allwinner,sun4i-a10-ccu.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ccu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner Clock Control Unit
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
properties:
"#clock-cells":
const: 1
"#reset-cells":
const: 1
compatible:
enum:
- allwinner,sun4i-a10-ccu
- allwinner,sun5i-a10s-ccu
- allwinner,sun5i-a13-ccu
- allwinner,sun6i-a31-ccu
- allwinner,sun7i-a20-ccu
- allwinner,sun8i-a23-ccu
- allwinner,sun8i-a33-ccu
- allwinner,sun8i-a83t-ccu
- allwinner,sun8i-a83t-r-ccu
- allwinner,sun8i-h3-ccu
- allwinner,sun8i-h3-r-ccu
- allwinner,sun8i-r40-ccu
- allwinner,sun8i-v3-ccu
- allwinner,sun8i-v3s-ccu
- allwinner,sun9i-a80-ccu
- allwinner,sun20i-d1-ccu
- allwinner,sun20i-d1-r-ccu
- allwinner,sun50i-a64-ccu
- allwinner,sun50i-a64-r-ccu
- allwinner,sun50i-a100-ccu
- allwinner,sun50i-a100-r-ccu
- allwinner,sun50i-h5-ccu
- allwinner,sun50i-h6-ccu
- allwinner,sun50i-h6-r-ccu
- allwinner,sun50i-h616-ccu
- allwinner,sun50i-h616-r-ccu
- allwinner,suniv-f1c100s-ccu
- nextthing,gr8-ccu
reg:
maxItems: 1
clocks:
minItems: 2
items:
- description: High Frequency Oscillator (usually at 24MHz)
- description: Low Frequency Oscillator (usually at 32kHz)
- description: Internal Oscillator
- description: Peripherals PLL
clock-names:
minItems: 2
items:
- const: hosc
- const: losc
- const: iosc
- const: pll-periph
required:
- "#clock-cells"
- "#reset-cells"
- compatible
- reg
- clocks
- clock-names
if:
properties:
compatible:
enum:
- allwinner,sun8i-a83t-r-ccu
- allwinner,sun8i-h3-r-ccu
- allwinner,sun20i-d1-r-ccu
- allwinner,sun50i-a64-r-ccu
- allwinner,sun50i-a100-r-ccu
- allwinner,sun50i-h6-r-ccu
- allwinner,sun50i-h616-r-ccu
then:
properties:
clocks:
minItems: 4
maxItems: 4
clock-names:
minItems: 4
maxItems: 4
else:
if:
properties:
compatible:
enum:
- allwinner,sun20i-d1-ccu
- allwinner,sun50i-a100-ccu
- allwinner,sun50i-h6-ccu
- allwinner,sun50i-h616-ccu
then:
properties:
clocks:
minItems: 3
maxItems: 3
clock-names:
minItems: 3
maxItems: 3
else:
properties:
clocks:
minItems: 2
maxItems: 2
clock-names:
minItems: 2
maxItems: 2
additionalProperties: false
examples:
- |
ccu: clock@1c20000 {
compatible = "allwinner,sun8i-h3-ccu";
reg = <0x01c20000 0x400>;
clocks = <&osc24M>, <&osc32k>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
};
- |
r_ccu: clock@1f01400 {
compatible = "allwinner,sun50i-a64-r-ccu";
reg = <0x01f01400 0x100>;
clocks = <&osc24M>, <&osc32k>, <&iosc>, <&ccu 11>;
clock-names = "hosc", "losc", "iosc", "pll-periph";
#clock-cells = <1>;
#reset-cells = <1>;
};
...

52
bindings/clock/allwinner,sun4i-a10-cpu-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-cpu-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 CPU Clock
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
deprecated: true
properties:
"#clock-cells":
const: 0
compatible:
const: allwinner,sun4i-a10-cpu-clk
reg:
maxItems: 1
clocks:
maxItems: 4
description: >
The parent order must match the hardware programming order.
clock-output-names:
maxItems: 1
required:
- "#clock-cells"
- compatible
- reg
- clocks
- clock-output-names
additionalProperties: false
examples:
- |
cpu@1c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-cpu-clk";
reg = <0x01c20054 0x4>;
clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
clock-output-names = "cpu";
};
...

57
bindings/clock/allwinner,sun4i-a10-display-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-display-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 Display Clock
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
deprecated: true
properties:
"#clock-cells":
const: 0
"#reset-cells":
const: 0
compatible:
const: allwinner,sun4i-a10-display-clk
reg:
maxItems: 1
clocks:
maxItems: 3
description: >
The parent order must match the hardware programming order.
clock-output-names:
maxItems: 1
required:
- "#clock-cells"
- "#reset-cells"
- compatible
- reg
- clocks
- clock-output-names
additionalProperties: false
examples:
- |
clk@1c20104 {
#clock-cells = <0>;
#reset-cells = <0>;
compatible = "allwinner,sun4i-a10-display-clk";
reg = <0x01c20104 0x4>;
clocks = <&pll3>, <&pll7>, <&pll5 1>;
clock-output-names = "de-be";
};
...

152
bindings/clock/allwinner,sun4i-a10-gates-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-gates-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 Bus Gates Clock
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
deprecated: true
properties:
"#clock-cells":
const: 1
description: >
This additional argument passed to that clock is the offset of
the bit controlling this particular gate in the register.
compatible:
oneOf:
- const: allwinner,sun4i-a10-gates-clk
- const: allwinner,sun4i-a10-axi-gates-clk
- const: allwinner,sun4i-a10-ahb-gates-clk
- const: allwinner,sun5i-a10s-ahb-gates-clk
- const: allwinner,sun5i-a13-ahb-gates-clk
- const: allwinner,sun7i-a20-ahb-gates-clk
- const: allwinner,sun6i-a31-ahb1-gates-clk
- const: allwinner,sun8i-a23-ahb1-gates-clk
- const: allwinner,sun9i-a80-ahb0-gates-clk
- const: allwinner,sun9i-a80-ahb1-gates-clk
- const: allwinner,sun9i-a80-ahb2-gates-clk
- const: allwinner,sun4i-a10-apb0-gates-clk
- const: allwinner,sun5i-a10s-apb0-gates-clk
- const: allwinner,sun5i-a13-apb0-gates-clk
- const: allwinner,sun7i-a20-apb0-gates-clk
- const: allwinner,sun9i-a80-apb0-gates-clk
- const: allwinner,sun8i-a83t-apb0-gates-clk
- const: allwinner,sun4i-a10-apb1-gates-clk
- const: allwinner,sun5i-a13-apb1-gates-clk
- const: allwinner,sun5i-a10s-apb1-gates-clk
- const: allwinner,sun6i-a31-apb1-gates-clk
- const: allwinner,sun7i-a20-apb1-gates-clk
- const: allwinner,sun8i-a23-apb1-gates-clk
- const: allwinner,sun9i-a80-apb1-gates-clk
- const: allwinner,sun6i-a31-apb2-gates-clk
- const: allwinner,sun8i-a23-apb2-gates-clk
- const: allwinner,sun8i-a83t-bus-gates-clk
- const: allwinner,sun9i-a80-apbs-gates-clk
- const: allwinner,sun4i-a10-dram-gates-clk
- items:
- const: allwinner,sun5i-a13-dram-gates-clk
- const: allwinner,sun4i-a10-gates-clk
- items:
- const: allwinner,sun8i-h3-apb0-gates-clk
- const: allwinner,sun4i-a10-gates-clk
reg:
maxItems: 1
clocks:
maxItems: 1
clock-indices:
minItems: 1
maxItems: 64
clock-output-names:
minItems: 1
maxItems: 64
required:
- "#clock-cells"
- compatible
- reg
- clocks
- clock-indices
- clock-output-names
additionalProperties: false
examples:
- |
clk@1c2005c {
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-axi-gates-clk";
reg = <0x01c2005c 0x4>;
clocks = <&axi>;
clock-indices = <0>;
clock-output-names = "axi_dram";
};
- |
clk@1c20060 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-ahb-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb>;
clock-indices = <0>, <1>,
<2>, <3>,
<4>, <5>, <6>,
<7>, <8>, <9>,
<10>, <11>, <12>,
<13>, <14>, <16>,
<17>, <18>, <20>,
<21>, <22>, <23>,
<24>, <25>, <26>,
<32>, <33>, <34>,
<35>, <36>, <37>,
<40>, <41>, <43>,
<44>, <45>,
<46>, <47>,
<50>, <52>;
clock-output-names = "ahb_usb0", "ahb_ehci0",
"ahb_ohci0", "ahb_ehci1",
"ahb_ohci1", "ahb_ss", "ahb_dma",
"ahb_bist", "ahb_mmc0", "ahb_mmc1",
"ahb_mmc2", "ahb_mmc3", "ahb_ms",
"ahb_nand", "ahb_sdram", "ahb_ace",
"ahb_emac", "ahb_ts", "ahb_spi0",
"ahb_spi1", "ahb_spi2", "ahb_spi3",
"ahb_pata", "ahb_sata", "ahb_gps",
"ahb_ve", "ahb_tvd", "ahb_tve0",
"ahb_tve1", "ahb_lcd0", "ahb_lcd1",
"ahb_csi0", "ahb_csi1", "ahb_hdmi",
"ahb_de_be0", "ahb_de_be1",
"ahb_de_fe0", "ahb_de_fe1",
"ahb_mp", "ahb_mali400";
};
- |
clk@1c20068 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-apb0-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb0>;
clock-indices = <0>, <1>,
<2>, <3>,
<5>, <6>,
<7>, <10>;
clock-output-names = "apb0_codec", "apb0_spdif",
"apb0_ac97", "apb0_iis",
"apb0_pio", "apb0_ir0",
"apb0_ir1", "apb0_keypad";
};
...

63
bindings/clock/allwinner,sun4i-a10-mbus-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mbus-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 MBUS Clock
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
deprecated: true
properties:
"#clock-cells":
const: 0
compatible:
enum:
- allwinner,sun5i-a13-mbus-clk
- allwinner,sun8i-a23-mbus-clk
reg:
maxItems: 1
clocks:
maxItems: 3
description: >
The parent order must match the hardware programming order.
clock-output-names:
maxItems: 1
required:
- "#clock-cells"
- compatible
- reg
- clocks
- clock-output-names
additionalProperties: false
examples:
- |
clk@1c2015c {
#clock-cells = <0>;
compatible = "allwinner,sun5i-a13-mbus-clk";
reg = <0x01c2015c 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mbus";
};
- |
clk@1c2015c {
#clock-cells = <0>;
compatible = "allwinner,sun8i-a23-mbus-clk";
reg = <0x01c2015c 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5>;
clock-output-names = "mbus";
};
...

87
bindings/clock/allwinner,sun4i-a10-mmc-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mmc-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 Module 1 Clock
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
deprecated: true
properties:
"#clock-cells":
const: 1
description: >
There is three different outputs: the main clock, with the ID 0,
and the output and sample clocks, with the IDs 1 and 2,
respectively.
compatible:
enum:
- allwinner,sun4i-a10-mmc-clk
- allwinner,sun9i-a80-mmc-clk
reg:
maxItems: 1
clocks:
minItems: 2
maxItems: 3
description: >
The parent order must match the hardware programming order.
clock-output-names:
maxItems: 3
required:
- "#clock-cells"
- compatible
- reg
- clocks
- clock-output-names
additionalProperties: false
if:
properties:
compatible:
contains:
const: allwinner,sun4i-a10-mmc-clk
then:
properties:
clocks:
maxItems: 3
else:
properties:
clocks:
maxItems: 2
examples:
- |
clk@1c20088 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c20088 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc0",
"mmc0_output",
"mmc0_sample";
};
- |
clk@6000410 {
#clock-cells = <1>;
compatible = "allwinner,sun9i-a80-mmc-clk";
reg = <0x06000410 0x4>;
clocks = <&osc24M>, <&pll4>;
clock-output-names = "mmc0", "mmc0_output",
"mmc0_sample";
};
...

80
bindings/clock/allwinner,sun4i-a10-mod0-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mod0-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 Module 0 Clock
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
deprecated: true
select:
properties:
compatible:
contains:
enum:
- allwinner,sun4i-a10-mod0-clk
- allwinner,sun9i-a80-mod0-clk
# The PRCM on the A31 and A23 will have the reg property missing,
# since it's set at the upper level node, and will be validated by
# PRCM's schema. Make sure we only validate standalone nodes.
required:
- compatible
- reg
properties:
"#clock-cells":
const: 0
compatible:
enum:
- allwinner,sun4i-a10-mod0-clk
- allwinner,sun9i-a80-mod0-clk
reg:
maxItems: 1
clocks:
# On the A80, the PRCM mod0 clocks have 2 parents.
minItems: 2
maxItems: 3
description: >
The parent order must match the hardware programming order.
clock-output-names:
maxItems: 1
required:
- "#clock-cells"
- compatible
- reg
- clocks
- clock-output-names
additionalProperties: false
examples:
- |
clk@1c20080 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c20080 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "nand";
};
- |
clk@8001454 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x08001454 0x4>;
clocks = <&osc32k>, <&osc24M>;
clock-output-names = "r_ir";
};
...

57
bindings/clock/allwinner,sun4i-a10-mod1-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mod1-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 Module 1 Clock
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
deprecated: true
properties:
"#clock-cells":
const: 0
compatible:
const: allwinner,sun4i-a10-mod1-clk
reg:
maxItems: 1
clocks:
maxItems: 4
description: >
The parent order must match the hardware programming order.
clock-output-names:
maxItems: 1
required:
- "#clock-cells"
- compatible
- reg
- clocks
- clock-output-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/sun4i-a10-pll2.h>
clk@1c200c0 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod1-clk";
reg = <0x01c200c0 0x4>;
clocks = <&pll2 SUN4I_A10_PLL2_8X>,
<&pll2 SUN4I_A10_PLL2_4X>,
<&pll2 SUN4I_A10_PLL2_2X>,
<&pll2 SUN4I_A10_PLL2_1X>;
clock-output-names = "spdif";
};
...

51
bindings/clock/allwinner,sun4i-a10-osc-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-osc-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 Gatable Oscillator Clock
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
deprecated: true
properties:
"#clock-cells":
const: 0
compatible:
const: allwinner,sun4i-a10-osc-clk
reg:
maxItems: 1
clock-frequency:
description: >
Frequency of the main oscillator.
clock-output-names:
maxItems: 1
required:
- "#clock-cells"
- compatible
- reg
- clock-frequency
- clock-output-names
additionalProperties: false
examples:
- |
osc24M: clk@1c20050 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-osc-clk";
reg = <0x01c20050 0x4>;
clock-frequency = <24000000>;
clock-output-names = "osc24M";
};
...

71
bindings/clock/allwinner,sun4i-a10-pll1-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll1-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 CPU PLL
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
deprecated: true
properties:
"#clock-cells":
const: 0
compatible:
enum:
- allwinner,sun4i-a10-pll1-clk
- allwinner,sun6i-a31-pll1-clk
- allwinner,sun8i-a23-pll1-clk
reg:
maxItems: 1
clocks:
maxItems: 1
clock-output-names:
maxItems: 1
required:
- "#clock-cells"
- compatible
- reg
- clocks
- clock-output-names
additionalProperties: false
examples:
- |
clk@1c20000 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-pll1-clk";
reg = <0x01c20000 0x4>;
clocks = <&osc24M>;
clock-output-names = "osc24M";
};
- |
clk@1c20000 {
#clock-cells = <0>;
compatible = "allwinner,sun6i-a31-pll1-clk";
reg = <0x01c20000 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll1";
};
- |
clk@1c20000 {
#clock-cells = <0>;
compatible = "allwinner,sun8i-a23-pll1-clk";
reg = <0x01c20000 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll1";
};
...

50
bindings/clock/allwinner,sun4i-a10-pll3-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll3-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 Video PLL
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
deprecated: true
properties:
"#clock-cells":
const: 0
compatible:
const: allwinner,sun4i-a10-pll3-clk
reg:
maxItems: 1
clocks:
maxItems: 1
clock-output-names:
maxItems: 1
required:
- "#clock-cells"
- compatible
- reg
- clocks
- clock-output-names
additionalProperties: false
examples:
- |
clk@1c20010 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-pll3-clk";
reg = <0x01c20010 0x4>;
clocks = <&osc3M>;
clock-output-names = "pll3";
};
...

53
bindings/clock/allwinner,sun4i-a10-pll5-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll5-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 DRAM PLL
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
deprecated: true
properties:
"#clock-cells":
const: 1
description: >
The first output is the DRAM clock output, the second is meant
for peripherals on the SoC.
compatible:
const: allwinner,sun4i-a10-pll5-clk
reg:
maxItems: 1
clocks:
maxItems: 1
clock-output-names:
maxItems: 2
required:
- "#clock-cells"
- compatible
- reg
- clocks
- clock-output-names
additionalProperties: false
examples:
- |
clk@1c20020 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-pll5-clk";
reg = <0x01c20020 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll5_ddr", "pll5_other";
};
...

53
bindings/clock/allwinner,sun4i-a10-pll6-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll6-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 Peripheral PLL
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
deprecated: true
properties:
"#clock-cells":
const: 1
description: >
The first output is the SATA clock output, the second is the
regular PLL output, the third is a PLL output at twice the rate.
compatible:
const: allwinner,sun4i-a10-pll6-clk
reg:
maxItems: 1
clocks:
maxItems: 1
clock-output-names:
maxItems: 3
required:
- "#clock-cells"
- compatible
- reg
- clocks
- clock-output-names
additionalProperties: false
examples:
- |
clk@1c20028 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-pll6-clk";
reg = <0x01c20028 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll6_sata", "pll6_other", "pll6";
};
...

77
bindings/clock/allwinner,sun4i-a10-tcon-ch0-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-tcon-ch0-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 TCON Channel 0 Clock
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
deprecated: true
properties:
"#clock-cells":
const: 0
"#reset-cells":
const: 1
compatible:
enum:
- allwinner,sun4i-a10-tcon-ch0-clk
- allwinner,sun4i-a10-tcon-ch1-clk
reg:
maxItems: 1
clocks:
maxItems: 4
description: >
The parent order must match the hardware programming order.
clock-output-names:
maxItems: 1
required:
- "#clock-cells"
- compatible
- reg
- clocks
- clock-output-names
if:
properties:
compatible:
contains:
const: allwinner,sun4i-a10-tcon-ch0-clk
then:
required:
- "#reset-cells"
additionalProperties: false
examples:
- |
clk@1c20118 {
#clock-cells = <0>;
#reset-cells = <1>;
compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
reg = <0x01c20118 0x4>;
clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
clock-output-names = "tcon-ch0-sclk";
};
- |
clk@1c2012c {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
reg = <0x01c2012c 0x4>;
clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
clock-output-names = "tcon-ch1-sclk";
};
...

166
bindings/clock/allwinner,sun4i-a10-usb-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-usb-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 USB Clock
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
deprecated: true
properties:
"#clock-cells":
const: 1
description: >
The additional ID argument passed to the clock shall refer to
the index of the output.
"#reset-cells":
const: 1
compatible:
enum:
- allwinner,sun4i-a10-usb-clk
- allwinner,sun5i-a13-usb-clk
- allwinner,sun6i-a31-usb-clk
- allwinner,sun8i-a23-usb-clk
- allwinner,sun8i-h3-usb-clk
reg:
maxItems: 1
clocks:
maxItems: 1
clock-output-names:
minItems: 2
maxItems: 8
required:
- "#clock-cells"
- "#reset-cells"
- compatible
- reg
- clocks
- clock-output-names
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
const: allwinner,sun4i-a10-usb-clk
then:
properties:
clock-output-names:
maxItems: 3
- if:
properties:
compatible:
contains:
const: allwinner,sun5i-a13-usb-clk
then:
properties:
clock-output-names:
maxItems: 2
- if:
properties:
compatible:
contains:
const: allwinner,sun6i-a31-usb-clk
then:
properties:
clock-output-names:
maxItems: 6
- if:
properties:
compatible:
contains:
const: allwinner,sun8i-a23-usb-clk
then:
properties:
clock-output-names:
maxItems: 5
- if:
properties:
compatible:
contains:
const: allwinner,sun8i-h3-usb-clk
then:
properties:
clock-output-names:
maxItems: 8
examples:
- |
clk@1c200cc {
#clock-cells = <1>;
#reset-cells = <1>;
compatible = "allwinner,sun4i-a10-usb-clk";
reg = <0x01c200cc 0x4>;
clocks = <&pll6 1>;
clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
};
- |
clk@1c200cc {
#clock-cells = <1>;
#reset-cells = <1>;
compatible = "allwinner,sun5i-a13-usb-clk";
reg = <0x01c200cc 0x4>;
clocks = <&pll6 1>;
clock-output-names = "usb_ohci0", "usb_phy";
};
- |
clk@1c200cc {
#clock-cells = <1>;
#reset-cells = <1>;
compatible = "allwinner,sun6i-a31-usb-clk";
reg = <0x01c200cc 0x4>;
clocks = <&osc24M>;
clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
"usb_ohci0", "usb_ohci1",
"usb_ohci2";
};
- |
clk@1c200cc {
#clock-cells = <1>;
#reset-cells = <1>;
compatible = "allwinner,sun8i-a23-usb-clk";
reg = <0x01c200cc 0x4>;
clocks = <&osc24M>;
clock-output-names = "usb_phy0", "usb_phy1", "usb_hsic",
"usb_hsic_12M", "usb_ohci0";
};
- |
clk@1c200cc {
#clock-cells = <1>;
#reset-cells = <1>;
compatible = "allwinner,sun8i-h3-usb-clk";
reg = <0x01c200cc 0x4>;
clocks = <&osc24M>;
clock-output-names = "usb_phy0", "usb_phy1",
"usb_phy2", "usb_phy3",
"usb_ohci0", "usb_ohci1",
"usb_ohci2", "usb_ohci3";
};
...

55
bindings/clock/allwinner,sun4i-a10-ve-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ve-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 Video Engine Clock
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
deprecated: true
properties:
"#clock-cells":
const: 0
"#reset-cells":
const: 0
compatible:
const: allwinner,sun4i-a10-ve-clk
reg:
maxItems: 1
clocks:
maxItems: 1
clock-output-names:
maxItems: 1
required:
- "#clock-cells"
- "#reset-cells"
- compatible
- reg
- clocks
- clock-output-names
additionalProperties: false
examples:
- |
clk@1c2013c {
#clock-cells = <0>;
#reset-cells = <0>;
compatible = "allwinner,sun4i-a10-ve-clk";
reg = <0x01c2013c 0x4>;
clocks = <&pll4>;
clock-output-names = "ve";
};
...

52
bindings/clock/allwinner,sun5i-a13-ahb-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun5i-a13-ahb-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A13 AHB Clock
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
deprecated: true
properties:
"#clock-cells":
const: 0
compatible:
const: allwinner,sun5i-a13-ahb-clk
reg:
maxItems: 1
clocks:
maxItems: 3
description: >
The parent order must match the hardware programming order.
clock-output-names:
maxItems: 1
required:
- "#clock-cells"
- compatible
- reg
- clocks
- clock-output-names
additionalProperties: false
examples:
- |
ahb@1c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun5i-a13-ahb-clk";
reg = <0x01c20054 0x4>;
clocks = <&axi>, <&cpu>, <&pll6 1>;
clock-output-names = "ahb";
};
...

53
bindings/clock/allwinner,sun6i-a31-pll6-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun6i-a31-pll6-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A31 Peripheral PLL
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
deprecated: true
properties:
"#clock-cells":
const: 1
description: >
The first output is the regular PLL output, the second is a PLL
output at twice the rate.
compatible:
const: allwinner,sun6i-a31-pll6-clk
reg:
maxItems: 1
clocks:
maxItems: 1
clock-output-names:
maxItems: 2
required:
- "#clock-cells"
- compatible
- reg
- clocks
- clock-output-names
additionalProperties: false
examples:
- |
clk@1c20028 {
#clock-cells = <1>;
compatible = "allwinner,sun6i-a31-pll6-clk";
reg = <0x01c20028 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll6", "pll6x2";
};
...

51
bindings/clock/allwinner,sun7i-a20-gmac-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun7i-a20-gmac-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A20 GMAC TX Clock
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
properties:
"#clock-cells":
const: 0
compatible:
const: allwinner,sun7i-a20-gmac-clk
reg:
maxItems: 1
clocks:
maxItems: 2
description: >
The parent clocks shall be fixed rate dummy clocks at 25 MHz and
125 MHz, respectively.
clock-output-names:
maxItems: 1
required:
- "#clock-cells"
- compatible
- reg
- clocks
- clock-output-names
additionalProperties: false
examples:
- |
clk@1c20164 {
#clock-cells = <0>;
compatible = "allwinner,sun7i-a20-gmac-clk";
reg = <0x01c20164 0x4>;
clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
clock-output-names = "gmac_tx";
};
...

52
bindings/clock/allwinner,sun7i-a20-out-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun7i-a20-out-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A20 Output Clock
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
deprecated: true
properties:
"#clock-cells":
const: 0
compatible:
const: allwinner,sun7i-a20-out-clk
reg:
maxItems: 1
clocks:
maxItems: 3
description: >
The parent order must match the hardware programming order.
clock-output-names:
maxItems: 1
required:
- "#clock-cells"
- compatible
- reg
- clocks
- clock-output-names
additionalProperties: false
examples:
- |
clk@1c201f0 {
#clock-cells = <0>;
compatible = "allwinner,sun7i-a20-out-clk";
reg = <0x01c201f0 0x4>;
clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
clock-output-names = "clk_out_a";
};
...

79
bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0+
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun8i-a83t-de2-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A83t Display Engine 2/3 Clock Controller
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
properties:
"#clock-cells":
const: 1
"#reset-cells":
const: 1
compatible:
oneOf:
- const: allwinner,sun8i-a83t-de2-clk
- const: allwinner,sun8i-h3-de2-clk
- const: allwinner,sun8i-v3s-de2-clk
- const: allwinner,sun50i-a64-de2-clk
- const: allwinner,sun50i-h5-de2-clk
- const: allwinner,sun50i-h6-de3-clk
- items:
- const: allwinner,sun8i-r40-de2-clk
- const: allwinner,sun8i-h3-de2-clk
- items:
- const: allwinner,sun20i-d1-de2-clk
- const: allwinner,sun50i-h5-de2-clk
reg:
maxItems: 1
clocks:
items:
- description: Bus Clock
- description: Module Clock
clock-names:
items:
- const: bus
- const: mod
resets:
maxItems: 1
required:
- "#clock-cells"
- "#reset-cells"
- compatible
- reg
- clocks
- clock-names
- resets
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/sun8i-h3-ccu.h>
#include <dt-bindings/reset/sun8i-h3-ccu.h>
de2_clocks: clock@1000000 {
compatible = "allwinner,sun8i-h3-de2-clk";
reg = <0x01000000 0x100000>;
clocks = <&ccu CLK_BUS_DE>,
<&ccu CLK_DE>;
clock-names = "bus",
"mod";
resets = <&ccu RST_BUS_DE>;
#clock-cells = <1>;
#reset-cells = <1>;
};
...

103
bindings/clock/allwinner,sun8i-h3-bus-gates-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun8i-h3-bus-gates-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 Bus Gates Clock
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
deprecated: true
properties:
"#clock-cells":
const: 1
description: >
This additional argument passed to that clock is the offset of
the bit controlling this particular gate in the register.
compatible:
const: allwinner,sun8i-h3-bus-gates-clk
reg:
maxItems: 1
clocks:
maxItems: 4
clock-names:
maxItems: 4
description: >
The parent order must match the hardware programming order.
clock-indices:
minItems: 1
maxItems: 64
clock-output-names:
minItems: 1
maxItems: 64
required:
- "#clock-cells"
- compatible
- reg
- clocks
- clock-indices
- clock-names
- clock-output-names
additionalProperties: false
examples:
- |
clk@1c20060 {
#clock-cells = <1>;
compatible = "allwinner,sun8i-h3-bus-gates-clk";
reg = <0x01c20060 0x14>;
clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
clock-names = "ahb1", "ahb2", "apb1", "apb2";
clock-indices = <5>, <6>, <8>,
<9>, <10>, <13>,
<14>, <17>, <18>,
<19>, <20>,
<21>, <23>,
<24>, <25>,
<26>, <27>,
<28>, <29>,
<30>, <31>, <32>,
<35>, <36>, <37>,
<40>, <41>, <43>,
<44>, <52>, <53>,
<54>, <64>,
<65>, <69>, <72>,
<76>, <77>, <78>,
<96>, <97>, <98>,
<112>, <113>,
<114>, <115>,
<116>, <128>, <135>;
clock-output-names = "bus_ce", "bus_dma", "bus_mmc0",
"bus_mmc1", "bus_mmc2", "bus_nand",
"bus_sdram", "bus_gmac", "bus_ts",
"bus_hstimer", "bus_spi0",
"bus_spi1", "bus_otg",
"bus_otg_ehci0", "bus_ehci1",
"bus_ehci2", "bus_ehci3",
"bus_otg_ohci0", "bus_ohci1",
"bus_ohci2", "bus_ohci3", "bus_ve",
"bus_lcd0", "bus_lcd1", "bus_deint",
"bus_csi", "bus_tve", "bus_hdmi",
"bus_de", "bus_gpu", "bus_msgbox",
"bus_spinlock", "bus_codec",
"bus_spdif", "bus_pio", "bus_ths",
"bus_i2s0", "bus_i2s1", "bus_i2s2",
"bus_i2c0", "bus_i2c1", "bus_i2c2",
"bus_uart0", "bus_uart1",
"bus_uart2", "bus_uart3",
"bus_scr", "bus_ephy", "bus_dbg";
};
...

52
bindings/clock/allwinner,sun9i-a80-ahb-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-ahb-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A80 AHB Clock
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
deprecated: true
properties:
"#clock-cells":
const: 0
compatible:
const: allwinner,sun9i-a80-ahb-clk
reg:
maxItems: 1
clocks:
maxItems: 4
description: >
The parent order must match the hardware programming order.
clock-output-names:
maxItems: 1
required:
- "#clock-cells"
- compatible
- reg
- clocks
- clock-output-names
additionalProperties: false
examples:
- |
clk@6000060 {
#clock-cells = <0>;
compatible = "allwinner,sun9i-a80-ahb-clk";
reg = <0x06000060 0x4>;
clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
clock-output-names = "ahb0";
};
...

63
bindings/clock/allwinner,sun9i-a80-apb0-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-apb0-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A80 APB0 Bus Clock
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
deprecated: true
properties:
"#clock-cells":
const: 0
compatible:
enum:
- allwinner,sun9i-a80-apb0-clk
- allwinner,sun9i-a80-apb1-clk
reg:
maxItems: 1
clocks:
maxItems: 2
description: >
The parent order must match the hardware programming order.
clock-output-names:
maxItems: 1
required:
- "#clock-cells"
- compatible
- reg
- clocks
- clock-output-names
additionalProperties: false
examples:
- |
clk@6000070 {
#clock-cells = <0>;
compatible = "allwinner,sun9i-a80-apb0-clk";
reg = <0x06000070 0x4>;
clocks = <&osc24M>, <&pll4>;
clock-output-names = "apb0";
};
- |
clk@6000074 {
#clock-cells = <0>;
compatible = "allwinner,sun9i-a80-apb1-clk";
reg = <0x06000074 0x4>;
clocks = <&osc24M>, <&pll4>;
clock-output-names = "apb1";
};
...

52
bindings/clock/allwinner,sun9i-a80-cpus-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-cpus-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A80 CPUS Clock
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
deprecated: true
properties:
"#clock-cells":
const: 0
compatible:
const: allwinner,sun9i-a80-cpus-clk
reg:
maxItems: 1
clocks:
maxItems: 4
description: >
The parent order must match the hardware programming order.
clock-output-names:
maxItems: 1
required:
- "#clock-cells"
- compatible
- reg
- clocks
- clock-output-names
additionalProperties: false
examples:
- |
clk@8001410 {
compatible = "allwinner,sun9i-a80-cpus-clk";
reg = <0x08001410 0x4>;
#clock-cells = <0>;
clocks = <&osc32k>, <&osc24M>, <&pll4>, <&pll3>;
clock-output-names = "cpus";
};
...

67
bindings/clock/allwinner,sun9i-a80-de-clks.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0+
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-de-clks.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A80 Display Engine Clock Controller
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
properties:
"#clock-cells":
const: 1
"#reset-cells":
const: 1
compatible:
const: allwinner,sun9i-a80-de-clks
reg:
maxItems: 1
clocks:
items:
- description: Bus Clock
- description: RAM Bus Clock
- description: Module Clock
clock-names:
items:
- const: mod
- const: dram
- const: bus
resets:
maxItems: 1
required:
- "#clock-cells"
- "#reset-cells"
- compatible
- reg
- clocks
- clock-names
- resets
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/sun9i-a80-ccu.h>
#include <dt-bindings/reset/sun9i-a80-ccu.h>
de_clocks: clock@3000000 {
compatible = "allwinner,sun9i-a80-de-clks";
reg = <0x03000000 0x30>;
clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>;
clock-names = "mod", "dram", "bus";
resets = <&ccu RST_BUS_DE>;
#clock-cells = <1>;
#reset-cells = <1>;
};
...

52
bindings/clock/allwinner,sun9i-a80-gt-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-gt-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A80 GT Bus Clock
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
deprecated: true
properties:
"#clock-cells":
const: 0
compatible:
const: allwinner,sun9i-a80-gt-clk
reg:
maxItems: 1
clocks:
maxItems: 4
description: >
The parent order must match the hardware programming order.
clock-output-names:
maxItems: 1
required:
- "#clock-cells"
- compatible
- reg
- clocks
- clock-output-names
additionalProperties: false
examples:
- |
clk@600005c {
#clock-cells = <0>;
compatible = "allwinner,sun9i-a80-gt-clk";
reg = <0x0600005c 0x4>;
clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
clock-output-names = "gt";
};
...

68
bindings/clock/allwinner,sun9i-a80-mmc-config-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-mmc-config-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A80 MMC Configuration Clock
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
deprecated: true
description: >
There is one clock/reset output per mmc controller. The number of
outputs is determined by the size of the address block, which is
related to the overall mmc block.
properties:
"#clock-cells":
const: 1
description: >
The additional ID argument passed to the clock shall refer to
the index of the output.
"#reset-cells":
const: 1
compatible:
const: allwinner,sun9i-a80-mmc-config-clk
reg:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
clock-output-names:
maxItems: 4
required:
- "#clock-cells"
- "#reset-cells"
- compatible
- reg
- clocks
- clock-output-names
additionalProperties: false
examples:
- |
clk@1c13000 {
#clock-cells = <1>;
#reset-cells = <1>;
compatible = "allwinner,sun9i-a80-mmc-config-clk";
reg = <0x01c13000 0x10>;
clocks = <&ahb0_gates 8>;
resets = <&ahb0_resets 8>;
clock-output-names = "mmc0_config", "mmc1_config",
"mmc2_config", "mmc3_config";
};
...

50
bindings/clock/allwinner,sun9i-a80-pll4-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-pll4-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A80 Peripheral PLL
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
deprecated: true
properties:
"#clock-cells":
const: 0
compatible:
const: allwinner,sun9i-a80-pll4-clk
reg:
maxItems: 1
clocks:
maxItems: 1
clock-output-names:
maxItems: 1
required:
- "#clock-cells"
- compatible
- reg
- clocks
- clock-output-names
additionalProperties: false
examples:
- |
clk@600000c {
#clock-cells = <0>;
compatible = "allwinner,sun9i-a80-pll4-clk";
reg = <0x0600000c 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll4";
};
...

59
bindings/clock/allwinner,sun9i-a80-usb-clks.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0+
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-usb-clks.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A80 USB Clock Controller
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
properties:
"#clock-cells":
const: 1
"#reset-cells":
const: 1
compatible:
const: allwinner,sun9i-a80-usb-clks
reg:
maxItems: 1
clocks:
items:
- description: Bus Clock
- description: High Frequency Oscillator
clock-names:
items:
- const: bus
- const: hosc
required:
- "#clock-cells"
- "#reset-cells"
- compatible
- reg
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/sun9i-a80-ccu.h>
usb_clocks: clock@a08000 {
compatible = "allwinner,sun9i-a80-usb-clks";
reg = <0x00a08000 0x8>;
clocks = <&ccu CLK_BUS_USB>, <&osc24M>;
clock-names = "bus", "hosc";
#clock-cells = <1>;
#reset-cells = <1>;
};
...

60
bindings/clock/allwinner,sun9i-a80-usb-mod-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-usb-mod-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A80 USB Module Clock
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
deprecated: true
properties:
"#clock-cells":
const: 1
description: >
The additional ID argument passed to the clock shall refer to
the index of the output.
"#reset-cells":
const: 1
compatible:
const: allwinner,sun9i-a80-usb-mod-clk
reg:
maxItems: 1
clocks:
maxItems: 1
clock-output-names:
maxItems: 6
required:
- "#clock-cells"
- "#reset-cells"
- compatible
- reg
- clocks
- clock-output-names
additionalProperties: false
examples:
- |
clk@a08000 {
#clock-cells = <1>;
#reset-cells = <1>;
compatible = "allwinner,sun9i-a80-usb-mod-clk";
reg = <0x00a08000 0x4>;
clocks = <&ahb1_gates 1>;
clock-output-names = "usb0_ahb", "usb_ohci0",
"usb1_ahb", "usb_ohci1",
"usb2_ahb", "usb_ohci2";
};
...

60
bindings/clock/allwinner,sun9i-a80-usb-phy-clk.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-usb-phy-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A80 USB PHY Clock
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
deprecated: true
properties:
"#clock-cells":
const: 1
description: >
The additional ID argument passed to the clock shall refer to
the index of the output.
"#reset-cells":
const: 1
compatible:
const: allwinner,sun9i-a80-usb-phy-clk
reg:
maxItems: 1
clocks:
maxItems: 1
clock-output-names:
maxItems: 6
required:
- "#clock-cells"
- "#reset-cells"
- compatible
- reg
- clocks
- clock-output-names
additionalProperties: false
examples:
- |
clk@a08004 {
#clock-cells = <1>;
#reset-cells = <1>;
compatible = "allwinner,sun9i-a80-usb-phy-clk";
reg = <0x00a08004 0x4>;
clocks = <&ahb1_gates 1>;
clock-output-names = "usb_phy0", "usb_hsic1_480M",
"usb_phy1", "usb_hsic2_480M",
"usb_phy2", "usb_hsic_12M";
};
...

114
bindings/clock/alphascale,acc.txt Normal file
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Alphascale Clock Controller
The ACC (Alphascale Clock Controller) is responsible of choising proper
clock source, setting deviders and clock gates.
Required properties for the ACC node:
- compatible: must be "alphascale,asm9260-clock-controller"
- reg: must contain the ACC register base and size
- #clock-cells : shall be set to 1.
Simple one-cell clock specifier format is used, where the only cell is used
as an index of the clock inside the provider.
It is encouraged to use dt-binding for clock index definitions. SoC specific
dt-binding should be included to the device tree descriptor. For example
Alphascale ASM9260:
#include <dt-bindings/clock/alphascale,asm9260.h>
This binding contains two types of clock providers:
_AHB_ - AHB gate;
_SYS_ - adjustable clock source. Not all peripheral have _SYS_ clock provider.
All clock specific details can be found in the SoC documentation.
CLKID_AHB_ROM 0
CLKID_AHB_RAM 1
CLKID_AHB_GPIO 2
CLKID_AHB_MAC 3
CLKID_AHB_EMI 4
CLKID_AHB_USB0 5
CLKID_AHB_USB1 6
CLKID_AHB_DMA0 7
CLKID_AHB_DMA1 8
CLKID_AHB_UART0 9
CLKID_AHB_UART1 10
CLKID_AHB_UART2 11
CLKID_AHB_UART3 12
CLKID_AHB_UART4 13
CLKID_AHB_UART5 14
CLKID_AHB_UART6 15
CLKID_AHB_UART7 16
CLKID_AHB_UART8 17
CLKID_AHB_UART9 18
CLKID_AHB_I2S0 19
CLKID_AHB_I2C0 20
CLKID_AHB_I2C1 21
CLKID_AHB_SSP0 22
CLKID_AHB_IOCONFIG 23
CLKID_AHB_WDT 24
CLKID_AHB_CAN0 25
CLKID_AHB_CAN1 26
CLKID_AHB_MPWM 27
CLKID_AHB_SPI0 28
CLKID_AHB_SPI1 29
CLKID_AHB_QEI 30
CLKID_AHB_QUADSPI0 31
CLKID_AHB_CAMIF 32
CLKID_AHB_LCDIF 33
CLKID_AHB_TIMER0 34
CLKID_AHB_TIMER1 35
CLKID_AHB_TIMER2 36
CLKID_AHB_TIMER3 37
CLKID_AHB_IRQ 38
CLKID_AHB_RTC 39
CLKID_AHB_NAND 40
CLKID_AHB_ADC0 41
CLKID_AHB_LED 42
CLKID_AHB_DAC0 43
CLKID_AHB_LCD 44
CLKID_AHB_I2S1 45
CLKID_AHB_MAC1 46
CLKID_SYS_CPU 47
CLKID_SYS_AHB 48
CLKID_SYS_I2S0M 49
CLKID_SYS_I2S0S 50
CLKID_SYS_I2S1M 51
CLKID_SYS_I2S1S 52
CLKID_SYS_UART0 53
CLKID_SYS_UART1 54
CLKID_SYS_UART2 55
CLKID_SYS_UART3 56
CLKID_SYS_UART4 56
CLKID_SYS_UART5 57
CLKID_SYS_UART6 58
CLKID_SYS_UART7 59
CLKID_SYS_UART8 60
CLKID_SYS_UART9 61
CLKID_SYS_SPI0 62
CLKID_SYS_SPI1 63
CLKID_SYS_QUADSPI 64
CLKID_SYS_SSP0 65
CLKID_SYS_NAND 66
CLKID_SYS_TRACE 67
CLKID_SYS_CAMM 68
CLKID_SYS_WDT 69
CLKID_SYS_CLKOUT 70
CLKID_SYS_MAC 71
CLKID_SYS_LCD 72
CLKID_SYS_ADCANA 73
Example of clock consumer with _SYS_ and _AHB_ sinks.
uart4: serial@80010000 {
compatible = "alphascale,asm9260-uart";
reg = <0x80010000 0x4000>;
clocks = <&acc CLKID_SYS_UART4>, <&acc CLKID_AHB_UART4>;
interrupts = <19>;
};
Clock consumer with only one, _AHB_ sink.
timer0: timer@80088000 {
compatible = "alphascale,asm9260-timer";
reg = <0x80088000 0x4000>;
clocks = <&acc CLKID_AHB_TIMER0>;
interrupts = <29>;
};

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Device Tree Clock bindings for Altera's SoCFPGA platform
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be one of the following:
"altr,socfpga-pll-clock" - for a PLL clock
"altr,socfpga-perip-clock" - The peripheral clock divided from the
PLL clock.
"altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
can get gated.
- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
- clocks : shall be the input parent clock phandle for the clock. This is
either an oscillator or a pll output.
- #clock-cells : from common clock binding, shall be set to 0.
Optional properties:
- fixed-divider : If clocks have a fixed divider value, use this property.
- clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
and the bit index.
- div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains
the divider register, bit shift, and width.
- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
hold/delay times that is needed for the SD/MMC CIU clock. The values of both
can be 0-315 degrees, in 45 degree increments.

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* Amlogic AXG Audio Clock Controllers
The Amlogic AXG audio clock controller generates and supplies clock to the
other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
devices.
Required Properties:
- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D,
"amlogic,g12a-audio-clkc" for G12A,
"amlogic,sm1-audio-clkc" for S905X3.
- reg : physical base address of the clock controller and length of
memory mapped region.
- clocks : a list of phandle + clock-specifier pairs for the clocks listed
in clock-names.
- clock-names : must contain the following:
* "pclk" - Main peripheral bus clock
may contain the following:
* "mst_in[0-7]" - 8 input plls to generate clock signals
* "slv_sclk[0-9]" - 10 slave bit clocks provided by external
components.
* "slv_lrclk[0-9]" - 10 slave sample clocks provided by external
components.
- resets : phandle of the internal reset line
- #clock-cells : should be 1.
- #reset-cells : should be 1 on the g12a (and following) soc family
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be
used in device tree sources.
Example:
clkc_audio: clock-controller@0 {
compatible = "amlogic,axg-audio-clkc";
reg = <0x0 0x0 0x0 0xb4>;
#clock-cells = <1>;
clocks = <&clkc CLKID_AUDIO>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL3>,
<&clkc CLKID_HIFI_PLL>,
<&clkc CLKID_FCLK_DIV3>,
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_GP0_PLL>;
clock-names = "pclk",
"mst_in0",
"mst_in1",
"mst_in2",
"mst_in3",
"mst_in4",
"mst_in5",
"mst_in6",
"mst_in7";
resets = <&reset RESET_AUDIO>;
};

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* Amlogic GXBB AO Clock and Reset Unit
The Amlogic GXBB AO clock controller generates and supplies clock to various
controllers within the Always-On part of the SoC.
Required Properties:
- compatible: value should be different for each SoC family as :
- GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
- GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
- GXM (S912) : "amlogic,meson-gxm-aoclkc"
- AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
- G12A (S905X2, S905D2, S905Y2) : "amlogic,meson-g12a-aoclkc"
followed by the common "amlogic,meson-gx-aoclkc"
- clocks: list of clock phandle, one for each entry clock-names.
- clock-names: should contain the following:
* "xtal" : the platform xtal
* "mpeg-clk" : the main clock controller mother clock (aka clk81)
* "ext-32k-0" : external 32kHz reference #0 if any (optional)
* "ext-32k-1" : external 32kHz reference #1 if any (optional - gx only)
* "ext-32k-2" : external 32kHz reference #2 if any (optional - gx only)
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/gxbb-aoclkc.h header and can be
used in device tree sources.
- #reset-cells: should be 1.
Each reset is assigned an identifier and client nodes can use this identifier
to specify the reset which they consume. All available resets are defined as
preprocessor macros in the dt-bindings/reset/gxbb-aoclkc.h header and can be
used in device tree sources.
Parent node should have the following properties :
- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"
- reg: base address and size of the AO system control register space.
Example: AO Clock controller node:
ao_sysctrl: sys-ctrl@0 {
compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
reg = <0x0 0x0 0x0 0x100>;
clkc_AO: clock-controller {
compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
#clock-cells = <1>;
#reset-cells = <1>;
clocks = <&xtal>, <&clkc CLKID_CLK81>;
clock-names = "xtal", "mpeg-clk";
};
Example: UART controller node that consumes the clock and reset generated
by the clock controller:
uart_AO: serial@4c0 {
compatible = "amlogic,meson-uart";
reg = <0x4c0 0x14>;
interrupts = <0 90 1>;
clocks = <&clkc_AO CLKID_AO_UART1>;
resets = <&clkc_AO RESET_AO_UART1>;
};

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* Amlogic GXBB Clock and Reset Unit
The Amlogic GXBB clock controller generates and supplies clock to various
controllers within the SoC.
Required Properties:
- compatible: should be:
"amlogic,gxbb-clkc" for GXBB SoC,
"amlogic,gxl-clkc" for GXL and GXM SoC,
"amlogic,axg-clkc" for AXG SoC.
"amlogic,g12a-clkc" for G12A SoC.
"amlogic,g12b-clkc" for G12B SoC.
"amlogic,sm1-clkc" for SM1 SoC.
- clocks : list of clock phandle, one for each entry clock-names.
- clock-names : should contain the following:
* "xtal": the platform xtal
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/gxbb-clkc.h header and can be
used in device tree sources.
Parent node should have the following properties :
- compatible: "syscon", "simple-mfd, and "amlogic,meson-gx-hhi-sysctrl" or
"amlogic,meson-axg-hhi-sysctrl"
- reg: base address and size of the HHI system control register space.
Example: Clock controller node:
sysctrl: system-controller@0 {
compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd";
reg = <0 0 0 0x400>;
clkc: clock-controller {
#clock-cells = <1>;
compatible = "amlogic,gxbb-clkc";
clocks = <&xtal>;
clock-names = "xtal";
};
};
Example: UART controller node that consumes the clock generated by the clock
controller:
uart_AO: serial@c81004c0 {
compatible = "amlogic,meson-uart";
reg = <0xc81004c0 0x14>;
interrupts = <0 90 1>;
clocks = <&clkc CLKID_CLK81>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/amlogic,meson8-ddr-clkc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic DDR Clock Controller
maintainers:
- Martin Blumenstingl <martin.blumenstingl@googlemail.com>
properties:
compatible:
enum:
- amlogic,meson8-ddr-clkc
- amlogic,meson8b-ddr-clkc
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: xtal
"#clock-cells":
const: 1
required:
- compatible
- reg
- clocks
- clock-names
- "#clock-cells"
additionalProperties: false
examples:
- |
ddr_clkc: clock-controller@400 {
compatible = "amlogic,meson8-ddr-clkc";
reg = <0x400 0x20>;
clocks = <&xtal>;
clock-names = "xtal";
#clock-cells = <1>;
};
...

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* Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit
The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and
supplies clock to various controllers within the SoC.
Required Properties:
- compatible: must be one of:
- "amlogic,meson8-clkc" for Meson8 (S802) SoCs
- "amlogic,meson8b-clkc" for Meson8 (S805) SoCs
- "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
- #clock-cells: should be 1.
- #reset-cells: should be 1.
- clocks: list of clock phandles, one for each entry in clock-names
- clock-names: should contain the following:
* "xtal": the 24MHz system oscillator
* "ddr_pll": the DDR PLL clock
* "clk_32k": (if present) the 32kHz clock signal from GPIOAO_6 (CLK_32K_IN)
Parent node should have the following properties :
- compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon"
- reg: base address and size of the HHI system control register space.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be
used in device tree sources.
Similarly a preprocessor macro for each reset line is defined in
dt-bindings/reset/amlogic,meson8b-clkc-reset.h (which can be used from the
device tree sources).
Example: Clock controller node:
clkc: clock-controller {
compatible = "amlogic,meson8b-clkc";
#clock-cells = <1>;
#reset-cells = <1>;
};
Example: UART controller node that consumes the clock generated by the clock
controller:
uart_AO: serial@c81004c0 {
compatible = "amlogic,meson-uart";
reg = <0xc81004c0 0x14>;
interrupts = <0 90 1>;
clocks = <&clkc CLKID_CLK81>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/apple,nco.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Apple SoCs' NCO block
maintainers:
- Martin Povišer <povik+lin@cutebit.org>
description: |
The NCO (Numerically Controlled Oscillator) block found on Apple SoCs
such as the t8103 (M1) is a programmable clock generator performing
fractional division of a high frequency input clock.
It carries a number of independent channels and is typically used for
generation of audio bitclocks.
properties:
compatible:
items:
- enum:
- apple,t6000-nco
- apple,t8103-nco
- const: apple,nco
clocks:
description:
Specifies the reference clock from which the output clocks
are derived through fractional division.
maxItems: 1
'#clock-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- clocks
- '#clock-cells'
- reg
additionalProperties: false
examples:
- |
nco_clkref: clock-ref {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <900000000>;
clock-output-names = "nco-ref";
};
nco: clock-controller@23b044000 {
compatible = "apple,t8103-nco", "apple,nco";
reg = <0x3b044000 0x14000>;
#clock-cells = <1>;
clocks = <&nco_clkref>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/arm,syscon-icst.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM System Controller ICST Clocks
maintainers:
- Linus Walleij <linusw@kernel.org>
description: |
The ICS525 and ICS307 oscillators are produced by Integrated
Devices Technology (IDT). ARM integrated these oscillators deeply into their
reference designs by adding special control registers that manage such
oscillators to their system controllers.
The various ARM system controllers contain logic to serialize and initialize
an ICST clock request after a write to the 32 bit register at an offset
into the system controller. Furthermore, to even be able to alter one of
these frequencies, the system controller must first be unlocked by
writing a special token to another offset in the system controller.
Some ARM hardware contain special versions of the serial interface that only
connects the low 8 bits of the VDW (missing one bit), hard-wires RDW to
different values and sometimes also hard-wires the output divider. They
therefore have special compatible strings as per this table (the OD value is
the value on the pins, not the resulting output divider).
In the core modules and logic tiles, the ICST is a configurable clock fed
from a 24 MHz clock on the motherboard (usually the main crystal) used for
generating e.g. video clocks. It is located on the core module and there is
only one of these. This clock node must be a subnode of the core module.
Hardware variant RDW OD VDW
Integrator/AP 22 1 Bit 8 0, rest variable
integratorap-cm
Integrator/AP 46 3 Bit 8 0, rest variable
integratorap-sys
Integrator/AP 22 or 1 17 or (33 or 25 MHz)
integratorap-pci 14 1 14
Integrator/CP 22 variable Bit 8 0, rest variable
integratorcp-cm-core
Integrator/CP 22 variable Bit 8 0, rest variable
integratorcp-cm-mem
The ICST oscillator must be provided inside a system controller node.
properties:
"#clock-cells":
const: 0
compatible:
enum:
- arm,syscon-icst525
- arm,syscon-icst307
- arm,syscon-icst525-integratorap-cm
- arm,syscon-icst525-integratorap-sys
- arm,syscon-icst525-integratorap-pci
- arm,syscon-icst525-integratorcp-cm-core
- arm,syscon-icst525-integratorcp-cm-mem
- arm,integrator-cm-auxosc
- arm,versatile-cm-auxosc
- arm,impd1-vco1
- arm,impd1-vco2
reg:
maxItems: 1
description: The VCO register
clocks:
description: Parent clock for the ICST VCO
maxItems: 1
clock-output-names:
maxItems: 1
lock-offset:
$ref: '/schemas/types.yaml#/definitions/uint32'
description: Offset to the unlocking register for the oscillator
vco-offset:
$ref: '/schemas/types.yaml#/definitions/uint32'
description: Offset to the VCO register for the oscillator
deprecated: true
required:
- "#clock-cells"
- compatible
- clocks
additionalProperties: false
examples:
- |
vco1: clock {
compatible = "arm,impd1-vco1";
#clock-cells = <0>;
lock-offset = <0x08>;
vco-offset = <0x00>;
clocks = <&sysclk>;
clock-output-names = "IM-PD1-VCO1";
};
...

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* Peripheral Clock bindings for Marvell Armada 37xx SoCs
Marvell Armada 37xx SoCs provide peripheral clocks which are
used as clock source for the peripheral of the SoC.
There are two different blocks associated to north bridge and south
bridge.
The peripheral clock consumer should specify the desired clock by
having the clock ID in its "clocks" phandle cell.
The following is a list of provided IDs for Armada 3700 North bridge clocks:
ID Clock name Description
-----------------------------------
0 mmc MMC controller
1 sata_host Sata Host
2 sec_at Security AT
3 sac_dap Security DAP
4 tsecm Security Engine
5 setm_tmx Serial Embedded Trace Module
6 avs Adaptive Voltage Scaling
7 sqf SPI
8 pwm PWM
9 i2c_2 I2C 2
10 i2c_1 I2C 1
11 ddr_phy DDR PHY
12 ddr_fclk DDR F clock
13 trace Trace
14 counter Counter
15 eip97 EIP 97
16 cpu CPU
The following is a list of provided IDs for Armada 3700 South bridge clocks:
ID Clock name Description
-----------------------------------
0 gbe-50 50 MHz parent clock for Gigabit Ethernet
1 gbe-core parent clock for Gigabit Ethernet core
2 gbe-125 125 MHz parent clock for Gigabit Ethernet
3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
7 gbe1-core Gigabit Ethernet core port 1
8 gbe0-core Gigabit Ethernet core port 0
9 gbe-bm Gigabit Ethernet Buffer Manager
10 sdio SDIO
11 usb32-sub2-sys USB 2 clock
12 usb32-ss-sys USB 3 clock
13 pcie PCIe controller
Required properties:
- compatible : shall be "marvell,armada-3700-periph-clock-nb" for the
north bridge block, or
"marvell,armada-3700-periph-clock-sb" for the south bridge block
- reg : must be the register address of North/South Bridge Clock register
- #clock-cells : from common clock binding; shall be set to 1
- clocks : list of the parent clock phandle in the following order:
TBG-A P, TBG-B P, TBG-A S, TBG-B S and finally the xtal clock.
Example:
nb_perih_clk: nb-periph-clk@13000{
compatible = "marvell,armada-3700-periph-clock-nb";
reg = <0x13000 0x1000>;
clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
<&tbg 3>, <&xtalclk>;
#clock-cells = <1>;
};

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* Time Base Generator Clock bindings for Marvell Armada 37xx SoCs
Marvell Armada 37xx SoCs provide Time Base Generator clocks which are
used as parent clocks for the peripheral clocks.
The TBG clock consumer should specify the desired clock by having the
clock ID in its "clocks" phandle cell.
The following is a list of provided IDs and clock names on Armada 3700:
0 = TBG A P
1 = TBG B P
2 = TBG A S
3 = TBG B S
Required properties:
- compatible : shall be "marvell,armada-3700-tbg-clock"
- reg : must be the register address of North Bridge PLL register
- #clock-cells : from common clock binding; shall be set to 1
Example:
tbg: tbg@13200 {
compatible = "marvell,armada-3700-tbg-clock";
reg = <0x13200 0x1000>;
clocks = <&xtalclk>;
#clock-cells = <1>;
};

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* Xtal Clock bindings for Marvell Armada 37xx SoCs
Marvell Armada 37xx SoCs allow to determine the xtal clock frequencies by
reading the gpio latch register.
This node must be a subnode of the node exposing the register address
of the GPIO block where the gpio latch is located.
See Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
Required properties:
- compatible : shall be one of the following:
"marvell,armada-3700-xtal-clock"
- #clock-cells : from common clock binding; shall be set to 0
Optional properties:
- clock-output-names : from common clock binding; allows overwrite default clock
output names ("xtal")
Example:
pinctrl_nb: pinctrl-nb@13800 {
compatible = "armada3710-nb-pinctrl", "syscon", "simple-mfd";
reg = <0x13800 0x100>, <0x13C00 0x20>;
xtalclk: xtal-clk {
compatible = "marvell,armada-3700-xtal-clock";
clock-output-names = "xtal";
#clock-cells = <0>;
};
};

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* Clock bindings for Axis ARTPEC-6 chip
The bindings are based on the clock provider binding in
Documentation/devicetree/bindings/clock/clock-bindings.txt
External clocks:
----------------
There are two external inputs to the main clock controller which should be
provided using the common clock bindings.
- "sys_refclk": External 50 Mhz oscillator (required)
- "i2s_refclk": Alternate audio reference clock (optional).
Main clock controller
---------------------
Required properties:
- #clock-cells: Should be <1>
See dt-bindings/clock/axis,artpec6-clkctrl.h for the list of valid identifiers.
- compatible: Should be "axis,artpec6-clkctrl"
- reg: Must contain the base address and length of the system controller
- clocks: Must contain a phandle entry for each clock in clock-names
- clock-names: Must include the external oscillator ("sys_refclk"). Optional
ones are the audio reference clock ("i2s_refclk") and the audio fractional
dividers ("frac_clk0" and "frac_clk1").
Examples:
ext_clk: ext_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
clkctrl: clkctrl@f8000000 {
#clock-cells = <1>;
compatible = "axis,artpec6-clkctrl";
reg = <0xf8000000 0x48>;
clocks = <&ext_clk>;
clock-names = "sys_refclk";
};

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Device Tree Clock bindings for arch-at91
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Slow Clock controller:
Required properties:
- compatible : shall be one of the following:
"atmel,at91sam9x5-sckc",
"atmel,sama5d3-sckc",
"atmel,sama5d4-sckc" or
"microchip,sam9x60-sckc":
at91 SCKC (Slow Clock Controller)
- #clock-cells : shall be 1 for "microchip,sam9x60-sckc" otherwise shall be 0.
- clocks : shall be the input parent clock phandle for the clock.
Optional properties:
- atmel,osc-bypass : boolean property. Set this when a clock signal is directly
provided on XIN.
For example:
sckc@fffffe50 {
compatible = "atmel,at91sam9x5-sckc";
reg = <0xfffffe50 0x4>;
clocks = <&slow_xtal>;
#clock-cells = <0>;
};
Power Management Controller (PMC):
Required properties:
- compatible : shall be "atmel,<chip>-pmc", "syscon" or
"microchip,sam9x60-pmc"
<chip> can be: at91rm9200, at91sam9260, at91sam9261,
at91sam9263, at91sam9g45, at91sam9n12, at91sam9rl, at91sam9g15,
at91sam9g25, at91sam9g35, at91sam9x25, at91sam9x35, at91sam9x5,
sama5d2, sama5d3 or sama5d4.
- #clock-cells : from common clock binding; shall be set to 2. The first entry
is the type of the clock (core, system, peripheral or generated) and the
second entry its index as provided by the datasheet
- clocks : Must contain an entry for each entry in clock-names.
- clock-names: Must include the following entries: "slow_clk", "main_xtal"
Optional properties:
- atmel,osc-bypass : boolean property. Set this when a clock signal is directly
provided on XIN.
For example:
pmc: pmc@f0018000 {
compatible = "atmel,sama5d4-pmc", "syscon";
reg = <0xf0018000 0x120>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
#clock-cells = <2>;
clocks = <&clk32k>, <&main_xtal>;
clock-names = "slow_clk", "main_xtal";
};

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Binding for the AXS10X I2S PLL clock
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible: shall be "snps,axs10x-i2s-pll-clock"
- reg : address and length of the I2S PLL register set.
- clocks: shall be the input parent clock phandle for the PLL.
- #clock-cells: from common clock binding; Should always be set to 0.
Example:
pll_clock: pll_clock {
compatible = "fixed-clock";
clock-frequency = <27000000>;
#clock-cells = <0>;
};
i2s_clock@100a0 {
compatible = "snps,axs10x-i2s-pll-clock";
reg = <0x100a0 0x10>;
clocks = <&pll_clock>;
#clock-cells = <0>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Baikal-T1 Clock Control Unit Dividers
maintainers:
- Serge Semin <fancer.lancer@gmail.com>
description: |
Clocks Control Unit is the core of Baikal-T1 SoC System Controller
responsible for the chip subsystems clocking and resetting. The CCU is
connected with an external fixed rate oscillator, which signal is transformed
into clocks of various frequencies and then propagated to either individual
IP-blocks or to groups of blocks (clock domains). The transformation is done
by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
later ones are described in this binding. Each clock domain can be also
individually reset by using the domain clocks divider configuration
registers. Baikal-T1 CCU is logically divided into the next components:
1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but
in general can provide any frequency supported by the CCU PLLs).
2) PLLs clocks generators (PLLs).
3) AXI-bus clock dividers (AXI) - described in this binding file.
4) System devices reference clock dividers (SYS) - described in this binding
file.
which are connected with each other as shown on the next figure:
+---------------+
| Baikal-T1 CCU |
| +----+------|- MIPS P5600 cores
| +-|PLLs|------|- DDR controller
| | +----+ |
+----+ | | | | |
|XTAL|--|-+ | | +---+-|
+----+ | | | +-|AXI|-|- AXI-bus
| | | +---+-|
| | | |
| | +----+---+-|- APB-bus
| +-------|SYS|-|- Low-speed Devices
| +---+-|- High-speed Devices
+---------------+
Each sub-block is represented as a separate DT node and has an individual
driver to be bound with.
In order to create signals of wide range frequencies the external oscillator
output is primarily connected to a set of CCU PLLs. Some of PLLs CLKOUT are
then passed over CCU dividers to create signals required for the target clock
domain (like AXI-bus or System Device consumers). The dividers have the
following structure:
+--------------+
CLKIN --|->+----+ 1|\ |
SETCLK--|--|/DIV|->| | |
CLKDIV--|--| | | |-|->CLKLOUT
LOCK----|--+----+ | | |
| |/ |
| | |
EN------|-----------+ |
RST-----|--------------|->RSTOUT
+--------------+
where CLKIN is the reference clock coming either from CCU PLLs or from an
external clock oscillator, SETCLK - a command to update the output clock in
accordance with a set divider, CLKDIV - clocks divider, LOCK - a signal of
the output clock stabilization, EN - enable/disable the divider block,
RST/RSTOUT - reset clocks domain signal. Depending on the consumer IP-core
peculiarities the dividers may lack of some functionality depicted on the
figure above (like EN, CLKDIV/LOCK/SETCLK). In this case the corresponding
clock provider just doesn't expose either switching functions, or the rate
configuration, or both of them.
The clock dividers, which output clock is then consumed by the SoC individual
devices, are united into a single clocks provider called System Devices CCU.
Similarly the dividers with output clocks utilized as AXI-bus reference clocks
are called AXI-bus CCU. Both of them use the common clock bindings with no
custom properties. The list of exported clocks and reset signals can be found
in the files: 'include/dt-bindings/clock/bt1-ccu.h' and
'include/dt-bindings/reset/bt1-ccu.h'. Since System Devices and AXI-bus CCU
are a part of the Baikal-T1 SoC System Controller their DT nodes are supposed
to be a children of later one.
if:
properties:
compatible:
contains:
const: baikal,bt1-ccu-axi
then:
properties:
clocks:
items:
- description: CCU SATA PLL output clock
- description: CCU PCIe PLL output clock
- description: CCU Ethernet PLL output clock
clock-names:
items:
- const: sata_clk
- const: pcie_clk
- const: eth_clk
else:
properties:
clocks:
items:
- description: External reference clock
- description: CCU SATA PLL output clock
- description: CCU PCIe PLL output clock
- description: CCU Ethernet PLL output clock
clock-names:
items:
- const: ref_clk
- const: sata_clk
- const: pcie_clk
- const: eth_clk
properties:
compatible:
enum:
- baikal,bt1-ccu-axi
- baikal,bt1-ccu-sys
reg:
maxItems: 1
"#clock-cells":
const: 1
"#reset-cells":
const: 1
clocks: true
clock-names: true
additionalProperties: false
required:
- compatible
- "#clock-cells"
- clocks
- clock-names
examples:
# AXI-bus Clock Control Unit node:
- |
#include <dt-bindings/clock/bt1-ccu.h>
clock-controller@1f04d030 {
compatible = "baikal,bt1-ccu-axi";
reg = <0x1f04d030 0x030>;
#clock-cells = <1>;
#reset-cells = <1>;
clocks = <&ccu_pll CCU_SATA_PLL>,
<&ccu_pll CCU_PCIE_PLL>,
<&ccu_pll CCU_ETH_PLL>;
clock-names = "sata_clk", "pcie_clk", "eth_clk";
};
# System Devices Clock Control Unit node:
- |
#include <dt-bindings/clock/bt1-ccu.h>
clock-controller@1f04d060 {
compatible = "baikal,bt1-ccu-sys";
reg = <0x1f04d060 0x0a0>;
#clock-cells = <1>;
#reset-cells = <1>;
clocks = <&clk25m>,
<&ccu_pll CCU_SATA_PLL>,
<&ccu_pll CCU_PCIE_PLL>,
<&ccu_pll CCU_ETH_PLL>;
clock-names = "ref_clk", "sata_clk", "pcie_clk",
"eth_clk";
};
# Required Clock Control Unit PLL node:
- |
ccu_pll: clock-controller@1f04d000 {
compatible = "baikal,bt1-ccu-pll";
reg = <0x1f04d000 0x028>;
#clock-cells = <1>;
clocks = <&clk25m>;
clock-names = "ref_clk";
};
...

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Baikal-T1 Clock Control Unit PLL
maintainers:
- Serge Semin <fancer.lancer@gmail.com>
description: |
Clocks Control Unit is the core of Baikal-T1 SoC System Controller
responsible for the chip subsystems clocking and resetting. The CCU is
connected with an external fixed rate oscillator, which signal is transformed
into clocks of various frequencies and then propagated to either individual
IP-blocks or to groups of blocks (clock domains). The transformation is done
by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
It's logically divided into the next components:
1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but
in general can provide any frequency supported by the CCU PLLs).
2) PLLs clocks generators (PLLs) - described in this binding file.
3) AXI-bus clock dividers (AXI).
4) System devices reference clock dividers (SYS).
which are connected with each other as shown on the next figure:
+---------------+
| Baikal-T1 CCU |
| +----+------|- MIPS P5600 cores
| +-|PLLs|------|- DDR controller
| | +----+ |
+----+ | | | | |
|XTAL|--|-+ | | +---+-|
+----+ | | | +-|AXI|-|- AXI-bus
| | | +---+-|
| | | |
| | +----+---+-|- APB-bus
| +-------|SYS|-|- Low-speed Devices
| +---+-|- High-speed Devices
+---------------+
Each CCU sub-block is represented as a separate dts-node and has an
individual driver to be bound with.
In order to create signals of wide range frequencies the external oscillator
output is primarily connected to a set of CCU PLLs. There are five PLLs
to create a clock for the MIPS P5600 cores, the embedded DDR controller,
SATA, Ethernet and PCIe domains. The last three domains though named by the
biggest system interfaces in fact include nearly all of the rest SoC
peripherals. Each of the PLLs is based on True Circuits TSMC CLN28HPM core
with an interface wrapper (so called safe PLL' clocks switcher) to simplify
the PLL configuration procedure. The PLLs work as depicted on the next
diagram:
+--------------------------+
| |
+-->+---+ +---+ +---+ | +---+ 0|\
CLKF--->|/NF|--->|PFD|...|VCO|-+->|/OD|--->| |
+---+ +->+---+ +---+ /->+---+ | |--->CLKOUT
CLKOD---------C----------------+ 1| |
+--------C--------------------------->|/
| | ^
Rclk-+->+---+ | |
CLKR--->|/NR|-+ |
+---+ |
BYPASS--------------------------------------+
BWADJ--->
where Rclk is the reference clock coming from XTAL, NR - reference clock
divider, NF - PLL clock multiplier, OD - VCO output clock divider, CLKOUT -
output clock, BWADJ is the PLL bandwidth adjustment parameter. At this moment
the binding supports the PLL dividers configuration in accordance with a
requested rate, while bypassing and bandwidth adjustment settings can be
added in future if it gets to be necessary.
The PLLs CLKOUT is then either directly connected with the corresponding
clocks consumer (like P5600 cores or DDR controller) or passed over a CCU
divider to create a signal required for the clock domain.
The CCU PLL dts-node uses the common clock bindings with no custom
parameters. The list of exported clocks can be found in
'include/dt-bindings/clock/bt1-ccu.h'. Since CCU PLL is a part of the
Baikal-T1 SoC System Controller its DT node is supposed to be a child of
later one.
properties:
compatible:
const: baikal,bt1-ccu-pll
reg:
maxItems: 1
"#clock-cells":
const: 1
clocks:
description: External reference clock
maxItems: 1
clock-names:
const: ref_clk
additionalProperties: false
required:
- compatible
- "#clock-cells"
- clocks
- clock-names
examples:
# Clock Control Unit PLL node:
- |
clock-controller@1f04d000 {
compatible = "baikal,bt1-ccu-pll";
reg = <0x1f04d000 0x028>;
#clock-cells = <1>;
clocks = <&clk25m>;
clock-names = "ref_clk";
};
# Required external oscillator:
- |
clk25m: clock-oscillator-25m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-output-names = "clk25m";
};
...

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/bitmain,bm1880-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Bitmain BM1880 Clock Controller
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
description: |
The Bitmain BM1880 clock controller generates and supplies clock to
various peripherals within the SoC.
This binding uses common clock bindings
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
properties:
compatible:
const: bitmain,bm1880-clk
reg:
items:
- description: pll registers
- description: system registers
reg-names:
items:
- const: pll
- const: sys
clocks:
maxItems: 1
clock-names:
const: osc
'#clock-cells':
const: 1
required:
- compatible
- reg
- reg-names
- clocks
- clock-names
- '#clock-cells'
additionalProperties: false
examples:
# Clock controller node:
- |
clk: clock-controller@e8 {
compatible = "bitmain,bm1880-clk";
reg = <0xe8 0x0c>, <0x800 0xb0>;
reg-names = "pll", "sys";
clocks = <&osc>;
clock-names = "osc";
#clock-cells = <1>;
};
...

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/brcm,bcm2711-dvp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM2711 HDMI DVP
maintainers:
- Maxime Ripard <mripard@kernel.org>
properties:
"#clock-cells":
const: 1
"#reset-cells":
const: 1
compatible:
const: brcm,brcm2711-dvp
reg:
maxItems: 1
clocks:
maxItems: 1
required:
- "#clock-cells"
- "#reset-cells"
- compatible
- reg
- clocks
additionalProperties: false
examples:
- |
dvp: clock@7ef00000 {
compatible = "brcm,brcm2711-dvp";
reg = <0x7ef00000 0x10>;
clocks = <&clk_108MHz>;
#clock-cells = <1>;
#reset-cells = <1>;
};
...

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Broadcom BCM2835 auxiliary peripheral support
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
The auxiliary peripherals (UART, SPI1, and SPI2) have a small register
area controlling clock gating to the peripherals, and providing an IRQ
status register.
Required properties:
- compatible: Should be "brcm,bcm2835-aux"
- #clock-cells: Should be <1>. The permitted clock-specifier values can be
found in include/dt-bindings/clock/bcm2835-aux.h
- reg: Specifies base physical address and size of the registers
- clocks: The parent clock phandle
Example:
clocks: cprman@7e101000 {
compatible = "brcm,bcm2835-cprman";
#clock-cells = <1>;
reg = <0x7e101000 0x2000>;
clocks = <&clk_osc>;
};
aux: aux@7e215004 {
compatible = "brcm,bcm2835-aux";
#clock-cells = <1>;
reg = <0x7e215000 0x8>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
};

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Broadcom BCM2835 CPRMAN clocks
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
The CPRMAN clock controller generates clocks in the audio power domain
of the BCM2835. There is a level of PLLs deriving from an external
oscillator, a level of PLL dividers that produce channels off of the
few PLLs, and a level of mostly-generic clock generators sourcing from
the PLL channels. Most other hardware components source from the
clock generators, but a few (like the ARM or HDMI) will source from
the PLL dividers directly.
Required properties:
- compatible: should be one of the following,
"brcm,bcm2711-cprman"
"brcm,bcm2835-cprman"
- #clock-cells: Should be <1>. The permitted clock-specifier values can be
found in include/dt-bindings/clock/bcm2835.h
- reg: Specifies base physical address and size of the registers
- clocks: phandles to the parent clocks used as input to the module, in
the following order:
- External oscillator
- DSI0 byte clock
- DSI0 DDR2 clock
- DSI0 DDR clock
- DSI1 byte clock
- DSI1 DDR2 clock
- DSI1 DDR clock
Only external oscillator is required. The DSI clocks may
not be present, in which case their children will be
unusable.
Example:
clk_osc: clock@3 {
compatible = "fixed-clock";
reg = <3>;
#clock-cells = <0>;
clock-output-names = "osc";
clock-frequency = <19200000>;
};
clocks: cprman@7e101000 {
compatible = "brcm,bcm2835-cprman";
#clock-cells = <1>;
reg = <0x7e101000 0x2000>;
clocks = <&clk_osc>;
};
i2c0: i2c@7e205000 {
compatible = "brcm,bcm2835-i2c";
reg = <0x7e205000 0x1000>;
interrupts = <2 21>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
#address-cells = <1>;
#size-cells = <0>;
};

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Broadcom BCM53573 ILP clock
===========================
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
This binding is used for ILP clock (sometimes referred as "slow clock")
on Broadcom BCM53573 devices using Cortex-A7 CPU.
ILP's rate has to be calculated on runtime and it depends on ALP clock
which has to be referenced.
This clock is part of PMU (Power Management Unit), a Broadcom's device
handing power-related aspects. Its node must be sub-node of the PMU
device.
Required properties:
- compatible: "brcm,bcm53573-ilp"
- clocks: has to reference an ALP clock
- #clock-cells: should be <0>
- clock-output-names: from common clock bindings, should contain clock
name
Example:
pmu@18012000 {
compatible = "simple-mfd", "syscon";
reg = <0x18012000 0x00001000>;
ilp {
compatible = "brcm,bcm53573-ilp";
clocks = <&alp>;
#clock-cells = <0>;
clock-output-names = "ilp";
};
};

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Gated Clock Controller Bindings for MIPS based BCM63XX SoCs
Required properties:
- compatible: must be one of:
"brcm,bcm3368-clocks"
"brcm,bcm6318-clocks"
"brcm,bcm6318-ubus-clocks"
"brcm,bcm6328-clocks"
"brcm,bcm6358-clocks"
"brcm,bcm6362-clocks"
"brcm,bcm6368-clocks"
"brcm,bcm63268-clocks"
- reg: Address and length of the register set
- #clock-cells: must be <1>
Example:
clkctl: clock-controller@10000004 {
compatible = "brcm,bcm6328-clocks";
reg = <0x10000004 0x4>;
#clock-cells = <1>;
};

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/brcm,iproc-clocks.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom iProc Family Clocks
maintainers:
- Ray Jui <rjui@broadcom.com>
- Scott Branden <sbranden@broadcom.com>
description: |
The iProc clock controller manages clocks that are common to the iProc family.
An SoC from the iProc family may have several PLLs, e.g., ARMPLL, GENPLL,
LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
comprises of several leaf clocks
ASIU clocks are a special case. These clocks are derived directly from the
reference clock of the onboard crystal.
properties:
compatible:
enum:
- brcm,bcm63138-armpll
- brcm,cygnus-armpll
- brcm,cygnus-genpll
- brcm,cygnus-lcpll0
- brcm,cygnus-mipipll
- brcm,cygnus-asiu-clk
- brcm,cygnus-audiopll
- brcm,hr2-armpll
- brcm,nsp-armpll
- brcm,nsp-genpll
- brcm,nsp-lcpll0
- brcm,ns2-genpll-scr
- brcm,ns2-genpll-sw
- brcm,ns2-lcpll-ddr
- brcm,ns2-lcpll-ports
- brcm,sr-genpll0
- brcm,sr-genpll1
- brcm,sr-genpll2
- brcm,sr-genpll3
- brcm,sr-genpll4
- brcm,sr-genpll5
- brcm,sr-genpll6
- brcm,sr-lcpll0
- brcm,sr-lcpll1
- brcm,sr-lcpll-pcie
reg:
minItems: 1
items:
- description: base register
- description: power register
- description: ASIU or split status register
clocks:
description: The input parent clock phandle for the PLL / ASIU clock. For
most iProc PLLs, this is an onboard crystal with a fixed rate.
maxItems: 1
'#clock-cells':
true
clock-output-names:
minItems: 1
maxItems: 45
allOf:
- if:
properties:
compatible:
contains:
enum:
- brcm,cygnus-armpll
- brcm,nsp-armpll
then:
properties:
'#clock-cells':
const: 0
else:
properties:
'#clock-cells':
const: 1
required:
- clock-output-names
- if:
properties:
compatible:
contains:
enum:
- brcm,cygnus-armpll
- brcm,cygnus-genpll
- brcm,cygnus-lcpll0
- brcm,cygnus-mipipll
- brcm,cygnus-asiu-clk
- brcm,cygnus-audiopll
then:
properties:
clock-output-names:
description: |
The following table defines the set of PLL/clock index and ID for Cygnus.
These clock IDs are defined in:
"include/dt-bindings/clock/bcm-cygnus.h"
Clock Source (Parent) Index ID
----- --------------- ----- --
crystal N/A N/A N/A
armpll crystal N/A N/A
keypad crystal (ASIU) 0 BCM_CYGNUS_ASIU_KEYPAD_CLK
adc/tsc crystal (ASIU) 1 BCM_CYGNUS_ASIU_ADC_CLK
pwm crystal (ASIU) 2 BCM_CYGNUS_ASIU_PWM_CLK
genpll crystal 0 BCM_CYGNUS_GENPLL
axi21 genpll 1 BCM_CYGNUS_GENPLL_AXI21_CLK
250mhz genpll 2 BCM_CYGNUS_GENPLL_250MHZ_CLK
ihost_sys genpll 3 BCM_CYGNUS_GENPLL_IHOST_SYS_CLK
enet_sw genpll 4 BCM_CYGNUS_GENPLL_ENET_SW_CLK
audio_125 genpll 5 BCM_CYGNUS_GENPLL_AUDIO_125_CLK
can genpll 6 BCM_CYGNUS_GENPLL_CAN_CLK
lcpll0 crystal 0 BCM_CYGNUS_LCPLL0
pcie_phy lcpll0 1 BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK
ddr_phy lcpll0 2 BCM_CYGNUS_LCPLL0_DDR_PHY_CLK
sdio lcpll0 3 BCM_CYGNUS_LCPLL0_SDIO_CLK
usb_phy lcpll0 4 BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK
smart_card lcpll0 5 BCM_CYGNUS_LCPLL0_SMART_CARD_CLK
ch5_unused lcpll0 6 BCM_CYGNUS_LCPLL0_CH5_UNUSED
mipipll crystal 0 BCM_CYGNUS_MIPIPLL
ch0_unused mipipll 1 BCM_CYGNUS_MIPIPLL_CH0_UNUSED
ch1_lcd mipipll 2 BCM_CYGNUS_MIPIPLL_CH1_LCD
ch2_v3d mipipll 3 BCM_CYGNUS_MIPIPLL_CH2_V3D
ch3_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH3_UNUSED
ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED
ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED
audiopll crystal 0 BCM_CYGNUS_AUDIOPLL
ch0_audio audiopll 1 BCM_CYGNUS_AUDIOPLL_CH0
ch1_audio audiopll 2 BCM_CYGNUS_AUDIOPLL_CH1
ch2_audio audiopll 3 BCM_CYGNUS_AUDIOPLL_CH2
- if:
properties:
compatible:
contains:
enum:
- brcm,hr2-armpll
then:
properties:
clock-output-names:
description: |
The following table defines the set of PLL/clock for Hurricane 2:
Clock Source Index ID
----- ------ ----- --
crystal N/A N/A N/A
armpll crystal N/A N/A
- if:
properties:
compatible:
contains:
enum:
- brcm,nsp-armpll
- brcm,nsp-genpll
- brcm,nsp-lcpll0
then:
properties:
clock-output-names:
description: |
The following table defines the set of PLL/clock index and ID for Northstar and
Northstar Plus. These clock IDs are defined in:
"include/dt-bindings/clock/bcm-nsp.h"
Clock Source Index ID
----- ------ ----- --
crystal N/A N/A N/A
armpll crystal N/A N/A
genpll crystal 0 BCM_NSP_GENPLL
phy genpll 1 BCM_NSP_GENPLL_PHY_CLK
ethernetclk genpll 2 BCM_NSP_GENPLL_ENET_SW_CLK
usbclk genpll 3 BCM_NSP_GENPLL_USB_PHY_REF_CLK
iprocfast genpll 4 BCM_NSP_GENPLL_IPROCFAST_CLK
sata1 genpll 5 BCM_NSP_GENPLL_SATA1_CLK
sata2 genpll 6 BCM_NSP_GENPLL_SATA2_CLK
lcpll0 crystal 0 BCM_NSP_LCPLL0
pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK
sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK
ddr_phy lcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK
- if:
properties:
compatible:
contains:
enum:
- brcm,ns2-genpll-scr
- brcm,ns2-genpll-sw
- brcm,ns2-lcpll-ddr
- brcm,ns2-lcpll-ports
then:
properties:
clock-output-names:
description: |
The following table defines the set of PLL/clock index and ID for Northstar 2.
These clock IDs are defined in:
"include/dt-bindings/clock/bcm-ns2.h"
Clock Source Index ID
----- ------ ----- --
crystal N/A N/A N/A
genpll_scr crystal 0 BCM_NS2_GENPLL_SCR
scr genpll_scr 1 BCM_NS2_GENPLL_SCR_SCR_CLK
fs genpll_scr 2 BCM_NS2_GENPLL_SCR_FS_CLK
audio_ref genpll_scr 3 BCM_NS2_GENPLL_SCR_AUDIO_CLK
ch3_unused genpll_scr 4 BCM_NS2_GENPLL_SCR_CH3_UNUSED
ch4_unused genpll_scr 5 BCM_NS2_GENPLL_SCR_CH4_UNUSED
ch5_unused genpll_scr 6 BCM_NS2_GENPLL_SCR_CH5_UNUSED
genpll_sw crystal 0 BCM_NS2_GENPLL_SW
rpe genpll_sw 1 BCM_NS2_GENPLL_SW_RPE_CLK
250 genpll_sw 2 BCM_NS2_GENPLL_SW_250_CLK
nic genpll_sw 3 BCM_NS2_GENPLL_SW_NIC_CLK
chimp genpll_sw 4 BCM_NS2_GENPLL_SW_CHIMP_CLK
port genpll_sw 5 BCM_NS2_GENPLL_SW_PORT_CLK
sdio genpll_sw 6 BCM_NS2_GENPLL_SW_SDIO_CLK
lcpll_ddr crystal 0 BCM_NS2_LCPLL_DDR
pcie_sata_usb lcpll_ddr 1 BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK
ddr lcpll_ddr 2 BCM_NS2_LCPLL_DDR_DDR_CLK
ch2_unused lcpll_ddr 3 BCM_NS2_LCPLL_DDR_CH2_UNUSED
ch3_unused lcpll_ddr 4 BCM_NS2_LCPLL_DDR_CH3_UNUSED
ch4_unused lcpll_ddr 5 BCM_NS2_LCPLL_DDR_CH4_UNUSED
ch5_unused lcpll_ddr 6 BCM_NS2_LCPLL_DDR_CH5_UNUSED
lcpll_ports crystal 0 BCM_NS2_LCPLL_PORTS
wan lcpll_ports 1 BCM_NS2_LCPLL_PORTS_WAN_CLK
rgmii lcpll_ports 2 BCM_NS2_LCPLL_PORTS_RGMII_CLK
ch2_unused lcpll_ports 3 BCM_NS2_LCPLL_PORTS_CH2_UNUSED
ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED
ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED
ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED
- if:
properties:
compatible:
contains:
enum:
- brcm,sr-genpll0
- brcm,sr-genpll1
- brcm,sr-genpll2
- brcm,sr-genpll3
- brcm,sr-genpll4
- brcm,sr-genpll5
- brcm,sr-genpll6
- brcm,sr-lcpll0
- brcm,sr-lcpll1
- brcm,sr-lcpll-pcie
then:
properties:
clock-output-names:
description: |
The following table defines the set of PLL/clock index and ID for Stingray.
These clock IDs are defined in:
"include/dt-bindings/clock/bcm-sr.h"
Clock Source Index ID
----- ------ ----- --
crystal N/A N/A N/A
crmu_ref25m crystal N/A N/A
genpll0 crystal 0 BCM_SR_GENPLL0
clk_125m genpll0 1 BCM_SR_GENPLL0_125M_CLK
clk_scr genpll0 2 BCM_SR_GENPLL0_SCR_CLK
clk_250 genpll0 3 BCM_SR_GENPLL0_250M_CLK
clk_pcie_axi genpll0 4 BCM_SR_GENPLL0_PCIE_AXI_CLK
clk_paxc_axi_x2 genpll0 5 BCM_SR_GENPLL0_PAXC_AXI_X2_CLK
clk_paxc_axi genpll0 6 BCM_SR_GENPLL0_PAXC_AXI_CLK
genpll1 crystal 0 BCM_SR_GENPLL1
clk_pcie_tl genpll1 1 BCM_SR_GENPLL1_PCIE_TL_CLK
clk_mhb_apb genpll1 2 BCM_SR_GENPLL1_MHB_APB_CLK
genpll2 crystal 0 BCM_SR_GENPLL2
clk_nic genpll2 1 BCM_SR_GENPLL2_NIC_CLK
clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK
clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK
clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK
clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH_CLK
clk_fs genpll2 6 BCM_SR_GENPLL2_FS_CLK
genpll3 crystal 0 BCM_SR_GENPLL3
clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK
clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK
genpll4 crystal 0 BCM_SR_GENPLL4
clk_ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK
clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK
clk_noc genpll4 3 BCM_SR_GENPLL4_NOC_CLK
clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK
clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK
genpll5 crystal 0 BCM_SR_GENPLL5
clk_fs4_hf genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK
clk_crypto_ae genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK
clk_raid_ae genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK
genpll6 crystal 0 BCM_SR_GENPLL6
clk_48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK
lcpll0 crystal 0 BCM_SR_LCPLL0
clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK
clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK
clk_sata_350 lcpll0 3 BCM_SR_LCPLL0_SATA_350_CLK
clk_sata_500 lcpll0 4 BCM_SR_LCPLL0_SATA_500_CLK
lcpll1 crystal 0 BCM_SR_LCPLL1
clk_wan lcpll1 1 BCM_SR_LCPLL1_WAN_CLK
clk_usb_ref lcpll1 2 BCM_SR_LCPLL1_USB_REF_CLK
clk_crmu_ts lcpll1 3 BCM_SR_LCPLL1_CRMU_TS_CLK
lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE
clk_pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK
- if:
properties:
compatible:
contains:
const: brcm,cygnus-genpll
then:
properties:
clock-output-names:
items:
- const: genpll
- const: axi21
- const: 250mhz
- const: ihost_sys
- const: enet_sw
- const: audio_125
- const: can
- if:
properties:
compatible:
contains:
const: brcm,nsp-lcpll0
then:
properties:
clock-output-names:
items:
- const: lcpll0
- const: pcie_phy
- const: sdio
- const: ddr_phy
- if:
properties:
compatible:
contains:
const: brcm,nsp-genpll
then:
properties:
clock-output-names:
items:
- const: genpll
- const: phy
- const: ethernetclk
- const: usbclk
- const: iprocfast
- const: sata1
- const: sata2
required:
- reg
- clocks
- '#clock-cells'
additionalProperties: false
examples:
- |
osc1: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
};
genpll@301d000 {
#clock-cells = <1>;
compatible = "brcm,cygnus-genpll";
reg = <0x301d000 0x2c>, <0x301c020 0x4>;
clocks = <&os1c>;
clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys",
"enet_sw", "audio_125", "can";
};
- |
osc2: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
};
asiu_clks@301d048 {
#clock-cells = <1>;
compatible = "brcm,cygnus-asiu-clk";
reg = <0x301d048 0xc>, <0x180aa024 0x4>;
clocks = <&osc2>;
clock-output-names = "keypad", "adc/touch", "pwm";
};
- |
arm_clk@0 {
#clock-cells = <0>;
compatible = "brcm,nsp-armpll";
clocks = <&osc>;
reg = <0x0 0x1000>;
};

138
bindings/clock/brcm,kona-ccu.txt Normal file
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Broadcom Kona Family Clocks
This binding is associated with Broadcom SoCs having "Kona" style
clock control units (CCUs). A CCU is a clock provider that manages
a set of clock signals. Each CCU is represented by a node in the
device tree.
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible
Shall have a value of the form "brcm,<model>-<which>-ccu",
where <model> is a Broadcom SoC model number and <which> is
the name of a defined CCU. For example:
"brcm,bcm11351-root-ccu"
The compatible strings used for each supported SoC family
are defined below.
- reg
Shall define the base and range of the address space
containing clock control registers
- #clock-cells
Shall have value <1>. The permitted clock-specifier values
are defined below.
- clock-output-names
Shall be an ordered list of strings defining the names of
the clocks provided by the CCU.
Device tree example:
slave_ccu: slave_ccu {
compatible = "brcm,bcm11351-slave-ccu";
reg = <0x3e011000 0x0f00>;
#clock-cells = <1>;
clock-output-names = "uartb",
"uartb2",
"uartb3",
"uartb4";
};
ref_crystal_clk: ref_crystal {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <26000000>;
};
uart@3e002000 {
compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
reg = <0x3e002000 0x1000>;
clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
};
BCM281XX family
---------------
CCU compatible string values for SoCs in the BCM281XX family are:
"brcm,bcm11351-root-ccu"
"brcm,bcm11351-aon-ccu"
"brcm,bcm11351-hub-ccu"
"brcm,bcm11351-master-ccu"
"brcm,bcm11351-slave-ccu"
The following table defines the set of CCUs and clock specifiers for
BCM281XX family clocks. When a clock consumer references a clocks,
its symbolic specifier (rather than its numeric index value) should
be used. These specifiers are defined in:
"include/dt-bindings/clock/bcm281xx.h"
CCU Clock Type Index Specifier
--- ----- ---- ----- ---------
root frac_1m peri 0 BCM281XX_ROOT_CCU_FRAC_1M
aon hub_timer peri 0 BCM281XX_AON_CCU_HUB_TIMER
aon pmu_bsc peri 1 BCM281XX_AON_CCU_PMU_BSC
aon pmu_bsc_var peri 2 BCM281XX_AON_CCU_PMU_BSC_VAR
hub tmon_1m peri 0 BCM281XX_HUB_CCU_TMON_1M
master sdio1 peri 0 BCM281XX_MASTER_CCU_SDIO1
master sdio2 peri 1 BCM281XX_MASTER_CCU_SDIO2
master sdio3 peri 2 BCM281XX_MASTER_CCU_SDIO3
master sdio4 peri 3 BCM281XX_MASTER_CCU_SDIO4
master dmac peri 4 BCM281XX_MASTER_CCU_DMAC
master usb_ic peri 5 BCM281XX_MASTER_CCU_USB_IC
master hsic2_48m peri 6 BCM281XX_MASTER_CCU_HSIC_48M
master hsic2_12m peri 7 BCM281XX_MASTER_CCU_HSIC_12M
slave uartb peri 0 BCM281XX_SLAVE_CCU_UARTB
slave uartb2 peri 1 BCM281XX_SLAVE_CCU_UARTB2
slave uartb3 peri 2 BCM281XX_SLAVE_CCU_UARTB3
slave uartb4 peri 3 BCM281XX_SLAVE_CCU_UARTB4
slave ssp0 peri 4 BCM281XX_SLAVE_CCU_SSP0
slave ssp2 peri 5 BCM281XX_SLAVE_CCU_SSP2
slave bsc1 peri 6 BCM281XX_SLAVE_CCU_BSC1
slave bsc2 peri 7 BCM281XX_SLAVE_CCU_BSC2
slave bsc3 peri 8 BCM281XX_SLAVE_CCU_BSC3
slave pwm peri 9 BCM281XX_SLAVE_CCU_PWM
BCM21664 family
---------------
CCU compatible string values for SoCs in the BCM21664 family are:
"brcm,bcm21664-root-ccu"
"brcm,bcm21664-aon-ccu"
"brcm,bcm21664-master-ccu"
"brcm,bcm21664-slave-ccu"
The following table defines the set of CCUs and clock specifiers for
BCM21664 family clocks. When a clock consumer references a clocks,
its symbolic specifier (rather than its numeric index value) should
be used. These specifiers are defined in:
"include/dt-bindings/clock/bcm21664.h"
CCU Clock Type Index Specifier
--- ----- ---- ----- ---------
root frac_1m peri 0 BCM21664_ROOT_CCU_FRAC_1M
aon hub_timer peri 0 BCM21664_AON_CCU_HUB_TIMER
master sdio1 peri 0 BCM21664_MASTER_CCU_SDIO1
master sdio2 peri 1 BCM21664_MASTER_CCU_SDIO2
master sdio3 peri 2 BCM21664_MASTER_CCU_SDIO3
master sdio4 peri 3 BCM21664_MASTER_CCU_SDIO4
master sdio1_sleep peri 4 BCM21664_MASTER_CCU_SDIO1_SLEEP
master sdio2_sleep peri 5 BCM21664_MASTER_CCU_SDIO2_SLEEP
master sdio3_sleep peri 6 BCM21664_MASTER_CCU_SDIO3_SLEEP
master sdio4_sleep peri 7 BCM21664_MASTER_CCU_SDIO4_SLEEP
slave uartb peri 0 BCM21664_SLAVE_CCU_UARTB
slave uartb2 peri 1 BCM21664_SLAVE_CCU_UARTB2
slave uartb3 peri 2 BCM21664_SLAVE_CCU_UARTB3
slave uartb4 peri 3 BCM21664_SLAVE_CCU_UARTB4
slave bsc1 peri 4 BCM21664_SLAVE_CCU_BSC1
slave bsc2 peri 5 BCM21664_SLAVE_CCU_BSC2
slave bsc3 peri 6 BCM21664_SLAVE_CCU_BSC3
slave bsc4 peri 7 BCM21664_SLAVE_CCU_BSC4

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/calxeda.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Device Tree Clock bindings for Calxeda highbank platform
description: |
This binding covers the Calxeda SoC internal peripheral and bus clocks
as used by peripherals. The clocks live inside the "system register"
region of the SoC, so are typically presented as children of an
"hb-sregs" node.
maintainers:
- Andre Przywara <andre.przywara@arm.com>
properties:
"#clock-cells":
const: 0
compatible:
enum:
- calxeda,hb-pll-clock
- calxeda,hb-a9periph-clock
- calxeda,hb-a9bus-clock
- calxeda,hb-emmc-clock
reg:
maxItems: 1
clocks:
maxItems: 1
required:
- "#clock-cells"
- compatible
- clocks
- reg
additionalProperties: false
examples:
- |
sregs@3fffc000 {
compatible = "calxeda,hb-sregs";
reg = <0x3fffc000 0x1000>;
clocks {
#address-cells = <1>;
#size-cells = <0>;
osc: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <33333000>;
};
ddrpll: ddrpll@108 {
#clock-cells = <0>;
compatible = "calxeda,hb-pll-clock";
clocks = <&osc>;
reg = <0x108>;
};
a9pll: a9pll@100 {
#clock-cells = <0>;
compatible = "calxeda,hb-pll-clock";
clocks = <&osc>;
reg = <0x100>;
};
a9periphclk: a9periphclk@104 {
#clock-cells = <0>;
compatible = "calxeda,hb-a9periph-clock";
clocks = <&a9pll>;
reg = <0x104>;
};
};
};
...

55
bindings/clock/canaan,k210-clk.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/canaan,k210-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Canaan Kendryte K210 Clock
maintainers:
- Damien Le Moal <damien.lemoal@wdc.com>
description: |
Canaan Kendryte K210 SoC clocks driver bindings. The clock
controller node must be defined as a child node of the K210
system controller node.
See also:
- dt-bindings/clock/k210-clk.h
properties:
compatible:
const: canaan,k210-clk
clocks:
maxItems: 1
description:
Phandle of the SoC 26MHz fixed-rate oscillator clock.
'#clock-cells':
const: 1
required:
- compatible
- '#clock-cells'
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/k210-clk.h>
clocks {
in0: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
};
/* ... */
sysclk: clock-controller {
#clock-cells = <1>;
compatible = "canaan,k210-clk";
clocks = <&in0>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/cirrus,cs2000-cp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Binding CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier
maintainers:
- Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
description: |
The CS2000-CP is an extremely versatile system clocking device that
utilizes a programmable phase lock loop.
Link: https://www.cirrus.com/products/cs2000/
properties:
compatible:
enum:
- cirrus,cs2000-cp
clocks:
description:
Common clock binding for CLK_IN, XTI/REF_CLK
maxItems: 2
clock-names:
items:
- const: clk_in
- const: ref_clk
'#clock-cells':
const: 0
reg:
maxItems: 1
cirrus,aux-output-source:
description:
Specifies the function of the auxiliary clock output pin
$ref: /schemas/types.yaml#/definitions/uint32
enum:
- 0 # CS2000CP_AUX_OUTPUT_REF_CLK: ref_clk input
- 1 # CS2000CP_AUX_OUTPUT_CLK_IN: clk_in input
- 2 # CS2000CP_AUX_OUTPUT_CLK_OUT: clk_out output
- 3 # CS2000CP_AUX_OUTPUT_PLL_LOCK: pll lock status
default: 0
cirrus,clock-skip:
description:
This mode allows the PLL to maintain lock even when CLK_IN
has missing pulses for up to 20 ms.
$ref: /schemas/types.yaml#/definitions/flag
cirrus,dynamic-mode:
description:
In dynamic mode, the CLK_IN input is used to drive the
digital PLL of the silicon.
If not given, the static mode shall be used to derive the
output signal directly from the REF_CLK input.
$ref: /schemas/types.yaml#/definitions/flag
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/cirrus,cs2000-cp.h>
i2c@0 {
reg = <0x0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
clock-controller@4f {
#clock-cells = <0>;
compatible = "cirrus,cs2000-cp";
reg = <0x4f>;
clocks = <&rcar_sound 0>, <&x12_clk>;
clock-names = "clk_in", "ref_clk";
cirrus,aux-output-source = <CS2000CP_AUX_OUTPUT_CLK_OUT>;
};
};

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/cirrus,lochnagar.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cirrus Logic Lochnagar Audio Development Board
maintainers:
- patches@opensource.cirrus.com
description: |
Lochnagar is an evaluation and development board for Cirrus Logic
Smart CODEC and Amp devices. It allows the connection of most Cirrus
Logic devices on mini-cards, as well as allowing connection of various
application processor systems to provide a full evaluation platform.
Audio system topology, clocking and power can all be controlled through
the Lochnagar, allowing the device under test to be used in a variety of
possible use cases.
This binding document describes the binding for the clock portion of the
driver.
Also see these documents for generic binding information:
[1] Clock : ../clock/clock-bindings.txt
And these for relevant defines:
[2] include/dt-bindings/clock/lochnagar.h
This binding must be part of the Lochnagar MFD binding:
[3] ../mfd/cirrus,lochnagar.yaml
properties:
compatible:
enum:
- cirrus,lochnagar1-clk
- cirrus,lochnagar2-clk
'#clock-cells':
description:
The first cell indicates the clock number, see [2] for available
clocks and [1].
const: 1
clock-names:
items:
enum:
- ln-cdc-clkout # Output clock from CODEC card.
- ln-dsp-clkout # Output clock from DSP card.
- ln-gf-mclk1 # Optional input clock from host system.
- ln-gf-mclk2 # Optional input clock from host system.
- ln-gf-mclk3 # Optional input clock from host system.
- ln-gf-mclk4 # Optional input clock from host system.
- ln-psia1-mclk # Optional input clock from external connector.
- ln-psia2-mclk # Optional input clock from external connector.
- ln-spdif-mclk # Optional input clock from SPDIF.
- ln-spdif-clkout # Optional input clock from SPDIF.
- ln-adat-mclk # Optional input clock from ADAT.
- ln-pmic-32k # On board fixed clock.
- ln-clk-12m # On board fixed clock.
- ln-clk-11m # On board fixed clock.
- ln-clk-24m # On board fixed clock.
- ln-clk-22m # On board fixed clock.
- ln-clk-8m # On board fixed clock.
- ln-usb-clk-24m # On board fixed clock.
- ln-usb-clk-12m # On board fixed clock.
minItems: 1
maxItems: 19
clocks: true
assigned-clocks: true
assigned-clock-parents: true
additionalProperties: false
required:
- compatible
- '#clock-cells'

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* Palmas 32KHz clocks *
Palmas device has two clock output pins for 32KHz, KG and KG_AUDIO.
This binding uses the common clock binding ./clock-bindings.txt.
Required properties:
- compatible : "ti,palmas-clk32kg" for clk32kg clock
"ti,palmas-clk32kgaudio" for clk32kgaudio clock
- #clock-cells : shall be set to 0.
Optional property:
- ti,external-sleep-control: The external enable input pins controlled the
enable/disable of clocks. The external enable input pins ENABLE1,
ENABLE2 and NSLEEP. The valid values for the external pins are:
PALMAS_EXT_CONTROL_PIN_ENABLE1 for ENABLE1 pin
PALMAS_EXT_CONTROL_PIN_ENABLE2 for ENABLE2 pin
PALMAS_EXT_CONTROL_PIN_NSLEEP for NSLEEP pin
Option 0 or missing this property means the clock is enabled/disabled
via register access and these pins do not have any control.
The macros of external control pins for DTS is defined at
dt-bindings/mfd/palmas.h
Example:
#include <dt-bindings/mfd/palmas.h>
...
palmas: tps65913@58 {
...
clk32kg: palmas_clk32k@0 {
compatible = "ti,palmas-clk32kg";
#clock-cells = <0>;
ti,external-sleep-control = <PALMAS_EXT_CONTROL_PIN_NSLEEP>;
};
...
};

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This file has moved to the clock binding schema:
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml

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* Clock bindings for the Cirrus Logic CLPS711X CPUs
Required properties:
- compatible : Shall contain "cirrus,ep7209-clk".
- reg : Address of the internal register set.
- startup-frequency: Factory set CPU startup frequency in HZ.
- #clock-cells : Should be <1>.
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/clps711x-clock.h
for the full list of CLPS711X clock IDs.
Example:
clks: clks@80000000 {
#clock-cells = <1>;
compatible = "cirrus,ep7312-clk", "cirrus,ep7209-clk";
reg = <0x80000000 0xc000>;
startup-frequency = <73728000>;
};

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PLL divider based Dove clocks
Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide
high speed clocks for a number of peripherals. These dividers are part of
the PMU, and thus this node should be a child of the PMU node.
The following clocks are provided:
ID Clock
-------------
0 AXI bus clock
1 GPU clock
2 VMeta clock
3 LCD clock
Required properties:
- compatible : shall be "marvell,dove-divider-clock"
- reg : shall be the register address of the Core PLL and Clock Divider
Control 0 register. This will cover that register, as well as the
Core PLL and Clock Divider Control 1 register. Thus, it will have
a size of 8.
- #clock-cells : from common clock binding; shall be set to 1
divider_clk: core-clock@64 {
compatible = "marvell,dove-divider-clock";
reg = <0x0064 0x8>;
#clock-cells = <1>;
};

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/fixed-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Binding for simple fixed-rate clock sources
maintainers:
- Michael Turquette <mturquette@baylibre.com>
- Stephen Boyd <sboyd@kernel.org>
properties:
compatible:
const: fixed-clock
"#clock-cells":
const: 0
clock-frequency: true
clock-accuracy:
description: accuracy of clock in ppb (parts per billion).
$ref: /schemas/types.yaml#/definitions/uint32
clock-output-names:
maxItems: 1
required:
- compatible
- "#clock-cells"
- clock-frequency
additionalProperties: false
examples:
- |
clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000000>;
clock-accuracy = <100>;
};
...

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/fixed-factor-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Binding for simple fixed factor rate clock sources
maintainers:
- Michael Turquette <mturquette@baylibre.com>
- Stephen Boyd <sboyd@kernel.org>
properties:
compatible:
enum:
- fixed-factor-clock
"#clock-cells":
const: 0
clocks:
maxItems: 1
clock-div:
description: Fixed divider
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 1
clock-mult:
description: Fixed multiplier
$ref: /schemas/types.yaml#/definitions/uint32
clock-output-names:
maxItems: 1
required:
- compatible
- clocks
- "#clock-cells"
- clock-div
- clock-mult
additionalProperties: false
examples:
- |
clock {
compatible = "fixed-factor-clock";
clocks = <&parentclk>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
};
...

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/fixed-mmio-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Binding for simple memory mapped IO fixed-rate clock sources
description:
This binding describes a fixed-rate clock for which the frequency can
be read from a single 32-bit memory mapped I/O register.
It was designed for test systems, like FPGA, not for complete,
finished SoCs.
maintainers:
- Jan Kotas <jank@cadence.com>
properties:
compatible:
const: fixed-mmio-clock
reg:
maxItems: 1
"#clock-cells":
const: 0
clock-output-names:
maxItems: 1
required:
- compatible
- reg
- "#clock-cells"
additionalProperties: false
examples:
- |
sysclock: sysclock@fd020004 {
compatible = "fixed-mmio-clock";
#clock-cells = <0>;
reg = <0xfd020004 0x4>;
clock-output-names = "sysclk";
};
...

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/fsl,flexspi-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale FlexSPI clock driver for Layerscape SoCs
maintainers:
- Michael Walle <michael@walle.cc>
description:
The Freescale Layerscape SoCs have a special FlexSPI clock which is
derived from the platform PLL.
properties:
compatible:
enum:
- fsl,ls1028a-flexspi-clk
- fsl,lx2160a-flexspi-clk
reg:
maxItems: 1
clocks:
maxItems: 1
'#clock-cells':
const: 0
clock-output-names:
maxItems: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
additionalProperties: false
examples:
- |
dcfg {
#address-cells = <1>;
#size-cells = <1>;
fspi_clk: clock-controller@900 {
compatible = "fsl,ls1028a-flexspi-clk";
reg = <0x900 0x4>;
#clock-cells = <0>;
clocks = <&parentclk>;
clock-output-names = "fspi_clk";
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/fsl,imx8m-anatop.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX8M Family Anatop Module
maintainers:
- Peng Fan <peng.fan@nxp.com>
description: |
NXP i.MX8M Family anatop PLL module which generates PLL to CCM root.
properties:
compatible:
oneOf:
- enum:
- fsl,imx8mm-anatop
- fsl,imx8mq-anatop
- items:
- enum:
- fsl,imx8mn-anatop
- fsl,imx8mp-anatop
- const: fsl,imx8mm-anatop
reg:
maxItems: 1
interrupts:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
anatop: clock-controller@30360000 {
compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop";
reg = <0x30360000 0x10000>;
#clock-cells = <1>;
};
...

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/fsl,plldig.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding
maintainers:
- Wen He <wen.he_1@nxp.com>
description: |
NXP LS1028A has a clock domain PXLCLK0 used for the Display output
interface in the display core, as implemented in TSMC CLN28HPM PLL.
which generate and offers pixel clocks to Display.
properties:
compatible:
const: fsl,ls1028a-plldig
reg:
maxItems: 1
clocks:
maxItems: 1
'#clock-cells':
const: 0
fsl,vco-hz:
description: Optional for VCO frequency of the PLL in Hertz. The VCO frequency
of this PLL cannot be changed during runtime only at startup. Therefore,
the output frequencies are very limited and might not even closely match
the requested frequency. To work around this restriction the user may specify
its own desired VCO frequency for the PLL.
minimum: 650000000
maximum: 1300000000
default: 1188000000
required:
- compatible
- reg
- clocks
- '#clock-cells'
additionalProperties: false
examples:
# Display PIXEL Clock node:
- |
dpclk: clock-display@f1f0000 {
compatible = "fsl,ls1028a-plldig";
reg = <0xf1f0000 0xffff>;
#clock-cells = <0>;
clocks = <&osc_27m>;
};
...

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/fsl,sai-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale SAI bitclock-as-a-clock binding
maintainers:
- Michael Walle <michael@walle.cc>
description: |
It is possible to use the BCLK pin of a SAI module as a generic clock
output. Some SoC are very constrained in their pin multiplexer
configuration. Eg. pins can only be changed groups. For example, on the
LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,
the second pins are wasted. Using this binding it is possible to use the
clock of the second SAI as a MCLK clock for an audio codec, for example.
This is a composite of a gated clock and a divider clock.
properties:
compatible:
const: fsl,vf610-sai-clock
reg:
maxItems: 1
clocks:
maxItems: 1
'#clock-cells':
const: 0
required:
- compatible
- reg
- clocks
- '#clock-cells'
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
mclk: clock-mclk@f130080 {
compatible = "fsl,vf610-sai-clock";
reg = <0x0 0xf130080 0x0 0x80>;
#clock-cells = <0>;
clocks = <&parentclk>;
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/fsl,scu-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: i.MX SCU Client Device Node - Clock bindings based on SCU Message Protocol
maintainers:
- Abel Vesa <abel.vesa@nxp.com>
description: i.MX SCU Client Device Node
Client nodes are maintained as children of the relevant IMX-SCU device node.
This binding uses the common clock binding.
(Documentation/devicetree/bindings/clock/clock-bindings.txt)
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See the full list of clock IDs from
include/dt-bindings/clock/imx8qxp-clock.h
properties:
compatible:
items:
- enum:
- fsl,imx8dxl-clk
- fsl,imx8qm-clk
- fsl,imx8qxp-clk
- const: fsl,scu-clk
'#clock-cells':
const: 2
required:
- compatible
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller {
compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
#clock-cells = <2>;
};

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Fujitsu CRG11 clock driver bindings
-----------------------------------
Required properties :
- compatible : Shall contain "fujitsu,mb86s70-crg11"
- #clock-cells : Shall be 3 {cntrlr domain port}
The consumer specifies the desired clock pointing to its phandle.
Example:
clock: crg11 {
compatible = "fujitsu,mb86s70-crg11";
#clock-cells = <3>;
};
mhu: mhu0@2b1f0000 {
#mbox-cells = <1>;
compatible = "arm,mhu";
reg = <0 0x2B1F0000 0x1000>;
interrupts = <0 36 4>, /* LP Non-Sec */
<0 35 4>, /* HP Non-Sec */
<0 37 4>; /* Secure */
clocks = <&clock 0 2 1>; /* Cntrlr:0 Domain:2 Port:1 */
clock-names = "clk";
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/gpio-gate-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Simple GPIO clock gate
maintainers:
- Jyri Sarha <jsarha@ti.com>
properties:
compatible:
const: gpio-gate-clock
clocks:
maxItems: 1
'#clock-cells':
const: 0
enable-gpios:
description: GPIO reference for enabling and disabling the clock.
maxItems: 1
required:
- compatible
- '#clock-cells'
- enable-gpios
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
clock {
compatible = "gpio-gate-clock";
clocks = <&parentclk>;
#clock-cells = <0>;
enable-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/gpio-mux-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Simple GPIO clock multiplexer
maintainers:
- Sergej Sawazki <ce3a@gmx.de>
properties:
compatible:
const: gpio-mux-clock
clocks:
items:
- description: First parent clock
- description: Second parent clock
'#clock-cells':
const: 0
select-gpios:
description: GPIO reference for selecting the parent clock.
maxItems: 1
required:
- compatible
- clocks
- '#clock-cells'
- select-gpios
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
clock {
compatible = "gpio-mux-clock";
clocks = <&parentclk1>, <&parentclk2>;
#clock-cells = <0>;
select-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
};

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* Hisilicon Hi3620 Clock Controller
The Hi3620 clock controller generates and supplies clock to various
controllers within the Hi3620 SoC.
Required Properties:
- compatible: should be one of the following.
- "hisilicon,hi3620-clock" - controller compatible with Hi3620 SoC.
- "hisilicon,hi3620-mmc-clock" - controller specific for Hi3620 mmc.
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.
All these identifier could be found in <dt-bindings/clock/hi3620-clock.h>.

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* Hisilicon Hi3660 Clock Controller
The Hi3660 clock controller generates and supplies clock to various
controllers within the Hi3660 SoC.
Required Properties:
- compatible: the compatible should be one of the following strings to
indicate the clock controller functionality.
- "hisilicon,hi3660-crgctrl"
- "hisilicon,hi3660-pctrl"
- "hisilicon,hi3660-pmuctrl"
- "hisilicon,hi3660-sctrl"
- "hisilicon,hi3660-iomcu"
- "hisilicon,hi3660-stub-clk"
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
Optional Properties:
- mboxes: Phandle to the mailbox for sending message to MCU.
(See: ../mailbox/hisilicon,hi3660-mailbox.txt for more info)
Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.
All these identifier could be found in <dt-bindings/clock/hi3660-clock.h>.
Examples:
crg_ctrl: clock-controller@fff35000 {
compatible = "hisilicon,hi3660-crgctrl", "syscon";
reg = <0x0 0xfff35000 0x0 0x1000>;
#clock-cells = <1>;
};
uart0: serial@fdf02000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfdf02000 0x0 0x1000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
<&crg_ctrl HI3660_PCLK>;
clock-names = "uartclk", "apb_pclk";
};

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* Hisilicon Hi3670 Clock Controller
The Hi3670 clock controller generates and supplies clock to various
controllers within the Hi3670 SoC.
Required Properties:
- compatible: the compatible should be one of the following strings to
indicate the clock controller functionality.
- "hisilicon,hi3670-crgctrl"
- "hisilicon,hi3670-pctrl"
- "hisilicon,hi3670-pmuctrl"
- "hisilicon,hi3670-sctrl"
- "hisilicon,hi3670-iomcu"
- "hisilicon,hi3670-media1-crg"
- "hisilicon,hi3670-media2-crg"
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.
All these identifier could be found in <dt-bindings/clock/hi3670-clock.h>.
Examples:
crg_ctrl: clock-controller@fff35000 {
compatible = "hisilicon,hi3670-crgctrl", "syscon";
reg = <0x0 0xfff35000 0x0 0x1000>;
#clock-cells = <1>;
};
uart0: serial@fdf02000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfdf02000 0x0 0x1000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3670_CLK_GATE_UART0>,
<&crg_ctrl HI3670_PCLK>;
clock-names = "uartclk", "apb_pclk";
};

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* Hisilicon Hi6220 Clock Controller
Clock control registers reside in different Hi6220 system controllers,
please refer the following document to know more about the binding rules
for these system controllers:
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml
Required Properties:
- compatible: the compatible should be one of the following strings to
indicate the clock controller functionality.
- "hisilicon,hi6220-acpu-sctrl"
- "hisilicon,hi6220-aoctrl"
- "hisilicon,hi6220-sysctrl"
- "hisilicon,hi6220-mediactrl"
- "hisilicon,hi6220-pmctrl"
- "hisilicon,hi6220-stub-clk"
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
Optional Properties:
- hisilicon,hi6220-clk-sram: phandle to the syscon managing the SoC internal sram;
the driver need use the sram to pass parameters for frequency change.
- mboxes: use the label reference for the mailbox as the first parameter, the
second parameter is the channel number.
Example 1:
sys_ctrl: sys_ctrl@f7030000 {
compatible = "hisilicon,hi6220-sysctrl", "syscon";
reg = <0x0 0xf7030000 0x0 0x2000>;
#clock-cells = <1>;
};
Example 2:
stub_clock: stub_clock {
compatible = "hisilicon,hi6220-stub-clk";
hisilicon,hi6220-clk-sram = <&sram>;
#clock-cells = <1>;
mboxes = <&mailbox 1>;
};
Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.
All these identifier could be found in <dt-bindings/clock/hi6220-clock.h>.

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* HiSilicon Clock and Reset Generator(CRG)
The CRG module provides clock and reset signals to various
modules within the SoC.
This binding uses the following bindings:
Documentation/devicetree/bindings/clock/clock-bindings.txt
Documentation/devicetree/bindings/reset/reset.txt
Required Properties:
- compatible: should be one of the following.
- "hisilicon,hi3516cv300-crg"
- "hisilicon,hi3516cv300-sysctrl"
- "hisilicon,hi3519-crg"
- "hisilicon,hi3798cv200-crg"
- "hisilicon,hi3798cv200-sysctrl"
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.
All these identifier could be found in <dt-bindings/clock/hi3519-clock.h>.
- #reset-cells: should be 2.
A reset signal can be controlled by writing a bit register in the CRG module.
The reset specifier consists of two cells. The first cell represents the
register offset relative to the base address. The second cell represents the
bit index in the register.
Example: CRG nodes
CRG: clock-reset-controller@12010000 {
compatible = "hisilicon,hi3519-crg";
reg = <0x12010000 0x10000>;
#clock-cells = <1>;
#reset-cells = <2>;
};
Example: consumer nodes
i2c0: i2c@12110000 {
compatible = "hisilicon,hi3519-i2c";
reg = <0x12110000 0x1000>;
clocks = <&CRG HI3519_I2C0_RST>;
resets = <&CRG 0xe4 0>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/hisilicon,hi3559av100-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Hisilicon SOC Clock for HI3559AV100
maintainers:
- Dongjiu Geng <gengdongjiu@huawei.com>
description: |
Hisilicon SOC clock control module which supports the clocks, resets and
power domains on HI3559AV100.
See also:
dt-bindings/clock/hi3559av100-clock.h
properties:
compatible:
enum:
- hisilicon,hi3559av100-clock
- hisilicon,hi3559av100-shub-clock
reg:
minItems: 1
maxItems: 2
'#clock-cells':
const: 1
'#reset-cells':
const: 2
description: |
First cell is reset request register offset.
Second cell is bit offset in reset request register.
required:
- compatible
- reg
- '#clock-cells'
- '#reset-cells'
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@12010000 {
compatible = "hisilicon,hi3559av100-clock";
#clock-cells = <1>;
#reset-cells = <2>;
reg = <0x0 0x12010000 0x0 0x10000>;
};
};
...

30
bindings/clock/hix5hd2-clock.txt Normal file
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* Hisilicon Hix5hd2 Clock Controller
The hix5hd2 clock controller generates and supplies clock to various
controllers within the hix5hd2 SoC.
Required Properties:
- compatible: should be "hisilicon,hix5hd2-clock"
- reg: Address and length of the register set
- #clock-cells: Should be <1>
Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.
All these identifier could be found in <dt-bindings/clock/hix5hd2-clock.h>.
Examples:
clock: clock@f8a22000 {
compatible = "hisilicon,hix5hd2-clock";
reg = <0xf8a22000 0x1000>;
#clock-cells = <1>;
};
uart0: uart@f8b00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xf8b00000 0x1000>;
interrupts = <0 49 4>;
clocks = <&clock HIX5HD2_FIXED_83M>;
clock-names = "apb_pclk";
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/idt,versaclock5.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Binding for IDT VersaClock 5 and 6 programmable I2C clock generators
description: |
The IDT VersaClock 5 and VersaClock 6 are programmable I2C
clock generators providing from 3 to 12 output clocks.
When referencing the provided clock in the DT using phandle and clock
specifier, the following mapping applies:
- 5P49V5923:
0 -- OUT0_SEL_I2CB
1 -- OUT1
2 -- OUT2
- 5P49V5933:
0 -- OUT0_SEL_I2CB
1 -- OUT1
2 -- OUT4
- other parts:
0 -- OUT0_SEL_I2CB
1 -- OUT1
2 -- OUT2
3 -- OUT3
4 -- OUT4
The idt,shutdown and idt,output-enable-active properties control the
SH (en_global_shutdown) and SP bits of the Primary Source and Shutdown
Register, respectively. Their behavior is summarized by the following
table:
SH SP Output when the SD/OE pin is Low/High
== == =====================================
0 0 Active/Inactive
0 1 Inactive/Active
1 0 Active/Shutdown
1 1 Inactive/Shutdown
The case where SH and SP are both 1 is likely not very interesting.
maintainers:
- Luca Ceresoli <luca.ceresoli@bootlin.com>
properties:
compatible:
enum:
- idt,5p49v5923
- idt,5p49v5925
- idt,5p49v5933
- idt,5p49v5935
- idt,5p49v6901
- idt,5p49v6965
- idt,5p49v6975
reg:
description: I2C device address
enum: [ 0x68, 0x6a ]
'#clock-cells':
const: 1
clock-names:
minItems: 1
maxItems: 2
items:
enum: [ xin, clkin ]
clocks:
minItems: 1
maxItems: 2
idt,xtal-load-femtofarads:
minimum: 9000
maximum: 22760
description: Optional load capacitor for XTAL1 and XTAL2
idt,shutdown:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
description: |
If 1, this enables the shutdown functionality: the chip will be
shut down if the SD/OE pin is driven high. If 0, this disables the
shutdown functionality: the chip will never be shut down based on
the value of the SD/OE pin. This property corresponds to the SH
bit of the Primary Source and Shutdown Register.
idt,output-enable-active:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
description: |
If 1, this enables output when the SD/OE pin is high, and disables
output when the SD/OE pin is low. If 0, this disables output when
the SD/OE pin is high, and enables output when the SD/OE pin is
low. This corresponds to the SP bit of the Primary Source and
Shutdown Register.
patternProperties:
"^OUT[1-4]$":
type: object
description:
Description of one of the outputs (OUT1..OUT4). See "Clock1 Output
Configuration" in the Versaclock 5/6/6E Family Register Description
and Programming Guide.
properties:
idt,mode:
description:
The output drive mode. Values defined in dt-bindings/clock/versaclock.h
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 6
idt,voltage-microvolt:
description: The output drive voltage.
enum: [ 1800000, 2500000, 3300000 ]
idt,slew-percent:
description: The Slew rate control for CMOS single-ended.
enum: [ 80, 85, 90, 100 ]
additionalProperties: false
required:
- compatible
- reg
- '#clock-cells'
- idt,shutdown
- idt,output-enable-active
allOf:
- if:
properties:
compatible:
enum:
- idt,5p49v5933
- idt,5p49v5935
- idt,5p49v6975
then:
# Devices with builtin crystal + optional external input
properties:
clock-names:
const: clkin
clocks:
maxItems: 1
else:
# Devices without builtin crystal
required:
- clock-names
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/versaclock.h>
/* 25MHz reference crystal */
ref25: ref25m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
i2c@0 {
reg = <0x0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
/* IDT 5P49V5923 I2C clock generator */
vc5: clock-generator@6a {
compatible = "idt,5p49v5923";
reg = <0x6a>;
#clock-cells = <1>;
/* Connect XIN input to 25MHz reference */
clocks = <&ref25m>;
clock-names = "xin";
/* Set the SD/OE pin's settings */
idt,shutdown = <0>;
idt,output-enable-active = <0>;
OUT1 {
idt,mode = <VC5_CMOSD>;
idt,voltage-microvolt = <1800000>;
idt,slew-percent = <80>;
};
OUT4 {
idt,mode = <VC5_LVDS>;
};
};
};
...

31
bindings/clock/img,boston-clock.txt Normal file
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Binding for Imagination Technologies MIPS Boston clock sources.
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
The device node must be a child node of the syscon node corresponding to the
Boston system's platform registers.
Required properties:
- compatible : Should be "img,boston-clock".
- #clock-cells : Should be set to 1.
Values available for clock consumers can be found in the header file:
<dt-bindings/clock/boston-clock.h>
Example:
system-controller@17ffd000 {
compatible = "img,boston-platform-regs", "syscon";
reg = <0x17ffd000 0x1000>;
clk_boston: clock {
compatible = "img,boston-clock";
#clock-cells = <1>;
};
};
uart0: uart@17ffe000 {
/* ... */
clocks = <&clk_boston BOSTON_CLK_SYS>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx1-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for Freescale i.MX1 CPUs
maintainers:
- Alexander Shiyan <shc_work@mail.ru>
description: |
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx1-clock.h
for the full list of i.MX1 clock IDs.
properties:
compatible:
const: fsl,imx1-ccm
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx1-clock.h>
clock-controller@21b000 {
#clock-cells = <1>;
compatible = "fsl,imx1-ccm";
reg = <0x0021b000 0x1000>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx21-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for Freescale i.MX21
maintainers:
- Alexander Shiyan <shc_work@mail.ru>
description: |
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx21-clock.h
for the full list of i.MX21 clock IDs.
properties:
compatible:
const: fsl,imx21-ccm
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx21-clock.h>
clock-controller@10027000 {
compatible = "fsl,imx21-ccm";
reg = <0x10027000 0x800>;
#clock-cells = <1>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx23-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for Freescale i.MX23
maintainers:
- Shawn Guo <shawnguo@kernel.org>
description: |
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of i.MX23
clocks and IDs.
Clock ID
------------------
ref_xtal 0
pll 1
ref_cpu 2
ref_emi 3
ref_pix 4
ref_io 5
saif_sel 6
lcdif_sel 7
gpmi_sel 8
ssp_sel 9
emi_sel 10
cpu 11
etm_sel 12
cpu_pll 13
cpu_xtal 14
hbus 15
xbus 16
lcdif_div 17
ssp_div 18
gpmi_div 19
emi_pll 20
emi_xtal 21
etm_div 22
saif_div 23
clk32k_div 24
rtc 25
adc 26
spdif_div 27
clk32k 28
dri 29
pwm 30
filt 31
uart 32
ssp 33
gpmi 34
spdif 35
emi 36
saif 37
lcdif 38
etm 39
usb 40
usb_phy 41
properties:
compatible:
const: fsl,imx23-clkctrl
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@80040000 {
compatible = "fsl,imx23-clkctrl";
reg = <0x80040000 0x2000>;
#clock-cells = <1>;
};

178
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx25-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for Freescale i.MX25
maintainers:
- Sascha Hauer <s.hauer@pengutronix.de>
description: |
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of i.MX25
clocks and IDs.
Clock ID
--------------------------
dummy 0
osc 1
mpll 2
upll 3
mpll_cpu_3_4 4
cpu_sel 5
cpu 6
ahb 7
usb_div 8
ipg 9
per0_sel 10
per1_sel 11
per2_sel 12
per3_sel 13
per4_sel 14
per5_sel 15
per6_sel 16
per7_sel 17
per8_sel 18
per9_sel 19
per10_sel 20
per11_sel 21
per12_sel 22
per13_sel 23
per14_sel 24
per15_sel 25
per0 26
per1 27
per2 28
per3 29
per4 30
per5 31
per6 32
per7 33
per8 34
per9 35
per10 36
per11 37
per12 38
per13 39
per14 40
per15 41
csi_ipg_per 42
epit_ipg_per 43
esai_ipg_per 44
esdhc1_ipg_per 45
esdhc2_ipg_per 46
gpt_ipg_per 47
i2c_ipg_per 48
lcdc_ipg_per 49
nfc_ipg_per 50
owire_ipg_per 51
pwm_ipg_per 52
sim1_ipg_per 53
sim2_ipg_per 54
ssi1_ipg_per 55
ssi2_ipg_per 56
uart_ipg_per 57
ata_ahb 58
reserved 59
csi_ahb 60
emi_ahb 61
esai_ahb 62
esdhc1_ahb 63
esdhc2_ahb 64
fec_ahb 65
lcdc_ahb 66
rtic_ahb 67
sdma_ahb 68
slcdc_ahb 69
usbotg_ahb 70
reserved 71
reserved 72
reserved 73
reserved 74
can1_ipg 75
can2_ipg 76
csi_ipg 77
cspi1_ipg 78
cspi2_ipg 79
cspi3_ipg 80
dryice_ipg 81
ect_ipg 82
epit1_ipg 83
epit2_ipg 84
reserved 85
esdhc1_ipg 86
esdhc2_ipg 87
fec_ipg 88
reserved 89
reserved 90
reserved 91
gpt1_ipg 92
gpt2_ipg 93
gpt3_ipg 94
gpt4_ipg 95
reserved 96
reserved 97
reserved 98
iim_ipg 99
reserved 100
reserved 101
kpp_ipg 102
lcdc_ipg 103
reserved 104
pwm1_ipg 105
pwm2_ipg 106
pwm3_ipg 107
pwm4_ipg 108
rngb_ipg 109
reserved 110
scc_ipg 111
sdma_ipg 112
sim1_ipg 113
sim2_ipg 114
slcdc_ipg 115
spba_ipg 116
ssi1_ipg 117
ssi2_ipg 118
tsc_ipg 119
uart1_ipg 120
uart2_ipg 121
uart3_ipg 122
uart4_ipg 123
uart5_ipg 124
reserved 125
wdt_ipg 126
cko_div 127
cko_sel 128
cko 129
properties:
compatible:
const: fsl,imx25-ccm
reg:
maxItems: 1
interrupts:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- interrupts
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@53f80000 {
compatible = "fsl,imx25-ccm";
reg = <0x53f80000 0x4000>;
interrupts = <31>;
#clock-cells = <1>;
};

46
bindings/clock/imx27-clock.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx27-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for Freescale i.MX27
maintainers:
- Fabio Estevam <festevam@gmail.com>
description: |
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx27-clock.h
for the full list of i.MX27 clock IDs.
properties:
compatible:
const: fsl,imx27-ccm
reg:
maxItems: 1
interrupts:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx27-clock.h>
clock-controller@10027000 {
compatible = "fsl,imx27-ccm";
reg = <0x10027000 0x1000>;
interrupts = <31>;
#clock-cells = <1>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx28-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for Freescale i.MX28
maintainers:
- Shawn Guo <shawnguo@kernel.org>
description: |
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of i.MX28
clocks and IDs.
Clock ID
------------------
ref_xtal 0
pll0 1
pll1 2
pll2 3
ref_cpu 4
ref_emi 5
ref_io0 6
ref_io1 7
ref_pix 8
ref_hsadc 9
ref_gpmi 10
saif0_sel 11
saif1_sel 12
gpmi_sel 13
ssp0_sel 14
ssp1_sel 15
ssp2_sel 16
ssp3_sel 17
emi_sel 18
etm_sel 19
lcdif_sel 20
cpu 21
ptp_sel 22
cpu_pll 23
cpu_xtal 24
hbus 25
xbus 26
ssp0_div 27
ssp1_div 28
ssp2_div 29
ssp3_div 30
gpmi_div 31
emi_pll 32
emi_xtal 33
lcdif_div 34
etm_div 35
ptp 36
saif0_div 37
saif1_div 38
clk32k_div 39
rtc 40
lradc 41
spdif_div 42
clk32k 43
pwm 44
uart 45
ssp0 46
ssp1 47
ssp2 48
ssp3 49
gpmi 50
spdif 51
emi 52
saif0 53
saif1 54
lcdif 55
etm 56
fec 57
can0 58
can1 59
usb0 60
usb1 61
usb0_phy 62
usb1_phy 63
enet_out 64
properties:
compatible:
const: fsl,imx28-clkctrl
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@80040000 {
compatible = "fsl,imx28-clkctrl";
reg = <0x80040000 0x2000>;
#clock-cells = <1>;
};

112
bindings/clock/imx31-clock.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx31-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for Freescale i.MX31
maintainers:
- Fabio Estevam <festevam@gmail.com>
description: |
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of i.MX31
clocks and IDs.
Clock ID
-----------------------
dummy 0
ckih 1
ckil 2
mpll 3
spll 4
upll 5
mcu_main 6
hsp 7
ahb 8
nfc 9
ipg 10
per_div 11
per 12
csi_sel 13
fir_sel 14
csi_div 15
usb_div_pre 16
usb_div_post 17
fir_div_pre 18
fir_div_post 19
sdhc1_gate 20
sdhc2_gate 21
gpt_gate 22
epit1_gate 23
epit2_gate 24
iim_gate 25
ata_gate 26
sdma_gate 27
cspi3_gate 28
rng_gate 29
uart1_gate 30
uart2_gate 31
ssi1_gate 32
i2c1_gate 33
i2c2_gate 34
i2c3_gate 35
hantro_gate 36
mstick1_gate 37
mstick2_gate 38
csi_gate 39
rtc_gate 40
wdog_gate 41
pwm_gate 42
sim_gate 43
ect_gate 44
usb_gate 45
kpp_gate 46
ipu_gate 47
uart3_gate 48
uart4_gate 49
uart5_gate 50
owire_gate 51
ssi2_gate 52
cspi1_gate 53
cspi2_gate 54
gacc_gate 55
emi_gate 56
rtic_gate 57
firi_gate 58
properties:
compatible:
const: fsl,imx31-ccm
reg:
maxItems: 1
interrupts:
description: CCM provides 2 interrupt requests, request 1 is to generate
interrupt for DVFS when a frequency change is requested, request 2 is
to generate interrupt for DPTC when a voltage change is requested.
items:
- description: CCM DVFS interrupt request 1
- description: CCM DPTC interrupt request 2
'#clock-cells':
const: 1
required:
- compatible
- reg
- interrupts
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@53f80000 {
compatible = "fsl,imx31-ccm";
reg = <0x53f80000 0x4000>;
interrupts = <31>, <53>;
#clock-cells = <1>;
};

131
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx35-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for Freescale i.MX35
maintainers:
- Steffen Trumtrar <s.trumtrar@pengutronix.de>
description: |
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of i.MX35
clocks and IDs.
Clock ID
---------------------------
ckih 0
mpll 1
ppll 2
mpll_075 3
arm 4
hsp 5
hsp_div 6
hsp_sel 7
ahb 8
ipg 9
arm_per_div 10
ahb_per_div 11
ipg_per 12
uart_sel 13
uart_div 14
esdhc_sel 15
esdhc1_div 16
esdhc2_div 17
esdhc3_div 18
spdif_sel 19
spdif_div_pre 20
spdif_div_post 21
ssi_sel 22
ssi1_div_pre 23
ssi1_div_post 24
ssi2_div_pre 25
ssi2_div_post 26
usb_sel 27
usb_div 28
nfc_div 29
asrc_gate 30
pata_gate 31
audmux_gate 32
can1_gate 33
can2_gate 34
cspi1_gate 35
cspi2_gate 36
ect_gate 37
edio_gate 38
emi_gate 39
epit1_gate 40
epit2_gate 41
esai_gate 42
esdhc1_gate 43
esdhc2_gate 44
esdhc3_gate 45
fec_gate 46
gpio1_gate 47
gpio2_gate 48
gpio3_gate 49
gpt_gate 50
i2c1_gate 51
i2c2_gate 52
i2c3_gate 53
iomuxc_gate 54
ipu_gate 55
kpp_gate 56
mlb_gate 57
mshc_gate 58
owire_gate 59
pwm_gate 60
rngc_gate 61
rtc_gate 62
rtic_gate 63
scc_gate 64
sdma_gate 65
spba_gate 66
spdif_gate 67
ssi1_gate 68
ssi2_gate 69
uart1_gate 70
uart2_gate 71
uart3_gate 72
usbotg_gate 73
wdog_gate 74
max_gate 75
admux_gate 76
csi_gate 77
csi_div 78
csi_sel 79
iim_gate 80
gpu2d_gate 81
ckli_gate 82
properties:
compatible:
const: fsl,imx35-ccm
reg:
maxItems: 1
interrupts:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- interrupts
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@53f80000 {
compatible = "fsl,imx35-ccm";
reg = <0x53f80000 0x4000>;
interrupts = <31>;
#clock-cells = <1>;
};

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