From 21931c9f8fc1e8734b5cd1806f07e3777be2fe44 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Mon, 22 Apr 2024 17:25:39 +0530 Subject: [PATCH] ARM: dts: msm: Add support for dummy clocks/GDSCs for kera Add the dummy clock and gdsc handles for clients to be able to request on them for kera platform. Change-Id: I24fa8bf818483947760c8b87497b25bcf40be84c Signed-off-by: Anaadi Mishra --- qcom/kera.dtsi | 229 ++++++++++++++++++++++++++++++++++++++++++++ qcom/tuna-gdsc.dtsi | 31 ++++++ 2 files changed, 260 insertions(+) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 47451b2e..a235c5d8 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -3,6 +3,14 @@ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include +#include +#include +#include +#include +#include +#include +#include #include #include @@ -293,6 +301,227 @@ #interrupt-cells = <3>; #mbox-cells = <2>; }; + + clocks { + xo_board: xo_board { + compatible = "fixed-clock"; + clock-frequency = <76800000>; + clock-output-names = "xo_board"; + #clock-cells = <0>; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + clock-output-names = "sleep_clk"; + #clock-cells = <0>; + }; + + pcie_0_pipe_clk: pcie_0_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_0_pipe_clk"; + #clock-cells = <0>; + }; + + pcie_1_pipe_clk: pcie_1_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_1_pipe_clk"; + #clock-cells = <0>; + }; + + ufs_phy_rx_symbol_0_clk: ufs_phy_rx_symbol_0_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_phy_rx_symbol_0_clk"; + #clock-cells = <0>; + }; + + ufs_phy_rx_symbol_1_clk: ufs_phy_rx_symbol_1_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_phy_rx_symbol_1_clk"; + #clock-cells = <0>; + }; + + ufs_phy_tx_symbol_0_clk: ufs_phy_tx_symbol_0_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_phy_tx_symbol_0_clk"; + #clock-cells = <0>; + }; + + usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk"; + #clock-cells = <0>; + }; + }; + + rpmhcc: clock-controller { + compatible = "fixed-clock"; + clock-output-names = "rpmh_clocks"; + clock-frequency = <19200000>; + #clock-cells = <1>; + }; + + cambistmclkcc: clock-controller@1760000 { + compatible = "qcom,dummycc"; + clock-output-names = "cambistmclkcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + camcc: clock-controller@ade0000 { + compatible = "qcom,dummycc"; + clock-output-names = "camcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,dummycc"; + clock-output-names = "dispcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gcc: clock-controller@100000 { + compatible = "qcom,dummycc"; + clock-output-names = "gcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,dummycc"; + clock-output-names = "gpucc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + tcsrcc: clock-controller@1f40000 { + compatible = "qcom,dummycc"; + clock-output-names = "tcsrcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + videocc: clock-controller@aaf0000 { + compatible = "qcom,dummycc"; + clock-output-names = "videocc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; +}; + +#include "tuna-gdsc.dtsi" + +&cam_cc_ipe_0_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&cam_cc_ofe_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&cam_cc_tfe_0_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&cam_cc_tfe_1_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&cam_cc_tfe_2_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&cam_cc_titan_top_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&disp_cc_mdss_core_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&disp_cc_mdss_core_int2_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&gcc_pcie_0_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&gcc_pcie_0_phy_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&gcc_pcie_1_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&gcc_pcie_1_phy_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&gcc_ufs_mem_phy_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&gcc_ufs_phy_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&gcc_usb30_prim_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&gcc_usb3_phy_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&gpu_cc_cx_gdsc_hw_ctrl { + reg = <0x3d99124 0x4>; +}; + +&gpu_cc_cx_gdsc { + compatible = "regulator-fixed"; + reg = <0x3d99110 0x4>; + status = "ok"; +}; + +&gpu_cc_gx_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&video_cc_mvs0_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&video_cc_mvs0c_gdsc { + compatible = "regulator-fixed"; + status = "ok"; }; #include "kera-pinctrl.dtsi" diff --git a/qcom/tuna-gdsc.dtsi b/qcom/tuna-gdsc.dtsi index 8524ab0f..d01386f7 100644 --- a/qcom/tuna-gdsc.dtsi +++ b/qcom/tuna-gdsc.dtsi @@ -138,6 +138,28 @@ status = "disabled"; }; + gcc_pcie_1_gdsc: qcom,gdsc@1ac004 { + compatible = "qcom,gdsc"; + reg = <0x1ac004 0x4>; + regulator-name = "gcc_pcie_1_gdsc"; + qcom,retain-regs; + qcom,no-status-check-on-disable; + qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 3>; + qcom,support-cfg-gdscr; + status = "disabled"; + }; + + gcc_pcie_1_phy_gdsc: qcom,gdsc@1ad000 { + compatible = "qcom,gdsc"; + reg = <0x1ad000 0x4>; + regulator-name = "gcc_pcie_1_phy_gdsc"; + qcom,retain-regs; + qcom,no-status-check-on-disable; + qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 4>; + qcom,support-cfg-gdscr; + status = "disabled"; + }; + gcc_ufs_mem_phy_gdsc: qcom,gdsc@19e000 { compatible = "qcom,gdsc"; reg = <0x19e000 0x4>; @@ -201,6 +223,15 @@ status = "disabled"; }; + gpu_cc_gx_gdsc: qcom,gdsc@3d9905c { + compatible = "regulator-fixed"; + reg = <0x3d9905c 0x4>; + regulator-name = "gpu_cc_gx_gdsc"; + qcom,retain-regs; + qcom,support-cfg-gdscr; + status = "disabled"; + }; + /* GX_CLKCTL GDSCs */ gx_clkctl_gx_gdsc: qcom,gdsc@3d68024 { compatible = "qcom,gdsc";