From 5c089eb2319e544683bb13794fcdc73542742074 Mon Sep 17 00:00:00 2001 From: Hrishabh Rajput Date: Wed, 22 May 2024 13:50:40 +0530 Subject: [PATCH 01/55] bindings: Update fields in TLMM VM bindings for Sun Current bindings do not cover many of the fields. Update TLMM VM bindings for Sun VM making the documentation more comprehensive. Change-Id: I99e6dda2b8a7dc86cc1c92dfe668ca2f954afb2f Signed-off-by: Hrishabh Rajput --- bindings/pinctrl/qcom,sun-vm-tlmm.yaml | 167 ++++++++++++++++++++++++- 1 file changed, 163 insertions(+), 4 deletions(-) diff --git a/bindings/pinctrl/qcom,sun-vm-tlmm.yaml b/bindings/pinctrl/qcom,sun-vm-tlmm.yaml index d2a07ff9..75e8e20b 100644 --- a/bindings/pinctrl/qcom,sun-vm-tlmm.yaml +++ b/bindings/pinctrl/qcom,sun-vm-tlmm.yaml @@ -13,19 +13,178 @@ maintainers: description: | This binding describes the Top Level Mode Multiplexer block for VM. +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + properties: compatible: const: qcom,sun-vm-tlmm + reg: + maxItems: 1 + + interrupts-extended: true + interrupt-controller: true + '#interrupt-cells': true + + gpio-controller: true + '#gpio-cells': true + gpio-ranges: true + gpios: + description: array of gpio pin number required by VM TLMM clients + +required: + - compatible + - reg + +additionalProperties: false + +patternProperties: + '-state$': + oneOf: + - $ref: "#/$defs/qcom-sun-vm-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sun-vm-tlmm-state" + additionalProperties: false + +$defs: + qcom-sun-vm-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-4])$" + - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ aoss_cti, atest_char0, atest_char1, atest_char2, atest_char3, + atest_char_start, atest_usb0, atest_usb00, atest_usb01, + atest_usb02, atest_usb03, audio_ext_mclk0, audio_ext_mclk1, + audio_ref_clk, cam_aon_mclk2, cam_aon_mclk4, cam_mclk, + cci_async_in0, cci_async_in1, cci_async_in2, cci_i2c_scl0, + cci_i2c_scl1, cci_i2c_scl2, cci_i2c_scl3, cci_i2c_scl4, + cci_i2c_scl5, cci_i2c_sda0, cci_i2c_sda1, cci_i2c_sda2, + cci_i2c_sda3, cci_i2c_sda4, cci_i2c_sda5, cci_timer0, + cci_timer1, cci_timer2, cci_timer3, cci_timer4, cmu_rng0, + cmu_rng1, cmu_rng2, cmu_rng3, coex_uart1_rx, coex_uart1_tx, + coex_uart2_rx, coex_uart2_tx, dbg_out_clk, ddr_bist_complete, + ddr_bist_fail, ddr_bist_start, ddr_bist_stop, ddr_pxi0, + ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, egpio, gcc_gp1, gcc_gp2, + gcc_gp3, gnss_adc0, gnss_adc1, gpio, i2chub0_se0_l0, + i2chub0_se0_l1, i2chub0_se1_l0, i2chub0_se1_l1, i2chub0_se2_l0, + i2chub0_se2_l1, i2chub0_se3_l0,i2chub0_se3_l1, i2chub0_se4_l0, + i2chub0_se4_l1, i2chub0_se5_l0, i2chub0_se5_l1, i2chub0_se6_l0, + i2chub0_se6_l1, i2chub0_se7_l0, i2chub0_se7_l1, i2chub0_se8_l0, + i2chub0_se8_l1, i2chub0_se9_l0, i2chub0_se9_l1, i2s0_data0, + i2s0_data1, i2s0_sck, i2s0_ws, i2s1_data0, i2s1_data1, i2s1_sck, + i2s1_ws, ibi_i3c, jitter_bist, mdp_esync_0, mdp_esync_1, + mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, mdp_vsync2_out, + mdp_vsync3_out, mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, + nav_gpio3, pcie0_clk_req_n, phase_flag0, phase_flag1, + phase_flag10, phase_flag11, phase_flag12, phase_flag13, + phase_flag14, phase_flag15, phase_flag16, phase_flag17, + phase_flag18, phase_flag19, phase_flag2, phase_flag20, + phase_flag21, phase_flag22, phase_flag23, phase_flag24, + phase_flag25, phase_flag26, phase_flag27, phase_flag28, + phase_flag29, phase_flag3, phase_flag30, phase_flag31, + phase_flag4, phase_flag5, phase_flag6, phase_flag7, phase_flag8, + phase_flag9, pll_bist_sync, pll_clk_aux, prng_rosc0, prng_rosc1, + prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, qdss_gpio0, + qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, + qdss_gpio14, qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, + qdss_gpio5, qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9, + qlink_big_enable, qlink_big_request, qlink_little_enable, + qlink_little_request, qlink_wmss, qspi0, qspi1, qspi2, qspi3, + qspi_clk, qspi_cs, qup1_se0_l0, qup1_se0_l1, qup1_se0_l2, + qup1_se0_l3, qup1_se1_l0, qup1_se1_l1, qup1_se1_l2, qup1_se1_l3, + qup1_se2_l0, qup1_se2_l1, qup1_se2_l2, qup1_se2_l3, qup1_se2_l4, + qup1_se2_l5, qup1_se2_l6, qup1_se3_l0, qup1_se3_l1, qup1_se3_l2, + qup1_se3_l3, qup1_se4_l0, qup1_se4_l1, qup1_se4_l2, qup1_se4_l3, + qup1_se5_l0, qup1_se5_l1, qup1_se5_l2, qup1_se5_l3, qup1_se6_l0, + qup1_se6_l1, qup1_se6_l2, qup1_se6_l3, qup1_se7_l0, qup1_se7_l1, + qup1_se7_l2, qup1_se7_l3, qup2_se0_l0, qup2_se0_l1, qup2_se0_l2, + qup2_se0_l3, qup2_se1_l0, qup2_se1_l1, qup2_se1_l2, qup2_se1_l3, + qup2_se2_l0, qup2_se2_l1, qup2_se2_l2, qup2_se2_l3, qup2_se2_l4, + qup2_se2_l5, qup2_se2_l6, qup2_se3_l0, qup2_se3_l1, qup2_se3_l2, + qup2_se3_l3, qup2_se4_l0, qup2_se4_l1, qup2_se4_l2, qup2_se4_l3, + qup2_se5_l0, qup2_se5_l1, qup2_se5_l2, qup2_se5_l3, qup2_se5_l6, + qup2_se6_l0, qup2_se6_l1, qup2_se6_l2, qup2_se6_l3, qup2_se7_l0, + qup2_se7_l1, qup2_se7_l2, qup2_se7_l3, sd_write_protect, sdc40, + sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, tb_trig_sdc2, + tb_trig_sdc4, tmess_prng0, tmess_prng1, tmess_prng2, + tmess_prng3, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4, + uim0_clk, uim0_data, uim0_present, uim0_reset, uim1_clk, + uim1_data, uim1_present, uim1_reset, usb1_hs, usb_phy, vfr_0, + vfr_1, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl ] + + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: true + input-enable: true + output-high: true + output-low: true + + required: + - pins + + allOf: + - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" + - if: + properties: + pins: + pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$" + then: + required: + - function + + additionalProperties: false + examples: - | - tlmm: pinctrl@03000000 { + #include + pinctrl@f100000 { compatible = "qcom,sun-vm-tlmm"; - reg = <0x03000000 0xdc2000>; - interrupts-extended = <0 208 0>; + reg = <0x0f100000 0x300000>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 211>; interrupt-controller; #interrupt-cells = <2>; - gpios = /bits/ 16 <0 1>; + interrupts-extended = ; + + gpio-wo-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-state { + rx-pins { + pins = "gpio26"; + function = "qup1_se7_l0"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio27"; + function = "qup1_se7_l1"; + bias-disable; + }; + }; }; +... From 0e2489326f56fbbdce7a7387770ecca73fe47d62 Mon Sep 17 00:00:00 2001 From: Ramireddy KrishnaKanth Reddy Date: Tue, 25 Jun 2024 18:03:31 +0530 Subject: [PATCH 02/55] ARM: dts: msm: Enable fsa4480 in parrot dtsi Add compatible string for fsa4480 parrot. Change-Id: I3c9bea536817c0a80fcc6342b6d0788e1e84d476 Signed-off-by: Ramireddy KrishnaKanth Reddy --- qcom/parrot.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/parrot.dtsi b/qcom/parrot.dtsi index 0b1c2cca..ec24ae5c 100644 --- a/qcom/parrot.dtsi +++ b/qcom/parrot.dtsi @@ -2884,6 +2884,7 @@ status = "ok"; fsa4480: fsa4480@42 { + compatible = "qcom,fsa4480-i2c"; reg = <0x42>; }; }; From d0c70244cbafa935085b89b7ceeae46b87ff834d Mon Sep 17 00:00:00 2001 From: Gaurav Kashyap Date: Thu, 27 Jun 2024 18:05:52 -0700 Subject: [PATCH 03/55] ARM: dts: msm: Disable clock gating for sun Disable the GPCE clock gating enabled on sun kernels. Change-Id: I6cf212c53dcc8252e2561089e2d7ad3c7bd4cea4 Signed-off-by: Gaurav Kashyap --- qcom/sun.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 23eb6915..a2a87a18 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -2363,6 +2363,7 @@ qcom,bam-ee = <0>; qcom,smmu-s1-enable; qcom,no-clock-support; + qcom,no-clk-gating; interconnect-names = "data_path"; interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; iommus = <&apps_smmu 0x0480 0x0>, From 58f53c452942d435f884dc6096ff5aaa7d5a4bcc Mon Sep 17 00:00:00 2001 From: Manish Pandey Date: Mon, 17 Jun 2024 13:51:28 +0530 Subject: [PATCH 04/55] ARM: dts: msm: Add UFS ESI CPU mask for pineapple Add CPUs for each CQ in qcom,esi-affinity-mask. Change-Id: I0f19b4b162f91f5a9e6a194fcb194fed4902fce4 Signed-off-by: Manish Pandey --- qcom/pineapple.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/pineapple.dtsi b/qcom/pineapple.dtsi index ef9c9d1a..394325b8 100644 --- a/qcom/pineapple.dtsi +++ b/qcom/pineapple.dtsi @@ -1501,7 +1501,7 @@ qcom,ice-use-hwkm; qcom,prime-mask = <0x80>; qcom,silver-mask = <0x0f>; - qcom,esi-affinity-mask = <0xe0>; + qcom,esi-affinity-mask = <5 6 7 5 6 7 5 6>; lanes-per-direction = <2>; dev-ref-clk-freq = <0>; /* 19.2 MHz */ From fb72445b5c24fb2bd1fb54231a8859be11d037e5 Mon Sep 17 00:00:00 2001 From: Pranav Mahesh Phansalkar Date: Mon, 13 May 2024 10:58:32 +0530 Subject: [PATCH 05/55] ARM: dts: qcom: Add aoss, aop and tme nodes for tuna Add devicetree nodes to enable qmp communication with aop and tme. Change-Id: If869e4d16758d53808852517532aaf2a2ed98846 Signed-off-by: Pranav Mahesh Phansalkar --- qcom/tuna.dtsi | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index eaaff929..8f2c86c8 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -493,6 +493,44 @@ #mbox-cells = <2>; }; + aoss_qmp: power-controller@c300000 { + compatible = "qcom,aoss-qmp"; + reg = <0xc300000 0x400>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + qmp_aop: qcom,qmp-aop { + compatible = "qcom,qmp-mbox"; + qcom,qmp = <&aoss_qmp>; + label = "aop"; + #mbox-cells = <1>; + }; + + qmp_tme: qcom,qmp-tme { + compatible = "qcom,qmp-mbox"; + qcom,remote-pid = <14>; + mboxes = <&ipcc_mproc IPCC_CLIENT_TME + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "tme_qmp"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "tme"; + qcom,early-boot; + priority = <0>; + mbox-desc-offset = <0x0>; + #mbox-cells = <1>; + }; + clocks { xo_board: xo_board { compatible = "fixed-clock"; From 65104c0f2c2173eefa75a5d3077eea83a189b97c Mon Sep 17 00:00:00 2001 From: Vijayanand Jitta Date: Mon, 22 Apr 2024 19:26:46 +0530 Subject: [PATCH 06/55] ARM: dts: msm: Add initial SMMU configuration for tuna Add initial apps and gpu SMMU configuration for tuna. Change-Id: Icee98ad4ce7639a398e026e9f2c805d67d3afb06 Signed-off-by: Vijayanand Jitta --- qcom/msm-arm-smmu-tuna.dtsi | 296 ++++++++++++++++++++++++++++++++++++ qcom/tuna.dtsi | 1 + 2 files changed, 297 insertions(+) create mode 100644 qcom/msm-arm-smmu-tuna.dtsi diff --git a/qcom/msm-arm-smmu-tuna.dtsi b/qcom/msm-arm-smmu-tuna.dtsi new file mode 100644 index 00000000..c2367e2c --- /dev/null +++ b/qcom/msm-arm-smmu-tuna.dtsi @@ -0,0 +1,296 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + kgsl_smmu: kgsl-smmu@3da0000 { + compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu"; + reg = <0x3da0000 0x40000>; + #iommu-cells = <2>; + qcom,use-3-lvl-tables; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + dma-coherent; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + gpu_qtb: gpu_qtb@3de8000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x3de8000 0x1000>; + qcom,stream-id-range = <0x0 0x400>; + qcom,iova-width = <49>; + qcom,num-qtb-ports = <2>; + }; + }; + + apps_smmu: apps-smmu@15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x100000>; + #iommu-cells = <2>; + qcom,use-3-lvl-tables; + qcom,handoff-smrs = <0x800 0x2>; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + dma-coherent; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + anoc_1_qtb: anoc_1_qtb@16f2000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x16f2000 0x1000>; + qcom,stream-id-range = <0x0 0x400>; + qcom,iova-width = <36>; + qcom,num-qtb-ports = <1>; + }; + + anoc_2_qtb: anoc_2_qtb@171b000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x171b000 0x1000>; + qcom,stream-id-range = <0x400 0x400>; + qcom,iova-width = <36>; + qcom,num-qtb-ports = <1>; + }; + + cam_hf_qtb: cam_hf_qtb@17f7000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x17f7000 0x1000>; + qcom,stream-id-range = <0x1c00 0x400>; + qcom,iova-width = <32>; + qcom,num-qtb-ports = <2>; + }; + + nsp_qtb: nsp_qtb@7d3000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x7d3000 0x1000>; + qcom,stream-id-range = <0xc00 0x400>; + qcom,iova-width = <32>; + qcom,num-qtb-ports = <2>; + }; + + lpass_qtb: lpass_qtb@7b3000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x7b3000 0x1000>; + qcom,stream-id-range = <0x1000 0x400>; + qcom,iova-width = <32>; + qcom,num-qtb-ports = <1>; + }; + + pcie_qtb: pcie_qtb@16cd000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x16cd000 0x1000>; + qcom,stream-id-range = <0x1400 0x400>; + qcom,iova-width = <32>; + qcom,num-qtb-ports = <1>; + qcom,opt-out-tbu-halting; + }; + + sf_qtb: sf_qtb@17b7000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x17b7000 0x1000>; + qcom,stream-id-range = <0x1800 0x400>; + qcom,iova-width = <32>; + qcom,num-qtb-ports = <2>; + }; + + mdp_hf_qtb: mdp_hf_qtb@17f6000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x17f6000 0x1000>; + qcom,stream-id-range = <0x800 0x400>; + qcom,iova-width = <36>; + qcom,num-qtb-ports = <2>; + }; + }; + + dma_dev { + compatible = "qcom,iommu-dma"; + memory-region = <&system_cma>; + }; + + iommu_test_device { + compatible = "qcom,iommu-debug-test"; + + usecase0_apps { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x400 0x0>; + }; + + usecase1_apps_fastmap { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x400 0x0>; + qcom,iommu-dma = "fastmap"; + }; + + usecase2_apps_atomic { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x400 0x0>; + qcom,iommu-dma = "atomic"; + }; + + usecase3_apps_dma { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x400 0x0>; + dma-coherent; + }; + + usecase4_apps_secure { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x400 0x0>; + qcom,iommu-vmid = <0xa>; /* VMID_CP_PIXEL */ + }; + + usecase5_kgsl { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&kgsl_smmu 0x7 0x0>; + }; + + usecase6_kgsl_dma { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&kgsl_smmu 0x7 0x0>; + dma-coherent; + }; + }; +}; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 59675080..5e35de50 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -211,6 +211,7 @@ }; #include "tuna-reserved-memory.dtsi" +#include "msm-arm-smmu-tuna.dtsi" &reserved_memory { #address-cells = <2>; From 1566dc4a8e99ff4dc67ad1998e74e178d3eed53f Mon Sep 17 00:00:00 2001 From: Pranav Mahesh Phansalkar Date: Thu, 16 May 2024 21:56:50 +0530 Subject: [PATCH 07/55] ARM: dts: msm: Add smp2p for tuna Add the smp2p nodes for lpaidsp, modem, cdsp and soccp for tuna. Change-Id: I465ddbfcb6e69a65b730e395e705e08bc75c5060 Signed-off-by: Pranav Mahesh Phansalkar --- qcom/tuna.dtsi | 154 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 154 insertions(+) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 8f2c86c8..c4e8de38 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -531,6 +531,160 @@ #mbox-cells = <1>; }; + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sleepstate_smp2p_out: sleepstate-out { + qcom,entry-name = "sleepstate"; + #qcom,smem-state-cells = <1>; + }; + + sleepstate_smp2p_in: qcom,sleepstate-in { + qcom,entry-name = "sleepstate_see"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg2_out: qcom,smp2p-rdbg2-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg2_in: qcom,smp2p-rdbg2-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + + qcom,smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg5_out: qcom,smp2p-rdbg5-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg5_in: qcom,smp2p-rdbg5-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + /* ipa - inbound entry from mss */ + smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_smem_mailbox_1_out: qcom,smp2p-smem-mailbox-1-out { + qcom,entry-name = "smem-mailbox"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_smem_mailbox_1_in: qcom,smp2p-smem-mailbox-1-in { + qcom,entry-name = "smem-mailbox"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-soccp { + compatible = "qcom,smp2p"; + qcom,smem = <617>, <616>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_SOCCP IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <19>; + + soccp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + soccp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p_sleepstate { + compatible = "qcom,smp2p-sleepstate"; + qcom,smem-states = <&sleepstate_smp2p_out 0>; + interrupt-parent = <&sleepstate_smp2p_in>; + interrupts = <0 0>; + interrupt-names = "smp2p-sleepstate-in"; + }; + clocks { xo_board: xo_board { compatible = "fixed-clock"; From 4b335c6e901e7b0611c66ff0864de68bc0886570 Mon Sep 17 00:00:00 2001 From: Shilpa Suresh Date: Tue, 2 Jul 2024 15:51:15 +0530 Subject: [PATCH 08/55] ARM: dts: msm: Add qcom,force-low-pwm-size prop for ravelin pm6450 For backward compatibility for ravelin target, add qcom,force-low-pwm-size property to limit setting PWM sizes to 6 and 9 bit modes only, rather than using the full 8 to 15 bit PWM sizes range. Change-Id: I3fdf12f49cec92cfb02ef994b6abbebbd29cc8e9 Signed-off-by: Shilpa Suresh --- qcom/ravelin-pmic-overlay.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/ravelin-pmic-overlay.dtsi b/qcom/ravelin-pmic-overlay.dtsi index d6bc3028..322063f1 100644 --- a/qcom/ravelin-pmic-overlay.dtsi +++ b/qcom/ravelin-pmic-overlay.dtsi @@ -636,6 +636,7 @@ &pm6450_pwm_1 { status = "ok"; + qcom,force-low-pwm-size; }; &pm6450_gpios { From a78b0ff36ecba9a8261af1915c7c788ee12ad5a9 Mon Sep 17 00:00:00 2001 From: Saranya R Date: Tue, 2 Jul 2024 18:38:54 +0530 Subject: [PATCH 09/55] ARM: dts: msm: Use "iommu-addresses" property for ravelin qup Use upstream compatible DT property "iommu-addresses" instead of "qcom,iommu-dma-addr-pool" for qup which describes the addresses that qup cannot use. Change-Id: I8912ee5a256a15ed8e0cb729dd784bce4568c4fb Signed-off-by: Saranya R --- qcom/ravelin-qupv3.dtsi | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/qcom/ravelin-qupv3.dtsi b/qcom/ravelin-qupv3.dtsi index aeceb616..904c2722 100644 --- a/qcom/ravelin-qupv3.dtsi +++ b/qcom/ravelin-qupv3.dtsi @@ -17,6 +17,13 @@ * Qup1 4: SE 9 */ + qup_iommu_region: qup_iommu_region { + iommu-addresses = <&gpi_dma0 0x0 0x100000>, <&gpi_dma0 0x200000 0xffe00000>, + <&qupv3_0 0x0 0x40000000>, <&qupv3_0 0x50000000 0xb0000000>, + <&gpi_dma1 0x0 0x100000>, <&gpi_dma1 0x200000 0xffe00000>, + <&qupv3_1 0x0 0x40000000>, <&qupv3_1 0x50000000 0xb0000000>; + }; + /* GPI Instance */ gpi_dma0: qcom,gpi-dma@900000 { compatible = "qcom,gpi-dma"; @@ -40,7 +47,7 @@ qcom,static-gpii-mask = <0x1>; qcom,gpii-mask = <0x3e>; qcom,ev-factor = <2>; - qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + memory-region = <&qup_iommu_region>; dma-coherent; qcom,gpi-ee-offset = <0x10000>; status = "ok"; @@ -56,7 +63,7 @@ clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; iommus = <&apps_smmu 0x163 0x0>; - qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + memory-region = <&qup_iommu_region>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; dma-coherent; @@ -294,7 +301,7 @@ ; qcom,gpii-mask = <0x3f>; qcom,ev-factor = <2>; - qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + memory-region = <&qup_iommu_region>; dma-coherent; qcom,gpi-ee-offset = <0x10000>; status = "ok"; @@ -310,7 +317,7 @@ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; iommus = <&apps_smmu 0x403 0x0>; - qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + memory-region = <&qup_iommu_region>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; dma-coherent; From 029a884638c14181ace49eb3dae9d7057f05c8a3 Mon Sep 17 00:00:00 2001 From: Akshay Gola Date: Thu, 27 Jun 2024 17:24:38 +0530 Subject: [PATCH 10/55] ARM: dts: msm: Enable parade touch driver node Enable parade touch driver node and add its documentation for bring-up. Change-Id: I717186399283741c7c1957acc3319148b4d843f3 Signed-off-by: Akshay Gola --- bindings/input/touchscreen/parade_pt.yaml | 69 +++++++++++++++++++++++ qcom/monaco.dtsi | 2 +- 2 files changed, 70 insertions(+), 1 deletion(-) create mode 100644 bindings/input/touchscreen/parade_pt.yaml diff --git a/bindings/input/touchscreen/parade_pt.yaml b/bindings/input/touchscreen/parade_pt.yaml new file mode 100644 index 00000000..e582ecad --- /dev/null +++ b/bindings/input/touchscreen/parade_pt.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/parade_pt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Parade pt touch controller + +description: The Parade Touch controller is connected to the + host processor via I2C. The controller generates interrupts + when the user touches the panel. The host controller is + expected to read the touch coordinates over I2C and pass + the coordinates to the rest of the system. + +maintainers: + - Akshay Gola + +allOf: + - $ref: touchscreen.yaml# + +properties: + compatible: + enum: + - parade,pt_i2c_adapter + + reg: + description: i2c slave address of the device. + + vdd-supply: + description: digital voltage power supply needed to power device. + + vcc_i2c-supply: + description: i2c voltage power supply needed to power device. + + parade,reset-gpio: + description: reset gpio + + parade,irq-gpio: + description: irq gpio + +unevaluatedProperties: false + +required: + - compatible + - reg + - vdd-supply + - vcc_i2c-supply + - parade,reset-gpio + - parade,irq-gpio + +examples: + - | + &i2c_1 { + status = "ok"; + + tsc@24 { + compatible = "parade,pt_i2c_adapter"; + reg = <0x24>; + status = "ok"; + + vdd-supply = <&L29A>; + vcc_i2c-supply = <&L21A>; + + parade,core { + parade,rst_gpio = <&tlmm 71 0x00>; + parade,irq_gpio = <&tlmm 80 0x2008>; + }; + }; + }; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index b1777b35..e99ea4d5 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -2157,7 +2157,7 @@ status = "ok"; tsc@24 { - /* compatible = "parade,pt_i2c_adapter"; */ + compatible = "parade,pt_i2c_adapter"; reg = <0x24>; status = "ok"; interrupt-parent = <&tlmm>; From e9b1f9d2ec8a0fa2f80b4c1a7c7b2d6ba0f986d5 Mon Sep 17 00:00:00 2001 From: Archana Sriram Date: Thu, 27 Jun 2024 16:12:52 +0530 Subject: [PATCH 11/55] ARM: dts: msm: Update iova-width for gfx tbu nodes for ravelin Update iova-width property for gfx_0_tbu and gfx_1_tbu nodes under kgsl-smmu for ravelin. Change-Id: Ib43fa6ca8a66716b8604658413f05551e5b04826 Signed-off-by: Archana Sriram --- qcom/msm-arm-smmu-ravelin.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/msm-arm-smmu-ravelin.dtsi b/qcom/msm-arm-smmu-ravelin.dtsi index 6ebf4e64..9a306b02 100644 --- a/qcom/msm-arm-smmu-ravelin.dtsi +++ b/qcom/msm-arm-smmu-ravelin.dtsi @@ -62,6 +62,7 @@ <0x3dc2200 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x0 0x400>; + qcom,iova-width = <49>; }; gfx_1_tbu: gfx_1_tbu@3dc9000 { @@ -70,6 +71,7 @@ <0x3dc2208 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x400 0x400>; + qcom,iova-width = <49>; }; }; From e66dd43421275c4a379b569351b198081847d7de Mon Sep 17 00:00:00 2001 From: Naini Singh Date: Wed, 29 May 2024 17:26:58 +0530 Subject: [PATCH 12/55] dt-bindings: arm: msm: qcom,llcc: Add compatible for Kera SoC Add compatible string for Kera SoC. Change-Id: If5b4edbea639c5720ddfbbfc2f98922f295126e2 Signed-off-by: Naini Singh Signed-off-by: Mukesh Ojha --- bindings/arm/msm/qcom,llcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/arm/msm/qcom,llcc.yaml b/bindings/arm/msm/qcom,llcc.yaml index 95f2011d..20bf3c49 100644 --- a/bindings/arm/msm/qcom,llcc.yaml +++ b/bindings/arm/msm/qcom,llcc.yaml @@ -34,6 +34,7 @@ properties: - qcom,sm8550-llcc - qcom,pineapple-llcc - qcom,sun-llcc + - qcom,kera-llcc - qcom,x1e80100-llcc reg: From 7fab9d6a3d6927dfa396a1873ff004583b18b76f Mon Sep 17 00:00:00 2001 From: Naini Singh Date: Thu, 6 Jun 2024 14:28:22 +0530 Subject: [PATCH 13/55] ARM: dts: msm: Add LLCC node for Kera SoC Add LLCC node for Kera SoC. Change-Id: Ib7cb07d1a36519dff7aa067da6fe54be2dafedfa Signed-off-by: Naini Singh Signed-off-by: Mukesh Ojha --- qcom/kera.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 63587bc6..6c28bff3 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -379,6 +379,16 @@ #mbox-cells = <2>; }; + cache-controller@24800000 { + compatible = "qcom,kera-llcc"; + reg = <0x24800000 0x200000>, <0x24C00000 0x200000>, + <0x26800000 0x200000>, <0x26C00000 0x200000>; + reg-names = "llcc0_base", "llcc2_base", + "llcc_broadcast_or_base", "llcc_broadcast_and_base"; + interrupts = ; + cap-based-alloc-and-pwr-collapse; + }; + clocks { xo_board: xo_board { compatible = "fixed-clock"; From 49bf43396be67d54e4069c6fab9c1ce63ef586a9 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 4 Jul 2024 12:33:07 +0530 Subject: [PATCH 14/55] ARM: dts: qcom: Add EUD node for Kera Add EUD node in device tree to enable EUD driver on Kera SoC. Change-Id: I94aacb9b223b9935c78045bfc3de9179f3bf9871 Signed-off-by: Mukesh Ojha --- qcom/kera.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 6c28bff3..1c383ac8 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -389,6 +389,19 @@ cap-based-alloc-and-pwr-collapse; }; + eud: qcom,msm-eud@88e0000 { + compatible = "qcom,msm-eud"; + interrupt-names = "eud_irq"; + interrupt-parent = <&pdc>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x88e0000 0x2000>, + <0x88e2000 0x1000>; + reg-names = "eud_base", "eud_mode_mgr2"; + qcom,secure-eud-en; + qcom,eud-utmi-delay = /bits/ 16 <255>; + status = "ok"; + }; + clocks { xo_board: xo_board { compatible = "fixed-clock"; From 9aeef947f4ae94f64573fb238df4ba4ad37e21b8 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 4 Jul 2024 12:54:27 +0530 Subject: [PATCH 15/55] ARM: dts: qcom: Add scm, syscon,shmbridge support in Kera Add a node for scm device and sysmon, shmbridge for Kera SoC. Change-Id: Ied886250dba41209cac68cbe52498061bd6daf51 Signed-off-by: Mukesh Ojha --- qcom/kera.dtsi | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 1c383ac8..0036927e 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -35,7 +35,9 @@ reserved_memory: reserved-memory {}; - firmware: firmware {}; + firmware: firmware { + qcom_scm: qcom_scm { }; + }; aliases {}; @@ -199,6 +201,17 @@ soc: soc { }; }; +&firmware { + qcom_scm { + compatible = "qcom,scm"; + qcom,dload-mode = <&tcsr 0x19000>; + }; + + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + }; +}; + &soc { #address-cells = <1>; #size-cells = <1>; @@ -389,6 +402,11 @@ cap-based-alloc-and-pwr-collapse; }; + tcsr: syscon@1fc0000 { + compatible = "syscon"; + reg = <0x1fc0000 0x30000>; + }; + eud: qcom,msm-eud@88e0000 { compatible = "qcom,msm-eud"; interrupt-names = "eud_irq"; From f153d3a9d9ffa0f854f9af18d3f8f2e45b57a81c Mon Sep 17 00:00:00 2001 From: Lei Chen Date: Mon, 24 Jul 2023 17:07:44 +0800 Subject: [PATCH 16/55] dt-bindings: bridge: lt9611uxc: Add bindings Add bindings for lt9611uxc. Display lt9611uxc bindings snapshot from msm-5.15 branch. commit 0a979012e870("dt-bindings: bridge: lt9611uxc: Add bindings"). Change-Id: I43999e93004393cc7b14cc9735c15388c90b33ba Signed-off-by: Lei Chen --- bindings/display/bridge/lt9611uxc.yaml | 97 ++++++++++++++++++++++++++ bindings/vendor-prefixes.yaml | 2 + 2 files changed, 99 insertions(+) create mode 100644 bindings/display/bridge/lt9611uxc.yaml diff --git a/bindings/display/bridge/lt9611uxc.yaml b/bindings/display/bridge/lt9611uxc.yaml new file mode 100644 index 00000000..f893e2d2 --- /dev/null +++ b/bindings/display/bridge/lt9611uxc.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/lt9611uxc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LT9611uxc DSI to HDMI bridge + +maintainers: + - Lei Chen + +description: | + LT9611UXC are bridge devices which convert DSI to HDMI + +properties: + compatible: + const: lt,lt9611uxc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + lt,irq-gpio: + description: Main IRQ gpio mapping + + lt,reset-gpio: + description: Main reset gpio mapping + + lt,hdmi-ps-gpio: + description: GPIO mapping for HDMI PS + + lt,hdmi-en-gpio: + description: GPIO mapping for HDMI EN + + vdd-supply: + description: Regulator for 1.8V MIPI phy power. + + vcc-supply: + description: Regulator for 3.3V IO power. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: MIPI port-1 for MIPI input + required: + - port@0 + +required: + - compatible + - reg + - interrupts + - vdd-supply + - vcc-supply + - ports + +allOf: + - $ref: ../dsi-controller.yaml# + +additionalProperties: false + +examples: + - | + &qupv3_se9_i2c { + lt9611@3b { + compatible = "lt,lt9611uxc"; + reg = <0x3b>; + interrupt-parent = <&tlmm>; + interrupts = <125 0>; + interrupt-names = "lt_irq"; + lt,irq-gpio = <&tlmm 125 0x0>; + lt,reset-gpio = <&tlmm 134 0x0>; + lt,hdmi-ps-gpio = <&tlmm 136 0x0>; + lt,hdmi-en-gpio = <&tlmm 137 0x0>; + + vcc-supply = <&pm660l_l6>; + vdd-supply = <&pm660_l11>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lt9611_in: endpoint { + remote-endpoint = <&ext_dsi_out>; + }; + }; + }; + }; + }; + +... diff --git a/bindings/vendor-prefixes.yaml b/bindings/vendor-prefixes.yaml index cbe12da6..1ffc736c 100644 --- a/bindings/vendor-prefixes.yaml +++ b/bindings/vendor-prefixes.yaml @@ -751,6 +751,8 @@ patternProperties: description: LSI Corp. (LSI Logic) "^lwn,.*": description: Liebherr-Werk Nenzing GmbH + "^lt,.*": + description: Lontium Semiconductor Corporation "^lxa,.*": description: Linux Automation GmbH "^m5stack,.*": From 9896d8515dc70194d12d690743277c91cb5756b9 Mon Sep 17 00:00:00 2001 From: Abhinav Parihar Date: Thu, 4 Jul 2024 15:57:06 +0530 Subject: [PATCH 17/55] ARM: dts: msm: Remove fastrpc nodes for monaco Currently fastrpc dt nodes are present in main dt file. With fastrpc driver migrating to upstream driver,rpc properties will be overlayed out of kernel. Change-Id: I91d915ae9ce7d55b5e81ff10d20eb7c370740172 Signed-off-by: Abhinav Parihar --- qcom/monaco.dtsi | 61 ------------------------------------------------ 1 file changed, 61 deletions(-) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index b1777b35..2e8a2947 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -986,12 +986,6 @@ qcom,non-wake-svc = <0x51 0x190>; }; - - qcom,msm_fastrpc_rpmsg { - compatible = "qcom,msm-fastrpc-rpmsg"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - qcom,intents = <0x64 64>; - }; }; }; @@ -1046,12 +1040,6 @@ 0x4400 2>; }; - qcom,msm_fastrpc_rpmsg { - compatible = "qcom,msm-fastrpc-rpmsg"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - qcom,intents = <0x64 64>; - }; - qcom,modem_ds { qcom,glink-channels = "DS"; qcom,intents = <0x4000 2>; @@ -1224,55 +1212,6 @@ restrict-access; }; - qcom,msm_fastrpc { - compatible = "qcom,msm-fastrpc-compute"; - qcom,rpc-latency-us = <611>; - qcom,adsp-remoteheap-vmid = <22 37>; - qcom,fastrpc-adsp-audio-pdr; - qcom,fastrpc-adsp-sensors-pdr; - - qcom,msm_fastrpc_compute_cb1 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "adsprpc-smd"; - iommus = <&apps_smmu 0x01C3 0x0>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; - qcom,iommu-faults = "stall-disable"; - }; - - qcom,msm_fastrpc_compute_cb2 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "adsprpc-smd"; - iommus = <&apps_smmu 0x01C4 0x0>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; - qcom,iommu-faults = "stall-disable"; - }; - - qcom,msm_fastrpc_compute_cb3 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "adsprpc-smd"; - iommus = <&apps_smmu 0x01C5 0x0>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; - qcom,iommu-faults = "stall-disable"; - }; - - qcom,msm_fastrpc_compute_cb4 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "adsprpc-smd"; - iommus = <&apps_smmu 0x01C6 0x0>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; - qcom,iommu-faults = "stall-disable"; - }; - - qcom,msm_fastrpc_compute_cb5 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "adsprpc-smd"; - iommus = <&apps_smmu 0x01C7 0x0>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; - qcom,iommu-faults = "stall-disable"; - }; - - }; - rpm-glink { compatible = "qcom,glink-rpm"; interrupts = ; From 49adf9d13c60796da88f028cc4ebb1acc1d54219 Mon Sep 17 00:00:00 2001 From: Prasad Arepalli Date: Thu, 4 Jul 2024 13:12:32 +0530 Subject: [PATCH 18/55] ARM: dts: msm: Remove ipa nodes for monaco target Disable ipa, gsi, rmnet and smp2p nodes for monaco target. All the nodes are added in data specific dt files. Change-Id: I8d0ead8276702aa3a03688b4b6b99630facac926 Signed-off-by: Prasad Arepalli --- qcom/monaco.dtsi | 109 ---------------------------------------------- qcom/monacop.dtsi | 5 --- 2 files changed, 114 deletions(-) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index b1777b35..dfc0eb67 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1864,115 +1864,6 @@ compatible = "qcom,secure-buffer"; }; - qcom,msm_gsi { - /* compatible = "qcom,msm_gsi"; */ - }; - - qcom,rmnet-ipa { - /* compatible = "qcom,rmnet-ipa3"; */ - qcom,rmnet-ipa-ssr; - qcom,ipa-platform-type-msm; - qcom,ipa-advertise-sg-support; - qcom,ipa-napi-enable; - }; - - ipa_hw: qcom,ipa@0x5800000 { - compatible = "qcom,ipa"; - reg = <0x5800000 0x34000>, - <0x5804000 0x28000>; - reg-names = "ipa-base", "gsi-base"; - interrupts = , - ; - interrupt-names = "ipa-irq", "gsi-irq"; - pas-ids = <0xf>; - firmware-names = "ipa_fws"; - memory-regions = <&pil_ipa_fw_mem>; - qcom,ipa-hw-ver = <16>; /* IPA core version = IPAv4.2 */ - qcom,ipa-hw-mode = <0>; - qcom,platform-type = <1>; /* MSM platform */ - qcom,ee = <0>; - qcom,use-ipa-tethering-bridge; - qcom,modem-cfg-emb-pipe-flt; - qcom,ipa-wdi2; - qcom,ipa-wdi2_over_gsi; - qcom,ipa-endp-delay-wa; - qcom,use-ipa-pm; - qcom,arm-smmu; - qcom,ipa-fltrt-not-hashable; - qcom,skip-ieob-mask-wa; - qcom,msm-bus,name = "ipa"; - qcom,max_num_smmu_cb = <3>; - clocks = <&rpmcc RPM_SMD_IPA_CLK>; - clock-names = "core_clk"; - qcom,interconnect,num-cases = <5>; - qcom,interconnect,num-paths = <4>; - interconnects = <&system_noc MASTER_IPA &system_noc SNOC_BIMC_SLV>, - <&bimc SNOC_BIMC_MAS &bimc SLAVE_EBI_CH0>, - <&system_noc MASTER_IPA &system_noc SLAVE_OCIMEM>, - <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_IPA_CFG>; - interconnect-names = "ipa_to_llcc", "llcc_to_ebi1", "ipa_to_imem", "appss_to_ipa"; - /* No vote */ - qcom,no-vote = - <0 0 0 0 0 0 0 0>; - - /* SVS2 */ - qcom,svs2 = - <80000 590000 80000 2160000 80000 560000 80000 120000>; - - /* SVS */ - qcom,svs = - <80000 800000 80000 5414000 80000 920000 80000 180000>; - - /* NOMINAL */ - qcom,nominal = - <206000 1500000 206000 7200000 206000 1560000 206000 380000>; - - /* TURBO */ - qcom,turbo = - <206000 1800000 206000 8500000 206000 1880000 206000 520000>; - qcom,bus-vector-names = - "MIN", "SVS2", "SVS", "NOMINAL", "TURBO"; - qcom,throughput-threshold = <310 600 1000>; - qcom,scaling-exceptions = <>; - - /* smp2p information */ - qcom,smp2p_map_ipa_1_out { - /* compatible = "qcom,smp2p-map-ipa-1-out"; */ - qcom,smem-states = <&smp2p_ipa_1_out 0>; - qcom,smem-state-names = "ipa-smp2p-out"; - }; - - qcom,smp2p_map_ipa_1_in { - /* compatible = "qcom,smp2p-map-ipa-1-in"; */ - interrupts-extended = <&smp2p_ipa_1_in 0 0>; - interrupt-names = "ipa-smp2p-in"; - }; - - ipa_smmu_ap: ipa_smmu_ap { - /* compatible = "qcom,ipa-smmu-ap-cb"; */ - iommus = <&apps_smmu 0x0140 0x0>; - qcom,iommu-dma-addr-pool = <0x10000000 0x30000000>; - /* modem tables in IMEM */ - qcom,additional-mapping = <0x0c123000 0x0c123000 0x2000>; - qcom,iommu-dma = "fastmap"; - qcom,iommu-geometry = <0 0xB0000000>; - }; - - ipa_smmu_wlan: ipa_smmu_wlan { - /* compatible = "qcom,ipa-smmu-wlan-cb"; */ - iommus = <&apps_smmu 0x141 0x0>; - /* ipa-uc ram */ - qcom,iommu-dma = "atomic"; - }; - - ipa_smmu_uc: ipa_smmu_uc { - /* compatible = "qcom,ipa-smmu-uc-cb"; */ - iommus = <&apps_smmu 0x0142 0x0>; - qcom,iommu-dma-addr-pool = <0x40400000 0x1fc00000>; - qcom,iommu-dma = "atomic"; - }; - }; - qcom,power-state { /* compatible = "qcom,power-state"; */ qcom,subsys-name = "lpass", "mpss"; diff --git a/qcom/monacop.dtsi b/qcom/monacop.dtsi index 4c07ceb8..e5049868 100644 --- a/qcom/monacop.dtsi +++ b/qcom/monacop.dtsi @@ -11,8 +11,3 @@ qcom,msm-id = <517 0x10000>; }; -&soc { - qcom,rmnet-ipa { - status = "disabled"; - }; -}; From ac1ca41e0693d0acaea7d665596545500948d3a8 Mon Sep 17 00:00:00 2001 From: Vijayanand Jitta Date: Wed, 24 Apr 2024 11:35:26 +0530 Subject: [PATCH 19/55] ARM: dts: msm: Add DMA-BUF heaps node for tuna Add the DMA-BUF heaps node for tuna. This adds default heaps like system and secure-system heap. Clients can add their own DMA-BUF heaps in here. Change-Id: I7b4d36250759e69248ec3fa371a4e5262885dc7f Signed-off-by: Vijayanand Jitta --- qcom/tuna-dma-heaps.dtsi | 13 +++++++++++++ qcom/tuna.dtsi | 1 + 2 files changed, 14 insertions(+) create mode 100644 qcom/tuna-dma-heaps.dtsi diff --git a/qcom/tuna-dma-heaps.dtsi b/qcom/tuna-dma-heaps.dtsi new file mode 100644 index 00000000..6472b080 --- /dev/null +++ b/qcom/tuna-dma-heaps.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + qcom,dma-heaps { + compatible = "qcom,dma-heaps"; + depends-on-supply = <&qcom_scm>; + }; +}; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 5e35de50..e4aaf5cf 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -212,6 +212,7 @@ #include "tuna-reserved-memory.dtsi" #include "msm-arm-smmu-tuna.dtsi" +#include "tuna-dma-heaps.dtsi" &reserved_memory { #address-cells = <2>; From f12b2d8069ea5d9843e7178d6d8f10c99faa5902 Mon Sep 17 00:00:00 2001 From: Saranya R Date: Tue, 2 Jul 2024 18:47:27 +0530 Subject: [PATCH 20/55] ARM: dts: msm: Use "iommu-addresses" property for ravelin dwc3 Use upstream compatible DT property "iommu-addresses" instead of "qcom,iommu-dma-addr-pool" for dwc3 which describes the addresses that dwc3 cannot use. Extend the address and size cells to ensure that IOMMU returns a 32 bit address, in order to define a region that will block 0xf0000000--0xffffffffffffffff. Change-Id: I211ba1b8bd1f7717f639d91dddb8adb86f17b42e Signed-off-by: Saranya R --- qcom/ravelin-usb.dtsi | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/qcom/ravelin-usb.dtsi b/qcom/ravelin-usb.dtsi index 3038be02..bd29bc5e 100644 --- a/qcom/ravelin-usb.dtsi +++ b/qcom/ravelin-usb.dtsi @@ -12,8 +12,8 @@ reg = <0xa600000 0x100000>; reg-names = "core_base"; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; ranges; USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; @@ -58,13 +58,13 @@ extcon = <&eud>; - dwc3@a600000 { + dwc3_0: dwc3@a600000 { compatible = "snps,dwc3"; - reg = <0xa600000 0xd800>; + reg = <0x0 0xa600000 0x0 0xd800>; iommus = <&apps_smmu 0x540 0x0>; qcom,iommu-dma = "atomic"; - qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + memory-region = <&dwc3_mem_region>; dma-coherent; interrupts = ; @@ -89,6 +89,11 @@ }; }; + dwc3_mem_region: dwc3_mem_region { + iommu-addresses = <&dwc3_0 0x0 0x0 0x0 0x90000000>, + <&dwc3_0 0x0 0xf0000000 0xffffffff 0x10000000>; + }; + /* USB port related High Speed PHY */ usb2_phy0: hsphy@88e3000 { compatible = "qcom,usb-hsphy-snps-femto"; From ce671354ea9aabcbbaa29268e612212f3372749b Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Sat, 6 Jul 2024 01:38:11 +0530 Subject: [PATCH 21/55] ARM: dts: qcom: update gpu mitigation for bcl for sun Update gpu mitigation for bcl for sun based on latest recommendation. Change-Id: Ieb25a08cc260252a6a71da954cb2b0e0879c35b1 Signed-off-by: Manaf Meethalavalappu Pallikunhi --- qcom/sun-thermal-overlay.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/qcom/sun-thermal-overlay.dtsi b/qcom/sun-thermal-overlay.dtsi index 06ca08fb..b5fa0f24 100644 --- a/qcom/sun-thermal-overlay.dtsi +++ b/qcom/sun-thermal-overlay.dtsi @@ -43,7 +43,7 @@ lbat_gpu0 { trip = <&b_bcl_lvl0>; - cooling-device = <&msm_gpu 2 2>; + cooling-device = <&msm_gpu 1 1>; }; }; }; @@ -57,7 +57,7 @@ lbat_gpu1 { trip = <&b_bcl_lvl1>; - cooling-device = <&msm_gpu 4 4>; + cooling-device = <&msm_gpu 2 2>; }; }; }; @@ -66,7 +66,7 @@ cooling-maps { lbat_gpu2 { trip = <&b_bcl_lvl2>; - cooling-device = <&msm_gpu 5 THERMAL_NO_LIMIT>; + cooling-device = <&msm_gpu 3 3>; }; }; }; @@ -80,7 +80,7 @@ vph_gpu0 { trip = <&bcl_lvl0>; - cooling-device = <&msm_gpu 2 2>; + cooling-device = <&msm_gpu 1 1>; }; }; }; @@ -94,7 +94,7 @@ vph_gpu1 { trip = <&bcl_lvl1>; - cooling-device = <&msm_gpu 4 4>; + cooling-device = <&msm_gpu 2 2>; }; }; }; @@ -103,7 +103,7 @@ cooling-maps { vph_gpu2 { trip = <&bcl_lvl2>; - cooling-device = <&msm_gpu 5 THERMAL_NO_LIMIT>; + cooling-device = <&msm_gpu 3 3>; }; }; }; From 0f1c1186013f0ab02385e93a9dc578aa45a3a246 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Fri, 17 Nov 2023 13:58:29 +0530 Subject: [PATCH 22/55] dt-bindings: interrupt-controller: Add SDX75 PDC compatible Add device tree bindings for PDC on SDX75 SOC. Change-Id: I261abde0a5905e8934727b4b251c068203b13612 Signed-off-by: Rohit Agarwal Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20231117082829.609882-1-quic_rohiagar@quicinc.com Signed-off-by: Rob Herring Git-commit: ca41ae8f445e0bb88fa84584b451bfbf39b2e7f1 Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git Signed-off-by: Khaja Hussain Shaik Khaji --- bindings/interrupt-controller/qcom,pdc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/interrupt-controller/qcom,pdc.yaml b/bindings/interrupt-controller/qcom,pdc.yaml index 7ca44441..06125c32 100644 --- a/bindings/interrupt-controller/qcom,pdc.yaml +++ b/bindings/interrupt-controller/qcom,pdc.yaml @@ -33,6 +33,7 @@ properties: - qcom,sm8150-pdc - qcom,sm8250-pdc - qcom,sm8350-pdc + - qcom,sdx75-pdc - qcom,sun-pdc - qcom,parrot-pdc - qcom,ravelin-pdc From 66293a021256db1e3e493997daae0a548d437891 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Fri, 9 Jun 2023 17:20:35 +0530 Subject: [PATCH 23/55] dt-bindings: firmware: scm: Add compatible for SDX75 Add devicetree compatible for SCM present in SDX75 platform. Change-Id: Ic1e101321cea49f2baf096bf57dcecc6b1c7ff17 Signed-off-by: Rohit Agarwal Acked-by: Conor Dooley Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1686311438-24177-3-git-send-email-quic_rohiagar@quicinc.com Git-commit: 677b9e85e8691c0bddc35eebf6d01836e109e5f4 Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git Signed-off-by: Khaja Hussain Shaik Khaji --- bindings/firmware/qcom,scm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/firmware/qcom,scm.yaml b/bindings/firmware/qcom,scm.yaml index 8e332ee1..9c09fe7f 100644 --- a/bindings/firmware/qcom,scm.yaml +++ b/bindings/firmware/qcom,scm.yaml @@ -45,6 +45,7 @@ properties: - qcom,scm-sdm845 - qcom,scm-sdx55 - qcom,scm-sdx65 + - qcom,scm-sdx75 - qcom,scm-sm6115 - qcom,scm-sm6125 - qcom,scm-sm6350 From 35d997d976d664caef2746673c00f87757b90be5 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Fri, 9 Jun 2023 17:20:37 +0530 Subject: [PATCH 24/55] dt-bindings: cpufreq: cpufreq-qcom-hw: Add SDX75 compatible Add compatible for EPSS CPUFREQ-HW on SDX75. Change-Id: I7ebb70c2b05fa2c0abf70aff03302b3fc41f9419 Signed-off-by: Rohit Agarwal Acked-by: Krzysztof Kozlowski Acked-by: Manivannan Sadhasivam Signed-off-by: Viresh Kumar Git-Commit: dce13a235a356363faf9385ba34681d9fc689f1a Git-Repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git Signed-off-by: Khaja Hussain Shaik Khaji --- bindings/cpufreq/cpufreq-qcom-hw.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/cpufreq/cpufreq-qcom-hw.yaml b/bindings/cpufreq/cpufreq-qcom-hw.yaml index 74a0c4c4..0eb59b91 100644 --- a/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -25,6 +25,7 @@ properties: - description: v2 of CPUFREQ HW (EPSS) items: - enum: + - qcom,sdx75-cpufreq-epss - qcom,sm6375-cpufreq-epss - qcom,sm8250-cpufreq-epss - qcom,cpufreq-epss-pdmem From a3ac740d0d885000fce7fd5304ce255a48a94523 Mon Sep 17 00:00:00 2001 From: Cong Zhang Date: Thu, 4 Jul 2024 11:02:00 +0800 Subject: [PATCH 25/55] ARM: dts: qcom: Enable keep-running for OEMVM Add keep-running property for OEMVM to let OEMVM shutdown gracefully even if qcrosvm got killed. Change-Id: I6b78f13f095ab8a3b068d94219b28cebbae2a75a Signed-off-by: Cong Zhang --- qcom/sun.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 2cd07115..615ae911 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -2297,6 +2297,7 @@ qcom,pas-id = <34>; qcom,vmid = <49>; qcom,firmware-name = "oemvm"; + qcom,keep-running; memory-region = <&oem_vm_mem &vm_comm_mem>; virtio-backends = <&oem_vm_virt_be0 &oem_vm_virt_be1>; }; From 3d7db740335e9d41adc369257fb8a5ccf0e272f1 Mon Sep 17 00:00:00 2001 From: Minghao Zhang Date: Tue, 9 Jul 2024 14:23:57 +0800 Subject: [PATCH 26/55] ARM: dts: qcom: Add fan thermal mitigation rules for SunP HDK Add cpu0-0-0 zone's trip to make fan run at level 50. Change-Id: Id3f38d165e513ec633f3a289cfddfc60284f8f7c Signed-off-by: Minghao Zhang --- qcom/sunp-hdk.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/qcom/sunp-hdk.dtsi b/qcom/sunp-hdk.dtsi index d7fa4e61..1e1bb10a 100644 --- a/qcom/sunp-hdk.dtsi +++ b/qcom/sunp-hdk.dtsi @@ -99,3 +99,22 @@ /* Tx pre-emphasis tuning */ 0x5 0x57>; }; + +&thermal_zones { + cpu-0-0-0 { + trips { + fan_cpu000_config0: fan-cpu000-config0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + + cooling-maps { + fan_cdev_0 { + trip = <&fan_cpu000_config0>; + cooling-device = <&fancontroller 50 50>; + }; + }; + }; +}; From 60bbc15bb52b57a5187f7c04d5cdce03259d7c40 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Fri, 9 Jun 2023 17:20:34 +0530 Subject: [PATCH 27/55] dt-bindings: arm: qcom: Document SDX75 platform and boards Document the SDX75 platform binding and also the boards using it. Change-Id: I821ae00b6c461ded39383bd8a3c131bb73c5914b Signed-off-by: Rohit Agarwal Acked-by: Conor Dooley Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1686311438-24177-2-git-send-email-quic_rohiagar@quicinc.com Git-commit: f9a97656ace80c617df2d6003c815877c026a9e3 Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git Signed-off-by: Khaja Hussain Shaik Khaji --- bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/bindings/arm/qcom.yaml b/bindings/arm/qcom.yaml index 27063a04..a2017b29 100644 --- a/bindings/arm/qcom.yaml +++ b/bindings/arm/qcom.yaml @@ -60,6 +60,7 @@ description: | sdm845 sdx55 sdx65 + sdx75 sm4250 sm6115 sm6125 @@ -738,6 +739,11 @@ properties: - qcom,sdx65-mtp - const: qcom,sdx65 + - items: + - enum: + - qcom,sdx75-idp + - const: qcom,sdx75 + - items: - enum: - qcom,ipq6018-cp01 From 10aadf09411bcfcec2b30333585c81c34dc69055 Mon Sep 17 00:00:00 2001 From: Khaja Hussain Shaik Khaji Date: Tue, 9 Jul 2024 12:17:55 +0530 Subject: [PATCH 28/55] dt-bindings: arm: qcom: Document sdxkova platform and boards Document the sdxkova platform binding and also the boards using it. Change-Id: Ifc488cf86c0113ce4df6140770b328851a786235 Signed-off-by: Khaja Hussain Shaik Khaji --- bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/bindings/arm/qcom.yaml b/bindings/arm/qcom.yaml index a2017b29..9ed6e827 100644 --- a/bindings/arm/qcom.yaml +++ b/bindings/arm/qcom.yaml @@ -61,6 +61,7 @@ description: | sdx55 sdx65 sdx75 + sdxkova sm4250 sm6115 sm6125 @@ -744,6 +745,11 @@ properties: - qcom,sdx75-idp - const: qcom,sdx75 + - items: + - enum: + - qcom,sdxkova-idp + - const: qcom,sdxkova + - items: - enum: - qcom,ipq6018-cp01 From 28e83f589e409a1dae35808855799dc3a83ed230 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Thu, 18 May 2023 21:27:10 +0530 Subject: [PATCH 29/55] dt-bindings: pinctrl: qcom: Add SDX75 pinctrl devicetree compatible Add device tree binding Documentation details for Qualcomm SDX75 pinctrl driver. Change-Id: I0d8e959a3dd7e4eb71bf47c693130af5f87117fb Signed-off-by: Rohit Agarwal Reviewed-by: Krzysztof Kozlowski Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/1684425432-10072-2-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Linus Walleij Git-Commit: 1dc3f8812cc5fe82c097811ea8251d7f8af5d54d Git-Repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git Signed-off-by: Khaja Hussain Shaik Khaji --- bindings/pinctrl/qcom,sdx75-tlmm.yaml | 137 ++++++++++++++++++++++++++ 1 file changed, 137 insertions(+) create mode 100644 bindings/pinctrl/qcom,sdx75-tlmm.yaml diff --git a/bindings/pinctrl/qcom,sdx75-tlmm.yaml b/bindings/pinctrl/qcom,sdx75-tlmm.yaml new file mode 100644 index 00000000..7cb96aa7 --- /dev/null +++ b/bindings/pinctrl/qcom,sdx75-tlmm.yaml @@ -0,0 +1,137 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sdx75-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SDX75 TLMM block + +maintainers: + - Rohit Agarwal + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SDX75 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sdx75-tlmm + + reg: + maxItems: 1 + + interrupts: true + interrupt-controller: true + "#interrupt-cells": true + gpio-controller: true + + gpio-reserved-ranges: + minItems: 1 + maxItems: 67 + + gpio-line-names: + maxItems: 133 + + "#gpio-cells": true + gpio-ranges: true + wakeup-parent: true + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sdx75-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sdx75-tlmm-state" + additionalProperties: false + +$defs: + qcom-sdx75-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ adsp_ext, atest_char, audio_ref_clk, bimc_dte, char_exec, coex_uart2, + coex_uart, cri_trng, cri_trng0, cri_trng1, dbg_out_clk, ddr_bist, + ddr_pxi0, ebi0_wrcdc, ebi2_a, ebi2_lcd, ebi2_lcd_te, emac0_mcg, + emac0_ptp, emac1_mcg, emac1_ptp, emac_cdc, emac_pps_in, eth0_mdc, + eth0_mdio, eth1_mdc, eth1_mdio, ext_dbg, gcc_125_clk, gcc_gp1_clk, + gcc_gp2_clk, gcc_gp3_clk, gcc_plltest, gpio, i2s_mclk, jitter_bist, + ldo_en, ldo_update, m_voc, mgpi_clk, native_char, native_tsens, + native_tsense, nav_dr_sync, nav_gpio, pa_indicator, pci_e, + pcie0_clkreq_n, pcie1_clkreq_n, pcie2_clkreq_n, pll_bist_sync, + pll_clk_aux, pll_ref_clk, pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, + qlink0_b_en, qlink0_b_req, qlink0_l_en, qlink0_l_req, qlink0_wmss, + qlink1_l_en, qlink1_l_req, qlink1_wmss, qup_se0, qup_se1_l2_mira, + qup_se1_l2_mirb, qup_se1_l3_mira, qup_se1_l3_mirb, qup_se2, qup_se3, + qup_se4, qup_se5, qup_se6, qup_se7, qup_se8, rgmii_rx_ctl, rgmii_rxc, + rgmii_rxd, rgmii_tx_ctl, rgmii_txc, rgmii_txd, sd_card, sdc1_tb, + sdc2_tb_trig, sec_mi2s, sgmii_phy_intr0_n, sgmii_phy_intr1_n, + spmi_coex, spmi_vgi, tgu_ch0_trigout, tmess_prng0, tmess_prng1, + tmess_prng2, tmess_prng3, tri_mi2s, uim1_clk, uim1_data, uim1_present, + uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset, + usb2phy_ac_en, vsense_trigger_mirnat] + + required: + - pins + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + tlmm: pinctrl@f100000 { + compatible = "qcom,sdx75-tlmm"; + reg = <0x0f100000 0x300000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 133>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + + gpio-wo-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-state { + rx-pins { + pins = "gpio12"; + function = "qup_se1_l2_mira"; + bias-disable; + }; + + tx-pins { + pins = "gpio13"; + function = "qup_se1_l3_mira"; + bias-disable; + }; + }; + }; +... From e99a0b90c7117b25ba19cf58ea5be2702ba0a954 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Fri, 12 May 2023 17:53:45 +0530 Subject: [PATCH 30/55] dt-bindings: clock: qcom: Add RPMHCC for SDX75 Add compatible string for qcom RPMHCC for SDX75 platform. Change-Id: Id69e2e9dc2961f70624a63053002f8e16dcfce9e Signed-off-by: Imran Shaik Signed-off-by: Taniya Das Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230512122347.1219-4-quic_tdas@quicinc.com Git-Commit: 379d72721bc4308fbc038e9858b7d2e9191725b5 Git-Repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git Signed-off-by: Khaja Hussain Shaik Khaji --- bindings/clock/qcom,rpmhcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/clock/qcom,rpmhcc.yaml b/bindings/clock/qcom,rpmhcc.yaml index 5088a111..20c801a4 100644 --- a/bindings/clock/qcom,rpmhcc.yaml +++ b/bindings/clock/qcom,rpmhcc.yaml @@ -25,6 +25,7 @@ properties: - qcom,sdm845-rpmh-clk - qcom,sdx55-rpmh-clk - qcom,sdx65-rpmh-clk + - qcom,sdx75-rpmh-clk - qcom,sm4450-rpmh-clk - qcom,sm6350-rpmh-clk - qcom,sm8150-rpmh-clk From 635da2f7e4f0445c0f1f279a2a053c5a4e2fc2ed Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Mon, 31 Jul 2023 17:00:06 +0530 Subject: [PATCH 31/55] dt-bindings: power: qcom,rpmpd: Add compatible for sdx75 Add a compatible string for power domains in sdx75. Change-Id: I0c9cfc823f74e537e50737b225ebb44805e36788 Signed-off-by: Rohit Agarwal Acked-by: Conor Dooley Link: https://lore.kernel.org/r/1690803007-8640-2-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Bjorn Andersson Git-Commit: 0b9d94e1f19acd19613386096d924af2333b620a Git-Repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git Signed-off-by: Khaja Hussain Shaik Khaji --- bindings/power/qcom,rpmpd.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/power/qcom,rpmpd.yaml b/bindings/power/qcom,rpmpd.yaml index 633d4988..8f09e8cf 100644 --- a/bindings/power/qcom,rpmpd.yaml +++ b/bindings/power/qcom,rpmpd.yaml @@ -39,6 +39,7 @@ properties: - qcom,sdm845-rpmhpd - qcom,sdx55-rpmhpd - qcom,sdx65-rpmhpd + - qcom,sdx75-rpmhpd - qcom,sm4250-rpmpd - qcom,sm6115-rpmpd - qcom,sm6125-rpmpd From 7497d82540180f9c24b55382764a7c82547d491a Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Fri, 9 Jun 2023 17:20:38 +0530 Subject: [PATCH 32/55] arm64: dts: qcom: Add SDX75 platform and IDP board support Add basic devicetree support for SDX75 platform and IDP board from Qualcomm. The SDX75 platform features an ARM Cortex A55 CPU which forms the Application Processor Sub System (APSS) along with standard Qualcomm peripherals like GCC, TLMM, UART, QPIC, and BAM etc... Also, there exists the networking parts such as IPA, MHI, PCIE-EP, EMAC, and Modem etc.. [Since we are not using sdx75-idp, do not include its DTS.] Change-Id: I1562002758e7b077662c69d5d9bbef247aef157d Signed-off-by: Rohit Agarwal Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1686311438-24177-6-git-send-email-quic_rohiagar@quicinc.com Git-Commit: 9181bb939984f1ad4f958c2be3ea10fd67344165 Git-Repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git Signed-off-by: Khaja Hussain Shaik Khaji --- qcom/sdx75.dtsi | 670 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 670 insertions(+) create mode 100644 qcom/sdx75.dtsi diff --git a/qcom/sdx75.dtsi b/qcom/sdx75.dtsi new file mode 100644 index 00000000..21d5d55d --- /dev/null +++ b/qcom/sdx75.dtsi @@ -0,0 +1,670 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * SDX75 SoC device tree source + * + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + */ + +#include +#include +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&intc>; + + chosen: chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <76800000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_0>; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-unified; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_100>; + + L2_100: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_200>; + + L2_200: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x300>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_300>; + + L2_300: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + CPU_OFF: cpu-sleep-0 { + compatible = "arm,idle-state"; + entry-latency-us = <235>; + exit-latency-us = <428>; + min-residency-us = <1774>; + arm,psci-suspend-param = <0x40000003>; + local-timer-stop; + }; + + CPU_RAIL_OFF: cpu-rail-sleep-1 { + compatible = "arm,idle-state"; + entry-latency-us = <800>; + exit-latency-us = <750>; + min-residency-us = <4090>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <1050>; + exit-latency-us = <2500>; + min-residency-us = <5309>; + }; + + CLUSTER_SLEEP_1: cluster-sleep-1 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41001344>; + entry-latency-us = <2761>; + exit-latency-us = <3964>; + min-residency-us = <8467>; + }; + + CLUSTER_SLEEP_2: cluster-sleep-2 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x4100b344>; + entry-latency-us = <2793>; + exit-latency-us = <4023>; + min-residency-us = <9826>; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-sdx75", "qcom,scm"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>; + }; + + CLUSTER_PD: power-domain-cpu-cluster0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1 &CLUSTER_SLEEP_2>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gunyah_hyp_mem: gunyah-hyp@80000000 { + reg = <0x0 0x80000000 0x0 0x800000>; + no-map; + }; + + hyp_elf_package_mem: hyp-elf-package@80800000 { + reg = <0x0 0x80800000 0x0 0x200000>; + no-map; + }; + + access_control_db_mem: access-control-db@81380000 { + reg = <0x0 0x81380000 0x0 0x80000>; + no-map; + }; + + qteetz_mem: qteetz@814e0000 { + reg = <0x0 0x814e0000 0x0 0x2a0000>; + no-map; + }; + + trusted_apps_mem: trusted-apps@81780000 { + reg = <0x0 0x81780000 0x0 0xa00000>; + no-map; + }; + + xbl_ramdump_mem: xbl-ramdump@87a00000 { + reg = <0x0 0x87a00000 0x0 0x1c0000>; + no-map; + }; + + cpucp_fw_mem: cpucp-fw@87c00000 { + reg = <0x0 0x87c00000 0x0 0x100000>; + no-map; + }; + + xbl_dtlog_mem: xbl-dtlog@87d00000 { + reg = <0x0 0x87d00000 0x0 0x40000>; + no-map; + }; + + xbl_sc_mem: xbl-sc@87d40000 { + reg = <0x0 0x87d40000 0x0 0x40000>; + no-map; + }; + + modem_efs_shared_mem: modem-efs-shared@87d80000 { + reg = <0x0 0x87d80000 0x0 0x10000>; + no-map; + }; + + aop_image_mem: aop-image@87e00000 { + reg = <0x0 0x87e00000 0x0 0x20000>; + no-map; + }; + + smem_mem: smem@87e20000 { + reg = <0x0 0x87e20000 0x0 0xc0000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db@87ee0000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x87ee0000 0x0 0x20000>; + no-map; + }; + + aop_config_mem: aop-config@87f00000 { + reg = <0x0 0x87f00000 0x0 0x20000>; + no-map; + }; + + ipa_fw_mem: ipa-fw@87f20000 { + reg = <0x0 0x87f20000 0x0 0x10000>; + no-map; + }; + + secdata_mem: secdata@87f30000 { + reg = <0x0 0x87f30000 0x0 0x1000>; + no-map; + }; + + tme_crashdump_mem: tme-crashdump@87f31000 { + reg = <0x0 0x87f31000 0x0 0x40000>; + no-map; + }; + + tme_log_mem: tme-log@87f71000 { + reg = <0x0 0x87f71000 0x0 0x4000>; + no-map; + }; + + uefi_log_mem: uefi-log@87f75000 { + reg = <0x0 0x87f75000 0x0 0x10000>; + no-map; + }; + + qdss_mem: qdss@88800000 { + reg = <0x0 0x88800000 0x0 0x300000>; + no-map; + }; + + audio_heap_mem: audio-heap@88b00000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x88b00000 0x0 0x400000>; + no-map; + }; + + mpss_dsmharq_mem: mpss-dsmharq@88f00000 { + reg = <0x0 0x88f00000 0x0 0x5080000>; + no-map; + }; + + q6_mpss_dtb_mem: q6-mpss-dtb@8df80000 { + reg = <0x0 0x8df80000 0x0 0x80000>; + no-map; + }; + + mpssadsp_mem: mpssadsp@8e000000 { + reg = <0x0 0x8e000000 0x0 0xf400000>; + no-map; + }; + + gunyah_trace_buffer_mem: gunyah-trace-buffer@bdb00000 { + reg = <0x0 0xbdb00000 0x0 0x2000000>; + no-map; + }; + + smmu_debug_buf_mem: smmu-debug-buf@bfb00000 { + reg = <0x0 0xbfb00000 0x0 0x100000>; + no-map; + }; + + hyp_smmu_s2_pt_mem: hyp-smmu-s2-pt@bfc00000 { + reg = <0x0 0xbfc00000 0x0 0x400000>; + no-map; + }; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + + gcc: clock-controller@80000 { + compatible = "qcom,sdx75-gcc"; + reg = <0x0 0x0080000 0x0 0x1f7400>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + qupv3_id_0: geniqup@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x009c0000 0x0 0x2000>; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + iommus = <&apps_smmu 0xe3 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + uart1: serial@984000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x00984000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interrupts = ; + pinctrl-0 = <&qupv3_se1_2uart_active>; + pinctrl-1 = <&qupv3_se1_2uart_sleep>; + pinctrl-names = "default", + "sleep"; + status = "disabled"; + }; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x40000>; + #hwlock-cells = <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sdx75-pdc", "qcom,pdc"; + reg = <0x0 0xb220000 0x0 0x30000>, + <0x0 0x174000f0 0x0 0x64>; + qcom,pdc-ranges = <0 147 52>, + <52 266 32>, + <84 500 59>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + tlmm: pinctrl@f000000 { + compatible = "qcom,sdx75-tlmm"; + reg = <0x0 0x0f000000 0x0 0x400000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 133>; + interrupt-controller; + #interrupt-cells = <2>; + wakeup-parent = <&pdc>; + + qupv3_se1_2uart_active: qupv3-se1-2uart-active-state { + tx-pins { + pins = "gpio12"; + function = "qup_se1_l2_mira"; + drive-strength= <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio13"; + function = "qup_se1_l3_mira"; + drive-strength= <2>; + bias-disable; + }; + }; + + qupv3_se1_2uart_sleep: qupv3-se1-2uart-sleep-state { + pins = "gpio12", "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,sdx75-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x15000000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + dma-coherent; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + intc: interrupt-controller@17200000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0x0 0x17200000 0x0 0x10000>, + <0x0 0x17260000 0x0 0x80000>; + interrupts = ; + }; + + timer@17420000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17420000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x20000000>; + + frame@17421000 { + reg = <0x17421000 0x1000>, + <0x17422000 0x1000>; + frame-number = <0>; + interrupts = , + ; + }; + + frame@17423000 { + reg = <0x17423000 0x1000>; + frame-number = <1>; + interrupts = ; + status = "disabled"; + }; + + frame@17425000 { + reg = <0x17425000 0x1000>; + frame-number = <2>; + interrupts = ; + status = "disabled"; + }; + + frame@17427000 { + reg = <0x17427000 0x1000>; + frame-number = <3>; + interrupts = ; + status = "disabled"; + }; + + frame@17429000 { + reg = <0x17429000 0x1000>; + frame-number = <4>; + interrupts = ; + status = "disabled"; + }; + + frame@1742b000 { + reg = <0x1742b000 0x1000>; + frame-number = <5>; + interrupts = ; + status = "disabled"; + }; + + frame@1742d000 { + reg = <0x1742d000 0x1000>; + frame-number = <6>; + interrupts = ; + status = "disabled"; + }; + }; + + apps_rsc: rsc@17a00000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x17a00000 0x0 0x10000>, + <0x0 0x17a10000 0x0 0x10000>, + <0x0 0x17a20000 0x0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + + power-domains = <&CLUSTER_PD>; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,sdx75-rpmh-clk"; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; + }; + }; + + cpufreq_hw: cpufreq@17d91000 { + compatible = "qcom,sdx75-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0x0 0x17d91000 0x0 0x1000>; + reg-names = "freq-domain0"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GPLL0>; + clock-names = "xo", + "alternate"; + interrupts = ; + interrupt-names = "dcvsh-irq-0"; + #freq-domain-cells = <1>; + #clock-cells = <1>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; From 2fcde9c1b5ae1c648eafe7783ef52fa326b2dacc Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Fri, 19 May 2023 14:39:06 +0530 Subject: [PATCH 33/55] dt-bindings: arm-smmu: Add SDX75 SMMU compatible Add devicetree binding for Qualcomm SDX75 SMMU. Change-Id: I393b6ac159f71fdd24cfaa665ccda0271b7531b5 Signed-off-by: Rohit Agarwal Acked-by: Conor Dooley Link: https://lore.kernel.org/r/1684487350-30476-5-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Will Deacon Git-Commit: 48989c0b25ca6ed75f3ea81053936ff0b64d02e7 Git-Repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git Signed-off-by: Khaja Hussain Shaik Khaji --- bindings/iommu/arm,smmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/iommu/arm,smmu.yaml b/bindings/iommu/arm,smmu.yaml index 66114fe5..e458082e 100644 --- a/bindings/iommu/arm,smmu.yaml +++ b/bindings/iommu/arm,smmu.yaml @@ -41,6 +41,7 @@ properties: - qcom,sdm845-smmu-500 - qcom,sdx55-smmu-500 - qcom,sdx65-smmu-500 + - qcom,sdx75-smmu-500 - qcom,sm6350-smmu-500 - qcom,sm6375-smmu-500 - qcom,sm8150-smmu-500 From 183bc362334507512fd76db5f96e452de65092a2 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 14 Nov 2022 20:06:29 +0300 Subject: [PATCH 34/55] dt-bindings: arm-smmu: Add generic qcom,smmu-500 bindings Add generic bindings for the Qualcomm variant of the ARM MMU-500. It is expected that all future platforms will use the generic qcom,smmu-500 compat string in addition to SoC-specific and the generic arm,mmu-500 ones. Older bindings are now described as deprecated. Note: I have split the sdx55 and sdx65 from the legacy bindings. They are not supported by the qcom SMMU implementation. I can suppose that they are using the generic implementation rather than the Qualcomm-speicific one. [Add dt-bindings for qcom,smmu-500 for Qcom SoCs]. Change-Id: Id2520441f556590403ac712f68aa7487ca4f205e Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20221114170635.1406534-5-dmitry.baryshkov@linaro.org Signed-off-by: Will Deacon Git-Commit: 6c84bbd103d85696af9cc0f746c01f9b2847637e Git-Repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git Signed-off-by: Khaja Hussain Shaik Khaji --- bindings/iommu/arm,smmu.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/bindings/iommu/arm,smmu.yaml b/bindings/iommu/arm,smmu.yaml index e458082e..402dc37c 100644 --- a/bindings/iommu/arm,smmu.yaml +++ b/bindings/iommu/arm,smmu.yaml @@ -30,7 +30,7 @@ properties: - qcom,msm8998-smmu-v2 - const: qcom,smmu-v2 - - description: Qcom SoCs implementing "arm,mmu-500" + - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500" items: - enum: - qcom,qcm2290-smmu-500 @@ -48,6 +48,7 @@ properties: - qcom,sm8250-smmu-500 - qcom,sm8350-smmu-500 - qcom,sm8450-smmu-500 + - const: qcom,smmu-500 - const: arm,mmu-500 - description: | Qcom SoCs implementing "qcom,qsmmu-v500", which is a arm,mmu-500 From 7754de5de43e03bc21ebf564204a9eca2791943c Mon Sep 17 00:00:00 2001 From: Akhil Manikoth Kallankandy Date: Wed, 10 Jul 2024 09:47:00 +0530 Subject: [PATCH 35/55] ARM: dts: msm: Remove qcom,msm_fastrpc from ravelin.dtsi Remove the qcom,msm_fastrpc nodes as these are moved to dsp-devicetree. Change-Id: I2ae6d3d27b27895859c4f1e241012d288f5f7a72 Signed-off-by: Akhil Manikoth Kallankandy --- qcom/ravelin.dtsi | 38 -------------------------------------- 1 file changed, 38 deletions(-) diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi index 56692c6b..755be717 100644 --- a/qcom/ravelin.dtsi +++ b/qcom/ravelin.dtsi @@ -1959,44 +1959,6 @@ qcom,pipe-attr-ee; }; - msm_fastrpc: qcom,msm_fastrpc { - compatible = "qcom,msm-fastrpc-compute"; - qcom,adsp-remoteheap-vmid = <22 37>; - qcom,fastrpc-adsp-audio-pdr; - qcom,fastrpc-adsp-sensors-pdr; - qcom,rpc-latency-us = <235>; - qcom,fastrpc-gids = <2908>; - qcom,qos-cores = <0 1 2 3 4 5>; - - qcom,msm_fastrpc_compute_cb1 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "adsprpc-smd"; - iommus = <&apps_smmu 0x1003 0x0>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - }; - - qcom,msm_fastrpc_compute_cb2 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "adsprpc-smd"; - iommus = <&apps_smmu 0x1004 0x0>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - }; - - qcom,msm_fastrpc_compute_cb3 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "adsprpc-smd"; - iommus = <&apps_smmu 0x1005 0x0>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - shared-cb = <4>; - }; - }; - clk_virt: interconnect@0 { compatible = "qcom,ravelin-clk_virt"; #interconnect-cells = <1>; From aef94e1a18b8095042a05b8407514e93f8a831fe Mon Sep 17 00:00:00 2001 From: Akhil Manikoth Kallankandy Date: Wed, 10 Jul 2024 09:49:51 +0530 Subject: [PATCH 36/55] ARM: dts: msm: Update ravelin glink node Fix for pmic glink node for ravelin without this change glink channel registration fails for the ADSP communication. Change-Id: I02d1ea7b11db6e5e5dfd0f85e384797b1b6b96b9 Signed-off-by: Akhil Manikoth Kallankandy --- qcom/ravelin.dtsi | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi index 56692c6b..22996339 100644 --- a/qcom/ravelin.dtsi +++ b/qcom/ravelin.dtsi @@ -2187,6 +2187,7 @@ qcom,adsp_qrtr { qcom,glink-channels = "IPCRTR"; + qcom,net-id = <2>; qcom,intents = <0x800 5 0x2000 3 0x4400 2>; @@ -2194,10 +2195,15 @@ qcom,no-wake-svc = <0x190>; }; - qcom,msm_fastrpc_rpmsg { - compatible = "qcom,msm-fastrpc-rpmsg"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - qcom,intents = <0x64 64>; + qcom,pmic_glink_rpmsg { + qcom,glink-channels = "PMIC_RTR_ADSP_APPS"; + }; + + qcom,pmic_glink_log_rpmsg { + qcom,glink-channels = "PMIC_LOGS_ADSP_APPS"; + qcom,intents = <0x800 5 + 0xc00 3 + 0x2000 1>; }; }; From dd7144ddab381bb0c37a6208c9f4ebe431974653 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Fri, 12 May 2023 17:53:44 +0530 Subject: [PATCH 37/55] dt-bindings: clock: qcom: Add GCC clocks for SDX75 Add support for qcom global clock controller bindings for SDX75 platform. Change-Id: I99f1a44dfe7f444c027d4b7098484ec57f8ef0d8 Signed-off-by: Imran Shaik Signed-off-by: Taniya Das Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230512122347.1219-3-quic_tdas@quicinc.com Git-Commit: 1c305ea86bc32b3f38413ef3dbb1f3c288da024e Git-Repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git Signed-off-by: Khaja Hussain Shaik Khaji --- bindings/clock/qcom,sdx75-gcc.yaml | 65 ++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 bindings/clock/qcom,sdx75-gcc.yaml diff --git a/bindings/clock/qcom,sdx75-gcc.yaml b/bindings/clock/qcom,sdx75-gcc.yaml new file mode 100644 index 00000000..98921fa2 --- /dev/null +++ b/bindings/clock/qcom,sdx75-gcc.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sdx75-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on SDX75 + +maintainers: + - Imran Shaik + - Taniya Das + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on SDX75 + + See also:: include/dt-bindings/clock/qcom,sdx75-gcc.h + +properties: + compatible: + const: qcom,sdx75-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: EMAC0 sgmiiphy mac rclk source + - description: EMAC0 sgmiiphy mac tclk source + - description: EMAC0 sgmiiphy rclk source + - description: EMAC0 sgmiiphy tclk source + - description: EMAC1 sgmiiphy mac rclk source + - description: EMAC1 sgmiiphy mac tclk source + - description: EMAC1 sgmiiphy rclk source + - description: EMAC1 sgmiiphy tclk source + - description: PCIE20 phy aux clock source + - description: PCIE_1 Pipe clock source + - description: PCIE_2 Pipe clock source + - description: PCIE Pipe clock source + - description: USB3 phy wrapper pipe clock source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + clock-controller@80000 { + compatible = "qcom,sdx75-gcc"; + reg = <0x80000 0x1f7400>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&emac0_sgmiiphy_mac_rclk>, + <&emac0_sgmiiphy_mac_tclk>, <&emac0_sgmiiphy_rclk>, <&emac0_sgmiiphy_tclk>, + <&emac1_sgmiiphy_mac_rclk>, <&emac1_sgmiiphy_mac_tclk>, <&emac1_sgmiiphy_rclk>, + <&emac1_sgmiiphy_tclk>, <&pcie20_phy_aux_clk>, <&pcie_1_pipe_clk>, + <&pcie_2_pipe_clk>, <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... From b0989c0eb7aa8e428afe3b13f136e2461742e7b1 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Wed, 13 Sep 2023 19:40:55 +0530 Subject: [PATCH 38/55] dt-bindings: interconnect: Add compatibles for SDX75 Add dt-bindings compatibles and interconnect IDs for Qualcomm SDX75 platform. Change-Id: I77372b70e4379593499f9d24e4a580edd3c8c051 Signed-off-by: Rohit Agarwal Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/1694614256-24109-2-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Georgi Djakov Git-Commit: 956329ec7c5eba430211b48cca1b0372b4a4d702 Git-Repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git Signed-off-by: Khaja Hussain Shaik Khaji --- bindings/interconnect/qcom,sdx75-rpmh.yaml | 92 ++++++++++++++++++++++ 1 file changed, 92 insertions(+) create mode 100644 bindings/interconnect/qcom,sdx75-rpmh.yaml diff --git a/bindings/interconnect/qcom,sdx75-rpmh.yaml b/bindings/interconnect/qcom,sdx75-rpmh.yaml new file mode 100644 index 00000000..71cf7e25 --- /dev/null +++ b/bindings/interconnect/qcom,sdx75-rpmh.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,sdx75-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on SDX75 + +maintainers: + - Rohit Agarwal + +description: + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is + able to communicate with the BCM through the Resource State Coordinator (RSC) + associated with each execution environment. Provider nodes must point to at + least one RPMh device child node pertaining to their RSC and each provider + can map to multiple RPMh resources. + +properties: + compatible: + enum: + - qcom,sdx75-clk-virt + - qcom,sdx75-dc-noc + - qcom,sdx75-gem-noc + - qcom,sdx75-mc-virt + - qcom,sdx75-pcie-anoc + - qcom,sdx75-system-noc + + '#interconnect-cells': true + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,sdx75-clk-virt + - qcom,sdx75-mc-virt + then: + properties: + reg: false + else: + required: + - reg + + - if: + properties: + compatible: + contains: + enum: + - qcom,sdx75-clk-virt + then: + properties: + clocks: + items: + - description: RPMH CC QPIC Clock + required: + - clocks + else: + properties: + clocks: false + +unevaluatedProperties: false + +examples: + - | + #include + + clk_virt: interconnect-0 { + compatible = "qcom,sdx75-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&rpmhcc RPMH_QPIC_CLK>; + }; + + system_noc: interconnect@1640000 { + compatible = "qcom,sdx75-system-noc"; + reg = <0x1640000 0x4b400>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; From 21e4e3bb9af3c46ec4966fe5d73d96cc8757a0dc Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Thu, 16 May 2024 14:30:30 -0700 Subject: [PATCH 39/55] dt-bindings: qcom: Add gh-large-dmabuf-test binding Add gh-large-dmabuf-test binding description and requirements which include compatible, label and optional properties. Change-Id: Ief22a3b609539ea307f289fb62e7c90b3a1284f6 Signed-off-by: Georgi Djakov --- .../soc/qcom/qcom,gh-large-dmabuf-test.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 bindings/soc/qcom/qcom,gh-large-dmabuf-test.yaml diff --git a/bindings/soc/qcom/qcom,gh-large-dmabuf-test.yaml b/bindings/soc/qcom/qcom,gh-large-dmabuf-test.yaml new file mode 100644 index 00000000..c3f7bdf5 --- /dev/null +++ b/bindings/soc/qcom/qcom,gh-large-dmabuf-test.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,gh-large-dmabuf-test.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QTI Gunyah Hypervisor Large DMA-BUF Test Driver + +maintainers: + - Georgi Djakov + +description: | + The Gunyah Hypervisor Test Driver is used to validate gunyah hypervisor + functionality. It includes test nodes for transferring large dma-bufs + between VMs. + +properties: + compatible: + const: qcom,gh-large-dmabuf-test + + gunyah-label: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: The test driver will request interrupts with this label + from the gunyah doorbell driver. + + qcom,primary: + type: boolean + description: Specify if this device is on the primary virtual machine. + +required: + - compatible + +additionalProperties: false + +examples: + - | + Master: qcom,test-large-dmabuf { + compatible = "qcom,gh-large-dmabuf-test"; + gunyah-label = <4>; + qcom,primary; + }; + Client: qcom,test-large-dmabuf { + compatible = "qcom,gh-large-dmabuf-test"; + gunyah-label = <4>; + }; From eefeac1056ef6daf2b765bb86aa6124de270d3e5 Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Thu, 9 May 2024 16:36:06 -0700 Subject: [PATCH 40/55] ARM: dts: msm: gunyah: Add large dmabuf test nodes for sun Add test node to sun.dtsi, sun-vm.dtsi and sun-oemvm.dtsi to validate large dmabuf transfer functionality. Change-Id: I17cd06d12e18f26a6afe7c2da13fcca23a375b04 Signed-off-by: Georgi Djakov --- qcom/sun-oemvm.dtsi | 14 ++++++++++++++ qcom/sun-vm.dtsi | 14 ++++++++++++++ qcom/sun.dtsi | 12 ++++++++++++ 3 files changed, 40 insertions(+) diff --git a/qcom/sun-oemvm.dtsi b/qcom/sun-oemvm.dtsi index 1e14534e..1750a749 100644 --- a/qcom/sun-oemvm.dtsi +++ b/qcom/sun-oemvm.dtsi @@ -188,6 +188,15 @@ peer-default; }; + test-large-dmabuf-oemvm { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/test-large-dmabuf-oemvm-pair"; + message-size = <0xf0>; + queue-depth = <0x8>; + qcom,label = <0xe>; + peer-default; + }; + msgqsock-msgq-pair { vdevice-type = "message-queue-pair"; generate = "/hypervisor/msgqsock-msgq-pair"; @@ -291,6 +300,11 @@ affinity = <0>; }; + qcom,test-large-dmabuf-oemvm { + compatible = "qcom,gh-large-dmabuf-test"; + gunyah-label = <0xe>; + }; + qcom,gh-qtimer@1680b000 { compatible = "qcom,gh-qtmr"; reg = <0x1680b000 0x1000>; diff --git a/qcom/sun-vm.dtsi b/qcom/sun-vm.dtsi index d4b3ebc1..03b0aa0a 100644 --- a/qcom/sun-vm.dtsi +++ b/qcom/sun-vm.dtsi @@ -247,6 +247,15 @@ peer-default; }; + test-large-dmabuf-tuivm { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/test-large-dmabuf-tuivm-pair"; + message-size = <0xf0>; + queue-depth = <0x8>; + qcom,label = <0xd>; + peer-default; + }; + mem-buf-message-queue-pair { vdevice-type = "message-queue-pair"; generate = "/hypervisor/membuf-msgq-pair"; @@ -676,6 +685,11 @@ affinity = <0>; }; + qcom,test-large-dmabuf-tuivm { + compatible = "qcom,gh-large-dmabuf-test"; + gunyah-label = <0xd>; + }; + qcom,gh-qtimer@1680b000 { compatible = "qcom,gh-qtmr"; reg = <0x1680b000 0x1000>; diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 2cd07115..1357f957 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -3060,6 +3060,18 @@ qcom,primary; }; + qcom,test-large-dmabuf-tuivm { + compatible = "qcom,gh-large-dmabuf-test"; + gunyah-label = <0xd>; + qcom,primary; + }; + + qcom,test-large-dmabuf-oemvm { + compatible = "qcom,gh-large-dmabuf-test"; + gunyah-label = <0xe>; + qcom,primary; + }; + qcom,gh-qtimer@1680b000 { compatible = "qcom,gh-qtmr"; reg = <0x1680b000 0x1000>; From 839c5fe40d786ca373889906c08a8ed038d25534 Mon Sep 17 00:00:00 2001 From: Prakash Yadachi Date: Thu, 11 Jul 2024 10:41:59 +0530 Subject: [PATCH 41/55] ARM: dts: qcom: Add ranges property for qupv3_0 node Added ranges property for qupv3_0 node for Ravelin. Change-Id: I441dc416c718f8da38a61fdd79c3ffbc676cbf14 Signed-off-by: Prakash Yadachi --- qcom/ravelin-qupv3.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/ravelin-qupv3.dtsi b/qcom/ravelin-qupv3.dtsi index 904c2722..d4e78382 100644 --- a/qcom/ravelin-qupv3.dtsi +++ b/qcom/ravelin-qupv3.dtsi @@ -67,6 +67,7 @@ qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; dma-coherent; + ranges; status = "ok"; /* HS UART Instance */ From 8e5cf0739a84e28aa2c7661660ad49ba0a2dbd1e Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Wed, 10 Jul 2024 16:51:40 +0800 Subject: [PATCH 42/55] ARM: dts: msm: Add ddr registers to DCC on sun Add ddr registers to DCC list on sun. Change-Id: Ie6b5485ca698760a27df47834b79f7bfd5c996e3 Signed-off-by: Yuanfang Zhang --- qcom/sun-debug.dtsi | 1312 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 1311 insertions(+), 1 deletion(-) diff --git a/qcom/sun-debug.dtsi b/qcom/sun-debug.dtsi index 0cfada4c..0c9eacf7 100644 --- a/qcom/sun-debug.dtsi +++ b/qcom/sun-debug.dtsi @@ -338,7 +338,1317 @@ , , , - ; + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , 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+ , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; link_list_1 { From c48c4da1989c0d39cf9cdef701d5131484ffa1ff Mon Sep 17 00:00:00 2001 From: Shivendra Pratap Date: Thu, 4 Jul 2024 18:16:28 +0530 Subject: [PATCH 43/55] ARM: dts: msm: Add qcom_scm node for tuna Add qcom_scm node for tuna. Change-Id: Ic9e54e2d809ae70d24c903843919d91b996905c4 Signed-off-by: Shivendra Pratap --- qcom/tuna.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index eaaff929..01acafc3 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -36,7 +36,12 @@ reserved_memory: reserved-memory {}; - firmware: firmware {}; + firmware: firmware { + qcom_scm: qcom_scm { + compatible = "qcom,scm"; + qcom,dload-mode = <&tcsr 0x19000>; + }; + }; aliases { serial0 = &qupv3_se7_2uart; @@ -647,6 +652,11 @@ #reset-cells = <1>; }; + tcsr: syscon@1fc0000 { + compatible = "syscon"; + reg = <0x1fc0000 0x30000>; + }; + }; #include "tuna-gdsc.dtsi" From 165dc87ece813c728a1a7e8b61b827d536377019 Mon Sep 17 00:00:00 2001 From: Balaji Vekatesh Kalkonda Date: Mon, 8 Jul 2024 13:27:58 +0530 Subject: [PATCH 44/55] ARM: dts: msm: ravelin: add compatible string for focaltech touch This change enables compatible string for focaltech touch driver. Change-Id: I66d416092a5cbb8fa06ea8b77b8955637134b56b Signed-off-by: Balaji Vekatesh Kalkonda --- qcom/ravelin-idp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/ravelin-idp.dtsi b/qcom/ravelin-idp.dtsi index 568b5aa0..4ae1b237 100644 --- a/qcom/ravelin-idp.dtsi +++ b/qcom/ravelin-idp.dtsi @@ -61,6 +61,7 @@ focaltech@38 { reg = <0x38>; + compatible = "focaltech,fts_ts"; interrupt-parent = <&tlmm>; interrupts = <13 0x2008>; From 14f61e9e1427b7564dcc4da7518d3159d98badb9 Mon Sep 17 00:00:00 2001 From: Srinivasarao Pathipati Date: Fri, 5 Jul 2024 20:12:12 +0530 Subject: [PATCH 45/55] ARM: dts: msm: parrot: remove atomic in secure use case Atomic and secure domains are not a legal combination so remove atomic entry for secure use case. Change-Id: Id897102499385f6c6c504f030f2d9b0aef4853d0 Signed-off-by: Srinivasarao Pathipati --- qcom/msm-arm-smmu-parrot.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/qcom/msm-arm-smmu-parrot.dtsi b/qcom/msm-arm-smmu-parrot.dtsi index 1d592d20..ef43b4a9 100644 --- a/qcom/msm-arm-smmu-parrot.dtsi +++ b/qcom/msm-arm-smmu-parrot.dtsi @@ -384,7 +384,6 @@ usecase4_apps_secure { compatible = "qcom,iommu-debug-usecase"; iommus = <&apps_smmu 0x7e0 0>; - qcom,iommu-dma = "atomic"; qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ }; From 5542d2793945be352c023556011841304d9833c3 Mon Sep 17 00:00:00 2001 From: Nitesh Kumar Date: Fri, 5 Jul 2024 17:38:10 +0530 Subject: [PATCH 46/55] ARM: dts: qcom: Add cx regulator cooling device in zeroc thermal-zone Add cooling device to monitor cold temperature interrupts. Use "hot" trip type for thermal zone software shutdown trip for all thermal zones. It just notifies userspace thermal manager which in turn triggers a graceful shutdown. Change-Id: Id82d4f29e839e31742fb4d02859984f4584d148a Signed-off-by: Nitesh Kumar --- qcom/pmi632.dtsi | 6 +- qcom/ravelin-pmic-overlay.dtsi | 2 +- qcom/ravelin-thermal.dtsi | 156 ++++++++++++++++----------------- 3 files changed, 82 insertions(+), 82 deletions(-) diff --git a/qcom/pmi632.dtsi b/qcom/pmi632.dtsi index 625aedac..a6c9a75c 100644 --- a/qcom/pmi632.dtsi +++ b/qcom/pmi632.dtsi @@ -384,16 +384,16 @@ type = "passive"; }; - pmi632_trip1: trip1 { + trip1 { temperature = <115000>; hysteresis = <0>; - type = "passive"; + type = "hot"; }; trip2 { temperature = <145000>; hysteresis = <0>; - type = "passive"; + type = "critical"; }; }; }; diff --git a/qcom/ravelin-pmic-overlay.dtsi b/qcom/ravelin-pmic-overlay.dtsi index d6bc3028..cf0b87cd 100644 --- a/qcom/ravelin-pmic-overlay.dtsi +++ b/qcom/ravelin-pmic-overlay.dtsi @@ -270,7 +270,7 @@ trip1 { temperature = <115000>; hysteresis = <0>; - type = "passive"; + type = "hot"; }; trip2 { diff --git a/qcom/ravelin-thermal.dtsi b/qcom/ravelin-thermal.dtsi index e0f26fff..83c3984f 100644 --- a/qcom/ravelin-thermal.dtsi +++ b/qcom/ravelin-thermal.dtsi @@ -285,17 +285,17 @@ type = "passive"; }; - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - cpu0_emerg: cpu0-emerg-cfg { temperature = <110000>; hysteresis = <10000>; type = "passive"; }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; }; cooling-maps { @@ -323,17 +323,17 @@ type = "passive"; }; - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - cpu1_emerg: cpu1-emerg-cfg { temperature = <110000>; hysteresis = <10000>; type = "passive"; }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; }; cooling-maps { @@ -361,17 +361,17 @@ type = "passive"; }; - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - cpu2_emerg: cpu2-emerg-cfg { temperature = <110000>; hysteresis = <10000>; type = "passive"; }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; }; cooling-maps { @@ -399,17 +399,17 @@ type = "passive"; }; - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - cpu3_emerg: cpu3-emerg-cfg { temperature = <110000>; hysteresis = <10000>; type = "passive"; }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; }; cooling-maps { @@ -437,17 +437,17 @@ type = "passive"; }; - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - cpu4_emerg: cpu4-emerg-cfg { temperature = <110000>; hysteresis = <10000>; type = "passive"; }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; }; cooling-maps { @@ -475,17 +475,17 @@ type = "passive"; }; - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - cpu5_emerg: cpu5-emerg-cfg { temperature = <110000>; hysteresis = <10000>; type = "passive"; }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; }; cooling-maps { @@ -509,8 +509,8 @@ reset-mon-cfg { temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + hysteresis = <0>; + type = "hot"; }; }; }; @@ -528,8 +528,8 @@ reset-mon-cfg { temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + hysteresis = <0>; + type = "hot"; }; }; }; @@ -551,17 +551,17 @@ type = "passive"; }; - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - cpu6_emerg0: cpu6-emerg0-cfg { temperature = <110000>; hysteresis = <10000>; type = "passive"; }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; }; cooling-maps { @@ -589,17 +589,17 @@ type = "passive"; }; - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - cpu6_emerg1: cpu6-emerg1-cfg { temperature = <110000>; hysteresis = <10000>; type = "passive"; }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; }; cooling-maps { @@ -629,8 +629,8 @@ reset-mon-cfg { temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + hysteresis = <0>; + type = "hot"; }; cpu7_emerg0: cpu7-emerg0-cfg { @@ -667,8 +667,8 @@ reset-mon-cfg { temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + hysteresis = <0>; + type = "hot"; }; cpu7_emerg1: cpu7-emerg1-cfg { @@ -703,17 +703,17 @@ type = "passive"; }; - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - gpu_tj_cfg: tj_cfg { temperature = <95000>; hysteresis = <5000>; type = "passive"; }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; }; cooling-maps { @@ -737,8 +737,8 @@ reset-mon-cfg { temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + hysteresis = <0>; + type = "hot"; }; }; }; @@ -756,8 +756,8 @@ reset-mon-cfg { temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + hysteresis = <0>; + type = "hot"; }; }; }; @@ -800,8 +800,8 @@ reset-mon-cfg { temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + hysteresis = <0>; + type = "hot"; }; }; @@ -826,8 +826,8 @@ reset-mon-cfg { temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + hysteresis = <0>; + type = "hot"; }; }; }; @@ -845,8 +845,8 @@ reset-mon-cfg { temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + hysteresis = <0>; + type = "hot"; }; }; }; @@ -864,8 +864,8 @@ reset-mon-cfg { temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + hysteresis = <0>; + type = "hot"; }; }; }; @@ -883,13 +883,13 @@ reset-mon-cfg { temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + hysteresis = <0>; + type = "hot"; }; }; }; - zeroc-0-step { + zeroc-0 { polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&tsens0 128>; @@ -908,7 +908,7 @@ }; }; - zeroc-1-step { + zeroc-1 { polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&tsens1 128>; From 636081e6bdeb9a0bab7f3f0ef156f5e731badb0c Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Tue, 2 Jul 2024 14:56:53 +0800 Subject: [PATCH 47/55] ARM: dts: msm: move apps_scandump dump entry to static table Move apps_scandump memory dump entry to static dump table. Change-Id: I26e9d8359d7d814ed88f3eca9edb2cbd87f7a91c Signed-off-by: Yuanfang Zhang --- qcom/sun-debug.dtsi | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/qcom/sun-debug.dtsi b/qcom/sun-debug.dtsi index 0cfada4c..0511ea0a 100644 --- a/qcom/sun-debug.dtsi +++ b/qcom/sun-debug.dtsi @@ -734,6 +734,11 @@ qcom,dump-size = <0x40000>; qcom,dump-id = <0x220>; }; + + apps_scandump { + qcom,dump-size = <0x380000>; + qcom,dump-id = <0x130>; + }; }; dynamic_mem_dump { @@ -856,13 +861,6 @@ }; }; - apps_scandump { - scandump_apps { - qcom,dump-size = <0x380000>; - qcom,dump-id = <0x130>; - }; - }; - cpu_cache { cache_cpu0 { qcom,dump-size = <0x2aa000>; From 79014c4f836b6a391216943e2185db9b42d9cfea Mon Sep 17 00:00:00 2001 From: Maria Yu Date: Sat, 13 Jul 2024 10:26:15 +0800 Subject: [PATCH 48/55] dt-bindings: Update dt-binding for cpu mpam and platform mpam Add support for cpu mpam and platform mpam. Change-Id: I5ca021b39c3878061f2bde1fe1481fb2cc56f478 Signed-off-by: Maria Yu --- bindings/soc/qcom/qcom,mpam.yaml | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/bindings/soc/qcom/qcom,mpam.yaml b/bindings/soc/qcom/qcom,mpam.yaml index 733b4c4a..540f1579 100644 --- a/bindings/soc/qcom/qcom,mpam.yaml +++ b/bindings/soc/qcom/qcom,mpam.yaml @@ -18,7 +18,10 @@ description: | properties: compatible: - const: qcom,mpam + enum: + - qcom,cpu-mpam + - qcom,platform-mpam + - qcom,mpam reg: items: @@ -39,6 +42,19 @@ examples: - | qcom_mpam: qcom,mpam { compatible = "qcom,mpam"; - reg = <0x17b6f000 0x1000>; + reg = <0x17b6f000 0x400>; reg-names = "mon-base"; }; + + cpu_mpam: qcom,cpu_mpam { + compatible = "qcom,cpu-mpam"; + reg = <0x17b6f400 0x400>; + reg-names = "mon-base"; + }; + + noc_bw_mpam: qcom,noc_bw_mpam { + compatible = "qcom,platform-mpam"; + reg = <0x17b6f800 0x400>; + reg-names = "mon-base"; + }; +... From fdfdd5e0d59d26a4ba9b8589ad56163163b6b5df Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Mon, 17 Jun 2024 21:53:51 +0530 Subject: [PATCH 49/55] ARM: dts: qcom: Update passive polling for gpuss tsens Update passive polling for all gpuss tsens based on latest recommendation. Change-Id: Iea8e1b964bd945c384253518cc7a7c2389fa411d Signed-off-by: Manaf Meethalavalappu Pallikunhi --- qcom/sun-thermal.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/qcom/sun-thermal.dtsi b/qcom/sun-thermal.dtsi index c1c4d9c7..0ecd0864 100644 --- a/qcom/sun-thermal.dtsi +++ b/qcom/sun-thermal.dtsi @@ -1422,7 +1422,7 @@ }; gpuss-0 { - polling-delay-passive = <10>; + polling-delay-passive = <4>; polling-delay = <0>; thermal-sensors = <&tsens2 1>; trips { @@ -1460,7 +1460,7 @@ }; gpuss-1 { - polling-delay-passive = <10>; + polling-delay-passive = <4>; polling-delay = <0>; thermal-sensors = <&tsens2 2>; trips { @@ -1498,7 +1498,7 @@ }; gpuss-2 { - polling-delay-passive = <10>; + polling-delay-passive = <4>; polling-delay = <0>; thermal-sensors = <&tsens2 3>; trips { @@ -1536,7 +1536,7 @@ }; gpuss-3 { - polling-delay-passive = <10>; + polling-delay-passive = <4>; polling-delay = <0>; thermal-sensors = <&tsens2 4>; trips { @@ -1574,7 +1574,7 @@ }; gpuss-4 { - polling-delay-passive = <10>; + polling-delay-passive = <4>; polling-delay = <0>; thermal-sensors = <&tsens2 5>; trips { @@ -1612,7 +1612,7 @@ }; gpuss-5 { - polling-delay-passive = <10>; + polling-delay-passive = <4>; polling-delay = <0>; thermal-sensors = <&tsens2 6>; trips { @@ -1650,7 +1650,7 @@ }; gpuss-6 { - polling-delay-passive = <10>; + polling-delay-passive = <4>; polling-delay = <0>; thermal-sensors = <&tsens2 7>; trips { @@ -1688,7 +1688,7 @@ }; gpuss-7 { - polling-delay-passive = <10>; + polling-delay-passive = <4>; polling-delay = <0>; thermal-sensors = <&tsens2 8>; trips { From 8dbf04a5a567ddf0b8eecb72a3e417d2dc9da86b Mon Sep 17 00:00:00 2001 From: Huang Yiwei Date: Thu, 27 Jun 2024 15:21:20 +0800 Subject: [PATCH 50/55] ARM: dts: msm: Add platform_mpam noc_bw node for sun Add platform_mpam noc_bw node for sun. Change-Id: I878908109eed35e7fe3cf6e70bc78e51d2a793b2 Signed-off-by: Huang Yiwei --- qcom/sun.dtsi | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 73bc4e24..af1dbd34 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -3204,7 +3204,11 @@ qcom_mpam: qcom,mpam { compatible = "qcom,mpam"; - reg = <0x17b6f000 0x1000>; + }; + + cpu_mpam: qcom,cpu_mpam { + compatible = "qcom,cpu-mpam"; + reg = <0x17b6f000 0x400>; reg-names = "mon-base"; L2_0 { @@ -3218,6 +3222,36 @@ }; }; + noc_bw_mpam: qcom,noc_bw_mpam { + compatible = "qcom,platform-mpam"; + reg = <0x17b6f400 0x400>; + reg-names = "mon-base"; + qcom,msc-id = <3>; + qcom,msc-name = "noc_bw"; + qcom,gears = "low", "medium", "high", "veryhigh"; + qcom,gear-id = <1>, <2>, <3>, <4>; + + cpu_cluster0 { + qcom,client-id = <0x1>; + qcom,client-name = "cpu_cluster0"; + }; + + cpu_cluster1 { + qcom,client-id = <0x2>; + qcom,client-name = "cpu_cluster1"; + }; + + gpu { + qcom,client-id = <0x10>; + qcom,client-name = "gpu"; + }; + + nsp { + qcom,client-id = <0x100>; + qcom,client-name = "nsp"; + }; + }; + llcc_pmu: llcc-pmu@24095000 { compatible = "qcom,llcc-pmu-ver2"; reg = <0x24095000 0x300>; From 9ece25b26d0360d066a057a247883d5a40af72fb Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Mon, 7 Aug 2023 19:08:53 +0530 Subject: [PATCH 51/55] arm64: dts: qcom: sdx75: Add rpmhpd node Add rpmhpd node and opps for this node to the SDX75 dts. Change-Id: I205b112cc6c5acef1b551cc1f37211ebc4014afb Signed-off-by: Rohit Agarwal Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/1691415534-31820-9-git-send-email-quic_rohiagar@quicinc.com [bjorn: include qcom-rpmpd.h as well] Signed-off-by: Bjorn Andersson Git-Commit: 1862d0e3eb1fcc863eb8c212abf99ce2923ee363 Git-Repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git Signed-off-by: Khaja Hussain Shaik Khaji --- qcom/sdx75.dtsi | 52 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/qcom/sdx75.dtsi b/qcom/sdx75.dtsi index 21d5d55d..698f2219 100644 --- a/qcom/sdx75.dtsi +++ b/qcom/sdx75.dtsi @@ -9,6 +9,8 @@ #include #include #include +#include +#include #include / { @@ -643,6 +645,56 @@ clock-names = "xo"; #clock-cells = <1>; }; + + rpmhpd: power-controller { + compatible = "qcom,sdx75-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp-16 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp-48 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp-64 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp-128 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp-192 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp-256 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp-320 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp-336 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp-384 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp-416 { + opp-level = ; + }; + }; + }; }; cpufreq_hw: cpufreq@17d91000 { From 5b492036a0a16e3a5884bed5e278d29048fd7364 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Mon, 7 Aug 2023 19:08:47 +0530 Subject: [PATCH 52/55] arm64: dts: qcom: sdx75: Add spmi node Add SPMI node to SDX75 dtsi. Change-Id: I3941cd44dd0cc9582f7dce677fcd9c328daa30a0 Signed-off-by: Rohit Agarwal Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/1691415534-31820-3-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Bjorn Andersson Git-Commit: 1020fca4f2381cb59ffb40bb81e41913d6193b97 Git-Repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git Signed-off-by: Khaja Hussain Shaik Khaji --- qcom/sdx75.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/qcom/sdx75.dtsi b/qcom/sdx75.dtsi index 21d5d55d..6e2d07f1 100644 --- a/qcom/sdx75.dtsi +++ b/qcom/sdx75.dtsi @@ -469,6 +469,29 @@ interrupt-controller; }; + spmi_bus: spmi@c400000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0x0c400000 0x0 0x3000>, + <0x0 0x0c500000 0x0 0x400000>, + <0x0 0x0c440000 0x0 0x80000>, + <0x0 0x0c4c0000 0x0 0x10000>, + <0x0 0x0c42d000 0x0 0x4000>; + reg-names = "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + qcom,ee = <0>; + qcom,channel = <0>; + qcom,bus-id = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + tlmm: pinctrl@f000000 { compatible = "qcom,sdx75-tlmm"; reg = <0x0 0x0f000000 0x0 0x400000>; From 64b3c10b9ba24ee157c6e7c2bfd21fda80164b42 Mon Sep 17 00:00:00 2001 From: Shashikala Katthi Date: Fri, 5 Jul 2024 13:13:34 +0530 Subject: [PATCH 53/55] ARM: dts: msm: parrot: Add hdcp device node This change add device tree node for hdcp smcinvoke interface for parrot. Change-Id: I1e4b1c45cbb96e472fb8e496db74ef23fe4b502c Signed-off-by: Shashikala Katthi --- qcom/parrot.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/parrot.dtsi b/qcom/parrot.dtsi index 3235f238..6f373c57 100644 --- a/qcom/parrot.dtsi +++ b/qcom/parrot.dtsi @@ -2030,6 +2030,11 @@ qcom,vmid = <3>; }; + qcom,hdcp { + compatible = "qcom,hdcp"; + qcom,use-smcinvoke = <1>; + }; + qcom,mem-buf-msgq { compatible = "qcom,mem-buf-msgq"; }; From 696610ee276fea6ad3e8633e86d8477c87bf4615 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Fri, 17 Nov 2023 13:37:35 +0530 Subject: [PATCH 54/55] arm64: dts: qcom: Add interconnect nodes for SDX75 Add interconnect nodes to support interconnects on SDX75. Also parallely add the interconnect property for UART required so that the bootup to shell does not break with interconnects in place. Change-Id: Ic5a433a27abcdc86ba5988f76aa8bb62f333c9a1 Signed-off-by: Rohit Agarwal Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20231117080737.606687-2-quic_rohiagar@quicinc.com Signed-off-by: Bjorn Andersson Git-commit: ea72a527bd205283db08287cd49737e889788065 Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git Signed-off-by: Khaja Hussain Shaik Khaji --- qcom/sdx75.dtsi | 52 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/qcom/sdx75.dtsi b/qcom/sdx75.dtsi index 698f2219..2c763ae5 100644 --- a/qcom/sdx75.dtsi +++ b/qcom/sdx75.dtsi @@ -8,6 +8,8 @@ #include #include +#include +#include #include #include #include @@ -203,6 +205,19 @@ }; }; + clk_virt: interconnect-0 { + compatible = "qcom,sdx75-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&rpmhcc RPMH_QPIC_CLK>; + }; + + mc_virt: interconnect-1 { + compatible = "qcom,sdx75-mc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x0>; @@ -434,6 +449,9 @@ clock-names = "m-ahb", "s-ahb"; iommus = <&apps_smmu 0xe3 0x0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core"; #address-cells = <2>; #size-cells = <2>; ranges; @@ -444,6 +462,12 @@ reg = <0x0 0x00984000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; interrupts = ; pinctrl-0 = <&qupv3_se1_2uart_active>; pinctrl-1 = <&qupv3_se1_2uart_sleep>; @@ -453,6 +477,20 @@ }; }; + system_noc: interconnect@1640000 { + compatible = "qcom,sdx75-system-noc"; + reg = <0x0 0x01640000 0x0 0x4b400>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + pcie_anoc: interconnect@16c0000 { + compatible = "qcom,sdx75-pcie-anoc"; + reg = <0x0 0x016c0000 0x0 0x14200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; @@ -710,6 +748,20 @@ #freq-domain-cells = <1>; #clock-cells = <1>; }; + + dc_noc: interconnect@190e0000 { + compatible = "qcom,sdx75-dc-noc"; + reg = <0x0 0x190e0000 0x0 0x8200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gem_noc: interconnect@19100000 { + compatible = "qcom,sdx75-gem-noc"; + reg = <0x0 0x19100000 0x0 0x34080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; }; timer { From 97878aa1abeb455b0e26e3d9a5cf35d374039ebd Mon Sep 17 00:00:00 2001 From: Khaja Hussain Shaik Khaji Date: Thu, 9 May 2024 13:21:07 +0530 Subject: [PATCH 55/55] ARM: dts: msm: Add initial device trees for sdxkova SoC Add initial device trees to support sdxkova SoC. Change-Id: I6423d06ff47ad79b2601a24d65a41cb40b3a4a9a Signed-off-by: Khaja Hussain Shaik Khaji --- qcom/Makefile | 7 +++++++ qcom/platform_map.bzl | 10 ++++++++++ qcom/sdxkova-idp-cpe.dts | 17 +++++++++++++++++ qcom/sdxkova-idp-cpe.dtsi | 4 ++++ qcom/sdxkova-idp-mbb.dts | 17 +++++++++++++++++ qcom/sdxkova-idp-mbb.dtsi | 4 ++++ qcom/sdxkova.dtsi | 16 ++++++++++++++++ 7 files changed, 75 insertions(+) create mode 100644 qcom/sdxkova-idp-cpe.dts create mode 100644 qcom/sdxkova-idp-cpe.dtsi create mode 100644 qcom/sdxkova-idp-mbb.dts create mode 100644 qcom/sdxkova-idp-mbb.dtsi create mode 100644 qcom/sdxkova.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 50bec119..1bcfd1a2 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -169,6 +169,13 @@ dtb-y += $(pineapple_tuivm-dtb-y) endif endif +ifeq ($(CONFIG_ARCH_SDXKOVA), y) +sdxkova-dtb-$(CONFIG_ARCH_SDXKOVA) += sdxkova-idp-cpe.dtb \ + sdxkova-idp-mbb.dtb +dtb-y += $(sdxkova-dtb-y) + +endif + ifeq ($(CONFIG_ARCH_SUN), y) ifeq ($(CONFIG_ARCH_QTI_VM), y) sun_tuivm-dtb-$(CONFIG_ARCH_QTI_VM) += sun-vm-rumi.dtb \ diff --git a/qcom/platform_map.bzl b/qcom/platform_map.bzl index deb66a79..19a77d53 100644 --- a/qcom/platform_map.bzl +++ b/qcom/platform_map.bzl @@ -1,4 +1,14 @@ _platform_map = { + "sdxkova": { + "dtb_list": [ + # keep sorted + {"name": "sdxkova-idp-cpe.dtb"}, + {"name": "sdxkova-idp-mbb.dtb"}, + ], + "dtbo_list": [ + # keep sorted + ], + }, "sun": { "dtb_list": [ # keep sorted diff --git a/qcom/sdxkova-idp-cpe.dts b/qcom/sdxkova-idp-cpe.dts new file mode 100644 index 00000000..079b3ec8 --- /dev/null +++ b/qcom/sdxkova-idp-cpe.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "sdxkova.dtsi" +#include "sdxkova-idp-cpe.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXKOVA IDP CPE"; + compatible = "qcom,sdxkova-idp", + "qcom,sdxkova", "qcom,idp"; + qcom,msm-id = <556 0x10000>; + qcom,board-id = <0x3010022 0x403>; +}; diff --git a/qcom/sdxkova-idp-cpe.dtsi b/qcom/sdxkova-idp-cpe.dtsi new file mode 100644 index 00000000..9df4770a --- /dev/null +++ b/qcom/sdxkova-idp-cpe.dtsi @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ diff --git a/qcom/sdxkova-idp-mbb.dts b/qcom/sdxkova-idp-mbb.dts new file mode 100644 index 00000000..bbe2a28e --- /dev/null +++ b/qcom/sdxkova-idp-mbb.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "sdxkova.dtsi" +#include "sdxkova-idp-mbb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXKOVA IDP MBB"; + compatible = "qcom,sdxkova-idp", + "qcom,sdxkova", "qcom,idp"; + qcom,msm-id = <556 0x10000>; + qcom,board-id = <0x2010022 0x302>, <0x2010022 0x402>; +}; diff --git a/qcom/sdxkova-idp-mbb.dtsi b/qcom/sdxkova-idp-mbb.dtsi new file mode 100644 index 00000000..9df4770a --- /dev/null +++ b/qcom/sdxkova-idp-mbb.dtsi @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ diff --git a/qcom/sdxkova.dtsi b/qcom/sdxkova.dtsi new file mode 100644 index 00000000..a4a57891 --- /dev/null +++ b/qcom/sdxkova.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "sdx75.dtsi" + +/ { + qcom_tzlog: tz-log@14680720 { + compatible = "qcom,tz-log"; + reg = <0x14680720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; + hyplog-size-offset = <0x414>; + }; +};