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Merge "dt-bindings: clock: Add clock controller bindings for SM4450"

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This commit is contained in:
qctecmdr
2024-05-29 20:13:18 -07:00
committed by Gerrit - the friendly Code Review server
parent 00a945a3bc e3338c6885
commit 6cbdcfce1d
6 changed files with 193 additions and 0 deletions
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1
bindings/clock/qcom,debugcc.yaml
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@@ -19,6 +19,7 @@ properties:
- qcom,pineapple-debugcc
- qcom,sun-debugcc
- qcom,parrot-debugcc
- qcom,sm4450-debugcc
clocks:
items:

2
bindings/clock/qcom,gpucc.yaml
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@@ -18,6 +18,7 @@ description: |
dt-bindings/clock/qcom,gpucc-sc7180.h
dt-bindings/clock/qcom,gpucc-sc7280.h
dt-bindings/clock/qcom,gpucc-sc8280xp.h
dt-bindings/clock/qcom,sm4450-gpucc.h
dt-bindings/clock/qcom,gpucc-sm6350.h
dt-bindings/clock/qcom,gpucc-sm8150.h
dt-bindings/clock/qcom,gpucc-sm8250.h
@@ -33,6 +34,7 @@ properties:
- qcom,sc7280-gpucc
- qcom,sc8180x-gpucc
- qcom,sc8280xp-gpucc
- qcom,sm4450-gpucc
- qcom,sm6350-gpucc
- qcom,sm8150-gpucc
- qcom,sm8250-gpucc

1
bindings/clock/qcom,rpmhcc.yaml
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@@ -25,6 +25,7 @@ properties:
- qcom,sdm845-rpmh-clk
- qcom,sdx55-rpmh-clk
- qcom,sdx65-rpmh-clk
- qcom,sm4450-rpmh-clk
- qcom,sm6350-rpmh-clk
- qcom,sm8150-rpmh-clk
- qcom,sm8250-rpmh-clk

63
bindings/clock/qcom,sm4450-camcc.yaml Normal file
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@@ -0,0 +1,63 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm4450-camcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Camera Clock & Reset Controller on SM4450
maintainers:
- Ajit Pandey <quic_ajipan@quicinc.com>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm Technologies, Inc. camera clock control module provides the clocks, resets and power
domains on SM4450
See also:: include/dt-bindings/clock/qcom,sm4450-camcc.h
properties:
compatible:
const: qcom,sm4450-camcc
reg:
maxItems: 1
clocks:
items:
- description: Board XO source
- description: Camera AHB clock source from GCC
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm4450-gcc.h>
clock-controller@ade0000 {
compatible = "qcom,sm4450-camcc";
reg = <0x0ade0000 0x20000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_CAMERA_AHB_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

71
bindings/clock/qcom,sm4450-dispcc.yaml Normal file
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@@ -0,0 +1,71 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm4450-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Display Clock & Reset Controller on SM4450
maintainers:
- Ajit Pandey <quic_ajipan@quicinc.com>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm Technologies, Inc. display clock control module provides the clocks, resets and power
domains on SM4450
See also:: include/dt-bindings/clock/qcom,sm4450-dispcc.h
properties:
compatible:
const: qcom,sm4450-dispcc
reg:
maxItems: 1
clocks:
items:
- description: Board XO source
- description: Board active XO source
- description: Display AHB clock source from GCC
- description: sleep clock source
- description: Byte clock from DSI PHY0
- description: Pixel clock from DSI PHY0
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm4450-gcc.h>
clock-controller@af00000 {
compatible = "qcom,sm4450-dispcc";
reg = <0x0af00000 0x20000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&gcc GCC_DISP_AHB_CLK>,
<&sleep_clk>,
<&dsi0_phy_pll_out_byteclk>,
<&dsi0_phy_pll_out_dsiclk>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

55
bindings/clock/qcom,sm4450-gcc.yaml Normal file
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@@ -0,0 +1,55 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm4450-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Global Clock & Reset Controller on SM4450
maintainers:
- Ajit Pandey <quic_ajipan@quicinc.com>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm Technologies, Inc. global clock control module provides the clocks, resets and power
domains on SM4450
See also:: include/dt-bindings/clock/qcom,sm4450-gcc.h
properties:
compatible:
const: qcom,sm4450-gcc
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: UFS Phy Rx symbol 0 clock source
- description: UFS Phy Rx symbol 1 clock source
- description: UFS Phy Tx symbol 0 clock source
- description: USB3 Phy wrapper pipe clock source
required:
- compatible
- clocks
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,sm4450-gcc";
reg = <0x00100000 0x001f4200>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
<&ufs_mem_phy 0>, <&ufs_mem_phy 1>,
<&ufs_mem_phy 2>, <&usb_1_qmpphy>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...