ARM: dts: msm: Add support for cpufreq_hw node on KERA

Add support for cpufreq_hw and cpufreq_hw_debug nodes on kera platform.
While at it, set the default governor to performance on kera platform.

Change-Id: Id6fd146d3c80f686780591e5efa594bd76155bcd
Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com>
This commit is contained in:
Ajit Pandey
2024-10-25 10:16:16 +05:30
committed by Anaadi Mishra
parent 7037f12c76
commit 6c751c7e73

View File

@@ -101,6 +101,7 @@
cpu-idle-states = <&SILVER_OFF &SILVER_RAIL_OFF>; cpu-idle-states = <&SILVER_OFF &SILVER_RAIL_OFF>;
power-domains = <&CPU_PD0>; power-domains = <&CPU_PD0>;
power-domain-names = "psci"; power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
#cooling-cells = <2>; #cooling-cells = <2>;
dynamic-power-coefficient = <100>; dynamic-power-coefficient = <100>;
@@ -125,6 +126,7 @@
cpu-idle-states = <&SILVER_OFF &SILVER_RAIL_OFF>; cpu-idle-states = <&SILVER_OFF &SILVER_RAIL_OFF>;
power-domains = <&CPU_PD1>; power-domains = <&CPU_PD1>;
power-domain-names = "psci"; power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
dynamic-power-coefficient = <100>; dynamic-power-coefficient = <100>;
capacity-dmips-mhz = <1024>; capacity-dmips-mhz = <1024>;
@@ -139,6 +141,7 @@
cpu-idle-states = <&SILVER_OFF &SILVER_RAIL_OFF>; cpu-idle-states = <&SILVER_OFF &SILVER_RAIL_OFF>;
power-domains = <&CPU_PD2>; power-domains = <&CPU_PD2>;
power-domain-names = "psci"; power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
next-level-cache = <&L2_2>; next-level-cache = <&L2_2>;
#cooling-cells = <2>; #cooling-cells = <2>;
dynamic-power-coefficient = <100>; dynamic-power-coefficient = <100>;
@@ -158,6 +161,7 @@
cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
power-domains = <&CPU_PD3>; power-domains = <&CPU_PD3>;
power-domain-names = "psci"; power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
next-level-cache = <&L2_3>; next-level-cache = <&L2_3>;
#cooling-cells = <2>; #cooling-cells = <2>;
dynamic-power-coefficient = <263>; dynamic-power-coefficient = <263>;
@@ -177,6 +181,7 @@
cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
power-domains = <&CPU_PD4>; power-domains = <&CPU_PD4>;
power-domain-names = "psci"; power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
next-level-cache = <&L2_4>; next-level-cache = <&L2_4>;
#cooling-cells = <2>; #cooling-cells = <2>;
dynamic-power-coefficient = <263>; dynamic-power-coefficient = <263>;
@@ -196,6 +201,7 @@
cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
power-domains = <&CPU_PD5>; power-domains = <&CPU_PD5>;
power-domain-names = "psci"; power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
next-level-cache = <&L2_5>; next-level-cache = <&L2_5>;
#cooling-cells = <2>; #cooling-cells = <2>;
dynamic-power-coefficient = <263>; dynamic-power-coefficient = <263>;
@@ -215,6 +221,7 @@
cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
power-domains = <&CPU_PD6>; power-domains = <&CPU_PD6>;
power-domain-names = "psci"; power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
next-level-cache = <&L2_6>; next-level-cache = <&L2_6>;
#cooling-cells = <2>; #cooling-cells = <2>;
dynamic-power-coefficient = <263>; dynamic-power-coefficient = <263>;
@@ -234,6 +241,7 @@
cpu-idle-states = <&GOLD_PLUS_OFF &GOLD_PLUS_RAIL_OFF>; cpu-idle-states = <&GOLD_PLUS_OFF &GOLD_PLUS_RAIL_OFF>;
power-domains = <&CPU_PD7>; power-domains = <&CPU_PD7>;
power-domain-names = "psci"; power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 2>;
next-level-cache = <&L2_7>; next-level-cache = <&L2_7>;
#cooling-cells = <2>; #cooling-cells = <2>;
dynamic-power-coefficient = <289>; dynamic-power-coefficient = <289>;
@@ -1905,6 +1913,24 @@
compatible = "smmu-proxy-sender"; compatible = "smmu-proxy-sender";
}; };
cpufreq_hw: qcom,cpufreq-hw {
compatible = "qcom,cpufreq-epss";
reg = <0x17d91000 0x1000>, <0x17d92000 0x1000>, <0x17d93000 0x1000>;
reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dcvsh0_int", "dcvsh1_int", "dcvsh2_int";
#freq-domain-cells = <1>;
};
qcom,cpufreq-hw-debug {
compatible = "qcom,cpufreq-hw-epss-debug";
qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>, <&cpufreq_hw 2>;
};
clk_virt: interconnect@0 { clk_virt: interconnect@0 {
compatible = "qcom,kera-clk_virt"; compatible = "qcom,kera-clk_virt";
#interconnect-cells = <1>; #interconnect-cells = <1>;