ARM: dts: msm: Add opensource wlan device tree support for
tuna-kiwi This change adds wlan opensource dt files for tuna-kiwi. Change-Id: Ieab01519346f3024a14dc766999488cea95b9ba2 CRs-Fixed: 3940905
This commit is contained in:
Prateek Patil
16
tuna-atp-kiwi.dts
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16
tuna-atp-kiwi.dts
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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/dts-v1/;
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/plugin/;
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#include "tuna-kiwi-cnss.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Tuna ATP + kiwi WLAN";
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compatible = "qcom,tuna-atp", "qcom,tuna", "qcom,atp";
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qcom,msm-id = <655 0x10000>, <681 0x10000>;
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qcom,board-id = <33 0>;
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};
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198
tuna-kiwi-cnss.dtsi
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198
tuna-kiwi-cnss.dtsi
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/interconnect/qcom,tuna.h>
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&wlan_msa_mem {
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status = "disabled";
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};
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&wpss_mem {
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status = "disabled";
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};
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&wpss_pas {
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status = "disabled";
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};
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&pcie0 {
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status = "ok";
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};
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&tlmm {
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cnss_pins {
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cnss_wlan_en_active: cnss_wlan_en_active {
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mux {
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pins = "gpio35";
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function = "gpio";
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};
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config {
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pins = "gpio35";
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drive-strength = <16>;
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output-high;
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bias-pull-up;
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};
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};
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cnss_wlan_en_sleep: cnss_wlan_en_sleep {
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mux {
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pins = "gpio35";
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function = "gpio";
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};
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config {
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pins = "gpio35";
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drive-strength = <2>;
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output-low;
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bias-pull-down;
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};
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};
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cnss_wlan_sw_ctrl: cnss_wlan_sw_ctrl {
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mux {
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pins = "gpio80";
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function = "wcn_sw_ctrl";
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};
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};
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cnss_wlan_sw_ctrl_wl_cx: cnss_wlan_sw_ctrl_wl_cx {
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mux {
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pins = "gpio34";
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function = "wcn_sw";
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};
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};
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};
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};
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&reserved_memory {
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cnss_wlan_mem: cnss_wlan_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x2000000>;
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};
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};
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&soc {
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wlan_kiwi: qcom,cnss-kiwi@b0000000 {
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compatible = "qcom,cnss-kiwi";
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reg = <0xb0000000 0x10000>;
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reg-names = "smmu_iova_ipa";
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qcom,wlan-sw-ctrl-gpio = <&tlmm 34 0>;
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supported-ids = <0x1107>;
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wlan-en-gpio = <&tlmm 35 0>;
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qcom,bt-en-gpio = <&pm8550vs_g_gpios 4 0>;
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qcom,sw-ctrl-gpio = <&tlmm 80 0>;
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/* List of GPIOs to be setup for interrupt wakeup capable */
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mpm_wake_set_gpios = <80 34>;
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pinctrl-names = "wlan_en_active", "wlan_en_sleep", "sw_ctrl",
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"sw_ctrl_wl_cx";
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pinctrl-0 = <&cnss_wlan_en_active>;
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pinctrl-1 = <&cnss_wlan_en_sleep>;
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pinctrl-2 = <&cnss_wlan_sw_ctrl>;
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pinctrl-3 = <&cnss_wlan_sw_ctrl_wl_cx>;
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qcom,wlan;
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qcom,wlan-rc-num = <0>;
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qcom,wlan-ramdump-dynamic = <0x780000>;
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cnss-enable-self-recovery;
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qcom,wlan-cbc-enabled;
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use-pm-domain;
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qcom,same-dt-multi-dev;
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/* For AOP communication, use direct QMP instead of mailbox */
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qcom,qmp = <&aoss_qmp>;
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interconnects =
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<&pcie_noc MASTER_PCIE_0 &pcie_noc SLAVE_ANOC_PCIE_GEM_NOC>,
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<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
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interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";
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qcom,icc-path-count = <2>;
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qcom,bus-bw-cfg-count = <9>;
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qcom,bus-bw-cfg =
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/** ICC Path 1 **/
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<0 0>, /* no vote */
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/* idle: 0-18 Mbps snoc/anoc: 100 Mhz */
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<2250 1200000>,
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/* low: 18-60 Mbps snoc/anoc: 100 Mhz */
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<7500 1200000>,
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/* medium: 60-240 Mbps snoc/anoc: 100 Mhz */
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<30000 1200000>,
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/* high: 240-1200 Mbps snoc/anoc: 100 Mhz */
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<100000 1200000>,
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/* very high: > 1200 Mbps snoc/anoc: 403 Mhz */
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<175000 3224000>,
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/* ultra high: DBS mode snoc/anoc: 403 Mhz */
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<312500 3224000>,
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/* super high: DBS mode snoc/anoc: 533 Mhz */
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<587500 4264000>,
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/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */
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<7500 1600000>,
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/** ICC Path 2 **/
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<0 0>,
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/* idle: 0-18 Mbps ddr: 451.2 MHz */
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<2250 2188800>,
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/* low: 18-60 Mbps ddr: 451.2 MHz */
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<7500 2188800>,
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/* medium: 60-240 Mbps ddr: 451.2 MHz */
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<30000 2188800>,
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/* high: 240-1200 Mbps ddr: 451.2 MHz */
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<100000 2188800>,
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/* very high: > 1200 Mbps ddr: 1555 MHz */
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<175000 6220800>,
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/* ultra high: DBS mode ddr: 2092 MHz */
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<312500 8368000>,
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/* super high: DBS mode ddr: 3.2 GHz */
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<587500 12800000>,
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/* low (latency critical): 18-60 Mbps ddr: 451.2 MHz */
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<7500 2188800>;
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qcom,pdc_init_table =
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" {class: wlan_pdc, ss: rf, res: s3b.v, upval: 976}",
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" {class: wlan_pdc, ss: rf, res: s3b.v, dwnval: 616}",
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" {class: wlan_pdc, ss: rf, res: s1g.m, enable: 0}",
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" {class: wlan_pdc, ss: rf, res: l18b.m, enable: 0}",
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" {class: wlan_pdc, ss: rf, res: b1b.m, enable: 0}",
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" {class: wlan_pdc, ss: bb, res: pdc, enable: 1}";
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/* cpu mask used for wlan tx rx interrupt affinity
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* <cpumask_for_rx_interrupts cpumask_for_tx_comp_interrupts>
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*/
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wlan-txrx-intr-cpumask = <0x3 0x30>;
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};
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};
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&pcie0_rp {
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cnss_pci0: cnss_pci0 {
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reg = <0 0 0 0 0>;
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qcom,iommu-group = <&cnss_pci_iommu_group0>;
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memory-region =
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<&cnss_wlan_mem &cnss_pci0_iommu_region_partition>;
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#address-cells = <1>;
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#size-cells = <1>;
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cnss_pci0_iommu_region_partition:
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cnss_pci0_iommu_region_partition {
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/* address-cells =3 size-cells=2 from sun-pcie.dtsi */
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iommu-addresses = <&cnss_pci0 0x0 0x0 0x0 0x0 0x98000000>,
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<&cnss_pci0 0x0 0x0 0xB0000000 0x0 0x50000000>;
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};
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cnss_pci_iommu_group0: cnss_pci_iommu_group0 {
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qcom,iommu-msi-size = <0x1000>;
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qcom,iommu-geometry = <0x98000000 0x18010000>;
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qcom,iommu-dma = "fastmap";
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qcom,iommu-pagetable = "coherent";
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qcom,iommu-faults = "stall-disable", "HUPCF",
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"non-fatal";
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};
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};
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};
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16
tuna-mtp-kiwi.dts
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16
tuna-mtp-kiwi.dts
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@@ -0,0 +1,16 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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/dts-v1/;
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/plugin/;
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#include "tuna-kiwi-cnss.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Tuna MTP + kiwi WLAN";
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compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,mtp";
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qcom,msm-id = <655 0x10000>, <681 0x10000>;
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qcom,board-id = <8 2>;
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};
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16
tuna-rcm-kiwi.dts
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16
tuna-rcm-kiwi.dts
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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/dts-v1/;
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/plugin/;
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#include "tuna-kiwi-cnss.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Tuna RCM + kiwi WLAN";
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compatible = "qcom,tuna-rcm", "qcom,tuna", "qcom,rcm";
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qcom,msm-id = <655 0x10000>, <681 0x10000>;
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qcom,board-id = <21 1>;
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};
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