From cc38699007b8108ddffbe22e0a1e7b2308cdac4e Mon Sep 17 00:00:00 2001 From: Jayasri Sampath Kumaran Date: Mon, 22 Jan 2024 13:11:45 -0500 Subject: [PATCH 01/21] ARM: dts: msm: update iommu address range for sun target Update unsecure iommu address pool to exclude memory region allocated to HW-Fence. Change-Id: I20ae5e357da5346e663044bbc1565135ff3a1ca7 Signed-off-by: Jayasri Sampath Kumaran --- display/sun-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 18c83c8e..1c714c37 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -183,6 +183,7 @@ smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition { iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>, + <&smmu_sde_unsec 0xd4e23000 0x002dd000>, <&smmu_sde_unsec 0xd5500000 0x02b00000>, <&smmu_sde_sec 0x0 0x00020000>; }; From 9e5057ad5b8d9c3b54b62e4d4fde2e33a35f5d2e Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Mon, 22 Jan 2024 22:43:57 -0800 Subject: [PATCH 02/21] ARM: dts: msm: add ATP variant DT support on sun target Add DT support for ATP variant on sun target. Change-Id: I3860457c497e311e625884dad6972496cc3729c0 Signed-off-by: Veera Sundaram Sankaran --- Kbuild | 3 ++- display/sun-sde-display-atp-overlay.dts | 16 ++++++++++++++++ 2 files changed, 18 insertions(+), 1 deletion(-) create mode 100644 display/sun-sde-display-atp-overlay.dts diff --git a/Kbuild b/Kbuild index a824c4d7..3060fd20 100644 --- a/Kbuild +++ b/Kbuild @@ -14,7 +14,8 @@ dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \ display/sun-sde-display-cdp-nfc-overlay.dtbo \ display/sun-sde-display-mtp-nfc-overlay.dtbo \ display/sun-sde-display-cdp-v8-overlay.dtbo \ - display/sun-sde-display-mtp-v8-overlay.dtbo + display/sun-sde-display-mtp-v8-overlay.dtbo \ + display/sun-sde-display-atp-overlay.dtbo else dtbo-$(CONFIG_ARCH_SUN) += display/trustedvm-sun-sde-display-cdp-overlay.dtbo \ display/trustedvm-sun-sde-display-mtp-overlay.dtbo diff --git a/display/sun-sde-display-atp-overlay.dts b/display/sun-sde-display-atp-overlay.dts new file mode 100644 index 00000000..d3b24f2d --- /dev/null +++ b/display/sun-sde-display-atp-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun ATP"; + compatible = "qcom,sun-atp", "qcom,sun", "qcom,sunp-atp", "qcom,sunp", "qcom,atp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,board-id = <0x10021 0>; +}; From ea996a0a93c9e9c5c22d3d69833d36cc38898cb5 Mon Sep 17 00:00:00 2001 From: Lei Chen Date: Wed, 10 Jan 2024 17:11:18 +0800 Subject: [PATCH 03/21] ARM: dts: msm: enable mmrm on sun target This change enables mmrm device tree entry for supporting mdp core clock voting through mmrm on sun target. Change-Id: Ie0a10345e53d29c7080f591b42405048c7ff494d Signed-off-by: Lei Chen --- display/sun-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 18c83c8e..105cab82 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -218,6 +218,7 @@ "lut_clk"; clock-rate = <0 0 575000000 575000000 19200000 575000000>; clock-max-rate = <0 0 575000000 575000000 19200000 575000000>; + clock-mmrm = <0 0 0 DISP_CC_MDSS_MDP_CLK_SRC 0 0>; vdd-supply = <&disp_cc_mdss_core_gdsc>; mmcx-supply = <&VDD_MMCX_LEVEL>; From ab7e80ddd8f1e9537e5afe84dbe582061ebb0b01 Mon Sep 17 00:00:00 2001 From: Ping Li Date: Fri, 26 Jan 2024 13:18:24 -0800 Subject: [PATCH 04/21] ARM: dts: msm: add entry for ssip fuse configuration Add dts entry for ssip fuse configuration on Sun platform. Change-Id: Ia88f0e73d0813c99b7464adc031c4aca8e331440 Signed-off-by: Ping Li --- bindings/sde.txt | 5 +++++ display/sun-sde.dtsi | 3 +++ 2 files changed, 8 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 779a3da7..e432ad8b 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -420,6 +420,8 @@ Optional properties: hardware. - qcom,sde-aiqe-has-feature-aiscaler: Boolean property indicating the presence of AIQE feature AI Scaler hardware. +- nvmem-cells: phandle list to the fuse configuration data provided by a nvmem device. +- nvmem-cell-names: nvmem cell name. - qcom,sde-lm-noise-off: A u32 value indicating noise layer offset from mixer base. - qcom,sde-lm-noise-version: A u32 value indicating the noise layer version. - qcom,sde-vbif-id: Array of vbif ids corresponding to the @@ -982,6 +984,9 @@ Example: qcom,sde-reg-dma-xin-id = <7>; qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; + nvmem-cells = <&ssip_config>; + nvmem-cell-names = "ssip_config"; + qcom,sde-sspp-vig-blocks { vcm@0 { cell-index = <0>; diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 18c83c8e..578d63e6 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -241,6 +241,9 @@ /* offsets are based off dspp 0, 1, 2, and 3 */ qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300 0x12300>; + nvmem-cells = <&ssip_config>; + nvmem-cell-names = "ssip_config"; + qcom,platform-supply-entries { #address-cells = <1>; #size-cells = <0>; From 672405ce89b79e671032c1bf3a8596af643efa87 Mon Sep 17 00:00:00 2001 From: Christina Oliveira Date: Tue, 30 Jan 2024 14:14:50 -0800 Subject: [PATCH 05/21] ARM: dts: msm: enable hw-fences in display driver for Sun Enable the use of hw-fences as the preferred synchronization primitives in the display driver for Sun target. Change-Id: I6f7d769f0a9002d27e68bac55095a3958587e47b Signed-off-by: Christina Oliveira --- bindings/sde.txt | 5 +++++ display/sun-sde.dtsi | 2 ++ 2 files changed, 7 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 6ceef390..48cba952 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -103,6 +103,10 @@ Optional properties: -- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off -- qcom,supply-post-off-sleep: time to sleep (ms) after turning off - qcom,sde-hw-version: A u32 value indicates the MDSS hw version +- qcom,hw-fence-sw-version: A u32 value to indicate the hw fencing version. If set to a value + greather than zero, driver will attempt to enable the feature (if + supported by the HW). Otherwise, if this value is not set or set + to zero, feature will remain disabled. - qcom,sde-sspp-src-size: A u32 value indicates the address range for each sspp. - qcom,sde-mixer-size: A u32 value indicates the address range for each mixer. - qcom,sde-ctl-size: A u32 value indicates the address range for each ctl. @@ -718,6 +722,7 @@ Example: #power-domain-cells = <0>; qcom,sde-hw-version = <0x70000000>; + qcom,hw-fence-sw-version = <0x1>; qcom,sde-emulated-env; qcom,sde-off = <0x1000>; qcom,sde-ctl-off = <0x00002000 0x00002200 0x00002400 diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 18c83c8e..8188c462 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -219,6 +219,8 @@ clock-rate = <0 0 575000000 575000000 19200000 575000000>; clock-max-rate = <0 0 575000000 575000000 19200000 575000000>; + qcom,hw-fence-sw-version = <0x1>; + vdd-supply = <&disp_cc_mdss_core_gdsc>; mmcx-supply = <&VDD_MMCX_LEVEL>; From 3d852df744721286bd59cc0b5d2e5d6bcbfee496 Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Thu, 1 Feb 2024 18:55:55 +0800 Subject: [PATCH 06/21] ARM: dts: msm: enable dfps on sun target This change enable dfps for video mode panel on sun target. Change-Id: I9ee3e2bd916b064550d2a0b64b67e6be0335610c Signed-off-by: Jinfeng Gu --- display/sun-sde-display-common.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index 54797f5e..a8bff957 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -375,6 +375,10 @@ &dsi_nt37801_amoled_video_cphy { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-supported-dfps-list = <120 110 100 90 80>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; @@ -414,6 +418,10 @@ &dsi_nt37801_amoled_video { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,dsi-supported-dfps-list = <120 110 100 90 80>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; From 8cc1a7778de16a5d92b167bb526cf676e3092817 Mon Sep 17 00:00:00 2001 From: Jayasri Sampath Kumaran Date: Wed, 31 Jan 2024 15:26:17 -0500 Subject: [PATCH 07/21] ARM: dts: msm: add supported platform variants for sun target Add Kiwi, v8 Power Grid, v8 Power Grid with Kiwi on RCM platform and 3.5mm on MTP platform for sun target. Add APQ SOC id and add more models for compatible property on Kiwi CDP and MTP platforms for sun target. Change-Id: I443e45414ba663cbb0672e686e9757e861379f5c Signed-off-by: Jayasri Sampath Kumaran --- Kbuild | 6 +++++- display/sun-sde-display-cdp-kiwi-overlay.dts | 6 +++--- display/sun-sde-display-mtp-3-5mm-overlay.dts | 16 ++++++++++++++++ display/sun-sde-display-mtp-kiwi-overlay.dts | 6 +++--- display/sun-sde-display-mtp-overlay.dts | 4 ++-- display/sun-sde-display-rcm-kiwi-overlay.dts | 16 ++++++++++++++++ display/sun-sde-display-rcm-kiwi-v8-overlay.dts | 16 ++++++++++++++++ display/sun-sde-display-rcm-v8-overlay.dts | 16 ++++++++++++++++ 8 files changed, 77 insertions(+), 9 deletions(-) create mode 100644 display/sun-sde-display-mtp-3-5mm-overlay.dts create mode 100644 display/sun-sde-display-rcm-kiwi-overlay.dts create mode 100644 display/sun-sde-display-rcm-kiwi-v8-overlay.dts create mode 100644 display/sun-sde-display-rcm-v8-overlay.dts diff --git a/Kbuild b/Kbuild index 3060fd20..56042b05 100644 --- a/Kbuild +++ b/Kbuild @@ -15,7 +15,11 @@ dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \ display/sun-sde-display-mtp-nfc-overlay.dtbo \ display/sun-sde-display-cdp-v8-overlay.dtbo \ display/sun-sde-display-mtp-v8-overlay.dtbo \ - display/sun-sde-display-atp-overlay.dtbo + display/sun-sde-display-atp-overlay.dtbo \ + display/sun-sde-display-mtp-3-5mm-overlay.dtbo \ + display/sun-sde-display-rcm-kiwi-overlay.dtbo \ + display/sun-sde-display-rcm-kiwi-v8-overlay.dtbo \ + display/sun-sde-display-rcm-v8-overlay.dtbo else dtbo-$(CONFIG_ARCH_SUN) += display/trustedvm-sun-sde-display-cdp-overlay.dtbo \ display/trustedvm-sun-sde-display-mtp-overlay.dtbo diff --git a/display/sun-sde-display-cdp-kiwi-overlay.dts b/display/sun-sde-display-cdp-kiwi-overlay.dts index acfc23ea..4ba523d6 100644 --- a/display/sun-sde-display-cdp-kiwi-overlay.dts +++ b/display/sun-sde-display-cdp-kiwi-overlay.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -10,7 +10,7 @@ / { model = "Qualcomm Technologies, Inc. Sun CDP Kiwi WLAN"; - compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp"; - qcom,msm-id = <618 0x10000>, <618 0x20000>; + compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp", "qcom,cdp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; qcom,board-id = <0x20001 0>; }; diff --git a/display/sun-sde-display-mtp-3-5mm-overlay.dts b/display/sun-sde-display-mtp-3-5mm-overlay.dts new file mode 100644 index 00000000..e7b19c30 --- /dev/null +++ b/display/sun-sde-display-mtp-3-5mm-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun MTP with 3.5mm"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x60008 0>; +}; diff --git a/display/sun-sde-display-mtp-kiwi-overlay.dts b/display/sun-sde-display-mtp-kiwi-overlay.dts index 6d755f25..7dd3d0f1 100644 --- a/display/sun-sde-display-mtp-kiwi-overlay.dts +++ b/display/sun-sde-display-mtp-kiwi-overlay.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -10,7 +10,7 @@ / { model = "Qualcomm Technologies, Inc. Sun MTP Kiwi WLAN"; - compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp"; - qcom,msm-id = <618 0x10000>, <618 0x20000>; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; qcom,board-id = <0x20008 0>; }; diff --git a/display/sun-sde-display-mtp-overlay.dts b/display/sun-sde-display-mtp-overlay.dts index 48ad6325..ba89d90c 100644 --- a/display/sun-sde-display-mtp-overlay.dts +++ b/display/sun-sde-display-mtp-overlay.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -10,7 +10,7 @@ / { model = "Qualcomm Technologies, Inc. Sun MTP"; - compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; qcom,board-id = <8 0>; }; diff --git a/display/sun-sde-display-rcm-kiwi-overlay.dts b/display/sun-sde-display-rcm-kiwi-overlay.dts new file mode 100644 index 00000000..21abbbbf --- /dev/null +++ b/display/sun-sde-display-rcm-kiwi-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun RCM Kiwi WLAN"; + compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm"; + qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,board-id = <0x40015 0>; +}; diff --git a/display/sun-sde-display-rcm-kiwi-v8-overlay.dts b/display/sun-sde-display-rcm-kiwi-v8-overlay.dts new file mode 100644 index 00000000..18bdb0e6 --- /dev/null +++ b/display/sun-sde-display-rcm-kiwi-v8-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun RCM Kiwi WLAN V8 Power Grid"; + compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm"; + qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,board-id = <0x20015 0>; +}; diff --git a/display/sun-sde-display-rcm-v8-overlay.dts b/display/sun-sde-display-rcm-v8-overlay.dts new file mode 100644 index 00000000..1c7308f2 --- /dev/null +++ b/display/sun-sde-display-rcm-v8-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun RCM V8 Power Grid"; + compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm"; + qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,board-id = <0x30015 0>; +}; From 4195a29a99c607be4bde16e70c58028e8266b8d5 Mon Sep 17 00:00:00 2001 From: Christina Oliveira Date: Thu, 8 Feb 2024 11:20:08 -0800 Subject: [PATCH 08/21] ARM: dts: msm: move soccp property for sun target This change moves the soccp phandle property needed for soccp power vote. Change-Id: I506c814517a2019a13450822f86d16e2c9a535e4 Signed-off-by: Christina Oliveira --- display/sun-sde-common.dtsi | 1 - display/sun-sde.dtsi | 2 ++ 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index 3300a722..0b2c0bb1 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -265,7 +265,6 @@ qcom,sde-ipcc-protocol-id = <0x4>; qcom,sde-ipcc-client-dpu-phys-id = <0x14>; - qcom,sde-soccp-controller = <&soccp_pas>; qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>; /* offsets are relative to "mdp_phys + qcom,sde-off */ diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 18c83c8e..b7ea2b0d 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -224,6 +224,8 @@ qti,smmu-proxy-cb-id = ; + qcom,sde-soccp-controller = <&soccp_pas>; + qcom,sde-vm-exclude-reg-names = "ipcc_reg"; /* data and reg bus scale settings */ From 33797c66a4c1382550d47480cb1d04fe7b5effe7 Mon Sep 17 00:00:00 2001 From: Christopher Braga Date: Thu, 1 Feb 2024 11:11:08 -0500 Subject: [PATCH 09/21] ARM: dts: msm: introduce disp cc memory region To support MDP LUT retention, programming of the disp cc memory region is required. Update the sun DTSI definition to define the minimal disp cc memory region needed for LUT retention functionality. Change-Id: I88eb0860a540e5f83ae86e5491f31aa19fbdac38 Signed-off-by: Christopher Braga --- display/sun-sde-common.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index 0b2c0bb1..6602d6d2 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -13,11 +13,13 @@ reg = <0x0ae00000 0x93800>, <0x0aeb0000 0x2008>, <0x0af80000 0x7000>, - <0x400000 0x2000>; + <0x400000 0x2000>, + <0x0af08000 0x24>; reg-names = "mdp_phys", "vbif_phys", "regdma_phys", - "ipcc_reg"; + "ipcc_reg", + "disp_cc"; /* interrupt config */ interrupts = ; From 10aa7ec653a368cbeb4ac94b7f7a7c93d9384745 Mon Sep 17 00:00:00 2001 From: Akash Gajjar Date: Wed, 14 Feb 2024 18:27:50 +0530 Subject: [PATCH 10/21] ARM: dts: msm: Add trustedvm device tree support for Sun MTP-V8 target Add the trusted VM devicetree nodes for Sun MTP-V8 target. Change-Id: I404667e153c7295b5868cac18c013dd084e18a1f Signed-off-by: Akash Gajjar --- display/trustedvm-sun-sde-display-mtp-overlay.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/trustedvm-sun-sde-display-mtp-overlay.dts b/display/trustedvm-sun-sde-display-mtp-overlay.dts index 438ebe59..0871ba20 100644 --- a/display/trustedvm-sun-sde-display-mtp-overlay.dts +++ b/display/trustedvm-sun-sde-display-mtp-overlay.dts @@ -13,5 +13,5 @@ model = "Qualcomm Technologies, Inc. Sun MTP - TrustedVM"; compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp"; qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; - qcom,board-id = <8 0>; + qcom,board-id = <8 0>, <0x40008 0>; }; From c64196b0d010b3f9fcca3feffd044c0a14f7ca54 Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Mon, 19 Feb 2024 21:08:43 -0800 Subject: [PATCH 11/21] ARM: dts: msm: modify cont-splash memory region on pakala target Modify the continuous splash memory region to match UEFI configured address. Add a gap in HLOS unsecure context-bank to avoid using the splash memory region. Change-Id: Ifa7927b8ecccd0542ef3f37cf781a97f594102b3 Signed-off-by: Veera Sundaram Sankaran --- display/sun-sde-display.dtsi | 4 ++-- display/sun-sde.dtsi | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index 072e04fe..4e8a2575 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -48,14 +48,14 @@ }; disp_rdump_memory: disp_rdump_region@0xd5500000 { - reg = <0xd5500000 0x00800000>; + reg = <0xfc800000 0x00800000>; label = "disp_rdump_region"; }; }; &reserved_memory { splash_memory: splash_region { - reg = <0x0 0xd5500000 0x0 0x02b00000>; + reg = <0x0 0xfc800000 0x0 0x02b00000>; label = "cont_splash_region"; }; }; diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index d5cdf800..61a0bb97 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -184,7 +184,7 @@ smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition { iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>, <&smmu_sde_unsec 0xd4e23000 0x002dd000>, - <&smmu_sde_unsec 0xd5500000 0x02b00000>, + <&smmu_sde_unsec 0xfc800000 0x02b00000>, <&smmu_sde_sec 0x0 0x00020000>; }; From 5521491e0241149e784565a76ce64dac7cc585b3 Mon Sep 17 00:00:00 2001 From: Yuchao Ma Date: Wed, 22 Nov 2023 18:46:08 +0800 Subject: [PATCH 12/21] ARM: dts: msm: updates demura version and size The change updates demura version and size. Change-Id: Ie3a71c6a04f38054d4a192c1b538fb53aa02e135 Signed-off-by: Yuchao Ma Signed-off-by: Alisha Thapaliya --- display/sun-sde-common.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index 0b2c0bb1..7e0b89cc 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -192,8 +192,8 @@ qcom,sde-dspp-spr-version = <0x00020000>; qcom,sde-dspp-demura-off = <0x15600 0x14600 0x13600 0x12600>; - qcom,sde-dspp-demura-size = <0xe4>; - qcom,sde-dspp-demura-version = <0x00020000>; + qcom,sde-dspp-demura-size = <0x150>; + qcom,sde-dspp-demura-version = <0x00030000>; qcom,sde-dspp-aiqe-off = <0x39000 0xffffffff 0x3a000 0xffffffff>; qcom,sde-dspp-aiqe-version = <0x00010000>; From bd64dc56a2ac2525d5e6c0cb42fe1ff694925094 Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Wed, 31 Jan 2024 20:58:49 +0800 Subject: [PATCH 13/21] ARM: dts: msm: add multiple timing nodes for nt37801 panel This change add multiple timing nodes for nt37801 on sun target. Change-Id: I36f3271c86a6765ca62bda60b23954d7d5efbf14 Signed-off-by: Jinfeng Gu --- ...-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi | 213 ++++++ .../dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi | 646 ++++++++++++++++++ display/sun-sde-display-common.dtsi | 56 ++ display/sun-sde-display.dtsi | 40 ++ 4 files changed, 955 insertions(+) diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi index 5612ec26..4e2eeca5 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi @@ -53,6 +53,17 @@ qcom,mdss-dsi-v-bottom-border = <0>; qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + qcom,mdss-dsi-on-command = [ 39 01 00 00 00 00 06 F0 55 AA 52 08 01 39 01 00 00 00 00 02 6F 01 @@ -110,6 +121,208 @@ qcom,mdss-dsc-bit-per-pixel = <8>; qcom,mdss-dsc-block-prediction-enable; }; + + timing@1 { + cell-index = <1>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <22>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 2f 01 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 24 45 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 D2 + 00 02 86 04 3A 00 0A 02 AB 01 E9 10 + F0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2F 00 + 39 01 00 00 00 00 02 2f 01 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 24 45 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + 39 01 00 00 00 00 05 FF AA 55 A5 82 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 03 F3 CC 0C + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2 { + cell-index = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <22>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <808730000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 01 01 00 01 + 01 01 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 D2 + 00 02 86 04 3A 00 0A 02 AB 01 E9 10 + F0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 01 01 00 01 + 01 01 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + 39 01 00 00 00 00 05 FF AA 55 A5 82 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 03 F3 CC 0C + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; }; }; }; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi index e417cdb2..105e1938 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi @@ -58,6 +58,14 @@ 39 01 00 00 00 00 05 2A 00 00 05 9F 39 01 00 00 00 00 05 2B 00 00 0C 7F 39 01 00 00 00 00 02 8F 00 + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 ]; qcom,mdss-dsi-on-command = [ @@ -137,6 +145,14 @@ 39 01 00 00 00 00 05 2A 00 00 04 37 39 01 00 00 00 00 05 2B 00 00 09 5F 39 01 00 00 00 00 02 8F 01 + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 ]; qcom,mdss-dsi-on-command = [ @@ -193,6 +209,636 @@ qcom,mdss-dsc-bit-per-pixel = <8>; qcom,mdss-dsc-block-prediction-enable; }; + + timing@2 { + cell-index = <2>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 05 2a 00 00 05 9f + 39 01 00 00 00 00 05 2b 00 00 0c 7f + 39 01 00 00 00 00 02 8f 00 + 39 01 00 00 00 00 02 2f 01 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 24 45 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 D2 + 00 02 86 04 3A 00 0A 02 AB 01 E9 10 + F0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2F 00 + 39 01 00 00 00 00 02 2f 01 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 24 45 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@3 { + cell-index = <3>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <1199900000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 05 2a 00 00 05 9f + 39 01 00 00 00 00 05 2b 00 00 0c 7f + 39 01 00 00 00 00 02 8f 00 + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 01 01 00 01 + 01 01 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 D2 + 00 02 86 04 3A 00 0A 02 AB 01 E9 10 + F0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 01 01 00 01 + 01 01 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@4 { + cell-index = <4>; + qcom,mdss-dsi-panel-framerate = <40>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <1199900000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 05 2a 00 00 05 9f + 39 01 00 00 00 00 05 2b 00 00 0c 7f + 39 01 00 00 00 00 02 8f 00 + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 02 02 00 01 + 02 02 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 D2 + 00 02 86 04 3A 00 0A 02 AB 01 E9 10 + F0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 02 02 00 01 + 02 02 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@5 { + cell-index = <5>; + qcom,mdss-dsi-panel-framerate = <30>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <1199900000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 05 2a 00 00 05 9f + 39 01 00 00 00 00 05 2b 00 00 0c 7f + 39 01 00 00 00 00 02 8f 00 + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 03 03 00 01 + 03 03 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 D2 + 00 02 86 04 3A 00 0A 02 AB 01 E9 10 + F0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 03 03 00 01 + 03 03 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@6 { + cell-index = <6>; + qcom,mdss-dsi-panel-framerate = <24>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <1199900000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 05 2a 00 00 05 9f + 39 01 00 00 00 00 05 2b 00 00 0c 7f + 39 01 00 00 00 00 02 8f 00 + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 04 04 00 01 + 04 04 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 D2 + 00 02 86 04 3A 00 0A 02 AB 01 E9 10 + F0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 04 04 00 01 + 04 04 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@7 { + cell-index = <7>; + qcom,mdss-dsi-panel-framerate = <20>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <1199900000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 05 2a 00 00 05 9f + 39 01 00 00 00 00 05 2b 00 00 0c 7f + 39 01 00 00 00 00 02 8f 00 + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 05 05 00 01 + 05 05 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 D2 + 00 02 86 04 3A 00 0A 02 AB 01 E9 10 + F0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 05 05 00 01 + 05 05 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; }; }; }; diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index a8bff957..f2ecb087 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -370,6 +370,48 @@ qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 1f 08 07 18 22 08 + 08 08 08 02 04 1a 0d]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@3 { + qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 1f 06 + 06 06 06 02 04 13 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@4 { + qcom,mdss-dsi-panel-phy-timings = [00 11 03 04 12 1e 04 + 04 04 03 02 04 0e 09]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@5 { + qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 10 1d 03 + 03 03 02 02 04 0c 08]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@6 { + qcom,mdss-dsi-panel-phy-timings = [00 0c 02 02 10 1c 03 + 03 03 02 02 04 0b 08]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@7 { + qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 0f 1c 02 + 02 02 02 02 04 0a 07]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; }; }; @@ -412,6 +454,20 @@ qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 20 1c 06 + 19 06 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 03 + 19 03 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; }; }; diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index 4e8a2575..13c6655e 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -162,6 +162,36 @@ qcom,partial-update-enabled = "single_roi"; qcom,panel-roi-alignment = <540 40 40 40 540 40>; }; + + timing@2 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 40 40 720 40>; + }; + + timing@3 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 40 40 720 40>; + }; + + timing@4 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 40 40 720 40>; + }; + + timing@5 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 40 40 720 40>; + }; + + timing@6 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 40 40 720 40>; + }; + + timing@7 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 40 40 720 40>; + }; }; }; @@ -171,6 +201,16 @@ qcom,partial-update-enabled = "single_roi"; qcom,panel-roi-alignment = <720 40 40 40 720 40>; }; + + timing@1 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 40 40 720 40>; + }; + + timing@2 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 40 40 720 40>; + }; }; }; From 8794f7fa807a4fbcf0629704ffb8891e7999e91e Mon Sep 17 00:00:00 2001 From: Jayasri Sampath Kumaran Date: Fri, 23 Feb 2024 15:26:47 -0500 Subject: [PATCH 14/21] ARM: dts: msm: add support for MTP QMP1000 variants for sun target Add QMP1000 with v6 and v8 power grid for MTP platforms for sun target. Change-Id: If9a6c99f15add5fa7d86bb821587dc971bd87619 Signed-off-by: Jayasri Sampath Kumaran --- Kbuild | 4 +++- display/sun-sde-display-mtp-qmp1000-overlay.dts | 16 ++++++++++++++++ .../sun-sde-display-mtp-qmp1000-v8-overlay.dts | 16 ++++++++++++++++ 3 files changed, 35 insertions(+), 1 deletion(-) create mode 100644 display/sun-sde-display-mtp-qmp1000-overlay.dts create mode 100644 display/sun-sde-display-mtp-qmp1000-v8-overlay.dts diff --git a/Kbuild b/Kbuild index 56a64758..1d451b47 100644 --- a/Kbuild +++ b/Kbuild @@ -19,7 +19,9 @@ dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \ display/sun-sde-display-mtp-3-5mm-overlay.dtbo \ display/sun-sde-display-rcm-kiwi-overlay.dtbo \ display/sun-sde-display-rcm-kiwi-v8-overlay.dtbo \ - display/sun-sde-display-rcm-v8-overlay.dtbo + display/sun-sde-display-rcm-v8-overlay.dtbo \ + display/sun-sde-display-mtp-qmp1000-overlay.dtbo \ + display/sun-sde-display-mtp-qmp1000-v8-overlay.dtbo else dtbo-$(CONFIG_ARCH_SUN) += display/trustedvm-sun-sde-display-cdp-overlay.dtbo \ display/trustedvm-sun-sde-display-mtp-overlay.dtbo \ diff --git a/display/sun-sde-display-mtp-qmp1000-overlay.dts b/display/sun-sde-display-mtp-qmp1000-overlay.dts new file mode 100644 index 00000000..00e92d1b --- /dev/null +++ b/display/sun-sde-display-mtp-qmp1000-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun MTP QMP1000"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x10108 0>; +}; diff --git a/display/sun-sde-display-mtp-qmp1000-v8-overlay.dts b/display/sun-sde-display-mtp-qmp1000-v8-overlay.dts new file mode 100644 index 00000000..ce16eb03 --- /dev/null +++ b/display/sun-sde-display-mtp-qmp1000-v8-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun MTP QMP1000 V8 Power Grid"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x40108 0>; +}; From c8fc77e24c0b4ec017c3a2394b29ee70468e20a4 Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Tue, 20 Feb 2024 18:58:57 +0800 Subject: [PATCH 15/21] ARM: dts: msm: add NT37801 10 bits video mode panel support This change add NT37801 10 bits video mode panel support. Change-Id: I7c82b55ed49d6e361278f8285a6ff4373febc3ed Signed-off-by: Jinfeng Gu --- .../dsi-panel-nt37801-dsc-10bit-video.dtsi | 118 ++++++++++++++++++ display/sun-sde-display-cdp.dtsi | 13 +- display/sun-sde-display-common.dtsi | 24 ++++ display/sun-sde-display-mtp.dtsi | 13 +- 4 files changed, 166 insertions(+), 2 deletions(-) create mode 100644 display/dsi-panel-nt37801-dsc-10bit-video.dtsi diff --git a/display/dsi-panel-nt37801-dsc-10bit-video.dtsi b/display/dsi-panel-nt37801-dsc-10bit-video.dtsi new file mode 100644 index 00000000..d7d968d6 --- /dev/null +++ b/display/dsi-panel-nt37801-dsc-10bit-video.dtsi @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_dsc_10b_video: qcom,mdss_dsi_nt37801_amoled_dsc_10b_vid { + qcom,mdss-dsi-panel-name = + "nt37801 amoled video mode dsi csot panel with DSC 10bit"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <30>; + qcom,mdss-dsi-border-color = <0>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <44>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 c2 81 + 39 01 00 00 00 00 06 f0 55 aa 52 08 03 + 39 01 00 00 00 00 02 c6 a2 + 39 01 00 00 00 00 06 f0 55 aa 52 08 05 + 39 01 00 00 00 00 02 6f 08 + 39 01 00 00 00 00 06 ec 10 00 00 00 ff + 39 01 00 00 00 00 02 17 01 + 39 01 00 00 00 00 05 3b 00 14 00 2c + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 02 c3 19 + 39 01 00 00 00 00 02 6f 01 + 39 01 00 00 00 00 04 c5 0b 0b 0b + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 02 f5 10 + 39 01 00 00 00 00 02 6f 1b + 39 01 00 00 00 00 02 f4 55 + 39 01 00 00 00 00 02 6f 18 + 39 01 00 00 00 00 02 f8 19 + 39 01 00 00 00 00 02 6f 0f + 39 01 00 00 00 00 02 fc 00 + 39 01 00 00 00 00 05 2a 00 00 05 9f + 39 01 00 00 00 00 05 2b 00 00 0c 7f + 39 01 00 00 00 00 02 90 03 + 39 01 00 00 00 00 13 91 ab 2a 00 28 f1 + 9a 02 68 03 92 00 0e 03 14 02 56 10 + ec + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 04 56 77 + 77 77 99 9b f0 00 02 78 9a bb bc dd + ee ff 00 + 39 01 00 00 00 00 02 f3 dc + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 ff 07 ff 0f + ff + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5f 00 + 39 01 00 00 00 00 02 9c 01 + 05 01 00 00 00 00 01 2c + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 b2 55 01 ff 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <10>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/sun-sde-display-cdp.dtsi b/display/sun-sde-display-cdp.dtsi index 7c979c54..2936b501 100644 --- a/display/sun-sde-display-cdp.dtsi +++ b/display/sun-sde-display-cdp.dtsi @@ -67,6 +67,16 @@ qcom,platform-sec-reset-gpio = <&tlmm 97 0>; }; +&dsi_nt37801_amoled_dsc_10b_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + &dsi_vtdr6130_amoled_120hz_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -175,7 +185,8 @@ panel = <&dsi_nt37801_amoled_cmd &dsi_nt37801_amoled_cmd_cphy &dsi_nt37801_amoled_video - &dsi_nt37801_amoled_video_cphy>; + &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_dsc_10b_video>; }; }; diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index f2ecb087..d905cd34 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -7,6 +7,7 @@ #include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi" #include "dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi" #include "dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi" +#include "dsi-panel-nt37801-dsc-10bit-video.dtsi" #include "dsi-panel-sharp-dsc-4k-cmd.dtsi" #include "dsi-panel-sharp-dsc-4k-video.dtsi" #include "dsi-panel-sim-cmd-au.dtsi" @@ -495,6 +496,29 @@ }; }; +&dsi_nt37801_amoled_dsc_10b_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-supported-dfps-list = <120 110 100 90 80>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 3e 0f 0f 22 1f 0f + 10 0e 02 04 00 30 14]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_sharp_4k_dsc_cmd { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; diff --git a/display/sun-sde-display-mtp.dtsi b/display/sun-sde-display-mtp.dtsi index b3ebded1..52cbb310 100644 --- a/display/sun-sde-display-mtp.dtsi +++ b/display/sun-sde-display-mtp.dtsi @@ -61,6 +61,16 @@ qcom,platform-reset-gpio = <&tlmm 98 0>; }; +&dsi_nt37801_amoled_dsc_10b_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + &dsi_vtdr6130_amoled_120hz_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -168,7 +178,8 @@ panel = <&dsi_nt37801_amoled_cmd &dsi_nt37801_amoled_cmd_cphy &dsi_nt37801_amoled_video - &dsi_nt37801_amoled_video_cphy>; + &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_dsc_10b_video>; }; }; From 33a37fea084f57bf61c98724dcd206df65b1da69 Mon Sep 17 00:00:00 2001 From: Kirill Shpin Date: Tue, 27 Feb 2024 17:06:43 -0800 Subject: [PATCH 16/21] ARM: dts: msm: add license/copyright to panels Adds missing license and copyright information to all panel files, which don't currently have them. Change-Id: I73b6b6da76a28a4d3e9f86924c8d2732b41f90de Signed-off-by: Kirill Shpin --- display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi | 5 +++++ display/dsi-panel-sharp-dsc-4k-cmd.dtsi | 5 +++++ display/dsi-panel-sharp-dsc-4k-video.dtsi | 5 +++++ display/dsi-panel-sim-cmd-au.dtsi | 5 +++++ display/dsi-panel-sim-cmd.dtsi | 5 +++++ display/dsi-panel-sim-dsc-10bit-cmd.dtsi | 5 +++++ display/dsi-panel-sim-dsc375-cmd.dtsi | 5 +++++ display/dsi-panel-sim-dualmipi-cmd.dtsi | 5 +++++ display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi | 5 +++++ display/dsi-panel-sim-dualmipi-video.dtsi | 5 +++++ display/dsi-panel-sim-sec-hd-cmd.dtsi | 5 +++++ display/dsi-panel-sim-video.dtsi | 5 +++++ display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi | 5 +++++ display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi | 5 +++++ display/dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi | 5 +++++ display/dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi | 5 +++++ display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi | 5 +++++ .../dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi | 5 +++++ 21 files changed, 105 insertions(+) diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi index 5612ec26..43b67ad0 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_nt37801_amoled_cmd_cphy: qcom,mdss_dsi_nt37801_wqhd_plus_cmd_cphy { qcom,mdss-dsi-panel-name = diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi index e417cdb2..a532daeb 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_nt37801_amoled_cmd: qcom,mdss_dsi_nt37801_wqhd_plus_cmd { qcom,mdss-dsi-panel-name = diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi index 53de247a..d9c48cd4 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_nt37801_amoled_video_cphy: qcom,mdss_dsi_nt37801_wqhd_plus_vid_cphy { qcom,mdss-dsi-panel-name = diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi index d4647340..8a36fe29 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_nt37801_amoled_video: qcom,mdss_dsi_nt37801_wqhd_plus_vid { qcom,mdss-dsi-panel-name = diff --git a/display/dsi-panel-sharp-dsc-4k-cmd.dtsi b/display/dsi-panel-sharp-dsc-4k-cmd.dtsi index 4231b746..e303a6d5 100644 --- a/display/dsi-panel-sharp-dsc-4k-cmd.dtsi +++ b/display/dsi-panel-sharp-dsc-4k-cmd.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_sharp_4k_dsc_cmd: qcom,mdss_dsi_sharp_4k_dsc_cmd { qcom,mdss-dsi-panel-name = "Sharp 4k cmd mode dsc dsi panel"; diff --git a/display/dsi-panel-sharp-dsc-4k-video.dtsi b/display/dsi-panel-sharp-dsc-4k-video.dtsi index a687b5ff..efe59f9b 100644 --- a/display/dsi-panel-sharp-dsc-4k-video.dtsi +++ b/display/dsi-panel-sharp-dsc-4k-video.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_sharp_4k_dsc_video: qcom,mdss_dsi_sharp_4k_dsc_video { qcom,mdss-dsi-panel-name = "Sharp 4k video mode dsc dsi panel"; diff --git a/display/dsi-panel-sim-cmd-au.dtsi b/display/dsi-panel-sim-cmd-au.dtsi index 3815307f..fcb8df52 100644 --- a/display/dsi-panel-sim-cmd-au.dtsi +++ b/display/dsi-panel-sim-cmd-au.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_sim_panel_au: qcom,mdss_dsi_cmd_sim_panel_au { qcom,mdss-dsi-panel-name = "cmd mode dsi sim panel au"; diff --git a/display/dsi-panel-sim-cmd.dtsi b/display/dsi-panel-sim-cmd.dtsi index c10c3bce..813fe166 100644 --- a/display/dsi-panel-sim-cmd.dtsi +++ b/display/dsi-panel-sim-cmd.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_sim_cmd: qcom,mdss_dsi_sim_cmd { qcom,mdss-dsi-panel-name = "Simulator cmd mode dsi panel"; diff --git a/display/dsi-panel-sim-dsc-10bit-cmd.dtsi b/display/dsi-panel-sim-dsc-10bit-cmd.dtsi index 6c624c30..8e5cba14 100644 --- a/display/dsi-panel-sim-dsc-10bit-cmd.dtsi +++ b/display/dsi-panel-sim-dsc-10bit-cmd.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_sim_dsc_10b_cmd: qcom,mdss_dsi_sim_dsc_10b_cmd { qcom,mdss-dsi-panel-name = diff --git a/display/dsi-panel-sim-dsc375-cmd.dtsi b/display/dsi-panel-sim-dsc375-cmd.dtsi index 0211f659..bed6ed91 100644 --- a/display/dsi-panel-sim-dsc375-cmd.dtsi +++ b/display/dsi-panel-sim-dsc375-cmd.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_sim_dsc_375_cmd: qcom,mdss_dsi_sim_dsc_375_cmd { qcom,mdss-dsi-panel-name = diff --git a/display/dsi-panel-sim-dualmipi-cmd.dtsi b/display/dsi-panel-sim-dualmipi-cmd.dtsi index b16c48d5..275c0960 100644 --- a/display/dsi-panel-sim-dualmipi-cmd.dtsi +++ b/display/dsi-panel-sim-dualmipi-cmd.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_dual_sim_cmd: qcom,mdss_dsi_dual_sim_cmd { qcom,mdss-dsi-panel-name = "Sim dual cmd mode dsi panel"; diff --git a/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi b/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi index e59bfb05..28f2c96f 100644 --- a/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi +++ b/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_dual_sim_dsc_375_cmd: qcom,mdss_dsi_dual_sim_dsc_375_cmd { qcom,mdss-dsi-panel-name = diff --git a/display/dsi-panel-sim-dualmipi-video.dtsi b/display/dsi-panel-sim-dualmipi-video.dtsi index 537a0181..e977a78b 100644 --- a/display/dsi-panel-sim-dualmipi-video.dtsi +++ b/display/dsi-panel-sim-dualmipi-video.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_dual_sim_vid: qcom,mdss_dsi_dual_sim_video { qcom,mdss-dsi-panel-name = "Sim dual video mode dsi panel"; diff --git a/display/dsi-panel-sim-sec-hd-cmd.dtsi b/display/dsi-panel-sim-sec-hd-cmd.dtsi index dd948313..3172af60 100644 --- a/display/dsi-panel-sim-sec-hd-cmd.dtsi +++ b/display/dsi-panel-sim-sec-hd-cmd.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_sim_sec_hd_cmd: qcom,mdss_dsi_sim_sec_hd_cmd { qcom,mdss-dsi-panel-name = diff --git a/display/dsi-panel-sim-video.dtsi b/display/dsi-panel-sim-video.dtsi index 78d18c82..02fd6ca9 100644 --- a/display/dsi-panel-sim-video.dtsi +++ b/display/dsi-panel-sim-video.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_sim_vid: qcom,mdss_dsi_sim_video { qcom,mdss-dsi-panel-name = "Simulator video mode dsi panel"; diff --git a/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi b/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi index 4096eb88..30dfc315 100644 --- a/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi +++ b/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_vtdr6130_amoled_120hz_cmd: qcom,mdss_dsi_vtdr6130_fhd_plus_120hz_cmd { qcom,mdss-dsi-panel-name = diff --git a/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi b/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi index 6f0e924b..bd6bbec8 100644 --- a/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi +++ b/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_vtdr6130_amoled_120hz_video: qcom,mdss_dsi_vtdr6130_fhd_plus_120hz_vid { qcom,mdss-dsi-panel-name = diff --git a/display/dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi b/display/dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi index 4fcb45d3..45850567 100644 --- a/display/dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi +++ b/display/dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_vtdr6130_amoled_cmd: qcom,mdss_dsi_vtdr6130_fhd_plus_cmd { qcom,mdss-dsi-panel-name = diff --git a/display/dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi b/display/dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi index df28a81f..4c4886f9 100644 --- a/display/dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi +++ b/display/dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_vtdr6130_amoled_video: qcom,mdss_dsi_vtdr6130_fhd_plus_vid { qcom,mdss-dsi-panel-name = diff --git a/display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi b/display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi index c14db0a0..5143cf11 100644 --- a/display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi +++ b/display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_vtdr6130_amoled_qsync_144hz_cmd: qcom,mdss_dsi_vtdr6130_qsync_fhd_plus_144hz_cmd { qcom,mdss-dsi-panel-name = diff --git a/display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi b/display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi index 6948326c..baa8e311 100644 --- a/display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi +++ b/display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_vtdr6130_amoled_qsync_144hz_video: qcom,mdss_dsi_vtdr6130_qsync_fhd_plus_144hz_video { qcom,mdss-dsi-panel-name = From 10a1d04ea4bbef0d45fc21e644dbaa5eb4746e13 Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Thu, 22 Feb 2024 17:58:49 +0800 Subject: [PATCH 17/21] ARM: dts: msm: update partial update roi for csot panel This change updates the partial update roi for csot cmd mode panel. Change-Id: Iafdbe00243a5a2f3162e2dbfc2a79143ab4a29ff Signed-off-by: Jinfeng Gu --- display/sun-sde-display.dtsi | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index 13c6655e..f58720d7 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -155,42 +155,42 @@ qcom,mdss-dsi-display-timings { timing@0 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 40 40 40 720 40>; + qcom,panel-roi-alignment = <0 0 720 40 1440 40>; }; timing@1 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <540 40 40 40 540 40>; + qcom,panel-roi-alignment = <0 0 540 40 1080 40>; }; timing@2 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 40 40 40 720 40>; + qcom,panel-roi-alignment = <0 0 720 40 1440 40>; }; timing@3 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 40 40 40 720 40>; + qcom,panel-roi-alignment = <0 0 720 40 1440 40>; }; timing@4 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 40 40 40 720 40>; + qcom,panel-roi-alignment = <0 0 720 40 1440 40>; }; timing@5 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 40 40 40 720 40>; + qcom,panel-roi-alignment = <0 0 720 40 1440 40>; }; timing@6 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 40 40 40 720 40>; + qcom,panel-roi-alignment = <0 0 720 40 1440 40>; }; timing@7 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 40 40 40 720 40>; + qcom,panel-roi-alignment = <0 0 720 40 1440 40>; }; }; }; @@ -199,17 +199,17 @@ qcom,mdss-dsi-display-timings { timing@0 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 40 40 40 720 40>; + qcom,panel-roi-alignment = <0 0 720 40 1440 40>; }; timing@1 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 40 40 40 720 40>; + qcom,panel-roi-alignment = <0 0 720 40 1440 40>; }; timing@2 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 40 40 40 720 40>; + qcom,panel-roi-alignment = <0 0 720 40 1440 40>; }; }; }; From 310142dab60ba20d60c7d76aa8e081cdfad0daf2 Mon Sep 17 00:00:00 2001 From: Kirill Shpin Date: Tue, 27 Feb 2024 14:56:58 -0800 Subject: [PATCH 18/21] ARM: dts: msm: add CSOT with SPR config Adds new variant of the CSOT command mode panel with SPR enabled on AP side, as opposed to DDIC side. Change-Id: I94cfc2150e7b714822349a5ff9392351e2e22356 Signed-off-by: Kirill Shpin --- ...i-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi | 132 ++++++++++++++++++ display/sun-sde-display-cdp.dtsi | 21 ++- display/sun-sde-display-common.dtsi | 21 +++ display/sun-sde-display-mtp.dtsi | 16 ++- display/trustedvm-sun-sde-display-cdp.dtsi | 9 ++ display/trustedvm-sun-sde-display-mtp.dtsi | 9 ++ 6 files changed, 203 insertions(+), 5 deletions(-) create mode 100644 display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi new file mode 100644 index 00000000..76401ecf --- /dev/null +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_cmd_spr: qcom,mdss_dsi_nt37801_wqhd_plus_cmd_spr { + qcom,mdss-dsi-panel-name = + "nt37801 amoled cmd mode dsi csot panel with DSC and AP SPR"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsc-version = <0x12>; + qcom,src-chroma-format = <1>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 A0 F0 00 32 D1 + 00 01 E2 01 9B 00 3C 02 20 08 A4 11 + 50 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2F 00 + + 39 01 00 00 00 00 06 F0 55 AA 52 08 03 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 02 DE 00 + 39 01 00 00 00 00 02 6F 09 + 39 01 00 00 00 00 07 DE 10 34 25 30 14 25 + 39 01 00 00 00 00 05 FF AA 55 A5 81 + 39 01 00 00 00 00 02 6F 1D + 39 01 00 00 00 00 02 FB 6F + + 39 01 00 00 00 00 06 F0 55 AA 52 08 07 + 39 01 00 00 00 00 02 B0 24 + 39 01 00 00 00 00 02 03 10 + + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/sun-sde-display-cdp.dtsi b/display/sun-sde-display-cdp.dtsi index 2936b501..548ccf02 100644 --- a/display/sun-sde-display-cdp.dtsi +++ b/display/sun-sde-display-cdp.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "sun-sde-display.dtsi" @@ -77,6 +77,19 @@ qcom,platform-reset-gpio = <&tlmm 98 0>; }; +&dsi_nt37801_amoled_cmd_spr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + &dsi_vtdr6130_amoled_120hz_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -185,8 +198,9 @@ panel = <&dsi_nt37801_amoled_cmd &dsi_nt37801_amoled_cmd_cphy &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_dsc_10b_video &dsi_nt37801_amoled_video_cphy - &dsi_nt37801_amoled_dsc_10b_video>; + &dsi_nt37801_amoled_cmd_spr>; }; }; @@ -196,6 +210,7 @@ panel = <&dsi_nt37801_amoled_cmd &dsi_nt37801_amoled_cmd_cphy &dsi_nt37801_amoled_video - &dsi_nt37801_amoled_video_cphy>; + &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_cmd_spr>; }; }; diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index d905cd34..14929b06 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -8,6 +8,7 @@ #include "dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi" #include "dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi" #include "dsi-panel-nt37801-dsc-10bit-video.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi" #include "dsi-panel-sharp-dsc-4k-cmd.dtsi" #include "dsi-panel-sharp-dsc-4k-video.dtsi" #include "dsi-panel-sim-cmd-au.dtsi" @@ -519,6 +520,26 @@ }; }; +&dsi_nt37801_amoled_cmd_spr { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_sharp_4k_dsc_cmd { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; diff --git a/display/sun-sde-display-mtp.dtsi b/display/sun-sde-display-mtp.dtsi index 52cbb310..ea129f5c 100644 --- a/display/sun-sde-display-mtp.dtsi +++ b/display/sun-sde-display-mtp.dtsi @@ -71,6 +71,16 @@ qcom,platform-reset-gpio = <&tlmm 98 0>; }; +&dsi_nt37801_amoled_cmd_spr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + &dsi_vtdr6130_amoled_120hz_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -179,7 +189,8 @@ &dsi_nt37801_amoled_cmd_cphy &dsi_nt37801_amoled_video &dsi_nt37801_amoled_video_cphy - &dsi_nt37801_amoled_dsc_10b_video>; + &dsi_nt37801_amoled_dsc_10b_video + &dsi_nt37801_amoled_cmd_spr>; }; }; @@ -187,5 +198,6 @@ qcom,display-panels = <&dsi_nt37801_amoled_cmd &dsi_nt37801_amoled_cmd_cphy &dsi_nt37801_amoled_video - &dsi_nt37801_amoled_video_cphy>; + &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_cmd_spr>; }; diff --git a/display/trustedvm-sun-sde-display-cdp.dtsi b/display/trustedvm-sun-sde-display-cdp.dtsi index 26a92cf5..4f7bd4ec 100644 --- a/display/trustedvm-sun-sde-display-cdp.dtsi +++ b/display/trustedvm-sun-sde-display-cdp.dtsi @@ -54,6 +54,15 @@ qcom,platform-reset-gpio = <&tlmm 98 0>; }; +&dsi_nt37801_amoled_cmd_spr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + &dsi_vtdr6130_amoled_120hz_video { qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <10>; diff --git a/display/trustedvm-sun-sde-display-mtp.dtsi b/display/trustedvm-sun-sde-display-mtp.dtsi index 8094ced6..61c97670 100644 --- a/display/trustedvm-sun-sde-display-mtp.dtsi +++ b/display/trustedvm-sun-sde-display-mtp.dtsi @@ -23,6 +23,15 @@ qcom,platform-reset-gpio = <&tlmm 98 0>; }; +&dsi_nt37801_amoled_cmd_spr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + &dsi_sim_panel_au { qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <10>; From 3c8a246c1f0c9381e9766e50e4f3f9a2c8585f9e Mon Sep 17 00:00:00 2001 From: Kirill Shpin Date: Fri, 1 Mar 2024 14:31:06 -0800 Subject: [PATCH 19/21] ARM: dts: msm: remove long regulator sleep Lowers the TVDD regulator's post on sleep duration from 2000ms. Change-Id: I4a0aed93eb56aab93f5b4f792c79ede1ac1fd4fc Signed-off-by: Kirill Shpin --- display/sun-sde-display-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index 14929b06..37faa1f5 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -86,7 +86,7 @@ qcom,supply-max-voltage = <1800000>; qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; - qcom,supply-post-on-sleep = <2000>; + qcom,supply-post-on-sleep = <20>; }; }; From 39f6c30dc49c057ebedbeb0bbf18ce1e26b15c3b Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Fri, 1 Mar 2024 17:30:43 +0800 Subject: [PATCH 20/21] ARM: dts: msm: add NT37801 10 bits cmd mode panel support This change add NT37801 10 bits cmd mode panel support. Change-Id: I0e5472ea28b0e7e1725194d8b23e67b6c79509b5 Signed-off-by: Jinfeng Gu --- display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi | 121 +++++++++++++++++++ display/sun-sde-display-cdp.dtsi | 11 ++ display/sun-sde-display-common.dtsi | 21 ++++ display/sun-sde-display-mtp.dtsi | 11 ++ 4 files changed, 164 insertions(+) create mode 100644 display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi diff --git a/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi b/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi new file mode 100644 index 00000000..499ea14e --- /dev/null +++ b/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_dsc_10b_cmd: qcom,mdss_dsi_nt37801_amoled_dsc_10b_cmd { + qcom,mdss-dsi-panel-name = + "nt37801 amoled cmd mode dsi csot panel with DSC 10bit"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <30>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <44>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 02 c3 19 + 39 01 00 00 00 00 02 6f 01 + 39 01 00 00 00 00 04 c5 0b 0b 0b + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 02 f5 10 + 39 01 00 00 00 00 02 6f 1b + 39 01 00 00 00 00 02 f4 55 + 39 01 00 00 00 00 02 6f 18 + 39 01 00 00 00 00 02 f8 19 + 39 01 00 00 00 00 02 6f 0f + 39 01 00 00 00 00 02 fc 00 + 39 01 00 00 00 00 05 2a 00 00 05 9f + 39 01 00 00 00 00 05 2b 00 00 0c 7f + 39 01 00 00 00 00 02 90 03 + 39 01 00 00 00 00 13 91 ab 28 00 28 f2 + 00 02 c2 03 e1 00 0a 03 14 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 03 04 55 77 + 77 77 99 9b 10 00 1e 48 9a bb bc de + f0 11 30 + 39 01 00 00 00 00 02 f3 dc + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3b 00 14 00 2c + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 ff 07 ff 0f + ff + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 5f 00 + 39 01 00 00 00 00 02 9c 01 + 05 01 00 00 00 00 01 2c + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 b2 55 01 ff 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/sun-sde-display-cdp.dtsi b/display/sun-sde-display-cdp.dtsi index 548ccf02..98d492ee 100644 --- a/display/sun-sde-display-cdp.dtsi +++ b/display/sun-sde-display-cdp.dtsi @@ -67,6 +67,16 @@ qcom,platform-sec-reset-gpio = <&tlmm 97 0>; }; +&dsi_nt37801_amoled_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + &dsi_nt37801_amoled_dsc_10b_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -198,6 +208,7 @@ panel = <&dsi_nt37801_amoled_cmd &dsi_nt37801_amoled_cmd_cphy &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_dsc_10b_cmd &dsi_nt37801_amoled_dsc_10b_video &dsi_nt37801_amoled_video_cphy &dsi_nt37801_amoled_cmd_spr>; diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index 14929b06..d7cfcb99 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -7,6 +7,7 @@ #include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi" #include "dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi" #include "dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi" +#include "dsi-panel-nt37801-dsc-10bit-cmd.dtsi" #include "dsi-panel-nt37801-dsc-10bit-video.dtsi" #include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi" #include "dsi-panel-sharp-dsc-4k-cmd.dtsi" @@ -497,6 +498,26 @@ }; }; +&dsi_nt37801_amoled_dsc_10b_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 35 0d 0d 1f 1c 0d + 0e 0e 0c 02 04 2a 12]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_nt37801_amoled_dsc_10b_video { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-supported-dfps-list = <120 110 100 90 80>; diff --git a/display/sun-sde-display-mtp.dtsi b/display/sun-sde-display-mtp.dtsi index ea129f5c..a3792376 100644 --- a/display/sun-sde-display-mtp.dtsi +++ b/display/sun-sde-display-mtp.dtsi @@ -61,6 +61,16 @@ qcom,platform-reset-gpio = <&tlmm 98 0>; }; +&dsi_nt37801_amoled_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + &dsi_nt37801_amoled_dsc_10b_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -189,6 +199,7 @@ &dsi_nt37801_amoled_cmd_cphy &dsi_nt37801_amoled_video &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_dsc_10b_cmd &dsi_nt37801_amoled_dsc_10b_video &dsi_nt37801_amoled_cmd_spr>; }; From 344e1a69e9054ee9ca3d4d2b77d78e959640afea Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Wed, 6 Mar 2024 12:00:04 +0800 Subject: [PATCH 21/21] ARM: dts: msm: enable qsync for csot panel on sun target This change enable qsync for csot panel on sun target. Change-Id: I50068d98a263f28bc68a300b445125ce5ee73dff Signed-off-by: Jinfeng Gu --- ...-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi | 138 ++++++++++++++++++ ...panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi | 137 +++++++++++++++++ ...t37801-qsync-dsc-wqhd-plus-video-cphy.dtsi | 120 +++++++++++++++ ...nel-nt37801-qsync-dsc-wqhd-plus-video.dtsi | 119 +++++++++++++++ display/sun-sde-display-cdp.dtsi | 30 +++- display/sun-sde-display-common.dtsi | 82 +++++++++++ display/sun-sde-display-mtp.dtsi | 24 ++- display/sun-sde-display-qrd.dtsi | 24 ++- 8 files changed, 671 insertions(+), 3 deletions(-) create mode 100644 display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi create mode 100644 display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi create mode 100644 display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi create mode 100644 display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi new file mode 100644 index 00000000..be7213c7 --- /dev/null +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_qsync_cmd_cphy: qcom,mdss_dsi_nt37801_qsync_wqhd_plus_cmd_cphy { + qcom,mdss-dsi-panel-name = + "nt37801 amoled qsync cmd mode dsi csot panel with DSC CPHY"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-cphy-mode; + qcom,spr-pack-type = "pentile"; + qcom,qsync-enable; + qcom,mdss-dsi-qsync-min-refresh-rate = <60>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <22>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 D2 + 00 02 86 04 3A 00 0A 02 AB 01 E9 10 + F0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2F 00 + 39 01 00 00 00 00 05 FF AA 55 A5 82 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 03 F3 CC 0C + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = [ + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1f + 39 01 00 00 00 00 02 c0 50 + 39 01 00 00 00 00 02 6f 22 + 39 01 00 00 00 00 03 c0 0C bf + 39 01 00 00 00 00 02 6f 13 + 39 01 00 00 00 00 03 c0 00 cc + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 03 44 00 00 + 39 01 00 00 00 00 02 2f 10 + ]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = [ + 39 01 00 00 00 00 02 2f 00 + ]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi new file mode 100644 index 00000000..acc300b4 --- /dev/null +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_qsync_cmd: qcom,mdss_dsi_nt37801_qsync_wqhd_plus_cmd { + qcom,mdss-dsi-panel-name = + "nt37801 amoled qsync cmd mode dsi csot panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,spr-pack-type = "pentile"; + qcom,qsync-enable; + qcom,mdss-dsi-qsync-min-refresh-rate = <60>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 D2 + 00 02 86 04 3A 00 0A 02 AB 01 E9 10 + F0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2F 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = [ + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1f + 39 01 00 00 00 00 02 c0 50 + 39 01 00 00 00 00 02 6f 22 + 39 01 00 00 00 00 03 c0 0C bf + 39 01 00 00 00 00 02 6f 13 + 39 01 00 00 00 00 03 c0 00 cc + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 03 44 00 00 + 39 01 00 00 00 00 02 2f 10 + ]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = [ + 39 01 00 00 00 00 02 2f 00 + ]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi new file mode 100644 index 00000000..7f33dd6f --- /dev/null +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_qsync_video_cphy: qcom,mdss_dsi_nt37801_qsync_wqhd_plus_vid_cphy { + qcom,mdss-dsi-panel-name = + "nt37801 amoled qsync video mode dsi csot panel with DSC CPHY"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,panel-cphy-mode; + qcom,spr-pack-type = "pentile"; + + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,qsync-enable; + qcom,mdss-dsi-qsync-min-refresh-rate = <80>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <44>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 00 + 39 01 00 00 00 00 02 C2 81 + 39 01 00 00 00 00 06 F0 55 AA 52 08 03 + 39 01 00 00 00 00 02 C6 A2 + 39 01 00 00 00 00 06 F0 55 AA 52 08 05 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 06 EC 10 00 00 00 FF + 39 01 00 00 00 00 02 17 01 + 39 01 00 00 00 00 05 3B 00 14 00 2C + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 C3 19 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 D2 + 00 02 86 04 3A 00 0A 02 AB 01 E9 10 + F0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 05 FF AA 55 A5 82 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 03 F3 CC 0C + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi new file mode 100644 index 00000000..7c3eadd2 --- /dev/null +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_qsync_video: qcom,mdss_dsi_nt37801_qsync_wqhd_plus_vid { + qcom,mdss-dsi-panel-name = + "nt37801 amoled qsync video mode dsi csot panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,spr-pack-type = "pentile"; + qcom,qsync-enable; + qcom,mdss-dsi-qsync-min-refresh-rate = <80>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <44>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 00 + 39 01 00 00 00 00 02 C2 81 + 39 01 00 00 00 00 06 F0 55 AA 52 08 03 + 39 01 00 00 00 00 02 C6 A2 + 39 01 00 00 00 00 06 F0 55 AA 52 08 05 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 06 EC 10 00 00 00 FF + 39 01 00 00 00 00 02 17 01 + 39 01 00 00 00 00 05 3B 00 14 00 2C + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 C3 19 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 D2 + 00 02 86 04 3A 00 0A 02 AB 01 E9 10 + F0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/sun-sde-display-cdp.dtsi b/display/sun-sde-display-cdp.dtsi index 548ccf02..dd2dac2e 100644 --- a/display/sun-sde-display-cdp.dtsi +++ b/display/sun-sde-display-cdp.dtsi @@ -90,6 +90,32 @@ qcom,platform-sec-reset-gpio = <&tlmm 97 0>; }; +&dsi_nt37801_amoled_qsync_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_nt37801_amoled_qsync_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + &dsi_vtdr6130_amoled_120hz_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -200,7 +226,9 @@ &dsi_nt37801_amoled_video &dsi_nt37801_amoled_dsc_10b_video &dsi_nt37801_amoled_video_cphy - &dsi_nt37801_amoled_cmd_spr>; + &dsi_nt37801_amoled_cmd_spr + &dsi_nt37801_amoled_qsync_cmd + &dsi_nt37801_amoled_qsync_video>; }; }; diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index 37faa1f5..c9bf3e20 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -9,6 +9,10 @@ #include "dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi" #include "dsi-panel-nt37801-dsc-10bit-video.dtsi" #include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi" +#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi" +#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi" +#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi" +#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi" #include "dsi-panel-sharp-dsc-4k-cmd.dtsi" #include "dsi-panel-sharp-dsc-4k-video.dtsi" #include "dsi-panel-sim-cmd-au.dtsi" @@ -540,6 +544,84 @@ }; }; +&dsi_nt37801_amoled_qsync_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_qsync_cmd_cphy { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 23 22 08 + 19 08 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_qsync_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_qsync_video_cphy { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 25 25 08 + 19 09 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_sharp_4k_dsc_cmd { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; diff --git a/display/sun-sde-display-mtp.dtsi b/display/sun-sde-display-mtp.dtsi index ea129f5c..a5777c6a 100644 --- a/display/sun-sde-display-mtp.dtsi +++ b/display/sun-sde-display-mtp.dtsi @@ -81,6 +81,26 @@ qcom,platform-reset-gpio = <&tlmm 98 0>; }; +&dsi_nt37801_amoled_qsync_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_qsync_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + &dsi_vtdr6130_amoled_120hz_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -190,7 +210,9 @@ &dsi_nt37801_amoled_video &dsi_nt37801_amoled_video_cphy &dsi_nt37801_amoled_dsc_10b_video - &dsi_nt37801_amoled_cmd_spr>; + &dsi_nt37801_amoled_cmd_spr + &dsi_nt37801_amoled_qsync_cmd + &dsi_nt37801_amoled_qsync_video>; }; }; diff --git a/display/sun-sde-display-qrd.dtsi b/display/sun-sde-display-qrd.dtsi index 38786570..a7ae76f7 100644 --- a/display/sun-sde-display-qrd.dtsi +++ b/display/sun-sde-display-qrd.dtsi @@ -81,6 +81,26 @@ qcom,platform-reset-gpio = <&tlmm 98 0>; }; +&dsi_nt37801_amoled_qsync_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_qsync_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + &dsi_vtdr6130_amoled_120hz_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -188,7 +208,9 @@ panel = <&dsi_nt37801_amoled_cmd_cphy &dsi_nt37801_amoled_video_cphy &dsi_nt37801_amoled_cmd - &dsi_nt37801_amoled_video>; + &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_qsync_cmd_cphy + &dsi_nt37801_amoled_qsync_video_cphy>; }; };