From 980d714a763ff3da28ff7d6052727a0f746edee2 Mon Sep 17 00:00:00 2001 From: Kaushal Sanadhya Date: Thu, 9 Jan 2025 13:30:44 +0530 Subject: [PATCH 1/3] ARM: dts: msm: Add the nvmem cells for gaming fuse on kera gpu Define the nvmem cells for gaming fuse support on kera gpu. Change-Id: I3e316771845e01f1bba42040084be1f735099298 Signed-off-by: Kaushal Sanadhya --- gpu/kera-gpu.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/gpu/kera-gpu.dtsi b/gpu/kera-gpu.dtsi index 22834a3f..fadae3a6 100644 --- a/gpu/kera-gpu.dtsi +++ b/gpu/kera-gpu.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024)) @@ -64,6 +64,9 @@ , /* TURBO index=9 */ ; /* TURBO_L1 index=10 */ + nvmem-cells = <&gpu_gaming_bin>; + nvmem-cell-names = "gaming_bin"; + zap-shader { memory-region = <&gpu_microcode_mem>; }; From a1c6877f852e1d35eda0d94f774a8b7ee7955ded Mon Sep 17 00:00:00 2001 From: Kaushal Sanadhya Date: Fri, 17 Jan 2025 19:41:40 +0530 Subject: [PATCH 2/3] ARM: dts: msm: Add freq limiter interrupt and reset support for Kera Add frequency limiter interrupt and reset support for GPU_CC_FREQUENCY_LIMITER_IRQ_CLEAR for Kera gpu. Change-Id: I6145a638b9a0435dfcacbaf60859e1adbe1ee2dc Signed-off-by: Kaushal Sanadhya --- gpu/kera-gpu.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/gpu/kera-gpu.dtsi b/gpu/kera-gpu.dtsi index fadae3a6..24fea604 100644 --- a/gpu/kera-gpu.dtsi +++ b/gpu/kera-gpu.dtsi @@ -15,8 +15,11 @@ reg-names = "kgsl_3d0_reg_memory", "rscc", "cx_dbgc", "cx_misc", "qdss_etr", "qdss_gfx", "qdss_tmc"; - interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "kgsl_3d0_irq"; + interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>, <0 286 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq", "freq_limiter_irq"; + + resets = <&gpucc GPU_CC_FREQUENCY_LIMITER_IRQ_CLEAR>; + reset-names = "freq_limiter_irq_clear"; clocks = <&gcc GCC_GPU_GEMNOC_GFX_CLK>, <&gpucc GPU_CC_AHB_CLK>, <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, <&aoss_qmp>; From 31cd596f9b7ad0fff38e23eed539648b7b55afa8 Mon Sep 17 00:00:00 2001 From: SIVA MULLATI Date: Wed, 4 Dec 2024 17:57:10 +0530 Subject: [PATCH 3/3] ARM: dts: msm: Update Tuna GPU frequency plan Update frequency plan as per the latest recommendation. Change-Id: I5c904b148f149f094dea735ba0a975862538dad6 Signed-off-by: SIVA MULLATI --- gpu/tuna-gpu-pwrlevels.dtsi | 163 ++++++++++++++++++++++++++++-------- 1 file changed, 127 insertions(+), 36 deletions(-) diff --git a/gpu/tuna-gpu-pwrlevels.dtsi b/gpu/tuna-gpu-pwrlevels.dtsi index 5d8edc86..9839dafb 100644 --- a/gpu/tuna-gpu-pwrlevels.dtsi +++ b/gpu/tuna-gpu-pwrlevels.dtsi @@ -3,6 +3,18 @@ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +/* ACD Control register values */ +#define ACD_LEVEL_TURBO_L2 0xa02f5ffd +#define ACD_LEVEL_TURBO_L1 0xa8285ffd +#define ACD_LEVEL_TURBO 0x88295ffd +#define ACD_LEVEL_NOM_L1 0xa8295ffd +#define ACD_LEVEL_NOM 0x882a5ffd +#define ACD_LEVEL_SVS_L2 0x882a5ffd +#define ACD_LEVEL_SVS_L1 0xa82a5ffd +#define ACD_LEVEL_SVS 0xa82c5ffd +#define ACD_LEVEL_LOW_SVS 0xc02c5ffd +#define ACD_LEVEL_LOW_SVS_D1 0xc02c5ffd + &msm_gpu { /* Power levels */ qcom,gpu-pwrlevel-bins { @@ -19,106 +31,137 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <8>; + qcom,initial-pwrlevel = <9>; qcom,speed-bin = <0>; - /* Turbo_L1 */ + /* Turbo_L2 */ qcom,gpu-pwrlevel@0 { reg = <0>; + qcom,gpu-freq = <1150000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* Turbo_L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; qcom,gpu-freq = <1050000000>; qcom,level = ; qcom,bus-freq = <11>; qcom,bus-min = <11>; qcom,bus-max = <11>; + + qcom,acd-level = ; }; /* Turbo */ - qcom,gpu-pwrlevel@1 { - reg = <1>; + qcom,gpu-pwrlevel@2 { + reg = <2>; qcom,gpu-freq = <937000000>; qcom,level = ; qcom,bus-freq = <10>; qcom,bus-min = <9>; qcom,bus-max = <10>; + + qcom,acd-level = ; }; /* Nom_L1 */ - qcom,gpu-pwrlevel@2 { - reg = <2>; + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <873000000>; qcom,level = ; qcom,bus-freq = <9>; qcom,bus-min = <7>; qcom,bus-max = <9>; + + qcom,acd-level = ; }; /* Nom */ - qcom,gpu-pwrlevel@3 { - reg = <3>; + qcom,gpu-pwrlevel@4 { + reg = <4>; qcom,gpu-freq = <763000000>; qcom,level = ; qcom,bus-freq = <8>; qcom,bus-min = <7>; qcom,bus-max = <9>; + + qcom,acd-level = ; }; /* SVS_L2 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <688000000>; qcom,level = ; qcom,bus-freq = <6>; qcom,bus-min = <4>; qcom,bus-max = <7>; + + qcom,acd-level = ; }; /* SVS_L1 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; + qcom,gpu-pwrlevel@6 { + reg = <6>; qcom,gpu-freq = <644000000>; qcom,level = ; qcom,bus-freq = <6>; qcom,bus-min = <4>; qcom,bus-max = <7>; + + qcom,acd-level = ; }; /* SVS */ - qcom,gpu-pwrlevel@6 { - reg = <6>; + qcom,gpu-pwrlevel@7 { + reg = <7>; qcom,gpu-freq = <510000000>; qcom,level = ; qcom,bus-freq = <4>; qcom,bus-min = <2>; qcom,bus-max = <6>; + + qcom,acd-level = ; }; /* Low_SVS */ - qcom,gpu-pwrlevel@7 { - reg = <7>; + qcom,gpu-pwrlevel@8 { + reg = <8>; qcom,gpu-freq = <362000000>; qcom,level = ; qcom,bus-freq = <3>; qcom,bus-min = <1>; qcom,bus-max = <3>; + + qcom,acd-level = ; }; /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@8 { - reg = <8>; + qcom,gpu-pwrlevel@9 { + reg = <9>; qcom,gpu-freq = <264000000>; qcom,level = ; qcom,bus-freq = <1>; qcom,bus-min = <1>; qcom,bus-max = <3>; + + qcom,acd-level = ; }; }; @@ -138,6 +181,8 @@ qcom,bus-freq = <11>; qcom,bus-min = <11>; qcom,bus-max = <11>; + + qcom,acd-level = ; }; /* Turbo */ @@ -149,6 +194,8 @@ qcom,bus-freq = <10>; qcom,bus-min = <9>; qcom,bus-max = <10>; + + qcom,acd-level = ; }; /* Nom_L1 */ @@ -160,6 +207,7 @@ qcom,bus-freq = <9>; qcom,bus-min = <7>; qcom,bus-max = <9>; + qcom,acd-level = ; }; /* Nom */ @@ -171,6 +219,8 @@ qcom,bus-freq = <8>; qcom,bus-min = <7>; qcom,bus-max = <9>; + + qcom,acd-level = ; }; /* SVS_L2 */ @@ -182,6 +232,8 @@ qcom,bus-freq = <6>; qcom,bus-min = <4>; qcom,bus-max = <7>; + + qcom,acd-level = ; }; /* SVS_L1 */ @@ -193,6 +245,8 @@ qcom,bus-freq = <6>; qcom,bus-min = <4>; qcom,bus-max = <7>; + + qcom,acd-level = ; }; /* SVS */ @@ -204,6 +258,8 @@ qcom,bus-freq = <4>; qcom,bus-min = <2>; qcom,bus-max = <6>; + + qcom,acd-level = ; }; /* Low_SVS */ @@ -215,6 +271,8 @@ qcom,bus-freq = <3>; qcom,bus-min = <1>; qcom,bus-max = <3>; + + qcom,acd-level = ; }; /* Low_SVS_D1 */ @@ -226,6 +284,8 @@ qcom,bus-freq = <1>; qcom,bus-min = <1>; qcom,bus-max = <3>; + + qcom,acd-level = ; }; }; @@ -233,106 +293,137 @@ #address-cells = <1>; #size-cells = <0>; - qcom,initial-pwrlevel = <8>; + qcom,initial-pwrlevel = <9>; qcom,speed-bin = <0xf2>; - /* Turbo_L1 */ + /* Turbo_L2 */ qcom,gpu-pwrlevel@0 { reg = <0>; + qcom,gpu-freq = <1150000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + + qcom,acd-level = ; + }; + + /* Turbo_L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; qcom,gpu-freq = <1050000000>; qcom,level = ; qcom,bus-freq = <11>; qcom,bus-min = <11>; qcom,bus-max = <11>; + + qcom,acd-level = ; }; /* Turbo */ - qcom,gpu-pwrlevel@1 { - reg = <1>; + qcom,gpu-pwrlevel@2 { + reg = <2>; qcom,gpu-freq = <937000000>; qcom,level = ; qcom,bus-freq = <10>; qcom,bus-min = <9>; qcom,bus-max = <10>; + + qcom,acd-level = ; }; /* Nom_L1 */ - qcom,gpu-pwrlevel@2 { - reg = <2>; + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <873000000>; qcom,level = ; qcom,bus-freq = <9>; qcom,bus-min = <7>; qcom,bus-max = <9>; + + qcom,acd-level = ; }; /* Nom */ - qcom,gpu-pwrlevel@3 { - reg = <3>; + qcom,gpu-pwrlevel@4 { + reg = <4>; qcom,gpu-freq = <763000000>; qcom,level = ; qcom,bus-freq = <8>; qcom,bus-min = <7>; qcom,bus-max = <9>; + + qcom,acd-level = ; }; /* SVS_L2 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <688000000>; qcom,level = ; qcom,bus-freq = <6>; qcom,bus-min = <4>; qcom,bus-max = <7>; + + qcom,acd-level = ; }; /* SVS_L1 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; + qcom,gpu-pwrlevel@6 { + reg = <6>; qcom,gpu-freq = <644000000>; qcom,level = ; qcom,bus-freq = <6>; qcom,bus-min = <4>; qcom,bus-max = <7>; + + qcom,acd-level = ; }; /* SVS */ - qcom,gpu-pwrlevel@6 { - reg = <6>; + qcom,gpu-pwrlevel@7 { + reg = <7>; qcom,gpu-freq = <510000000>; qcom,level = ; qcom,bus-freq = <4>; qcom,bus-min = <2>; qcom,bus-max = <6>; + + qcom,acd-level = ; }; /* Low_SVS */ - qcom,gpu-pwrlevel@7 { - reg = <7>; + qcom,gpu-pwrlevel@8 { + reg = <8>; qcom,gpu-freq = <362000000>; qcom,level = ; qcom,bus-freq = <3>; qcom,bus-min = <1>; qcom,bus-max = <3>; + + qcom,acd-level = ; }; /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@8 { - reg = <8>; + qcom,gpu-pwrlevel@9 { + reg = <9>; qcom,gpu-freq = <264000000>; qcom,level = ; qcom,bus-freq = <1>; qcom,bus-min = <1>; qcom,bus-max = <3>; + + qcom,acd-level = ; }; }; };