diff --git a/Kbuild b/Kbuild new file mode 100644 index 00000000..c145349b --- /dev/null +++ b/Kbuild @@ -0,0 +1,10 @@ +ifeq ($(CONFIG_ARCH_SUN),y) +dtbo-y += sun-kiwi-cnss.dtbo +dtbo-y += sun-kiwi-cnss-v8.dtbo +dtbo-y += sun-peach-cnss.dtbo +dtbo-y += sun-peach-cnss-v8.dtbo +endif + +always-y := $(dtb-y) $(dtbo-y) +subdir-y := $(dts-dirs) +clean-files := *.dtb *.dtbo diff --git a/Makefile b/Makefile new file mode 100644 index 00000000..4b03b08a --- /dev/null +++ b/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0 +KBUILD_OPTIONS += KBUILD_EXTMOD_DTS=. + +all: dtbs + +clean: + $(MAKE) -C $(KERNEL_SRC) M=$(M) clean + +%: + $(MAKE) -C $(KERNEL_SRC) M=$(M) $@ $(KBUILD_OPTIONS) diff --git a/bindings/cnss-wlan.yaml b/bindings/cnss-wlan.yaml new file mode 100644 index 00000000..e2ef1e30 --- /dev/null +++ b/bindings/cnss-wlan.yaml @@ -0,0 +1,357 @@ +# Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- + +title: Connectivity SubSystem Platform Driver + +description: + Connectivity SubSystem platform driver adds support for the CNSS subsystem + used for PCIe based Wi-Fi devices. It also adds support to integrate PCIe + WLAN module to subsystem restart framework. Apart from that, it also manages + the 3.3V voltage regulator, WLAN Enable GPIO signal and PCIe link dynamically + with support for suspend and resume by retaining the PCI config space + states when PCIe link is shutdown. The main purpose of this device tree + entry below is to invoke the CNSS platform driver and provide handle to + the WLAN enable GPIO, 3.3V fixed voltage regulator resources. It also + provides the reserved RAM dump memory location and size. + +properties: + compatible: + enum: + - qcom,cnss #for QCA6174 device + - qcom,cnss-qca6290 #for QCA6290 device + - qcom,cnss-qca6390 #for QCA6390 device + - qcom,cnss-qca6490 #for QCA6490 device + - qcom,cnss-kiwi #for KIWI device + - qcom,cnss-qca-converged #for converged QCA devices + + wlan-en-gpio: + description: WLAN_EN GPIO signal specified by the chip specifications. + + vdd-wlan-supply: + description: phandle to the regulator device tree node. + + pinctrl-names: + description: Names corresponding to the numbered pinctrl states. + + pinctrl-: + description: | + Pinctrl states as described in + bindings/pinctrl/pinctrl-bindings.txt. + + qcom,wlan-rc-num: + description: | + List of PCIe root complex numbers which WLAN device may + attach to. + + qcom,wlan: + description: | + Signature string for WLAN devices which all CNSS family drivers + are able to search for. + + mpm_wake_set_gpios: + description: | + U32 array of GPIOs which need to be setup for + interrupt wakeup capable. + + qcom,notify-modem-status: + description: | + Boolean property to decide whether modem + notification should be enabled or not in this + platform. + + wlan-soc-swreg-supply: + description: phandle to the external 1.15V regulator for QCA6174. + + wlan-ant-switch-supply: + description: | + phandle to the 2.7V regulator for the antenna + switch of QCA6174. + + qcom,wlan-uart-access: + description: | + Boolean property to decide whether QCA6174 + has exclusive access to UART. + + vdd-wlan-io-supply: + description: phandle to the 1.8V IO regulator for QCA6174. + + vdd-wlan-io12-supply: + description: phandle to the 1.2V IO regulator for Kiwi. + + vdd-wlan-ant-share-supply: + description: phandle to the Antenna Sharing regulator. + + vdd-wlan-xtal-supply: + description: phandle to the 1.8V XTAL regulator for QCA6174. + + vdd-wlan-xtal-aon-supply: + description: | + phandle to the LDO-4 regulator. This is needed + on platforms where XTAL regulator depends on + always on regulator in VDDmin. + + vdd-wlan-ctrl1-supply: + description: | + phandle to the DBU1 - 1.8V for QCA6595 or 3.3V for + QCA6174 on auto platform. + + vdd-wlan-ctrl2-supply: + description: | + phandle to the DBU4 - 2.2V for QCA6595 or 3.85V for + QCA6696 on auto platform. + + vdd-wlan-core-supply: + description: phandle to the 1.3V CORE regulator for QCA6174. + + vdd-wlan-sp2t-supply: + description: phandle to the 2.7V SP2T regulator for QCA6174. + + -supply: + description: | + phandle to the regulator device tree node. + optional "supply-name" is "vdd-wlan-rfa". + + qcom,-config: + description: | + Specifies voltage levels for supply. Should specified + in pairs (min, max), units uV. There can be optional + load in uA and Regulator settle delay in us. + + qcom,smmu-s1-enable: + description: | + Boolean property to decide whether to enable SMMU + S1 stage or not. + + qcom,wlan-smmu-iova-address: + description: | + I/O virtual address range as + format to be used for allocations associated + between WLAN/PCIe and SMMU. + + qcom,wlan-ramdump-dynamic: + description: | + To enable CNSS RAMDUMP collection + by providing the size of CNSS DUMP. + + qcom,cmd_db_name: + description: | + CommandDB name indicating the PMIC rail used for open + loop CPR. + + reg: + description: Memory regions defined as starting address and size. + + reg-names: + description: Names of the memory regions defined in reg entry. + + wlan-bootstrap-gpio: + description: | + WLAN_BOOTSTRAP GPIO signal specified by QCA6174 + which should be drived depending on platforms. + + qcom,is-dual-wifi-enabled: + description: | + Boolean property to control wlan enable(wlan-en) + gpio on dual-wifi platforms. + + vdd-wlan-en-supply: + description: | + WLAN_EN fixed regulator specified by QCA6174 + specifications. + + qcom,wlan-en-vreg-support: + description: | + Boolean property to decide the whether the + WLAN_EN pin is a gpio or fixed regulator. + + qcom,mhi: + description: phandle to indicate the device which needs MHI support. + + qcom,cap-tsf-gpio: + description: | + WLAN_TSF_CAPTURED GPIO signal specified by the chip + specifications, should be drived depending on products. + + cnss-daemon-support: + description: | + Boolean property to decide whether cnss_daemon + userspace QMI client is supported. + + use-nv-mac: + description: Boolean property to indicate whether NV MAC is used or not. + + qcom,set-wlaon-pwr-ctrl: + description: | + Boolean property to indicate if set + WLAON_QFPROM_PWR_CTRL_REG register during power on + and off sequences. + + use-pm-domain: + description: | + Boolean property to indicate if driver needs to use PM + domain or not. + + qcom,wlan-cbc-enabled: + description: boolean property to control cold boot calibration. + + interconnects: + description: Interconnect framework setup for bus configuration. + + interconnect-names: + description: Interconnect path names as strings. + + qcom,icc-path-count: + description: Number of Interconnect paths for this platform. + + qcom,bus-bw-cfg-count: + description: Number of bus bandwidth voting cases. + + qcom,bus-bw-cfg: + description: Bus bandwidth voting data. + + qcom,tcs_offset_int_pow_amp_vreg: + description: | + TCS CMD register offset for Voltage + regulator used in internal power amplifier for QCA6490. + + cnss-enable-self-recovery: + description: | + Boolean property to enable self recovery when + recovery is trigeered with reason link down. + + qcom,bt-en-gpio: + description: | + QCA6490 requires synchronization for BT and WLAN GPIO + enable to resolve PMU power up issues. Provide BT GPIO using + this config param. + + qcom,same-dt-multi-dev: + description: | + Boolean property to decide whether it supports + multiple WLAN devices using the same DT node + without sub-nodes. + + qcom,converged-dt: + description: | + Boolean property to decide whether it supports multiple + WLAN devices using the same DT node with sub-nodes. + + mboxes: + description: Specifies mbox channel data for AOP messaging. + + qcom,vreg_ipa: + description: | + Specifies voltage regulator used for WLAN device internal + power amp config. + + qcom,xo-clk-gpio: + description: Added for QCA6490 XO CLK selection leakage prevention. + + platform-name-required: + description: | + Boolean property to decide whether + platform name required. + + chip_cfg@X: + description: represent chip specific configurations + enum: + -supported-ids #U32 array to decide which device ids are supported by sub node. + +required: + - compatible + - wlan-en-gpio + - vdd-wlan-supply + - pinctrl-names + - pinctrl- + - qcom,wlan-rc-num + - qcom,wlan + +examples: + - | + qcom,cnss@0d400000 { + compatible = "qcom,cnss"; + reg = <0x0d400000 0x200000>; + reg-names = "ramdump"; + qcom,wlan-ramdump-dynamic = <0x200000>; + wlan-en-gpio = <&msmgpio 82 0>; + vdd-wlan-supply = <&wlan_vreg>; + qcom,notify-modem-status; + wlan-soc-swreg-supply = <&pma8084_l27>; + pinctrl-names = "default"; + pinctrl-0 = <&cnss_default>; + qcom,wlan; + qcom,wlan-rc-num = <0>; + qcom,wlan-smmu-iova-address = <0 0x10000000>; + qcom,mhi = <&mhi_wlan>; + qcom,cap-tsf-gpio = <&tlmm 126 1>; + }; + + wlan: qcom,cnss-qca6490@b0000000 { + compatible = "qcom,cnss-qca6490"; + reg = <0xb0000000 0x10000>; + reg-names = "smmu_iova_ipa"; + wlan-en-gpio = <&tlmm 80 0>; + qcom,bt-en-gpio = <&tlmm 81 0>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <&cnss_wlan_en_active>; + pinctrl-1 = <&cnss_wlan_en_sleep>; + qcom,wlan; + qcom,wlan-rc-num = <0>; + qcom,wlan-ramdump-dynamic = <0x420000>; + qcom,wlan-cbc-enabled; + use-pm-domain; + cnss-enable-self-recovery; + qcom,same-dt-multi-dev; + mboxes = <&qmp_aop 0>; + qcom,vreg_ipa="s3e"; + qcom,xo-clk-gpio = <&tlmm 204 0>; + vdd-wlan-aon-supply = <&S2E>; + qcom,vdd-wlan-aon-config = <1012000 1012000 0 0 1>; + vdd-wlan-dig-supply = <&S11B>; + qcom,vdd-wlan-dig-config = <966000 966000 0 0 1>; + vdd-wlan-io-supply = <&S10B>; + qcom,vdd-wlan-io-config = <1800000 1800000 0 0 1>; + vdd-wlan-rfa1-supply = <&S1C>; + qcom,vdd-wlan-rfa1-config = <1900000 2100000 0 0 1>; + vdd-wlan-rfa2-supply = <&S12B>; + qcom,vdd-wlan-rfa2-config = <1350000 1350000 0 0 1>; + wlan-ant-switch-supply = <&L7E>; + qcom,wlan-ant-switch-config = <2800000 2800000 0 0 1>; + }; + + wlan: qcom,cnss-qca-converged { + compatible = "qcom,cnss-qca-converged"; + qcom,converged-dt; + qcom,wlan-sw-ctrl-gpio = <&tlmm 83 0>; + chip_cfg@0 { + supported-ids = <0x1103>; + reg = <0xb0000000 0x10000>; + reg-names = "smmu_iova_ipa"; + wlan-en-gpio = <&tlmm 80 0>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <&cnss_wlan_en_active>; + pinctrl-1 = <&cnss_wlan_en_sleep>; + qcom,wlan; + qcom,wlan-rc-num = <0>; + qcom,wlan-ramdump-dynamic = <0x780000>; + qcom,wlan-cbc-enabled; + use-pm-domain; + mboxes = <&qmp_aop 0>; + vdd-wlan-io-supply = <&L15B>; + qcom,vdd-wlan-io-config = <1800000 1800000 0 0 1>; + vdd-wlan-supply = <&S5G>; + qcom,vdd-wlan-config = <1000000 1000000 0 0 1>; + vdd-wlan-aon-supply = <&S2G>; + qcom,vdd-wlan-aon-config = <980000 980000 0 0 1>; + vdd-wlan-dig-supply = <&S4E>; + qcom,vdd-wlan-dig-config = <950000 950000 0 0 1>; + vdd-wlan-rfa1-supply = <&S6G>; + qcom,vdd-wlan-rfa1-config = <1900000 1900000 0 0 1>; + vdd-wlan-rfa2-supply = <&S4G>; + qcom,vdd-wlan-rfa2-config = <1350000 1350000 0 0 1>; + }; + }; +... + diff --git a/bindings/icnss-wlan.yaml b/bindings/icnss-wlan.yaml new file mode 100644 index 00000000..1d8903fe --- /dev/null +++ b/bindings/icnss-wlan.yaml @@ -0,0 +1,138 @@ +# Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- + +title: Integrated connectivity Platform Driver + +description: + Integrated connectivity platform driver adds support for the Integrated WLAN + that runs on Q6 based platforms. WLAN FW on these architecture runs on Q6. This + platform driver communicates with WLAN FW over QMI, WLAN on/off messages + to FW are communicated thru this interface. This driver also listens to + WLAN PD restart notifications. + +properties: + compatible: + enum: + - qcom,icnss #for ADRASTEA architecture + - qcom,wcn6750 #for iWCN architecture + - qcom,wcn6450 #for evros architecture + + reg: + description: Memory regions defined as starting address and size. + + reg-names: + description: Names of the memory regions defined in reg entry. + + interrupts: + description: Copy engine interrupt table. + + qcom,wlan-msa-memory: + description: MSA memory size. + + clocks: + description: List of clock phandles. + + clock-names: + description: List of clock names corresponding to the "clocks" property. + + iommus: + description: SMMUs and corresponding Stream IDs needed by WLAN. + + qcom,wlan-smmu-iova-address: + description: | + I/O virtual address range as + format to be used for allocations associated between WLAN and SMMU. + + qcom,wlan: + description: | + Signature string for WLAN devices which all CNSS family drivers + are able to search for. + + -supply: + description: | + phandle to the regulator device tree node + optional "supply-name" is "vdd-0.8-cx-mx". + + qcom,-config: + description: | + Specifies voltage levels for supply. Should be + specified in pairs (min, max), units uV. There can + be optional load in uA and Regulator settle delay in + uS. + qcom,icnss-vadc: + description: VADC handle for vph_pwr read APIs. + + qcom,icnss-adc_tm: + description: VADC handle for vph_pwr notification APIs. + + io-channels: + description: IIO channel to monitor for vph_pwr power. + + io-channel-names: + description: IIO channel name as per the client name. + + qcom,smmu-s1-bypass: + description: Boolean context flag to set SMMU to S1 bypass. + + qcom,wlan-msa-fixed-region: + description: phandle, specifier pairs to children of /reserved-memory. + + qcom,hyp_disabled: + description: Boolean context flag to disable hyperviser. + + qcom,smp2p_map_wlan_1_in: + description: Represents the in smp2p to wlan driver from modem. + +required: + - compatible + - reg + - reg-names + - interrupts + - qcom,wlan-msa-memory + - clocks + - clock-names + - iommus + - qcom,wlan-smmu-iova-address + - qcom,wlan + +examples: + - | + qcom,icnss@0a000000 { + compatible = "qcom,icnss"; + reg = <0x0a000000 0x1000000>; + reg-names = "membase"; + clocks = <&clock_gcc clk_aggre2_noc_clk>; + clock-names = "smmu_aggre2_noc_clk"; + iommus = <&anoc2_smmu 0x1900>, + <&anoc2_smmu 0x1901>; + qcom,wlan-smmu-iova-address = <0 0x10000000>; + qcom,wlan; + interrupts = <0 130 0 /* CE0 */ >, + <0 131 0 /* CE1 */ >, + <0 132 0 /* CE2 */ >, + <0 133 0 /* CE3 */ >, + <0 134 0 /* CE4 */ >, + <0 135 0 /* CE5 */ >, + <0 136 0 /* CE6 */ >, + <0 137 0 /* CE7 */ >, + <0 138 0 /* CE8 */ >, + <0 139 0 /* CE9 */ >, + <0 140 0 /* CE10 */ >, + <0 141 0 /* CE11 */ >; + qcom,wlan-msa-memory = <0x200000>; + qcom,wlan-msa-fixed-region = <&wlan_msa_mem>; + qcom,smmu-s1-bypass; + vdd-0.8-cx-mx-supply = <&pm8998_l5>; + qcom,vdd-0.8-cx-mx-config = <800000 800000 2400 1000>; + qcom,hyp_disabled; + qcom,smp2p_map_wlan_1_in { + interrupts-extended = <&smp2p_wlan_1_in 0 0>, + <&smp2p_wlan_1_in 1 0>; + interrupt-names = "qcom,smp2p-force-fatal-error", + "qcom,smp2p-early-crash-ind"; + }; + }; +... + diff --git a/sun-kiwi-cnss-v8.dts b/sun-kiwi-cnss-v8.dts new file mode 100644 index 00000000..a8c61576 --- /dev/null +++ b/sun-kiwi-cnss-v8.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-kiwi-cnss-v8.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun SoCs"; + compatible = "qcom,sun", "qcom,sunp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, + <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x60001 0>, <0x50008 0>; +}; diff --git a/sun-kiwi-cnss-v8.dtsi b/sun-kiwi-cnss-v8.dtsi new file mode 100644 index 00000000..7b29ccf7 --- /dev/null +++ b/sun-kiwi-cnss-v8.dtsi @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&tlmm { + cnss_pins { + cnss_wlan_en_active: cnss_wlan_en_active { + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + drive-strength = <16>; + output-high; + bias-pull-up; + }; + }; + + cnss_wlan_en_sleep: cnss_wlan_en_sleep { + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + }; + + cnss_wlan_sw_ctrl: cnss_wlan_sw_ctrl { + mux { + pins = "gpio18"; + function = "wcn_sw_ctrl"; + }; + }; + + cnss_wlan_sw_ctrl_wl_cx: cnss_wlan_sw_ctrl_wl_cx { + mux { + pins = "gpio19"; + function = "wcn_sw"; + }; + }; + }; +}; + +&reserved_memory { + cnss_wlan_mem: cnss_wlan_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + }; +}; + +&soc { + wlan_kiwi: qcom,cnss-kiwi@b0000000 { + compatible = "qcom,cnss-kiwi"; + reg = <0xb0000000 0x10000>; + reg-names = "smmu_iova_ipa"; + qcom,wlan-sw-ctrl-gpio = <&tlmm 19 0>; + + supported-ids = <0x1107>; + wlan-en-gpio = <&tlmm 16 0>; + qcom,bt-en-gpio = <&pm8550ve_f 3 0>; + qcom,sw-ctrl-gpio = <&tlmm 18 0>; + /* List of GPIOs to be setup for interrupt wakeup capable */ + mpm_wake_set_gpios = <18 19>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep", "sw_ctrl", + "sw_ctrl_wl_cx"; + pinctrl-0 = <&cnss_wlan_en_active>; + pinctrl-1 = <&cnss_wlan_en_sleep>; + pinctrl-2 = <&cnss_wlan_sw_ctrl>; + pinctrl-3 = <&cnss_wlan_sw_ctrl_wl_cx>; + qcom,wlan; + qcom,wlan-rc-num = <0>; + qcom,wlan-ramdump-dynamic = <0x780000>; + cnss-enable-self-recovery; + qcom,wlan-cbc-enabled; + use-pm-domain; + qcom,same-dt-multi-dev; + /* For AOP communication, use direct QMP instead of mailbox */ + qcom,qmp = <&aoss_qmp>; + + vdd-wlan-io-supply = <&L3F>; + qcom,vdd-wlan-io-config = <1800000 1800000 0 0 0>; + vdd-wlan-io12-supply = <&L2F>; + qcom,vdd-wlan-io12-config = <1200000 1200000 0 0 0>; + vdd-wlan-supply = <&S5F>; + qcom,vdd-wlan-config = <932000 1000000 0 0 0>; + vdd-wlan-aon-supply = <&S4D>; + qcom,vdd-wlan-aon-config = <976000 1036000 0 0 0>; + vdd-wlan-dig-supply = <&S1D>; + qcom,vdd-wlan-dig-config = <916000 1100000 0 0 0>; + vdd-wlan-rfa1-supply = <&S3G>; + qcom,vdd-wlan-rfa1-config = <1864000 2000000 0 0 0>; + vdd-wlan-rfa2-supply = <&S7I>; + qcom,vdd-wlan-rfa2-config = <1316000 1340000 0 0 0>; + vdd-wlan-ant-share-supply = <&L6K>; + qcom,vdd-wlan-ant-share-config = <1800000 1800000 0 0 0>; + + qcom,vreg_pdc_map = + "s5f", "bb", + "s4d", "bb", + "s3g", "rf", + "s7i", "rf", + "s1d", "rf"; + + qcom,pmu_vreg_map = + "VDD095_MX_PMU", "s4d", + "VDD095_PMU", "s5f", + "VDD_PMU_AON_I", "s1d", + "VDD095_PMU_BT", "s1d", + "VDD09_PMU_RFA_I", "s1d", + "VDD13_PMU_PCIE_I", "s7i", + "VDD13_PMU_RFA_I", "s7i", + "VDD19_PMU_PCIE_I", "s3g", + "VDD19_PMU_RFA_I", "s3g"; + + qcom,pdc_init_table = + "{class: wlan_pdc, ss: rf, res: s3g.v, upval: 1856}", + "{class: wlan_pdc, ss: rf, res: s3g.v, dwnval: 1844}", + "{class: wlan_pdc, ss: rf, res: s7i.v, upval: 1316}", + "{class: wlan_pdc, ss: rf, res: s7i.v, dwnval: 972}", + "{class: wlan_pdc, ss: rf, res: s1d.m, enable: 1}", + "{class: wlan_pdc, ss: rf, res: s1d.v, enable: 1}", + "{class: wlan_pdc, ss: rf, res: s1d.v, upval: 916}", + "{class: wlan_pdc, ss: rf, res: s1d.v, dwnval: 880}", + "{class: wlan_pdc, ss: bb, res: s4d.v, upval: 976}", + "{class: wlan_pdc, ss: bb, res: s4d.v, dwnval: 536}", + "{class: wlan_pdc, ss: bb, res: s5f.m, enable: 1}", + "{class: wlan_pdc, ss: bb, res: s5f.v, enable: 1}", + "{class: wlan_pdc, ss: bb, res: s5f.v, upval: 932}", + "{class: wlan_pdc, ss: bb, res: s5f.v, dwnval: 444}"; + }; +}; + +&pcie0_rp { + #address-cells = <5>; + #size-cells = <0>; + + cnss_pci0: cnss_pci0 { + reg = <0 0 0 0 0>; + qcom,iommu-group = <&cnss_pci_iommu_group0>; + memory-region = <&cnss_wlan_mem>; + + #address-cells = <1>; + #size-cells = <1>; + + cnss_pci_iommu_group0: cnss_pci_iommu_group0 { + qcom,iommu-msi-size = <0x1000>; + qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + qcom,iommu-geometry = <0xa0000000 0x10010000>; + qcom,iommu-dma = "fastmap"; + qcom,iommu-pagetable = "coherent"; + qcom,iommu-faults = "stall-disable", "HUPCF", + "non-fatal"; + }; + }; +}; diff --git a/sun-kiwi-cnss.dts b/sun-kiwi-cnss.dts new file mode 100644 index 00000000..9613ce97 --- /dev/null +++ b/sun-kiwi-cnss.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-kiwi-cnss.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun SoCs"; + compatible = "qcom,sun", "qcom,sunp", "qcom,sun-mtp", "qcom,sun-cdp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x20001 0>, <0x20008 0>; +}; diff --git a/sun-kiwi-cnss.dtsi b/sun-kiwi-cnss.dtsi new file mode 100644 index 00000000..f3261e33 --- /dev/null +++ b/sun-kiwi-cnss.dtsi @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&tlmm { + cnss_pins { + cnss_wlan_en_active: cnss_wlan_en_active { + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + drive-strength = <16>; + output-high; + bias-pull-up; + }; + }; + + cnss_wlan_en_sleep: cnss_wlan_en_sleep { + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + }; + + cnss_wlan_sw_ctrl: cnss_wlan_sw_ctrl { + mux { + pins = "gpio18"; + function = "wcn_sw_ctrl"; + }; + }; + + cnss_wlan_sw_ctrl_wl_cx: cnss_wlan_sw_ctrl_wl_cx { + mux { + pins = "gpio19"; + function = "wcn_sw"; + }; + }; + }; +}; + +&reserved_memory { + cnss_wlan_mem: cnss_wlan_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + }; +}; + +&soc { + wlan_kiwi: qcom,cnss-kiwi@b0000000 { + compatible = "qcom,cnss-kiwi"; + reg = <0xb0000000 0x10000>; + reg-names = "smmu_iova_ipa"; + qcom,wlan-sw-ctrl-gpio = <&tlmm 19 0>; + + supported-ids = <0x1107>; + wlan-en-gpio = <&tlmm 16 0>; + qcom,bt-en-gpio = <&pm8550vs_f 3 0>; + qcom,sw-ctrl-gpio = <&tlmm 18 0>; + /* List of GPIOs to be setup for interrupt wakeup capable */ + mpm_wake_set_gpios = <18 19>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep", "sw_ctrl", + "sw_ctrl_wl_cx"; + pinctrl-0 = <&cnss_wlan_en_active>; + pinctrl-1 = <&cnss_wlan_en_sleep>; + pinctrl-2 = <&cnss_wlan_sw_ctrl>; + pinctrl-3 = <&cnss_wlan_sw_ctrl_wl_cx>; + qcom,wlan; + qcom,wlan-rc-num = <0>; + qcom,wlan-ramdump-dynamic = <0x780000>; + cnss-enable-self-recovery; + qcom,wlan-cbc-enabled; + use-pm-domain; + qcom,same-dt-multi-dev; + /* For AOP communication, use direct QMP instead of mailbox */ + qcom,qmp = <&aoss_qmp>; + + vdd-wlan-io-supply = <&L3F>; + qcom,vdd-wlan-io-config = <1800000 1800000 0 0 1>; + vdd-wlan-io12-supply = <&L2F>; + qcom,vdd-wlan-io12-config = <1200000 1200000 0 0 1>; + vdd-wlan-supply = <&S4J>; + qcom,vdd-wlan-config = <932000 1000000 0 0 0>; + vdd-wlan-aon-supply = <&S4D>; + qcom,vdd-wlan-aon-config = <976000 1036000 0 0 1>; + vdd-wlan-dig-supply = <&S1D>; + qcom,vdd-wlan-dig-config = <916000 1100000 0 0 1>; + vdd-wlan-rfa1-supply = <&S3G>; + qcom,vdd-wlan-rfa1-config = <1864000 2000000 0 0 1>; + vdd-wlan-rfa2-supply = <&S7I>; + qcom,vdd-wlan-rfa2-config = <1316000 1340000 0 0 1>; + vdd-wlan-ant-share-supply = <&L6K>; + qcom,vdd-wlan-ant-share-config = <1800000 1800000 0 0 1>; + + qcom,vreg_pdc_map = + "s4j", "bb", + "s4d", "bb", + "s3g", "rf", + "s7i", "rf", + "s1d", "rf"; + + qcom,pmu_vreg_map = + "VDD095_MX_PMU", "s4d", + "VDD095_PMU", "s4j", + "VDD_PMU_AON_I", "s1d", + "VDD095_PMU_BT", "s1d", + "VDD09_PMU_RFA_I", "s1d", + "VDD13_PMU_PCIE_I", "s7i", + "VDD13_PMU_RFA_I", "s7i", + "VDD19_PMU_PCIE_I", "s3g", + "VDD19_PMU_RFA_I", "s3g"; + + qcom,pdc_init_table = + "{class: wlan_pdc, ss: rf, res: s3g.v, upval: 1856}", + "{class: wlan_pdc, ss: rf, res: s3g.v, dwnval: 1844}", + "{class: wlan_pdc, ss: rf, res: s7i.v, upval: 1316}", + "{class: wlan_pdc, ss: rf, res: s7i.v, dwnval: 972}", + "{class: wlan_pdc, ss: rf, res: s1d.m, enable: 1}", + "{class: wlan_pdc, ss: rf, res: s1d.v, enable: 1}", + "{class: wlan_pdc, ss: rf, res: s1d.v, upval: 916}", + "{class: wlan_pdc, ss: rf, res: s1d.v, dwnval: 880}", + "{class: wlan_pdc, ss: rf, res: s4j.m, enable: 0}", + "{class: wlan_pdc, ss: rf, res: s4j.v, enable: 0}", + "{class: wlan_pdc, ss: bb, res: s4d.v, upval: 976}", + "{class: wlan_pdc, ss: bb, res: s4d.v, dwnval: 536}", + "{class: wlan_pdc, ss: bb, res: s4j.m, enable: 1}", + "{class: wlan_pdc, ss: bb, res: s4j.v, enable: 1}", + "{class: wlan_pdc, ss: bb, res: s4j.v, upval: 932}", + "{class: wlan_pdc, ss: bb, res: s4j.v, dwnval: 444}"; + }; +}; + +&pcie0_rp { + #address-cells = <5>; + #size-cells = <0>; + + cnss_pci0: cnss_pci0 { + reg = <0 0 0 0 0>; + qcom,iommu-group = <&cnss_pci_iommu_group0>; + memory-region = <&cnss_wlan_mem>; + + #address-cells = <1>; + #size-cells = <1>; + + cnss_pci_iommu_group0: cnss_pci_iommu_group0 { + qcom,iommu-msi-size = <0x1000>; + qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + qcom,iommu-geometry = <0xa0000000 0x10010000>; + qcom,iommu-dma = "fastmap"; + qcom,iommu-pagetable = "coherent"; + qcom,iommu-faults = "stall-disable", "HUPCF", + "non-fatal"; + }; + }; +}; diff --git a/sun-peach-cnss-v8.dts b/sun-peach-cnss-v8.dts new file mode 100644 index 00000000..bb2addf3 --- /dev/null +++ b/sun-peach-cnss-v8.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-peach-cnss-v8.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun SoCs"; + compatible = "qcom,sun", "qcom,sunp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, + <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x50001 0>, <0x40008 0>, <0x3000B 0>, <0x2000B 0>; +}; diff --git a/sun-peach-cnss-v8.dtsi b/sun-peach-cnss-v8.dtsi new file mode 100644 index 00000000..8c83796e --- /dev/null +++ b/sun-peach-cnss-v8.dtsi @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&tlmm { + cnss_pins { + cnss_wlan_en_active: cnss_wlan_en_active { + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + drive-strength = <16>; + output-high; + bias-pull-up; + }; + }; + + cnss_wlan_en_sleep: cnss_wlan_en_sleep { + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + }; + + cnss_wlan_sw_ctrl: cnss_wlan_sw_ctrl { + mux { + pins = "gpio18"; + function = "wcn_sw_ctrl"; + + }; + }; + + cnss_wlan_sw_ctrl_wl_cx: cnss_wlan_sw_ctrl_wl_cx { + mux { + pins = "gpio19"; + function = "wcn_sw"; + }; + }; + }; +}; + +&reserved_memory { + cnss_wlan_mem: cnss_wlan_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + }; +}; + +&soc { + wlan_peach: qcom,cnss-peach@b0000000 { + compatible = "qcom,cnss-peach"; + reg = <0xb0000000 0x10000>; + reg-names = "smmu_iova_ipa"; + qcom,wlan-sw-ctrl-gpio = <&tlmm 19 0>; + + supported-ids = <0x110E>; + wlan-en-gpio = <&tlmm 16 0>; + qcom,bt-en-gpio = <&pm8550ve_f 3 0>; + qcom,sw-ctrl-gpio = <&tlmm 18 0>; + /* List of GPIOs to be setup for interrupt wakeup capable */ + mpm_wake_set_gpios = <18 19>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep", "sw_ctrl", + "sw_ctrl_wl_cx"; + pinctrl-0 = <&cnss_wlan_en_active>; + pinctrl-1 = <&cnss_wlan_en_sleep>; + pinctrl-2 = <&cnss_wlan_sw_ctrl>; + pinctrl-3 = <&cnss_wlan_sw_ctrl_wl_cx>; + qcom,wlan; + qcom,wlan-rc-num = <0>; + qcom,wlan-ramdump-dynamic = <0x780000>; + cnss-enable-self-recovery; + use-pm-domain; + qcom,same-dt-multi-dev; + /* For AOP communication, use direct QMP instead of mailbox */ + qcom,qmp = <&aoss_qmp>; + msix-match-addr = <0x3000>; + + vdd-wlan-io-supply = <&L3F>; + qcom,vdd-wlan-io-config = <1800000 1800000 0 0 1>; + vdd-wlan-io12-supply = <&L2F>; + qcom,vdd-wlan-io12-config = <1200000 1200000 0 0 1>; + vdd-wlan-aon-supply = <&S4D>; + qcom,vdd-wlan-aon-config = <876000 1036000 0 0 1>; + vdd-wlan-dig-supply = <&S5F>; + qcom,vdd-wlan-dig-config = <876000 1000000 0 0 1>; + vdd-wlan-rfa1-supply = <&S3G>; + qcom,vdd-wlan-rfa1-config = <1860000 2000000 0 0 1>; + vdd-wlan-rfa2-supply = <&S7I>; + qcom,vdd-wlan-rfa2-config = <1312000 1340000 0 0 1>; + vdd-wlan-ant-share-supply = <&L6K>; + qcom,vdd-wlan-ant-share-config = <1800000 1860000 0 0 1>; + + qcom,pdc_init_table = + "{class: wlan_pdc, ss: rf, res: s5f.m, enable: 1}", + "{class: wlan_pdc, ss: rf, res: s5f.v, enable: 1}", + "{class: wlan_pdc, ss: rf, res: s5f.v, upval: 876}", + "{class: wlan_pdc, ss: rf, res: s5f.v, dwnval: 796}"; + }; +}; + +&pcie0_rp { + #address-cells = <5>; + #size-cells = <0>; + + cnss_pci0: cnss_pci0 { + reg = <0 0 0 0 0>; + qcom,iommu-group = <&cnss_pci_iommu_group0>; + memory-region = <&cnss_wlan_mem>; + + #address-cells = <1>; + #size-cells = <1>; + + cnss_pci_iommu_group0: cnss_pci_iommu_group0 { + qcom,iommu-msi-size = <0x1000>; + qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + qcom,iommu-geometry = <0xa0000000 0x10010000>; + qcom,iommu-dma = "fastmap"; + qcom,iommu-pagetable = "coherent"; + qcom,iommu-faults = "stall-disable", "HUPCF", + "non-fatal"; + }; + }; +}; diff --git a/sun-peach-cnss.dts b/sun-peach-cnss.dts new file mode 100644 index 00000000..5c8fbfb5 --- /dev/null +++ b/sun-peach-cnss.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-peach-cnss.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun SoCs"; + compatible = "qcom,sun", "qcom,sunp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, + <639 0x10000>, <639 0x20000>; + qcom,board-id = <1 0>, <8 0>, <0x1000B 0>; +}; diff --git a/sun-peach-cnss.dtsi b/sun-peach-cnss.dtsi new file mode 100644 index 00000000..01eb6f80 --- /dev/null +++ b/sun-peach-cnss.dtsi @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&tlmm { + cnss_pins { + cnss_wlan_en_active: cnss_wlan_en_active { + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + drive-strength = <16>; + output-high; + bias-pull-up; + }; + }; + + cnss_wlan_en_sleep: cnss_wlan_en_sleep { + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + }; + + cnss_wlan_sw_ctrl: cnss_wlan_sw_ctrl { + mux { + pins = "gpio18"; + function = "wcn_sw_ctrl"; + }; + }; + + cnss_wlan_sw_ctrl_wl_cx: cnss_wlan_sw_ctrl_wl_cx { + mux { + pins = "gpio19"; + function = "wcn_sw"; + }; + }; + }; +}; + +&reserved_memory { + cnss_wlan_mem: cnss_wlan_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + }; +}; + +&soc { + wlan_peach: qcom,cnss-peach@b0000000 { + compatible = "qcom,cnss-peach"; + reg = <0xb0000000 0x10000>; + reg-names = "smmu_iova_ipa"; + qcom,wlan-sw-ctrl-gpio = <&tlmm 19 0>; + + supported-ids = <0x110E>; + wlan-en-gpio = <&tlmm 16 0>; + qcom,bt-en-gpio = <&pm8550vs_f 3 0>; + qcom,sw-ctrl-gpio = <&tlmm 18 0>; + /* List of GPIOs to be setup for interrupt wakeup capable */ + mpm_wake_set_gpios = <18 19>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep", "sw_ctrl", + "sw_ctrl_wl_cx"; + pinctrl-0 = <&cnss_wlan_en_active>; + pinctrl-1 = <&cnss_wlan_en_sleep>; + pinctrl-2 = <&cnss_wlan_sw_ctrl>; + pinctrl-3 = <&cnss_wlan_sw_ctrl_wl_cx>; + qcom,wlan; + qcom,wlan-rc-num = <0>; + qcom,wlan-ramdump-dynamic = <0x780000>; + cnss-enable-self-recovery; + use-pm-domain; + qcom,same-dt-multi-dev; + /* For AOP communication, use direct QMP instead of mailbox */ + qcom,qmp = <&aoss_qmp>; + msix-match-addr = <0x3000>; + + vdd-wlan-io-supply = <&L3F>; + qcom,vdd-wlan-io-config = <1800000 1800000 0 0 1>; + vdd-wlan-io12-supply = <&L2F>; + qcom,vdd-wlan-io12-config = <1200000 1200000 0 0 1>; + vdd-wlan-aon-supply = <&S4D>; + qcom,vdd-wlan-aon-config = <876000 1036000 0 0 1>; + vdd-wlan-dig-supply = <&S4J>; + qcom,vdd-wlan-dig-config = <876000 1000000 0 0 1>; + vdd-wlan-rfa1-supply = <&S3G>; + qcom,vdd-wlan-rfa1-config = <1860000 2000000 0 0 1>; + vdd-wlan-rfa2-supply = <&S7I>; + qcom,vdd-wlan-rfa2-config = <1312000 1340000 0 0 1>; + vdd-wlan-ant-share-supply = <&L6K>; + qcom,vdd-wlan-ant-share-config = <1800000 1860000 0 0 1>; + }; +}; + +&pcie0_rp { + #address-cells = <5>; + #size-cells = <0>; + + cnss_pci0: cnss_pci0 { + reg = <0 0 0 0 0>; + qcom,iommu-group = <&cnss_pci_iommu_group0>; + memory-region = <&cnss_wlan_mem>; + + #address-cells = <1>; + #size-cells = <1>; + + cnss_pci_iommu_group0: cnss_pci_iommu_group0 { + qcom,iommu-msi-size = <0x1000>; + qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + qcom,iommu-geometry = <0xa0000000 0x10010000>; + qcom,iommu-dma = "fastmap"; + qcom,iommu-pagetable = "coherent"; + qcom,iommu-faults = "stall-disable", "HUPCF", + "non-fatal"; + }; + }; +};