Merge "ARM: dts: msm: Disable low power modes for sun"
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@@ -87,6 +87,11 @@ properties:
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description:
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description:
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The offset of the TCS blocks.
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The offset of the TCS blocks.
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qcom,tcs-distance:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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The distance between each TCS for a DRV.
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reg:
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reg:
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minItems: 1
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minItems: 1
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maxItems: 4
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maxItems: 4
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@@ -149,6 +154,7 @@ examples:
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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label = "apps_rsc";
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label = "apps_rsc";
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qcom,tcs-offset = <0xd00>;
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qcom,tcs-offset = <0xd00>;
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qcom,tcs-distance= <0x150>;
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qcom,drv-id = <2>;
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qcom,drv-id = <2>;
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qcom,tcs-config = <ACTIVE_TCS 2>,
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qcom,tcs-config = <ACTIVE_TCS 2>,
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<SLEEP_TCS 3>,
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<SLEEP_TCS 3>,
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@@ -173,6 +179,7 @@ examples:
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interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
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label = "disp_rsc";
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label = "disp_rsc";
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qcom,tcs-offset = <0x1c00>;
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qcom,tcs-offset = <0x1c00>;
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qcom,tcs-distance= <0x150>;
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qcom,drv-id = <0>;
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qcom,drv-id = <0>;
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qcom,tcs-config = <ACTIVE_TCS 0>,
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qcom,tcs-config = <ACTIVE_TCS 0>,
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<SLEEP_TCS 1>,
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<SLEEP_TCS 1>,
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104
qcom/sun.dtsi
104
qcom/sun.dtsi
@@ -34,7 +34,7 @@
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chosen: chosen {
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chosen: chosen {
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bootargs = "nokaslr kpti=0 log_buf_len=256K swiotlb=0 loop.max_part=7 pcie_ports=compat mem-offline.bypass_send_msg=1";
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bootargs = "nokaslr kpti=0 log_buf_len=256K swiotlb=0 loop.max_part=7 pcie_ports=compat mem-offline.bypass_send_msg=1 cpuidle.off=1";
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stdout-path = "/soc/qcom,qupv3_1_geni_se@ac0000/qcom,qup_uart@a9c000:115200n8";
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stdout-path = "/soc/qcom,qupv3_1_geni_se@ac0000/qcom,qup_uart@a9c000:115200n8";
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};
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};
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@@ -956,6 +956,7 @@
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apps_rsc_drv2: drv@2 {
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apps_rsc_drv2: drv@2 {
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qcom,drv-id = <2>;
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qcom,drv-id = <2>;
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qcom,tcs-offset = <0xd00>;
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qcom,tcs-offset = <0xd00>;
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qcom,tcs-distance = <0x2a0>;
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channel@0 {
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channel@0 {
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qcom,tcs-config = <ACTIVE_TCS 3>,
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qcom,tcs-config = <ACTIVE_TCS 3>,
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<SLEEP_TCS 2>,
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<SLEEP_TCS 2>,
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@@ -981,6 +982,107 @@
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};
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};
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};
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};
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cam_rsc: rsc@adc8000 {
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label = "cam_rsc";
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compatible = "qcom,rpmh-rsc";
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reg = <0xadc8000 0x1000>,
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<0xadc9000 0x1000>,
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<0xadca000 0x1000>;
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reg-names = "drv-0", "drv-1", "drv-2";
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qcom,drv-count = <3>;
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qcom,hw-channel;
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interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&camcc CAM_CC_DRV_AHB_CLK>;
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cam_rsc_drv0: drv@0 {
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qcom,drv-id = <0>;
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qcom,tcs-offset = <0x520>;
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qcom,tcs-distance = <0x150>;
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channel@0 {
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qcom,tcs-config = <ACTIVE_TCS 0>,
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<WAKE_TCS 1>,
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<SLEEP_TCS 1>,
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<CONTROL_TCS 0>,
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<FAST_PATH_TCS 0>;
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};
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channel@1 {
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qcom,tcs-config = <ACTIVE_TCS 0>,
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<WAKE_TCS 1>,
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<SLEEP_TCS 1>,
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<CONTROL_TCS 0>,
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<FAST_PATH_TCS 0>;
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};
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};
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cam_rsc_drv1: drv@1 {
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qcom,drv-id = <1>;
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qcom,tcs-offset = <0x520>;
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qcom,tcs-distance = <0x150>;
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channel@0 {
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qcom,tcs-config = <ACTIVE_TCS 0>,
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<WAKE_TCS 1>,
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<SLEEP_TCS 1>,
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<CONTROL_TCS 0>,
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<FAST_PATH_TCS 0>;
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};
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channel@1 {
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qcom,tcs-config = <ACTIVE_TCS 0>,
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<WAKE_TCS 1>,
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<SLEEP_TCS 1>,
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<CONTROL_TCS 0>,
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<FAST_PATH_TCS 0>;
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};
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};
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cam_rsc_drv2: drv@2 {
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qcom,drv-id = <2>;
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qcom,tcs-offset = <0x520>;
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qcom,tcs-distance = <0x150>;
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channel@0 {
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qcom,tcs-config = <ACTIVE_TCS 0>,
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<WAKE_TCS 1>,
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<SLEEP_TCS 1>,
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<CONTROL_TCS 0>,
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<FAST_PATH_TCS 0>;
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};
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channel@1 {
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qcom,tcs-config = <ACTIVE_TCS 0>,
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<WAKE_TCS 1>,
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<SLEEP_TCS 1>,
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<CONTROL_TCS 0>,
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<FAST_PATH_TCS 0>;
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};
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};
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};
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disp_rsc: rsc@af20000 {
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label = "disp_rsc";
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compatible = "qcom,rpmh-rsc";
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reg = <0xaf20000 0x10000>;
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reg-names = "drv-0";
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qcom,drv-count = <1>;
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interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
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disp_rsc_drv0: drv@0 {
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qcom,drv-id = <0>;
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qcom,tcs-offset = <0x520>;
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qcom,tcs-distance = <0x150>;
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channel@0 {
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qcom,tcs-config = <ACTIVE_TCS 0>,
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<SLEEP_TCS 1>,
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<WAKE_TCS 1>,
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<CONTROL_TCS 0>,
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<FAST_PATH_TCS 0>;
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};
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};
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};
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cam_crm: crm@adcb000 {
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cam_crm: crm@adcb000 {
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label = "cam_crm";
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label = "cam_crm";
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compatible = "qcom,cam-crm-v2";
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compatible = "qcom,cam-crm-v2";
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