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ARM: dts: msm: Initial commit for Adreno GPU

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Add initial Adreno GPU devicetree files.

Change-Id: I460cc1d37a49b2b92d55fd6426d51bcb629fcdf5
Signed-off-by: Hareesh Gundu <quic_hareeshg@quicinc.com>
This commit is contained in:
Hareesh Gundu
2023-08-23 17:01:48 -07:00
parent 994933d50b
commit 63075d8f63
13 changed files with 2046 additions and 0 deletions
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Kbuild Normal file
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ifeq ($(CONFIG_ARCH_PINEAPPLE), y)
dtbo-y += gpu/pineapple-gpu.dtbo \
gpu/pineapple-v2-gpu.dtbo
endif
always-y := $(dtb-y) $(dtbo-y)
subdir-y := $(dts-dirs)
clean-files := *.dtb *.dtbo

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KBUILD_OPTIONS+=KBUILD_EXTMOD_DTS=.
all: dtbs
clean:
$(MAKE) -C $(KERNEL_SRC) M=$(M) clean
%:
$(MAKE) -C $(KERNEL_SRC) M=$(M) $@ $(KBUILD_OPTIONS)

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Adreno bus monitor device
kgsl-busmon is a pseudo device that represents a devfreq bus bandwidth
governor. If this device is present then two different governors are used
for GPU DCVS and bus DCVS.
Required properties:
- compatible: Must be "qcom,kgsl-busmon"
- label: Device name used for sysfs entry.
Example:
qcom,kgsl-busmon {
compatible = "qcom,kgsl-busmon";
label = "kgsl-busmon";
};

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bindings/adreno-gmu.txt Normal file
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Qualcomm Technologies, Inc. GPU Graphics Management Unit (GMU)
Required properties:
- compatible :
- "qcom,gpu-gmu"
- "qcom,gpu-gmu-hwsched"
- "qcom,gpu-rgmu"
- "qcom,gen7-gmu"
- "qcom,gen7-gmu-hwsched"
- reg: Specifies the GMU register base address and size.
- reg-names: Resource names used for the physical address
and length of GMU registers.
- interrupts: Interrupt mapping for GMU and HFI IRQs.
- interrupt-names: String property to describe the name of each interrupt.
Bus Scaling Data:
qcom,msm-bus,name: String property to describe the name of bus client.
qcom,msm-bus,num-cases: This is the the number of Bus Scaling use cases defined in the vectors property.
qcom,msm-bus,num-paths: This represents the number of paths in each Bus Scaling Usecase.
qcom,msm-bus,vectors-KBps: A series of 4 cell properties, format of which is:
<src dst ab ib>, <src dst ab ib>, // For Bus Scaling Usecase 1
<src dst ab ib>, <src dst ab ib>, // For Bus Scaling Usecase 2
<.. .. .. ..>, <.. .. .. ..>; // For Bus Scaling Usecase n
This property is a series of all vectors for all Bus Scaling Usecases.
Each set of vectors for each usecase describes bandwidth votes for a combination
of src/dst ports. The driver will set the desired use case based on the selected
power level and the desired bandwidth vote will be registered for the port pairs.
GMU GDSC/regulators:
- regulator-names: List of regulator name strings
- vddcx-supply: Phandle for vddcx regulator device node.
- vdd-supply: Phandle for vdd regulator device node.
- clock: List of clocks to be used for GMU register access and DCVS. See
Documentation/devicetree/bindings/clock/clock-bindings.txt
for information about the format. For each clock specified
here, there must be a corresponding entry in clock-names
(see below).
- clock-names: List of clock names corresponding to the clocks specified in
the "clocks" property (above). See
Documentation/devicetree/bindings/clock/clock-bindings.txt
for more info. Currently GMU required these clock names:
"gmu_clk", "ahb_clk", "cxo_clk", "axi_clk", "memnoc_clk",
"rbcpr_clk"
- qcom,gmu-freq-table: List of frequencies the GMU clock can run at with their corresponding
voltage levels.
- List of sub nodes, one for each of the translation context banks needed
for GMU to access system memory in different operating mode. Currently
supported names are:
- gmu_user: used for GMU 'user' mode address space.
- gmu_kernel: used for GMU 'kernel' mode address space.
Each sub node has the following required properties:
- compatible : "qcom,smmu-gmu-user-cb" or "qcom,smmu-gmu-kernel-cb"
- iommus : Specifies the SID's used by this context bank, this
needs to be <kgsl_smmu SID> pair, kgsl_smmu is the string
parsed by iommu driver to match this context bank with the
kgsl_smmu device defined in iommu device tree. On targets
where the msm iommu driver is used rather than the arm smmu
driver, this property may be absent.
- qcom,ipc-core: <baseAddr size>
baseAddr - base address of the IPC region
size - size of the IPC region
Example:
gmu: qcom,gmu@2c6a000 {
label = "kgsl-gmu";
compatible = "qcom,gpu-gmu";
reg = <0x2c6a000 0x30000>;
reg-names = "kgsl_gmu_reg";
interrupts = <0 304 0>, <0 305 0>;
interrupt-names = "kgsl_gmu_irq", "kgsl_hfi_irq";
qcom,msm-bus,name = "cnoc";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<26 10036 0 0>, // CNOC off
<26 10036 0 100>; // CNOC on
regulator-name = "vddcx", "vdd";
vddcx-supply = <&gpu_cx_gdsc>;
vdd-supply = <&gpu_gx_gdsc>;
clocks = <&clock_gpugcc clk_gcc_gmu_clk>,
<&clock_gcc GCC_GPU_CFG_AHB_CLK>,
<&clock_gpucc GPU_CC_CXO_CLK>,
<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,
<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
<&clock_gpucc GPU_CC_RBCPR_CLK>;
clock-names = "gmu_clk", "ahb_clk", "cxo_clk",
"axi_clk", "memnoc_clk", "rbcpr_clk";
qcom,gmu-freq-table = <200000000 RPMH_REGULATOR_LEVEL_LOW_SVS>,
<500000000 RPMH_REGULATOR_LEVEL_SVS>;
gmu_user: gmu_user {
compatible = "qcom,smmu-gmu-user-cb";
iommus = <&kgsl_smmu 4>;
};
gmu_kernel: gmu_kernel {
compatible = "qcom,smmu-gmu-kernel-cb";
iommus = <&kgsl_smmu 5>;
};
};

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Qualcomm Technologies, Inc. GPU IOMMU
Required properties:
Required properties:
- compatible : one of:
- "qcom,kgsl-smmu-v1"
- "qcom,kgsl-smmu-v2"
- reg : Base address and size of the SMMU.
- clocks : List of clocks to be used during SMMU register access. See
Documentation/devicetree/bindings/clock/clock-bindings.txt
for information about the format. For each clock specified
here, there must be a corresponding entry in clock-names
(see below).
- clock-names : List of clock names corresponding to the clocks specified in
the "clocks" property (above). See
Documentation/devicetree/bindings/clock/clock-bindings.txt
for more info.
- qcom,protect : The GPU register region which must be protected by a CP
protected mode. On some targets this region must cover
the entire SMMU register space, on others there
is a separate aperture for CP to program context banks.
Optional properties:
- qcom,retention : A boolean specifying if retention is supported on this target
- qcom,global_pt : A boolean specifying if global pagetable should be used.
When not set we use per process pagetables
- qcom,hyp_secure_alloc : A bool specifying if the hypervisor is used on this target
for secure buffer allocation
- List of sub nodes, one for each of the translation context banks supported.
The driver uses the names of these nodes to determine how they are used,
currently supported names are:
- gfx3d_user : Used for the 'normal' GPU address space.
- gfx3d_secure : Used for the content protection address space.
- gfx3d_secure_alt : Used for the content protection address space for alternative SID.
Each sub node has the following required properties:
- compatible : "qcom,smmu-kgsl-cb"
- iommus : Specifies the SID's used by this context bank, this needs to be
<kgsl_smmu SID> pair, kgsl_smmu is the string parsed by iommu
driver to match this context bank with the kgsl_smmu device
defined in iommu device tree. On targets where the msm iommu
driver is used rather than the arm smmu driver, this property
may be absent.
Example:
msm_iommu: qcom,kgsl-iommu@2ca0000 {
compatible = "qcom,kgsl-smmu-v2";
reg = <0x2ca0000 0x10000>;
qcom,protect = <0xa0000 0xc000>;
clocks = <&clock_mmss clk_gpu_ahb_clk>,
<&clock_gcc clk_gcc_mmss_bimc_gfx_clk>,
<&clock_mmss clk_mmss_mmagic_ahb_clk>,
<&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>;
clock-names = "gpu_ahb_clk", "bimc_gfx_clk", "mmagic_ahb_clk", "mmagic_cfg_ahb_clk";
qcom,secure_align_mask = <0xfff>;
qcom,retention;
qcom,global_pt;
gfx3d_user: gfx3d_user {
compatible = "qcom,smmu-kgsl-cb";
iommus = <&kgsl_smmu 0>,
<&kgsl_smmu 1>;
};
gfx3d_secure: gfx3d_secure {
compatible = "qcom,smmu-kgsl-cb";
iommus = <&kgsl_smmu 2>;
};
gfx3d_secure_alt: gfx3d_secure_alt {
compatible = "qcom,smmu-kgsl-cb";
iommus = <&kgsl_smmu 2>, <&kgsl_smmu 1>;
};
};

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Qualcomm Technologies, Inc. GPU powerlevels
Powerlevels are defined in sets by qcom,gpu-pwrlevels. Multiple sets (bins)
can be defined within qcom,gpu-pwrelvel-bins. Each powerlevel defines a
voltage, bus, bandwidth level, and a DVM value.
- qcom,gpu-pwrlevel-bins: Contains one or more qcom,gpu-pwrlevels sets
Properties:
- compatible: Must be qcom,gpu-pwrlevel-bins
- qcom,gpu-pwrlevels: Defines a set of powerlevels
Properties:
- qcom,speed-bin: Speed bin identifier for the set - if present
must match the value read from the hardware
- qcom,sku-codes: List of SKU versions specified by P-Code and
Feature Code that can support this set of
powerlevels. An entry of 0 in this list matches
any SKU and can be used as a fallback if other
powerlevel sets are not matched
- qcom,initial-pwrlevel: GPU wakeup powerlevel
- qcom,initial-min-pwrlevel: Initial minimum available GPU powerlevel
- qcom,gpu-pwrlevel: A single powerlevel
- qcom,ca-target-pwrlevel:
This value indicates which qcom,gpu-pwrlevel
to jump on in case of context aware power level
jump.
Required Properties:
- reg: Index of the powerlevel (0 = highest perf)
- qcom,gpu-freq GPU frequency for the powerlevel (in Hz)
- qcom,bus-freq Index to a bus level (defined by the bus
settings).
- qcom,bus-freq-ddrX If specified, define the DDR specific bus
frequency for the power level. X will be the
return value from of_fdt_get_ddrtype().
Optional Properties:
- qcom,bus-min Minimum bus level to set for the power level
- qcom,bus-min-ddrX If specified, define the DDR specific minimum
bus level for the power level. X will be the
return value from of_fdt_get_ddrtype().
- qcom,bus-max maximum bus level to set for the power level
- qcom,bus-max-ddrX If specified, define the DDR specific maximum
bus level for the power level. X will be the
return value from of_fdt_get_ddrtype().
- qcom,acd-level: Value that is used as a register setting for
the ACD power feature. It helps to determine
the threshold for when ACD activates. Zero is
the default value, and the setting where ACD
will never activate.
- qcom,cx-level: Specifies the CX vote required for each GPU power
level.
Example:
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <0>;
qcom,bus-freq = <0>;
qcom,bus-min = <0>;
qcom,bus-max = <0>;
qcom,acd-level = <0xffffffff>;
qcom,cx-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
};
Example for DDR4/DDR5 specific part:
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <480000000>;
qcom,cx-level = <RPMH_REGULATOR_LEVEL_SVS>;
/* DDR5 */
qcom,bus-freq-ddr8 = <10>;
qcom,bus-min-ddr8 = <9>;
qcom,bus-max-ddr8 = <11>;
/* DDR 4 */
qcom,bus-freq-ddr7 = <9>;
qcom,bus-min-ddr7 = <7>;
qcom,bus-max-ddr7 = <9>;
qcom,acd-level = <0xffffffff>;
};

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Qualcomm Technologies, Inc. GPU
Qualcomm Technologies, Inc. Adreno GPU
Required properties:
- compatible: Must be "qcom,kgsl-3d0".
May also includes "qcom,adreno-gpu-*" for few targets.
Must include "qcom,adreno-gpu-a619-holi" for Holi target.
Must include "qcom,adreno-gpu-a621" for Neo target.
Must include "qcom,adreno-gpu-a660-shima" for Shima target.
Must include "qcom,adreno-gpu-gen7-0-0" for Waipio target.
Must include "qcom,adreno-gpu-gen7-0-1" for Waipio V2 target.
Must include "qcom,adreno-gpu-gen7-2-0" for Kalama target.
Must include "qcom,adreno-gpu-gen7-2-1" for Kalama V2 target.
Must include "qcom,adreno-gpu-gen7-4-0" for Cape target.
Must include "qcom,adreno-gpu-gen7-3-0" for Parrot target.
Must include "qcom,adreno-gpu-gen7-9-0" for Pineapple target.
Must include "qcom,adreno-gpu-gen7-9-1" for Pineapple V2 target.
- reg: Specifies the list of register regions for the device.
- reg-names: Resource names used for the register regions specified
in reg.
- interrupts: Interrupt mapping for GPU nterrupts.
- interrupt-names: String property to describe the names of the interrupts.
- qcom,gpu-bimc-interface-clk-freq:
GPU-BIMC interface clock needs to set to this value for
targets where B/W requirements does not meet GPU Turbo
use cases.
- clocks: List of phandle and clock specifier pairs, one pair
for each clock input to the device.
- clock-names: List of clock input name strings sorted in the same
order as the clocks property.
- qcom,base-leakage-coefficient: Dynamic leakage coefficient.
- qcom,lm-limit: Current limit for GPU limit management.
- qcom,isense-clk-on-level: below or equal this power level isense clock is at XO rate,
above this powerlevel isense clock is at working frequency.
Bus Scaling Data:
- qcom,gpu-bus-table: Defines a bus voting table with the below properties. Multiple sets of bus
voting tables can be defined for given platform based on the type of ddr system.
Properties:
- compatible: Must be "qcom,gpu-bus-table". Additionally, "qcom,gpu-bus-table-ddr" must also
be provided, with the ddr type value(integer) appended to the string.
- qcom,msm-bus,name: String property to describe the name of the 3D graphics processor.
- qcom,msm-bus,num-cases: This is the the number of Bus Scaling use cases defined in the vectors property.
- qcom,msm-bus,active-only: A boolean flag indicating if it is active only.
- qcom,msm-bus,num-paths: This represents the number of paths in each Bus Scaling Usecase.
- qcom,msm-bus,vectors-KBps: A series of 4 cell properties, format of which is:
<src dst ab ib>, <src dst ab ib>, // For Bus Scaling Usecase 1
<src dst ab ib>, <src dst ab ib>, // For Bus Scaling Usecase 2
<.. .. .. ..>, <.. .. .. ..>; // For Bus Scaling Usecase n
This property is a series of all vectors for all Bus Scaling Usecases.
Each set of vectors for each usecase describes bandwidth votes for a combination
of src/dst ports. The driver will set the desired use case based on the selected
power level and the desired bandwidth vote will be registered for the port pairs.
Current values of src are:
0 = MSM_BUS_MASTER_GRAPHICS_3D
1 = MSM_BUS_MASTER_GRAPHICS_3D_PORT1
2 = MSM_BUS_MASTER_V_OCMEM_GFX3D
Current values of dst are:
0 = MSM_BUS_SLAVE_EBI_CH0
1 = MSM_BUS_SLAVE_OCMEM
ab: Represents aggregated bandwidth. This value is 0 for Graphics.
ib: Represents instantaneous bandwidth. This value has a range <0 8000 MB/s>
- qcom,ocmem-bus-client: Container for another set of bus scaling properties
qcom,msm-bus,name
qcom,msm-bus,num-cases
qcom,msm-bus,num-paths
qcom,msm-bus,vectors-KBps
to be used by ocmem msm bus scaling client.
GDSC Oxili Regulators:
- regulator-names: List of regulator name strings sorted in power-on order
- vddcx-supply: Phandle for vddcx regulator device node.
- vdd-supply: Phandle for vdd regulator device node.
IOMMU Data:
- iommu: Phandle for the KGSL IOMMU device node
GPU Power levels:
- qcom,gpu-pwrlevel-bins: Container for sets of GPU power levels (see
adreno-pwrlevels.txt)
DCVS Core info
- qcom,dcvs-core-info Container for the DCVS core info (see
dcvs-core-info.txt)
Optional Properties:
- qcom,initial-powerlevel: This value indicates which qcom,gpu-pwrlevel should be used at start time
and when coming back out of resume
- qcom,throttle-pwrlevel: This value indicates which qcom,gpu-pwrlevel LM throttling
may start to occur
- qcom,bus-control: Boolean. Enables an independent bus vote from the gpu frequency
- qcom,bus-width: Bus width in number of bytes. This enables dynamic AB bus voting based on
bus width and actual bus transactions.
- qcom,bus-accesses: Parameter for tuning bus dcvs.
- qcom,bus-accesses-ddrX: Parameter for tuning bus dcvs for each DDR configuration where
X will be the return value from of_fdt_get_ddrtype().
- qcom,gpubw-dev: a phandle to a device representing bus bandwidth requirements
(see devdw.txt)
- qcom,idle-timeout: This property represents the time in milliseconds for idle timeout.
- qcom,no-nap: If it exists software clockgating will be disabled at boot time.
- qcom,chipid: If it exists this property is used to replace
the chip identification read from the GPU hardware.
This is used to override faulty hardware readings.
- qcom,gpu-model: If it exists this property is used for GPU model name.
- qcom,vk-device-id: If it exists this property is used to specify vulkan device ID.
- qcom,disable-wake-on-touch: Boolean. Disables the GPU power up on a touch input event.
- qcom,disable-busy-time-burst:
Boolean. Disables the busy time burst to avoid switching
of power level for large frames based on the busy time limit.
- qcom,pm-qos-active-latency:
Right after GPU wakes up from sleep, driver votes for
acceptable maximum latency to the pm-qos driver. This
voting demands that the system can not go into any
power save state *if* the latency to bring system back
into active state is more than this value.
Value is in microseconds.
- qcom,pm-qos-wakeup-latency:
Similar to the above. Driver votes against deep low
power modes right before GPU wakes up from sleep.
- qcom,l2pc-cpu-mask-latency:
The CPU mask latency in microseconds to avoid L2PC
on masked CPUs.
- qcom,gpu-cx-ipeak:
CX Ipeak is a mitigation scheme which throttles cDSP frequency
if all the clients are running at their respective threshold
frequencies to limit CX peak current.
<phandle bit>
phandle - phandle of CX Ipeak device node
bit - Every bit corresponds to a client of CX Ipeak
driver in the relevant register.
- qcom, gpu-cx-ipeak-freq:
GPU frequency threshold for CX Ipeak voting. GPU votes
to CX Ipeak driver when GPU clock crosses this threshold.
CX Ipeak can limit peak current based on voting from other clients.
- qcom,force-32bit:
Force the GPU to use 32 bit data sizes even if
it is capable of doing 64 bit.
- qcom,gpu-speed-bin: GPU speed bin information in the format
<offset mask shift>
offset - offset of the efuse register from the base.
mask - mask for the relevant bits in the efuse register.
shift - number of bits to right shift to get the speed bin
value.
- qcom,gpu-disable-fuse: GPU disable fuse
<offset mask shift>
offset - offset of the efuse register from the base.
mask - mask for the relevant bits in the efuse register.
shift - number of bits to right shift to get the disable_gpu
fuse bit value.
- qcom,soc-hw-rev-efuse: SOC hardware revision fuse information in the format
<offset bit_position mask>
offset - offset of the efuse register from the base.
bit_position - hardware revision starting bit in the efuse register.
mask - mask for the relevant bits in the efuse register.
- qcom,highest-bank-bit:
Specify the bit of the highest DDR bank. This
is programmed into protected registers and also
passed to the user as a property.
- qcom,min-access-length:
Specify the minimum access length for the chip.
Either 32 or 64 bytes.
Based on the above options, program the appropriate bit into
certain protected registers and also pass to the user as
a property.
- qcom,ubwc-mode:
Specify the ubwc mode for this chip.
1: UBWC 1.0
2: UBWC 2.0
3: UBWC 3.0
Based on the ubwc mode, program the appropriate bit into
certain protected registers and also pass to the user as
a property.
- qcom,l2pc-cpu-mask:
Disables L2PC on masked CPUto the string.rendering thread is running on masked CPUs.
Bit 0 is for CPU-0, bit 1 is for CPU-1...
- qcom,l2pc-update-queue:
Disables L2PC on masked CPUs at queue time when it's true.
- qcom,snapshot-size:
Specify the size of snapshot in bytes. This will override
snapshot size defined in the driver code.
- qcom,enable-ca-jump:
Boolean. Enables use of context aware DCVS
- qcom,ca-busy-penalty:
This property represents the time in microseconds required to
initiate context aware power level jump.
- qcom,ca-target-pwrlevel:
This value indicates which qcom,gpu-pwrlevel to jump on in case
of context aware power level jump.
- qcom,gpu-qdss-stm:
<baseAddr size>
baseAddr - base address of the gpu channels in the qdss stm memory region
size - size of the gpu stm region
- qcom,gpu-timer:
<baseAddr size>
baseAddr - base address of the qtimer memory region
size - size of the qtimer region
- qcom,tzone-names:
Specify the names of GPU thermal zones. These will be used
to get gpu temperature from the thermal driver API.
nvmem-cells:
A phandle to the configuration data such as gpu speed bin, gpu gaming mode,
gpu model name provided by a nvmem device. If unspecified default values shall be used.
nvmem-cell-names:
Should be "speed_bin", "gaming_bin", "gpu_model"
GPU Quirks:
- qcom,gpu-quirk-two-pass-use-wfi:
Signal the GPU to set Set TWOPASSUSEWFI bit in
PC_DBG_ECO_CNTL (5XX and 6XX only)
- qcom,gpu-quirk-critical-packets:
Submit a set of critical PM4 packets when the GPU wakes up
- qcom,gpu-quirk-fault-detect-mask:
Mask out RB1-3 activity signals from HW hang
detection logic
- qcom,gpu-quirk-dp2clockgating-disable:
Disable RB sampler data path clock gating optimization
- qcom,gpu-quirk-lmloadkill-disable:
Use register setting to disable local memory(LM) feature
to avoid corner case error
- qcom,gpu-quirk-hfi-use-reg:
Use registers to replace DCVS HFI message to avoid GMU failure
to access system memory during IFPC
- qcom,gpu-quirk-limit-uche-gbif-rw:
Limit number of read and write transactions from UCHE block to
GBIF to avoid possible deadlock between GBIF, SMMU and MEMNOC.
- qcom,gpu-quirk-mmu-secure-cb-alt:
Select alternate secure context bank to generate SID1 for
secure playback.
KGSL Memory Pools:
- qcom,gpu-mempools: Container for sets of GPU mempools.Multiple sets
(pools) can be defined within qcom,gpu-mempools.
Each mempool defines a pool order, reserved pages,
allocation allowed.
Properties:
- compatible: Must be qcom,gpu-mempools.
- qcom,mempool-max-pages: Max pages for all mempools, If not defined there is no limit.
- qcom,gpu-mempool: Defines a set of mempools.
Properties:
- reg: Index of the pool (0 = lowest pool order).
- qcom,mempool-page-size: Size of page.
- qcom,mempool-reserved: Number of pages reserved at init time for a pool.
- qcom,mempool-allocate: Allocate memory from the system memory when the
reserved pool exhausted.
- qcom,mempool-max-pages: Limit on max pages this pool can hold, If not defined
there is no limit.
GPU model configuration:
- qcom,gpu-models:
Container of sets of GPU model names specified by qcom,gpu-models.
Properties:
- compatible:
Must be qcom,gpu-models.
- qcom,gpu-model:
Defines a GPU model name for specific GPU model ID.
Properties:
- compatible:
May also include "qcom,adreno-gpu-*" for few targets.
- qcom,gpu-model-id:
Identifier for the specific GPU hardware configuration - must match the value read
from the hardware.
- qcom,gpu-model:
GPU model name for a specific GPU hardware.
- qcom,vk-device-id:
Vulkan device id unique for specific GPU hardware model.
SOC Hardware revisions:
- qcom,soc-hw-revisions:
Container of sets of SOC hardware revisions specified by
qcom,soc-hw-revision.
Properties:
- compatible:
Must be qcom,soc-hw-revisions.
- qcom,soc-hw-revision:
Defines a SOC hardware revision.
Properties:
- qcom,soc-hw-revision:
Identifier for the hardware revision - must match the value read
from the hardware.
- qcom,chipid:
GPU Chip ID to be used for this hardware revision.
- qcom,gpu-quirk-*:
GPU quirks applicable for this hardware revision.
GPU LLC slice info:
- cache-slice-names: List of LLC cache slices for GPU transactions
and pagetable walk.
- cache-slices: phandle to the system LLC driver, cache slice index.
L3 Power levels:
- qcom,l3-pwrlevels: Container for sets of L3 power levels, the
L3 frequency is adjusted according to the
performance hint received from userspace.
Properties:
- compatible: Must be qcom,l3-pwrlevels
- qcom,l3-pwrlevel: A single L3 powerlevel
Properties:
- reg: Index of the L3 powerlevel
0 = powerlevel for no L3 vote
1 = powerlevel for medium L3 vote
2 = powerlevel for maximum L3 vote
- qcom,l3-freq: The L3 frequency for the powerlevel (in Hz)
GPU coresight info:
The following properties are optional as collecting data via coresight might
not be supported for every chipset. The documentation for coresight
properties can be found in:
Documentation/devicetree/bindings/coresight/coresight.txt
- qcom,gpu-coresights: Container for sets of GPU coresight sources.
- coresight-id: Unique integer identifier for the bus.
- coresight-name: Unique descriptive name of the bus.
- coresight-nr-inports: Number of input ports on the bus.
- coresight-outports: List of output port numbers on the bus.
- coresight-child-list: List of phandles pointing to the children of this
component.
- coresight-child-ports: List of input port numbers of the children.
- coresight-atid: The unique ATID value of the coresight device
Example of A330 GPU in MSM8916:
&soc {
msm_gpu: qcom,kgsl-3d0@1c00000 {
label = "kgsl-3d0";
compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
reg = <0x1c00000 0x10000
0x1c20000 0x20000>;
reg-names = "kgsl_3d0_reg_memory" , "kgsl_3d0_shader_memory";
interrupts = <0 33 0>;
interrupt-names = "kgsl_3d0_irq";
qcom,id = <0>;
qcom,chipid = <0x03000600>;
qcom,initial-pwrlevel = <1>;
/* Idle Timeout = HZ/12 */
qcom,idle-timeout = <8>;
qcom,strtstp-sleepwake;
clocks = <&clock_gcc clk_gcc_oxili_gfx3d_clk>,
<&clock_gcc clk_gcc_oxili_ahb_clk>,
<&clock_gcc clk_gcc_oxili_gmem_clk>,
<&clock_gcc clk_gcc_bimc_gfx_clk>,
<&clock_gcc clk_gcc_bimc_gpu_clk>;
clock-names = "core_clk", "iface_clk", "mem_clk",
"mem_iface_clk", "alt_mem_iface_clk";
/* Bus Scale Settings */
qcom, gpu-bus-table {
compatible="qcom,gpu-bus-table","qcom,gpu-bus-table-ddr7";
qcom,msm-bus,name = "grp3d";
qcom,msm-bus,num-cases = <4>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<26 512 0 0>,
<26 512 0 1600000>,
<26 512 0 3200000>,
<26 512 0 4264000>;
};
/* GDSC oxili regulators */
vdd-supply = <&gdsc_oxili_gx>;
nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>, <&gpu_model_bin>;
nvmem-cell-names = "speed_bin", "gaming_bin","gpu_model";
/* IOMMU Data */
iommu = <&gfx_iommu>;
/* Trace bus */
coresight-id = <67>;
coresight-name = "coresight-gfx";
coresight-nr-inports = <0>;
coresight-outports = <0>;
coresight-child-list = <&funnel_in0>;
coresight-child-ports = <5>;
/* Enable context aware freq. scaling */
qcom,enable-ca-jump;
/* Context aware jump busy penalty in us */
qcom,ca-busy-penalty = <12000>;
/* Context aware jump target power level */
qcom,ca-target-pwrlevel = <1>;
qcom,soc-hw-revisions {
#address-cells = <1>;
#size-cells = <0>;
compatible="qcom,soc-hw-revisions";
qcom,soc-hw-revision@0 {
reg = <0>;
qcom,chipid = <0x06010500>;
qcom,gpu-quirk-hfi-use-reg;
qcom,gpu-quirk-limit-uche-gbif-rw;
};
qcom,soc-hw-revision@1 {
reg = <1>;
qcom,chipid = <0x06010501>;
qcom,gpu-quirk-hfi-use-reg;
};
};
qcom,gpu-models {
#address-cells = <1>;
#size-cells = <0>;
compatible="qcom,gpu-models";
qcom,gpu-model@0 {
compatible="qcom,adreno-gpu-a642l";
qcom,gpu-model-id = <0>;
qcom,gpu-model = "Adreno642Lv1";
qcom,vk-device-id= <0x06030500>;
};
qcom,gpu-model@1 {
compatible="qcom,adreno-gpu-a645";
qcom,gpu-model-id = <190>;
qcom,gpu-model = "Adreno645";
qcom,vk-device-id= <0x06030500>;
};
}
/* GPU Mempools */
qcom,gpu-mempools {
#address-cells= <1>;
#size-cells = <0>;
compatible = "qcom,gpu-mempools";
/* 4K Page Pool configuration */
qcom,gpu-mempool@0 {
reg = <0>;
qcom,mempool-page-size = <4096>;
qcom,mempool-reserved = <2048>;
qcom,mempool-allocate;
};
/* 8K Page Pool configuration */
qcom,gpu-mempool@1 {
reg = <1>;
qcom,mempool-page-size = <8192>;
qcom,mempool-reserved = <1024>;
qcom,mempool-allocate;
};
/* 64K Page Pool configuration */
qcom,gpu-mempool@2 {
reg = <2>;
qcom,mempool-page-size = <65536>;
qcom,mempool-reserved = <256>;
};
/* 1M Page Pool configuration */
qcom,gpu-mempool@3 {
reg = <3>;
qcom,mempool-page-size = <1048576>;
qcom,mempool-reserved = <32>;
};
};
/* Power levels */
qcom,gpu-pwrlevels-bins {
#address-cells = <1>;
#size-cells = <0>;
qcom,gpu-pwrlevels-0 {
#address-cells = <1>;
#size-cells = <0>;
qcom,speed-bin = <0>;
qcom,ca-target-pwrlevel = <1>;
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <400000000>;
qcom,bus-freq = <3>;
qcom,io-fraction = <33>;
};
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <310000000>;
qcom,bus-freq = <2>;
qcom,io-fraction = <66>;
};
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <200000000>;
qcom,bus-freq = <1>;
qcom,io-fraction = <100>;
};
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <27000000>;
qcom,bus-freq = <0>;
qcom,io-fraction = <0>;
};
};
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/* ACD Control register values */
#define ACD_LEVEL_TURBO_L1 0x882f5ffd
#define ACD_LEVEL_TURBO 0x882f5ffd
#define ACD_LEVEL_NOM_L1 0x882f5ffd
#define ACD_LEVEL_NOM 0xc0285ffd
#define ACD_LEVEL_SVS_L2 0xe0295ffd
#define ACD_LEVEL_SVS_L1 0xe0295ffd
#define ACD_LEVEL_SVS_L0 0xc02a5ffd
#define ACD_LEVEL_SVS 0xc02a5ffd
#define ACD_LEVEL_LOW_SVS_L1 0xc02c5ffd
#define ACD_LEVEL_LOW_SVS 0xc02f5ffd
#define ACD_LEVEL_LOW_SVS_D0 0xc02f5ffd
&msm_gpu {
/* Power levels */
qcom,gpu-pwrlevel-bins {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,gpu-pwrlevels-bins";
qcom,gpu-pwrlevels-0 {
#address-cells = <1>;
#size-cells = <0>;
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_AC)>;
qcom,speed-bin = <2>;
qcom,initial-pwrlevel = <12>;
/* Turbo_L1 */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <903000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
qcom,bus-freq = <9>;
qcom,bus-min = <9>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_TURBO_L1>;
};
/* Turbo */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <869000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
qcom,bus-freq = <8>;
qcom,bus-min = <8>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_TURBO>;
};
/* Nom_L1 */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <834000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq = <8>;
qcom,bus-min = <7>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_NOM_L1>;
};
/* Nom */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <770000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <7>;
qcom,bus-min = <6>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_NOM>;
};
/* SVS_L2 */
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <720000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
qcom,bus-freq = <7>;
qcom,bus-min = <6>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
};
/* SVS_L1 */
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <680000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <7>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
};
/* SVS_L0 */
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <629000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
qcom,bus-freq = <6>;
qcom,bus-min = <4>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_SVS_L0>;
};
/* SVS */
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <578000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <5>;
qcom,bus-min = <4>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_SVS>;
};
/* Low_SVS_L1 */
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <500000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
qcom,bus-freq = <5>;
qcom,bus-min = <3>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_L1>;
};
/* Low_SVS */
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-freq = <422000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq = <5>;
qcom,bus-min = <3>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS>;
};
/* Low_SVS_D0 */
qcom,gpu-pwrlevel@10 {
reg = <10>;
qcom,gpu-freq = <366000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
qcom,bus-freq = <3>;
qcom,bus-min = <2>;
qcom,bus-max = <5>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D0>;
};
/* Low_SVS_D1 */
qcom,gpu-pwrlevel@11 {
reg = <11>;
qcom,gpu-freq = <310000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
qcom,bus-freq = <1>;
qcom,bus-min = <1>;
qcom,bus-max = <4>;
};
/* Low_SVS_D2 */
qcom,gpu-pwrlevel@12 {
reg = <12>;
qcom,gpu-freq = <231000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
qcom,bus-freq = <1>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
};
};
qcom,gpu-pwrlevels-1 {
#address-cells = <1>;
#size-cells = <0>;
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_AC)>;
qcom,initial-pwrlevel = <11>;
/* Turbo */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <869000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
qcom,bus-freq = <9>;
qcom,bus-min = <9>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_TURBO>;
};
/* Nom_L1 */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <834000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq = <8>;
qcom,bus-min = <7>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_NOM_L1>;
};
/* Nom */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <770000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <7>;
qcom,bus-min = <6>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_NOM>;
};
/* SVS_L2 */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <720000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
qcom,bus-freq = <7>;
qcom,bus-min = <6>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
};
/* SVS_L1 */
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <680000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <7>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
};
/* SVS_L0 */
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <629000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
qcom,bus-freq = <6>;
qcom,bus-min = <3>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_SVS_L0>;
};
/* SVS */
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <578000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <5>;
qcom,bus-min = <2>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_SVS>;
};
/* Low_SVS_L1 */
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <500000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
qcom,bus-freq = <5>;
qcom,bus-min = <1>;
qcom,bus-max = <5>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_L1>;
};
/* Low_SVS */
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <422000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq = <5>;
qcom,bus-min = <1>;
qcom,bus-max = <5>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS>;
};
/* Low_SVS_D0 */
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-freq = <366000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
qcom,bus-freq = <3>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D0>;
};
/* Low_SVS_D1 */
qcom,gpu-pwrlevel@10 {
reg = <10>;
qcom,gpu-freq = <310000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
qcom,bus-freq = <1>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
};
/* Low_SVS_D2 */
qcom,gpu-pwrlevel@11 {
reg = <11>;
qcom,gpu-freq = <231000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
qcom,bus-freq = <1>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
};
};
qcom,gpu-pwrlevels-2 {
#address-cells = <1>;
#size-cells = <0>;
qcom,sku-codes = <SKU_CODE(PCODE_0, FC_Y0)
SKU_CODE(PCODE_1, FC_Y0)
SKU_CODE(PCODE_0, FC_Y1)>;
qcom,initial-pwrlevel = <12>;
/* Turbo_L1 */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <903000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
qcom,bus-freq = <9>;
qcom,bus-min = <9>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_TURBO_L1>;
};
/* Turbo */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <869000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
qcom,bus-freq = <8>;
qcom,bus-min = <8>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_TURBO>;
};
/* Nom_L1 */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <834000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq = <8>;
qcom,bus-min = <7>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_NOM_L1>;
};
/* Nom */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <770000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <7>;
qcom,bus-min = <6>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_NOM>;
};
/* SVS_L2 */
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <720000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
qcom,bus-freq = <7>;
qcom,bus-min = <6>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
};
/* SVS_L1 */
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <680000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <7>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
};
/* SVS_L0 */
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <629000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
qcom,bus-freq = <6>;
qcom,bus-min = <3>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_SVS_L0>;
};
/* SVS */
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <578000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <5>;
qcom,bus-min = <2>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_SVS>;
};
/* Low_SVS_L1 */
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <500000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
qcom,bus-freq = <5>;
qcom,bus-min = <1>;
qcom,bus-max = <5>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_L1>;
};
/* Low_SVS */
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-freq = <422000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq = <5>;
qcom,bus-min = <1>;
qcom,bus-max = <5>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS>;
};
/* Low_SVS_D0 */
qcom,gpu-pwrlevel@10 {
reg = <10>;
qcom,gpu-freq = <366000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
qcom,bus-freq = <3>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D0>;
};
/* Low_SVS_D1 */
qcom,gpu-pwrlevel@11 {
reg = <11>;
qcom,gpu-freq = <310000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
qcom,bus-freq = <1>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
};
/* Low_SVS_D2 */
qcom,gpu-pwrlevel@12 {
reg = <12>;
qcom,gpu-freq = <231000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
qcom,bus-freq = <1>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
};
};
qcom,gpu-pwrlevels-3 {
#address-cells = <1>;
#size-cells = <0>;
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;
qcom,initial-pwrlevel = <10>;
/* Nom_L1 */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <834000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq = <9>;
qcom,bus-min = <9>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_NOM_L1>;
};
/* Nom */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <770000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <7>;
qcom,bus-min = <6>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_NOM>;
};
/* SVS_L2 */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <720000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
qcom,bus-freq = <7>;
qcom,bus-min = <6>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
};
/* SVS_L1 */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <680000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <7>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
};
/* SVS_L0 */
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <629000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
qcom,bus-freq = <6>;
qcom,bus-min = <3>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_SVS_L0>;
};
/* SVS */
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <578000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <5>;
qcom,bus-min = <2>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_SVS>;
};
/* Low_SVS_L1 */
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <500000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
qcom,bus-freq = <5>;
qcom,bus-min = <1>;
qcom,bus-max = <5>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_L1>;
};
/* Low_SVS */
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <422000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq = <5>;
qcom,bus-min = <1>;
qcom,bus-max = <5>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS>;
};
/* Low_SVS_D0 */
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <366000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
qcom,bus-freq = <3>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D0>;
};
/* Low_SVS_D1 */
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-freq = <310000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
qcom,bus-freq = <1>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
};
/* Low_SVS_D2 */
qcom,gpu-pwrlevel@10 {
reg = <10>;
qcom,gpu-freq = <231000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
qcom,bus-freq = <1>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
};
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/clock/qcom,aop-qmp.h>
#include <dt-bindings/clock/qcom,gcc-pineapple.h>
#include <dt-bindings/clock/qcom,gpucc-pineapple.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interconnect/qcom,pineapple.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "pineapple-gpu.dtsi"
#include "pineapple-gpu-pwrlevels.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Pineapple";
compatible = "qcom,pineapple";
qcom,msm-id = <557 0x10000>, <577 0x10000>;
qcom,board-id = <0 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
/* External feature codes */
#define FC_UNKNOWN 0x0
#define FC_AA 0x1
#define FC_AB 0x2
#define FC_AC 0x3
#define FC_AD 0x4
/* Internal feature codes */
#define FC_Y0 0x00f1
#define FC_Y1 0x00f2
/* Pcodes */
#define PCODE_UNKNOWN 0
#define PCODE_0 1
#define PCODE_1 2
#define PCODE_2 3
#define PCODE_3 4
#define PCODE_4 5
#define PCODE_5 6
#define PCODE_6 7
#define PCODE_7 8
#define SKU_CODE(pcode, featurecode) ((pcode << 16) + featurecode)
&msm_gpu {
compatible = "qcom,adreno-gpu-gen7-9-0", "qcom,kgsl-3d0";
status = "ok";
reg = <0x3d00000 0x40000>, <0x3d61000 0x3000>,
<0x03d50000 0x10000>, <0x03d9e000 0x2000>,
<0x10900000 0x80000>, <0x10048000 0x8000>,
<0x10b05000 0x1000>;
reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc", "cx_misc",
"qdss_gfx", "qdss_etr", "qdss_tmc";
interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "kgsl_3d0_irq";
clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
<&gpucc GPU_CC_AHB_CLK>,
<&aoss_qmp QDSS_CLK>;
clock-names = "gcc_gpu_memnoc_gfx",
"gcc_gpu_snoc_dvm_gfx",
"gpu_cc_ahb",
"apb_pclk";
qcom,gpu-model = "Adreno750";
qcom,chipid = <0x43051400>;
qcom,no-nap;
qcom,min-access-length = <32>;
qcom,ubwc-mode = <4>;
qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */
qcom,tzone-names = "gpuss-0", "gpuss-1", "gpuss-2", "gpuss-3",
"gpuss-4", "gpuss-5", "gpuss-6", "gpuss-7";
interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
interconnect-names = "gpu_icc_path";
qcom,bus-table-cnoc =
<0>, /* Off */
<100>; /* On */
qcom,bus-table-ddr =
<MHZ_TO_KBPS(0, 4)>, /* index=0 */
<MHZ_TO_KBPS(547, 4) >, /* index=1 */
<MHZ_TO_KBPS(768, 4) >, /* index=2 */
<MHZ_TO_KBPS(1555, 4)>, /* index=3 */
<MHZ_TO_KBPS(1708, 4)>, /* index=4 */
<MHZ_TO_KBPS(2092, 4)>, /* index=5 */
<MHZ_TO_KBPS(2736, 4)>, /* index=6 */
<MHZ_TO_KBPS(3187, 4)>, /* index=7 */
<MHZ_TO_KBPS(3686, 4)>, /* index=8 */
<MHZ_TO_KBPS(4224, 4)>; /* index=9 */
nvmem-cells = <&gpu_speed_bin>;
nvmem-cell-names = "speed_bin";
zap-shader {
memory-region = <&gpu_micro_code_mem>;
};
qcom,gpu-mempools {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,gpu-mempools";
/* 4K Page Pool configuration */
qcom,gpu-mempool@0 {
reg = <0>;
qcom,mempool-page-size = <4096>;
qcom,mempool-reserved = <2048>;
};
/* 8K Page Pool configuration */
qcom,gpu-mempool@1 {
reg = <1>;
qcom,mempool-page-size = <8192>;
qcom,mempool-reserved = <1024>;
};
/* 64K Page Pool configuration */
qcom,gpu-mempool@2 {
reg = <2>;
qcom,mempool-page-size = <65536>;
qcom,mempool-reserved = <256>;
};
/* 128K Page Pool configuration */
qcom,gpu-mempool@3 {
reg = <3>;
qcom,mempool-page-size = <131072>;
qcom,mempool-reserved = <128>;
};
/* 256K Page Pool configuration */
qcom,gpu-mempool@4 {
reg = <4>;
qcom,mempool-page-size = <262144>;
qcom,mempool-reserved = <80>;
};
/* 1M Page Pool configuration */
qcom,gpu-mempool@5 {
reg = <5>;
qcom,mempool-page-size = <1048576>;
qcom,mempool-reserved = <32>;
};
};
};
&soc {
kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 {
compatible = "qcom,kgsl-smmu-v2";
reg = <0x03da0000 0x40000>;
vddcx-supply = <&gpu_cc_cx_gdsc>;
gfx3d_user: gfx3d_user {
compatible = "qcom,smmu-kgsl-cb";
iommus = <&kgsl_smmu 0x0 0x000>;
qcom,iommu-dma = "disabled";
};
gfx3d_lpac: gfx3d_lpac {
compatible = "qcom,smmu-kgsl-cb";
iommus = <&kgsl_smmu 0x1 0x000>;
qcom,iommu-dma = "disabled";
};
gfx3d_secure: gfx3d_secure {
compatible = "qcom,smmu-kgsl-cb";
iommus = <&kgsl_smmu 0x2 0x000>;
qcom,iommu-dma = "disabled";
};
};
gmu: qcom,gmu@3d69000 {
compatible = "qcom,gen7-gmu";
reg = <0x3d68000 0x37000>,
<0xb280000 0x10000>,
<0x03D40000 0x10000>;
reg-names = "gmu", "gmu_pdc", "gmu_ao_blk_dec0";
interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
<0 305 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hfi", "gmu";
regulator-names = "vddcx", "vdd";
vddcx-supply = <&gpu_cc_cx_gdsc>;
vdd-supply = <&gpu_cc_gx_gdsc>;
clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
<&gpucc GPU_CC_CXO_CLK>,
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
<&gpucc GPU_CC_AHB_CLK>,
<&gpucc GPU_CC_HUB_CX_INT_CLK>;
clock-names = "gmu_clk", "cxo_clk", "axi_clk",
"memnoc_clk", "ahb_clk", "hub_clk";
qcom,gmu-freq-table = <260000000 RPMH_REGULATOR_LEVEL_LOW_SVS>,
<625000000 RPMH_REGULATOR_LEVEL_SVS>;
qcom,gmu-perf-ddr-bw = <MHZ_TO_KBPS(768, 4)>;
iommus = <&kgsl_smmu 0x5 0x000>;
qcom,iommu-dma = "disabled";
qcom,ipc-core = <0x00400000 0x140000>;
mboxes = <&qmp_aop 0>;
mbox-names = "aop";
};
coresight_cx_dgbc: qcom,gpu-coresight-cx {
compatible = "qcom,gpu-coresight-cx";
coresight-name = "coresight-gfx-cx";
coresight-atid = <52>;
out-ports {
port {
cx_dbgc_out_funnel_gfx: endpoint {
remote-endpoint =
<&funnel_gfx_in_cx_dbgc>;
};
};
};
};
coresight_gx_dgbc: qcom,gpu-coresight-gx {
compatible = "qcom,gpu-coresight-gx";
coresight-name = "coresight-gfx";
coresight-atid = <53>;
out-ports {
port {
gx_dbgc_out_funnel_gfx: endpoint {
remote-endpoint =
<&funnel_gfx_in_gx_dbgc>;
};
};
};
};
};
&funnel_gfx {
status = "ok";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
funnel_gfx_in_gx_dbgc: endpoint {
remote-endpoint =
<&gx_dbgc_out_funnel_gfx>;
};
};
port@1 {
reg = <1>;
funnel_gfx_in_cx_dbgc: endpoint {
remote-endpoint =
<&cx_dbgc_out_funnel_gfx>;
};
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/* ACD Control register values */
#define ACD_LEVEL_TURBO_L1 0x882f5ffd
#define ACD_LEVEL_TURBO 0x882f5ffd
#define ACD_LEVEL_NOM_L1 0x882f5ffd
#define ACD_LEVEL_NOM 0xc0285ffd
#define ACD_LEVEL_SVS_L2 0xe0295ffd
#define ACD_LEVEL_SVS_L1 0xe0295ffd
#define ACD_LEVEL_SVS_L0 0xc02a5ffd
#define ACD_LEVEL_SVS 0xc02a5ffd
#define ACD_LEVEL_LOW_SVS_L1 0xc02c5ffd
#define ACD_LEVEL_LOW_SVS 0xc02f5ffd
#define ACD_LEVEL_LOW_SVS_D0 0xc02f5ffd
&msm_gpu {
/* Power levels */
qcom,gpu-pwrlevels {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,gpu-pwrlevels";
qcom,initial-pwrlevel = <11>;
/* Turbo */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <903000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
qcom,bus-freq = <9>;
qcom,bus-min = <9>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_TURBO>;
};
/* Nom_L1 */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <834000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq = <8>;
qcom,bus-min = <7>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_NOM_L1>;
};
/* Nom */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <770000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <7>;
qcom,bus-min = <6>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_NOM>;
};
/* SVS_L2 */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <720000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
qcom,bus-freq = <7>;
qcom,bus-min = <6>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
};
/* SVS_L1 */
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <680000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <7>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
};
/* SVS_L0 */
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <629000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
qcom,bus-freq = <6>;
qcom,bus-min = <4>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_SVS_L0>;
};
/* SVS */
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <578000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <5>;
qcom,bus-min = <4>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_SVS>;
};
/* Low_SVS_L1 */
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <500000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
qcom,bus-freq = <5>;
qcom,bus-min = <3>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_L1>;
};
/* Low_SVS */
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <422000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq = <5>;
qcom,bus-min = <3>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS>;
};
/* Low_SVS_D0 */
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-freq = <366000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
qcom,bus-freq = <3>;
qcom,bus-min = <2>;
qcom,bus-max = <5>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D0>;
};
/* Low_SVS_D1 */
qcom,gpu-pwrlevel@10 {
reg = <10>;
qcom,gpu-freq = <310000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
qcom,bus-freq = <1>;
qcom,bus-min = <1>;
qcom,bus-max = <4>;
};
/* Low_SVS_D2 */
qcom,gpu-pwrlevel@11 {
reg = <11>;
qcom,gpu-freq = <231000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
qcom,bus-freq = <1>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/clock/qcom,aop-qmp.h>
#include <dt-bindings/clock/qcom,gcc-pineapple.h>
#include <dt-bindings/clock/qcom,gpucc-pineapple.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interconnect/qcom,pineapple.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "pineapple-v2-gpu.dtsi"
#include "pineapple-v2-gpu-pwrlevels.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Pineapple";
compatible = "qcom,pineapple";
qcom,msm-id = <557 0x20000>, <577 0x20000>;
qcom,board-id = <0 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "pineapple-gpu.dtsi"
&msm_gpu {
compatible = "qcom,adreno-gpu-gen7-9-1", "qcom,kgsl-3d0";
qcom,gpu-model = "Adreno750v2";
qcom,chipid = <0x43051401>;
};