From 07276212b35812e8e40d7578f53e99b78d8a212b Mon Sep 17 00:00:00 2001 From: Gerrit SelfHelp Service Account Date: Sun, 31 Mar 2024 22:59:29 -0700 Subject: [PATCH 1/8] Initial empty repository From e538abe50e44629cfcc1871ecde2c0061b7805d6 Mon Sep 17 00:00:00 2001 From: Megha Byahatti Date: Tue, 2 Apr 2024 14:39:40 +0530 Subject: [PATCH 2/8] mmrm: devicetree: Align with upstream osdt According to upstream requirement moving devicetree form vendor/qcom/proprietary/mmrm-devicetree to vendor/qcom/opensource/mmrm-devicetree by creating new project. All the changes to the devicetree need to be done in this project to be merged. All changes will need Signed-off-by: tags and will need to use open source emails. Change-Id: Ia6ca401d094e934503c54718716ab0d1c64015af Signed-off-by: Megha Byahatti --- Kbuild | 38 ++++++++ Makefile | 9 ++ bindings/msm-mmrm-test.txt | 32 +++++++ bindings/msm-mmrm.txt | 35 ++++++++ kalama/kalama-mmrm-test-v2.dts | 20 +++++ kalama/kalama-mmrm-test-v2.dtsi | 114 ++++++++++++++++++++++++ kalama/kalama-mmrm-test.dts | 20 +++++ kalama/kalama-mmrm-test.dtsi | 114 ++++++++++++++++++++++++ kalama/kalama-mmrm-v2.dts | 19 ++++ kalama/kalama-mmrm-v2.dtsi | 59 +++++++++++++ kalama/kalama-mmrm-vm-be.dts | 20 +++++ kalama/kalama-mmrm-vm-be.dtsi | 12 +++ kalama/kalama-mmrm-vm-fe-test.dts | 20 +++++ kalama/kalama-mmrm-vm-fe-test.dtsi | 52 +++++++++++ kalama/kalama-mmrm-vm-fe.dts | 20 +++++ kalama/kalama-mmrm-vm-fe.dtsi | 39 ++++++++ kalama/kalama-mmrm.dts | 19 ++++ kalama/kalama-mmrm.dtsi | 59 +++++++++++++ pineapple/pineapple-mmrm-test-v2.dts | 20 +++++ pineapple/pineapple-mmrm-test-v2.dtsi | 122 ++++++++++++++++++++++++++ pineapple/pineapple-mmrm-test.dts | 20 +++++ pineapple/pineapple-mmrm-test.dtsi | 122 ++++++++++++++++++++++++++ pineapple/pineapple-mmrm.dts | 20 +++++ pineapple/pineapple-mmrm.dtsi | 60 +++++++++++++ sun/sun-mmrm-test.dts | 20 +++++ sun/sun-mmrm-test.dtsi | 107 ++++++++++++++++++++++ sun/sun-mmrm.dts | 20 +++++ sun/sun-mmrm.dtsi | 54 ++++++++++++ waipio/waipio-mmrm-test.dts | 18 ++++ waipio/waipio-mmrm-test.dtsi | 100 +++++++++++++++++++++ waipio/waipio-mmrm.dts | 19 ++++ waipio/waipio-mmrm.dtsi | 54 ++++++++++++ waipio/waipio-v2-mmrm-test.dts | 19 ++++ waipio/waipio-v2-mmrm-test.dtsi | 100 +++++++++++++++++++++ waipio/waipio-v2-mmrm.dts | 19 ++++ waipio/waipio-v2-mmrm.dtsi | 53 +++++++++++ 36 files changed, 1648 insertions(+) create mode 100644 Kbuild create mode 100644 Makefile create mode 100644 bindings/msm-mmrm-test.txt create mode 100644 bindings/msm-mmrm.txt create mode 100644 kalama/kalama-mmrm-test-v2.dts create mode 100644 kalama/kalama-mmrm-test-v2.dtsi create mode 100644 kalama/kalama-mmrm-test.dts create mode 100644 kalama/kalama-mmrm-test.dtsi create mode 100644 kalama/kalama-mmrm-v2.dts create mode 100644 kalama/kalama-mmrm-v2.dtsi create mode 100644 kalama/kalama-mmrm-vm-be.dts create mode 100644 kalama/kalama-mmrm-vm-be.dtsi create mode 100644 kalama/kalama-mmrm-vm-fe-test.dts create mode 100644 kalama/kalama-mmrm-vm-fe-test.dtsi create mode 100644 kalama/kalama-mmrm-vm-fe.dts create mode 100644 kalama/kalama-mmrm-vm-fe.dtsi create mode 100644 kalama/kalama-mmrm.dts create mode 100644 kalama/kalama-mmrm.dtsi create mode 100644 pineapple/pineapple-mmrm-test-v2.dts create mode 100644 pineapple/pineapple-mmrm-test-v2.dtsi create mode 100644 pineapple/pineapple-mmrm-test.dts create mode 100644 pineapple/pineapple-mmrm-test.dtsi create mode 100644 pineapple/pineapple-mmrm.dts create mode 100644 pineapple/pineapple-mmrm.dtsi create mode 100644 sun/sun-mmrm-test.dts create mode 100644 sun/sun-mmrm-test.dtsi create mode 100644 sun/sun-mmrm.dts create mode 100644 sun/sun-mmrm.dtsi create mode 100644 waipio/waipio-mmrm-test.dts create mode 100644 waipio/waipio-mmrm-test.dtsi create mode 100644 waipio/waipio-mmrm.dts create mode 100644 waipio/waipio-mmrm.dtsi create mode 100644 waipio/waipio-v2-mmrm-test.dts create mode 100644 waipio/waipio-v2-mmrm-test.dtsi create mode 100644 waipio/waipio-v2-mmrm.dts create mode 100644 waipio/waipio-v2-mmrm.dtsi diff --git a/Kbuild b/Kbuild new file mode 100644 index 00000000..d4bed0d9 --- /dev/null +++ b/Kbuild @@ -0,0 +1,38 @@ +ifeq ($(CONFIG_ARCH_SUN), y) +dtbo-y += sun/sun-mmrm.dtbo +dtbo-y += sun/sun-mmrm-test.dtbo +endif + +ifeq ($(CONFIG_ARCH_PINEAPPLE), y) +dtbo-y += pineapple/pineapple-mmrm.dtbo +dtbo-y += pineapple/pineapple-mmrm-test.dtbo +dtbo-y += pineapple/pineapple-mmrm-test-v2.dtbo +endif + +ifeq ($(CONFIG_ARCH_KALAMA), y) + ifneq ($(CONFIG_ARCH_QTI_VM), y) + dtbo-y += kalama/kalama-mmrm.dtbo + dtbo-y += kalama/kalama-mmrm-test.dtbo + dtbo-y += kalama/kalama-mmrm-v2.dtbo + dtbo-y += kalama/kalama-mmrm-test-v2.dtbo + ifeq ($(CONFIG_MSM_MMRM_VM),y) + dtbo-y += kalama/kalama-mmrm-vm-be.dtbo + endif + else + ifeq ($(CONFIG_MSM_MMRM_VM),y) + dtbo-y += kalama/kalama-mmrm-vm-fe.dtbo + dtbo-y += kalama/kalama-mmrm-vm-fe-test.dtbo + endif + endif +endif + +ifeq ($(CONFIG_ARCH_WAIPIO), y) +dtbo-y += waipio/waipio-mmrm.dtbo +dtbo-y += waipio/waipio-mmrm-test.dtbo +dtbo-y += waipio/waipio-v2-mmrm.dtbo +dtbo-y += waipio/waipio-v2-mmrm-test.dtbo +endif + +always-y := $(dtb-y) $(dtbo-y) +subdir-y := $(dts-dirs) +clean-files := *.dtb *.dtbo diff --git a/Makefile b/Makefile new file mode 100644 index 00000000..b1e0dfe9 --- /dev/null +++ b/Makefile @@ -0,0 +1,9 @@ +KBUILD_OPTIONS+=KBUILD_EXTMOD_DTS=. + +all: dtbs + +clean: + $(MAKE) -C $(KERNEL_SRC) M=$(M) clean + +%: + $(MAKE) -C $(KERNEL_SRC) M=$(M) $@ $(KBUILD_OPTIONS) diff --git a/bindings/msm-mmrm-test.txt b/bindings/msm-mmrm-test.txt new file mode 100644 index 00000000..b85b5846 --- /dev/null +++ b/bindings/msm-mmrm-test.txt @@ -0,0 +1,32 @@ +* Qualcomm Technologies, Inc. MSM MMRM + +[Root level node] +MMRM +===== +Required properties: +- compatible : one of: + - "qcom,msm-mmrm-test" + - "qcom,waipio-mmrm-test" : Invokes driver specific data for Waipio. +- clock-names: an array of clocks that the driver uses for testing. + The clocks names here correspond to the clock names used in + clk_get. +- clocks: Must contain an entry for each clock in clock-names. + +Example: + + qcom,mmrm-test { + compatible = "qcom,msm-mmrm-test"; + + clock-names = + "cam_cc_ife_0_clk_src", + "cam_cc_ife_1_clk_src", + "video_cc_mvs1_clk_src", + "disp_cc_mdss_mdp_clk_src", + "video_cc_mvs0_clk_src"; + clocks = + <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, + <&clock_videocc VIDEO_CC_MVS1_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_MDP_CLK_SRC>, + <&clock_videocc VIDEO_CC_MVS0_CLK_SRC>; + }; diff --git a/bindings/msm-mmrm.txt b/bindings/msm-mmrm.txt new file mode 100644 index 00000000..9019bc5c --- /dev/null +++ b/bindings/msm-mmrm.txt @@ -0,0 +1,35 @@ +* Qualcomm Technologies, Inc. MSM MMRM + +[Root level node] +MMRM +===== +Required properties: +- compatible : one of: + - "qcom,msm-mmrm" + - "qcom,waipio-mmrm" : Invokes driver specific data for Waipio. +Optional properties: +- mm-rail-corners : an array of voltage corner names supported by driver. +- mm-rail-fact-volt : an array of voltage coner factors corresponding to + voltage corners supported by driver for a chipset. +- scaling-fact-dyn : an array of dynamic scaling factors corresponding to + voltage corners supported by driver for a chipset. +- scaling-fact-leak: an array of leakage scaling factors corresponding to + voltage corners supported by driver for a chipset. +- client-info : an array of information for each clock source. Each entry + includes client domain, clk src id & corresponding power factors. + +Example: + + qcom,mmrm { + compatible = "qcom,msm-mmrm"; + + mm-rail-corners = "lowsvs", "svs", "svsl1", "nom", "turbo"; + mm-rail-fact-volt = <36439 41157 44827 49152 54526>; + + /* Scaling factors */ + scaling-fact-dyn = <35390 45876 54395 66192 82576>; + scaling-fact-leak = <451544 548537 633078 746456 920126>; + + client-info = + <0x4 VIDEO_CC_MVS0_CLK_SRC 28970189 582288>; + }; diff --git a/kalama/kalama-mmrm-test-v2.dts b/kalama/kalama-mmrm-test-v2.dts new file mode 100644 index 00000000..72824853 --- /dev/null +++ b/kalama/kalama-mmrm-test-v2.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +#include "kalama-mmrm-test-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kalama v2 SoC"; + compatible = "qcom,kalama"; + qcom,msm-id = <519 0x20000>, <536 0x20000>, <600 0x20000>, <601 0x20000>; + qcom,board-id = <0 0>; /* required by merge_dtbs.py */ +}; diff --git a/kalama/kalama-mmrm-test-v2.dtsi b/kalama/kalama-mmrm-test-v2.dtsi new file mode 100644 index 00000000..9a0ca347 --- /dev/null +++ b/kalama/kalama-mmrm-test-v2.dtsi @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + msm_mmrm_test: qcom,mmrm-test { + compatible = "qcom,msm-mmrm-test", "qcom,kalama-mmrm-test"; + status = "disable"; + + /* Clock info */ + clock-names = + "cam_cc_ife_0_clk_src", + "cam_cc_ife_1_clk_src", + "cam_cc_ife_2_clk_src", + "cam_cc_csid_clk_src", + "cam_cc_sfe_0_clk_src", + "cam_cc_sfe_1_clk_src", + "cam_cc_ipe_nps_clk_src", + "cam_cc_bps_clk_src", + "cam_cc_ife_lite_clk_src", + "cam_cc_jpeg_clk_src", + "cam_cc_camnoc_axi_clk_src", + "cam_cc_ife_lite_csid_clk_src", + "cam_cc_icp_clk_src", + "cam_cc_cphy_rx_clk_src", + "cam_cc_csi0phytimer_clk_src", + "cam_cc_csi1phytimer_clk_src", + "cam_cc_csi2phytimer_clk_src", + "cam_cc_csi3phytimer_clk_src", + "cam_cc_csi4phytimer_clk_src", + "cam_cc_csi5phytimer_clk_src", + "cam_cc_csi6phytimer_clk_src", + "cam_cc_csi7phytimer_clk_src", + "cam_cc_cci_0_clk_src", + "cam_cc_cci_1_clk_src", + "cam_cc_cci_2_clk_src", + "cam_cc_slow_ahb_clk_src", + "cam_cc_fast_ahb_clk_src", + "cam_cc_cre_clk_src", + "video_cc_mvs1_clk_src", + "disp_cc_mdss_mdp_clk_src", + "disp_cc_mdss_dptx0_link_clk_src", + "video_cc_mvs0_clk_src"; + + clocks = + <&camcc CAM_CC_IFE_0_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CLK_SRC>, + <&camcc CAM_CC_IFE_2_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_SFE_0_CLK_SRC>, + <&camcc CAM_CC_SFE_1_CLK_SRC>, + <&camcc CAM_CC_IPE_NPS_CLK_SRC>, + <&camcc CAM_CC_BPS_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_ICP_CLK_SRC>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI6PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI7PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CCI_0_CLK_SRC>, + <&camcc CAM_CC_CCI_1_CLK_SRC>, + <&camcc CAM_CC_CCI_2_CLK_SRC>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_CRE_CLK_SRC>, + <&videocc VIDEO_CC_MVS1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&videocc VIDEO_CC_MVS0_CLK_SRC>; + + clock_rates = + <0x1 CAM_CC_IFE_0_CLK_SRC 432000000 594000000 675000000 785000000 785000000>, + <0x1 CAM_CC_IFE_1_CLK_SRC 432000000 594000000 675000000 785000000 785000000>, + <0x1 CAM_CC_IFE_2_CLK_SRC 432000000 594000000 675000000 785000000 785000000>, + <0x1 CAM_CC_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000>, + <0x1 CAM_CC_SFE_0_CLK_SRC 432000000 594000000 675000000 785000000 785000000>, + <0x1 CAM_CC_SFE_1_CLK_SRC 364000000 500000000 600000000 700000000 700000000>, + <0x1 CAM_CC_IPE_NPS_CLK_SRC 200000000 400000000 480000000 600000000 600000000>, + <0x1 CAM_CC_BPS_CLK_SRC 200000000 400000000 480000000 600000000 600000000>, + <0x1 CAM_CC_IFE_LITE_CLK_SRC 400000000 480000000 480000000 480000000 480000000>, + <0x1 CAM_CC_JPEG_CLK_SRC 200000000 400000000 480000000 600000000 600000000>, + <0x1 CAM_CC_CAMNOC_AXI_CLK_SRC 300000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000>, + <0x1 CAM_CC_ICP_CLK_SRC 400000000 480000000 600000000 600000000 600000000>, + <0x1 CAM_CC_CPHY_RX_CLK_SRC 400000000 480000000 480000000 480000000 480000000>, + <0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_CSI6PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_CSI7PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_CCI_0_CLK_SRC 37500000 37500000 37500000 37500000 37500000>, + <0x1 CAM_CC_CCI_1_CLK_SRC 37500000 37500000 37500000 37500000 37500000>, + <0x1 CAM_CC_CCI_2_CLK_SRC 37500000 37500000 37500000 37500000 37500000>, + <0x1 CAM_CC_SLOW_AHB_CLK_SRC 80000000 80000000 80000000 80000000 80000000>, + <0x1 CAM_CC_FAST_AHB_CLK_SRC 100000000 200000000 300000000 400000000 400000000>, + <0x1 CAM_CC_CRE_CLK_SRC 37500000 37500000 37500000 37500000 37500000>, + <0x2 VIDEO_CC_MVS1_CLK_SRC 1050000000 1350000000 1500000000 1650000000 1650000000>, + <0x3 DISP_CC_MDSS_MDP_CLK_SRC 200000000 325000000 375000000 500000000 500000000>, + <0x3 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 270000 270000 540000 810000 810000>, + <0x4 VIDEO_CC_MVS0_CLK_SRC 720000000 1014000000 1098000000 1332000000 1332000000>; + }; +}; diff --git a/kalama/kalama-mmrm-test.dts b/kalama/kalama-mmrm-test.dts new file mode 100644 index 00000000..5e96ac0a --- /dev/null +++ b/kalama/kalama-mmrm-test.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +#include "kalama-mmrm-test.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kalama v1 SoC"; + compatible = "qcom,kalama"; + qcom,msm-id = <519 0x10000>, <536 0x10000>, <600 0x10000>, <601 0x10000>; + qcom,board-id = <0 0>; /* required by merge_dtbs.py */ +}; diff --git a/kalama/kalama-mmrm-test.dtsi b/kalama/kalama-mmrm-test.dtsi new file mode 100644 index 00000000..9a0ca347 --- /dev/null +++ b/kalama/kalama-mmrm-test.dtsi @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + msm_mmrm_test: qcom,mmrm-test { + compatible = "qcom,msm-mmrm-test", "qcom,kalama-mmrm-test"; + status = "disable"; + + /* Clock info */ + clock-names = + "cam_cc_ife_0_clk_src", + "cam_cc_ife_1_clk_src", + "cam_cc_ife_2_clk_src", + "cam_cc_csid_clk_src", + "cam_cc_sfe_0_clk_src", + "cam_cc_sfe_1_clk_src", + "cam_cc_ipe_nps_clk_src", + "cam_cc_bps_clk_src", + "cam_cc_ife_lite_clk_src", + "cam_cc_jpeg_clk_src", + "cam_cc_camnoc_axi_clk_src", + "cam_cc_ife_lite_csid_clk_src", + "cam_cc_icp_clk_src", + "cam_cc_cphy_rx_clk_src", + "cam_cc_csi0phytimer_clk_src", + "cam_cc_csi1phytimer_clk_src", + "cam_cc_csi2phytimer_clk_src", + "cam_cc_csi3phytimer_clk_src", + "cam_cc_csi4phytimer_clk_src", + "cam_cc_csi5phytimer_clk_src", + "cam_cc_csi6phytimer_clk_src", + "cam_cc_csi7phytimer_clk_src", + "cam_cc_cci_0_clk_src", + "cam_cc_cci_1_clk_src", + "cam_cc_cci_2_clk_src", + "cam_cc_slow_ahb_clk_src", + "cam_cc_fast_ahb_clk_src", + "cam_cc_cre_clk_src", + "video_cc_mvs1_clk_src", + "disp_cc_mdss_mdp_clk_src", + "disp_cc_mdss_dptx0_link_clk_src", + "video_cc_mvs0_clk_src"; + + clocks = + <&camcc CAM_CC_IFE_0_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CLK_SRC>, + <&camcc CAM_CC_IFE_2_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_SFE_0_CLK_SRC>, + <&camcc CAM_CC_SFE_1_CLK_SRC>, + <&camcc CAM_CC_IPE_NPS_CLK_SRC>, + <&camcc CAM_CC_BPS_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_ICP_CLK_SRC>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI6PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI7PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CCI_0_CLK_SRC>, + <&camcc CAM_CC_CCI_1_CLK_SRC>, + <&camcc CAM_CC_CCI_2_CLK_SRC>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_CRE_CLK_SRC>, + <&videocc VIDEO_CC_MVS1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&videocc VIDEO_CC_MVS0_CLK_SRC>; + + clock_rates = + <0x1 CAM_CC_IFE_0_CLK_SRC 432000000 594000000 675000000 785000000 785000000>, + <0x1 CAM_CC_IFE_1_CLK_SRC 432000000 594000000 675000000 785000000 785000000>, + <0x1 CAM_CC_IFE_2_CLK_SRC 432000000 594000000 675000000 785000000 785000000>, + <0x1 CAM_CC_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000>, + <0x1 CAM_CC_SFE_0_CLK_SRC 432000000 594000000 675000000 785000000 785000000>, + <0x1 CAM_CC_SFE_1_CLK_SRC 364000000 500000000 600000000 700000000 700000000>, + <0x1 CAM_CC_IPE_NPS_CLK_SRC 200000000 400000000 480000000 600000000 600000000>, + <0x1 CAM_CC_BPS_CLK_SRC 200000000 400000000 480000000 600000000 600000000>, + <0x1 CAM_CC_IFE_LITE_CLK_SRC 400000000 480000000 480000000 480000000 480000000>, + <0x1 CAM_CC_JPEG_CLK_SRC 200000000 400000000 480000000 600000000 600000000>, + <0x1 CAM_CC_CAMNOC_AXI_CLK_SRC 300000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000>, + <0x1 CAM_CC_ICP_CLK_SRC 400000000 480000000 600000000 600000000 600000000>, + <0x1 CAM_CC_CPHY_RX_CLK_SRC 400000000 480000000 480000000 480000000 480000000>, + <0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_CSI6PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_CSI7PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_CCI_0_CLK_SRC 37500000 37500000 37500000 37500000 37500000>, + <0x1 CAM_CC_CCI_1_CLK_SRC 37500000 37500000 37500000 37500000 37500000>, + <0x1 CAM_CC_CCI_2_CLK_SRC 37500000 37500000 37500000 37500000 37500000>, + <0x1 CAM_CC_SLOW_AHB_CLK_SRC 80000000 80000000 80000000 80000000 80000000>, + <0x1 CAM_CC_FAST_AHB_CLK_SRC 100000000 200000000 300000000 400000000 400000000>, + <0x1 CAM_CC_CRE_CLK_SRC 37500000 37500000 37500000 37500000 37500000>, + <0x2 VIDEO_CC_MVS1_CLK_SRC 1050000000 1350000000 1500000000 1650000000 1650000000>, + <0x3 DISP_CC_MDSS_MDP_CLK_SRC 200000000 325000000 375000000 500000000 500000000>, + <0x3 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 270000 270000 540000 810000 810000>, + <0x4 VIDEO_CC_MVS0_CLK_SRC 720000000 1014000000 1098000000 1332000000 1332000000>; + }; +}; diff --git a/kalama/kalama-mmrm-v2.dts b/kalama/kalama-mmrm-v2.dts new file mode 100644 index 00000000..85009584 --- /dev/null +++ b/kalama/kalama-mmrm-v2.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include "kalama-mmrm-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kalama v2 SoC"; + compatible = "qcom,kalama"; + qcom,msm-id = <519 0x20000>, <536 0x20000>, <600 0x20000>, <601 0x20000>; + qcom,board-id = <0 0>; /* required by merge_dtbs.py */ +}; diff --git a/kalama/kalama-mmrm-v2.dtsi b/kalama/kalama-mmrm-v2.dtsi new file mode 100644 index 00000000..8173cc6e --- /dev/null +++ b/kalama/kalama-mmrm-v2.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + msm_mmrm: qcom,mmrm { + compatible = "qcom,msm-mmrm", "qcom,kalama-mmrm"; + status = "okay"; + + /* MMRM clock threshold */ + mmrm-peak-threshold = <10000>; + + /* MM Rail info */ + mm-rail-corners = "lowsvs", "svs", "svsl1", "nom", "noml1", "turbo"; + mm-rail-fact-volt = <37484 41157 44827 47710 52429 52429>; + + /* Scaling factors */ + scaling-fact-dyn = <39951 48654 58347 66676 81756 81756>; + scaling-fact-leak = <39951 671796 784171 884467 1082937 1082937>; + + /* Client info */ + mmrm-client-info = + <0x1 CAM_CC_IFE_0_CLK_SRC 31201472 238551 1>, + <0x1 CAM_CC_IFE_1_CLK_SRC 31201427 238551 1>, + <0x1 CAM_CC_IFE_2_CLK_SRC 31201427 238551 1>, + <0x1 CAM_CC_CSID_CLK_SRC 1858221 0 3>, + <0x1 CAM_CC_SFE_0_CLK_SRC 15273820 257556 1>, + <0x1 CAM_CC_SFE_1_CLK_SRC 15273820 257556 1>, + <0x1 CAM_CC_IPE_NPS_CLK_SRC 88824873 986972 1>, + <0x1 CAM_CC_BPS_CLK_SRC 30096753 84541 1>, + <0x1 CAM_CC_IFE_LITE_CLK_SRC 1460651 20054 2>, + <0x1 CAM_CC_JPEG_CLK_SRC 661914 18350 4>, + <0x1 CAM_CC_CAMNOC_AXI_CLK_SRC 2930770 388628 1>, + <0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 225444 0 2>, + <0x1 CAM_CC_ICP_CLK_SRC 270533 0 1>, + + <0x1 CAM_CC_CPHY_RX_CLK_SRC 19661 0 10>, + <0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 5636 0 1>, + <0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 5636 0 1>, + <0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 5636 0 1>, + <0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 5636 0 1>, + <0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 5636 0 1>, + <0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 5636 0 1>, + <0x1 CAM_CC_CSI6PHYTIMER_CLK_SRC 5636 0 1>, + <0x1 CAM_CC_CSI7PHYTIMER_CLK_SRC 5636 0 1>, + <0x1 CAM_CC_CCI_0_CLK_SRC 0 0 1>, + <0x1 CAM_CC_CCI_1_CLK_SRC 0 0 1>, + <0x1 CAM_CC_CCI_2_CLK_SRC 0 0 1>, + <0x1 CAM_CC_SLOW_AHB_CLK_SRC 60306 0 1>, + <0x1 CAM_CC_FAST_AHB_CLK_SRC 30435 0 1>, + <0x1 CAM_CC_CRE_CLK_SRC 327680 0 1>, + + <0x2 VIDEO_CC_MVS1_CLK_SRC 66109440 476447 1>, + <0x3 DISP_CC_MDSS_MDP_CLK_SRC 22714778 196608 1>, + <0x3 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 897843 3277 1>, + <0x4 VIDEO_CC_MVS0_CLK_SRC 13745521 486277 1>; + }; +}; diff --git a/kalama/kalama-mmrm-vm-be.dts b/kalama/kalama-mmrm-vm-be.dts new file mode 100644 index 00000000..d31edb7f --- /dev/null +++ b/kalama/kalama-mmrm-vm-be.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +#include "kalama-mmrm-vm-be.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kalama v1 SoC"; + compatible = "qcom,kalama"; + qcom,msm-id = <519 0x10000>; + qcom,board-id = <0 0>; /* required by merge_dtbs.py */ +}; diff --git a/kalama/kalama-mmrm-vm-be.dtsi b/kalama/kalama-mmrm-vm-be.dtsi new file mode 100644 index 00000000..3aa9d0e7 --- /dev/null +++ b/kalama/kalama-mmrm-vm-be.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + mmrm_vm_be: qcom,mmrm-vm-be { + compatible = "qcom,mmrm-vm-be"; + status = "disable"; + }; +}; + diff --git a/kalama/kalama-mmrm-vm-fe-test.dts b/kalama/kalama-mmrm-vm-fe-test.dts new file mode 100644 index 00000000..e79508d9 --- /dev/null +++ b/kalama/kalama-mmrm-vm-fe-test.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +#include "kalama-mmrm-vm-fe-test.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kalama"; + compatible = "qcom,kalama"; + qcom,msm-id = <519 0x10000>, <536 0x10000>; + qcom,board-id = <0x10001 0>; +}; diff --git a/kalama/kalama-mmrm-vm-fe-test.dtsi b/kalama/kalama-mmrm-vm-fe-test.dtsi new file mode 100644 index 00000000..74d5738a --- /dev/null +++ b/kalama/kalama-mmrm-vm-fe-test.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + mmrm_vm_fe_test: qcom,mmrm-vm-fe-test { + compatible = "qcom,mmrm-vm-fe-test"; + status = "okay"; + + /* Clock info */ + clock-names = + "cam_cc_ife_0_clk_src", + "cam_cc_ife_1_clk_src", + "cam_cc_ife_2_clk_src", + "cam_cc_csid_clk_src", + "cam_cc_sfe_0_clk_src", + "cam_cc_sfe_1_clk_src", + "cam_cc_ipe_nps_clk_src", + "cam_cc_bps_clk_src", + "cam_cc_ife_lite_clk_src", + "cam_cc_jpeg_clk_src", + "cam_cc_camnoc_axi_clk_src", + "cam_cc_ife_lite_csid_clk_src", + "cam_cc_icp_clk_src", + "cam_cc_cphy_rx_clk_src", + "cam_cc_cci_0_clk_src", + "cam_cc_cci_1_clk_src", + "cam_cc_slow_ahb_clk_src", + "cam_cc_fast_ahb_clk_src"; + + clock_rates = + <0x1 CAM_CC_IFE_0_CLK_SRC 432000000 594000000 675000000 727000000 727000000>, + <0x1 CAM_CC_IFE_1_CLK_SRC 432000000 594000000 675000000 727000000 727000000>, + <0x1 CAM_CC_IFE_2_CLK_SRC 432000000 594000000 675000000 727000000 727000000>, + <0x1 CAM_CC_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000>, + <0x1 CAM_CC_SFE_0_CLK_SRC 432000000 594000000 675000000 727000000 727000000>, + <0x1 CAM_CC_SFE_1_CLK_SRC 432000000 594000000 675000000 727000000 727000000>, + <0x1 CAM_CC_IPE_NPS_CLK_SRC 364000000 500000000 600000000 700000000 700000000>, + <0x1 CAM_CC_BPS_CLK_SRC 200000000 400000000 480000000 600000000 600000000>, + <0x1 CAM_CC_IFE_LITE_CLK_SRC 400000000 480000000 480000000 480000000 480000000>, + <0x1 CAM_CC_JPEG_CLK_SRC 200000000 400000000 480000000 600000000 600000000>, + <0x1 CAM_CC_CAMNOC_AXI_CLK_SRC 300000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000>, + <0x1 CAM_CC_ICP_CLK_SRC 400000000 480000000 600000000 600000000 600000000>, + <0x1 CAM_CC_CPHY_RX_CLK_SRC 400000000 480000000 480000000 480000000 480000000>, + <0x1 CAM_CC_CCI_0_CLK_SRC 37500000 37500000 37500000 37500000 37500000>, + <0x1 CAM_CC_CCI_1_CLK_SRC 37500000 37500000 37500000 37500000 37500000>, + <0x1 CAM_CC_SLOW_AHB_CLK_SRC 80000000 80000000 80000000 80000000 80000000>, + <0x1 CAM_CC_FAST_AHB_CLK_SRC 100000000 200000000 300000000 400000000 400000000>; + }; +}; diff --git a/kalama/kalama-mmrm-vm-fe.dts b/kalama/kalama-mmrm-vm-fe.dts new file mode 100644 index 00000000..fc1f265d --- /dev/null +++ b/kalama/kalama-mmrm-vm-fe.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +#include "kalama-mmrm-vm-fe.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kalama"; + compatible = "qcom,kalama"; + qcom,msm-id = <519 0x10000>, <536 0x10000>; + qcom,board-id = <0x10001 0>; +}; diff --git a/kalama/kalama-mmrm-vm-fe.dtsi b/kalama/kalama-mmrm-vm-fe.dtsi new file mode 100644 index 00000000..61af7020 --- /dev/null +++ b/kalama/kalama-mmrm-vm-fe.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + mmrm_vm_fe: qcom,mmrm-vm-fe { + compatible = "qcom,mmrm-vm-fe"; + status = "disable"; + + /* Client info */ + mmrm-client-info = + <0x1 CAM_CC_IFE_0_CLK_SRC>, + <0x1 CAM_CC_IFE_1_CLK_SRC>, + <0x1 CAM_CC_IFE_2_CLK_SRC>, + <0x1 CAM_CC_CSID_CLK_SRC>, + <0x1 CAM_CC_SFE_0_CLK_SRC>, + <0x1 CAM_CC_SFE_1_CLK_SRC>, + <0x1 CAM_CC_IPE_NPS_CLK_SRC>, + <0x1 CAM_CC_BPS_CLK_SRC>, + <0x1 CAM_CC_IFE_LITE_CLK_SRC>, + <0x1 CAM_CC_JPEG_CLK_SRC>, + <0x1 CAM_CC_CAMNOC_AXI_CLK_SRC>, + <0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <0x1 CAM_CC_ICP_CLK_SRC>, + <0x1 CAM_CC_CPHY_RX_CLK_SRC>, + <0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC>, + <0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC>, + <0x1 CAM_CC_CCI_0_CLK_SRC>, + <0x1 CAM_CC_CCI_1_CLK_SRC>, + <0x1 CAM_CC_SLOW_AHB_CLK_SRC>, + <0x1 CAM_CC_FAST_AHB_CLK_SRC>; + }; +}; + diff --git a/kalama/kalama-mmrm.dts b/kalama/kalama-mmrm.dts new file mode 100644 index 00000000..3e0a6c8e --- /dev/null +++ b/kalama/kalama-mmrm.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include "kalama-mmrm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kalama v1 SoC"; + compatible = "qcom,kalama"; + qcom,msm-id = <519 0x10000>, <536 0x10000>, <600 0x10000>, <601 0x10000>; + qcom,board-id = <0 0>; /* required by merge_dtbs.py */ +}; diff --git a/kalama/kalama-mmrm.dtsi b/kalama/kalama-mmrm.dtsi new file mode 100644 index 00000000..8173cc6e --- /dev/null +++ b/kalama/kalama-mmrm.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + msm_mmrm: qcom,mmrm { + compatible = "qcom,msm-mmrm", "qcom,kalama-mmrm"; + status = "okay"; + + /* MMRM clock threshold */ + mmrm-peak-threshold = <10000>; + + /* MM Rail info */ + mm-rail-corners = "lowsvs", "svs", "svsl1", "nom", "noml1", "turbo"; + mm-rail-fact-volt = <37484 41157 44827 47710 52429 52429>; + + /* Scaling factors */ + scaling-fact-dyn = <39951 48654 58347 66676 81756 81756>; + scaling-fact-leak = <39951 671796 784171 884467 1082937 1082937>; + + /* Client info */ + mmrm-client-info = + <0x1 CAM_CC_IFE_0_CLK_SRC 31201472 238551 1>, + <0x1 CAM_CC_IFE_1_CLK_SRC 31201427 238551 1>, + <0x1 CAM_CC_IFE_2_CLK_SRC 31201427 238551 1>, + <0x1 CAM_CC_CSID_CLK_SRC 1858221 0 3>, + <0x1 CAM_CC_SFE_0_CLK_SRC 15273820 257556 1>, + <0x1 CAM_CC_SFE_1_CLK_SRC 15273820 257556 1>, + <0x1 CAM_CC_IPE_NPS_CLK_SRC 88824873 986972 1>, + <0x1 CAM_CC_BPS_CLK_SRC 30096753 84541 1>, + <0x1 CAM_CC_IFE_LITE_CLK_SRC 1460651 20054 2>, + <0x1 CAM_CC_JPEG_CLK_SRC 661914 18350 4>, + <0x1 CAM_CC_CAMNOC_AXI_CLK_SRC 2930770 388628 1>, + <0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 225444 0 2>, + <0x1 CAM_CC_ICP_CLK_SRC 270533 0 1>, + + <0x1 CAM_CC_CPHY_RX_CLK_SRC 19661 0 10>, + <0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 5636 0 1>, + <0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 5636 0 1>, + <0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 5636 0 1>, + <0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 5636 0 1>, + <0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 5636 0 1>, + <0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 5636 0 1>, + <0x1 CAM_CC_CSI6PHYTIMER_CLK_SRC 5636 0 1>, + <0x1 CAM_CC_CSI7PHYTIMER_CLK_SRC 5636 0 1>, + <0x1 CAM_CC_CCI_0_CLK_SRC 0 0 1>, + <0x1 CAM_CC_CCI_1_CLK_SRC 0 0 1>, + <0x1 CAM_CC_CCI_2_CLK_SRC 0 0 1>, + <0x1 CAM_CC_SLOW_AHB_CLK_SRC 60306 0 1>, + <0x1 CAM_CC_FAST_AHB_CLK_SRC 30435 0 1>, + <0x1 CAM_CC_CRE_CLK_SRC 327680 0 1>, + + <0x2 VIDEO_CC_MVS1_CLK_SRC 66109440 476447 1>, + <0x3 DISP_CC_MDSS_MDP_CLK_SRC 22714778 196608 1>, + <0x3 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 897843 3277 1>, + <0x4 VIDEO_CC_MVS0_CLK_SRC 13745521 486277 1>; + }; +}; diff --git a/pineapple/pineapple-mmrm-test-v2.dts b/pineapple/pineapple-mmrm-test-v2.dts new file mode 100644 index 00000000..a80a9e17 --- /dev/null +++ b/pineapple/pineapple-mmrm-test-v2.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +#include "pineapple-mmrm-test-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Pineapple SoC"; + compatible = "qcom,pineapple"; + qcom,msm-id = <557 0x20000>, <577 0x20000>; + qcom,board-id = <0 0>; /* required by merge_dtbs.py */ +}; diff --git a/pineapple/pineapple-mmrm-test-v2.dtsi b/pineapple/pineapple-mmrm-test-v2.dtsi new file mode 100644 index 00000000..c873f1e5 --- /dev/null +++ b/pineapple/pineapple-mmrm-test-v2.dtsi @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + msm_mmrm_test: qcom,mmrm-test { + compatible = "qcom,msm-mmrm-test", "qcom,pineapple-mmrm-test"; + status = "disable"; + + /* Clock info */ + clock-names = + "cam_cc_ife_0_clk_src", + "cam_cc_ife_1_clk_src", + "cam_cc_ife_2_clk_src", + "cam_cc_csid_clk_src", + "cam_cc_sfe_0_clk_src", + "cam_cc_sfe_1_clk_src", + "cam_cc_sfe_2_clk_src", + "cam_cc_ipe_nps_clk_src", + "cam_cc_bps_clk_src", + "cam_cc_ife_lite_clk_src", + "cam_cc_jpeg_clk_src", + "cam_cc_camnoc_axi_rt_clk_src", + "cam_cc_ife_lite_csid_clk_src", + "cam_cc_icp_clk_src", + "cam_cc_cphy_rx_clk_src", + "cam_cc_csi0phytimer_clk_src", + "cam_cc_csi1phytimer_clk_src", + "cam_cc_csi2phytimer_clk_src", + "cam_cc_csi3phytimer_clk_src", + "cam_cc_csi4phytimer_clk_src", + "cam_cc_csi5phytimer_clk_src", + "cam_cc_csi6phytimer_clk_src", + "cam_cc_csi7phytimer_clk_src", + "cam_cc_cci_0_clk_src", + "cam_cc_cci_1_clk_src", + "cam_cc_cci_2_clk_src", + "cam_cc_slow_ahb_clk_src", + "cam_cc_fast_ahb_clk_src", + "cam_cc_cre_clk_src", + "video_cc_mvs1_clk_src", + "disp_cc_mdss_mdp_clk_src", + "disp_cc_mdss_dptx0_link_clk_src", + "video_cc_mvs0_clk_src"; + + clocks = + <&camcc CAM_CC_IFE_0_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CLK_SRC>, + <&camcc CAM_CC_IFE_2_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_SFE_0_CLK_SRC>, + <&camcc CAM_CC_SFE_1_CLK_SRC>, + <&camcc CAM_CC_SFE_2_CLK_SRC>, + <&camcc CAM_CC_IPE_NPS_CLK_SRC>, + <&camcc CAM_CC_BPS_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_ICP_CLK_SRC>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI6PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI7PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CCI_0_CLK_SRC>, + <&camcc CAM_CC_CCI_1_CLK_SRC>, + <&camcc CAM_CC_CCI_2_CLK_SRC>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_CRE_CLK_SRC>, + <&videocc VIDEO_CC_MVS1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&videocc VIDEO_CC_MVS0_CLK_SRC>; + + /* + * clock_data : domain, clock-ID, + * rate-LOWSVS, rate-SVS, rate-SVS_L1, rate-NOM, rate-TURBO, + * num_hw_blocks, hw_drv_instances, num_pwr_states + */ + clock_data = + <0x1 CAM_CC_IFE_0_CLK_SRC 466000000 594000000 675000000 785000000 785000000 1 3 2>, + <0x1 CAM_CC_IFE_1_CLK_SRC 466000000 594000000 675000000 785000000 785000000 1 3 2>, + <0x1 CAM_CC_IFE_2_CLK_SRC 466000000 594000000 675000000 785000000 785000000 1 3 2>, + <0x1 CAM_CC_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000 3 3 2>, + <0x1 CAM_CC_SFE_0_CLK_SRC 466000000 594000000 675000000 785000000 785000000 1 3 2>, + <0x1 CAM_CC_SFE_1_CLK_SRC 466000000 594000000 675000000 785000000 785000000 1 3 2>, + <0x1 CAM_CC_SFE_2_CLK_SRC 466000000 594000000 675000000 785000000 785000000 1 3 2>, + <0x1 CAM_CC_IPE_NPS_CLK_SRC 475000000 575000000 675000000 825000000 825000000 1 0 0>, + <0x1 CAM_CC_BPS_CLK_SRC 200000000 400000000 480000000 785000000 785000000 1 0 0>, + <0x1 CAM_CC_IFE_LITE_CLK_SRC 400000000 480000000 480000000 480000000 480000000 2 0 0>, + <0x1 CAM_CC_JPEG_CLK_SRC 200000000 400000000 480000000 600000000 600000000 4 0 0>, + <0x1 CAM_CC_CAMNOC_AXI_RT_CLK_SRC 300000000 400000000 400000000 400000000 400000000 1 3 2>, + <0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000 2 0 0>, + <0x1 CAM_CC_ICP_CLK_SRC 400000000 480000000 600000000 600000000 600000000 1 0 0>, + <0x1 CAM_CC_CPHY_RX_CLK_SRC 400000000 480000000 480000000 480000000 480000000 10 3 2>, + <0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI6PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI7PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CCI_0_CLK_SRC 37500000 37500000 37500000 37500000 37500000 1 0 0>, + <0x1 CAM_CC_CCI_1_CLK_SRC 37500000 37500000 37500000 37500000 37500000 1 0 0>, + <0x1 CAM_CC_CCI_2_CLK_SRC 37500000 37500000 37500000 37500000 37500000 1 0 0>, + <0x1 CAM_CC_SLOW_AHB_CLK_SRC 80000000 80000000 80000000 80000000 80000000 1 0 0>, + <0x1 CAM_CC_FAST_AHB_CLK_SRC 300000000 300000000 300000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CRE_CLK_SRC 200000000 400000000 480000000 600000000 600000000 1 0 0>, + <0x2 VIDEO_CC_MVS1_CLK_SRC 1110000000 1350000000 1500000000 1650000000 1650000000 1 0 0>, + <0x3 DISP_CC_MDSS_MDP_CLK_SRC 200000000 325000000 402000000 514000000 514000000 1 0 0>, + <0x3 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 270000000 270000000 540000000 810000000 810000000 1 0 0>, + <0x4 VIDEO_CC_MVS0_CLK_SRC 900000000 1140000000 1305000000 1440000000 1600000000 1 0 0>; + }; +}; diff --git a/pineapple/pineapple-mmrm-test.dts b/pineapple/pineapple-mmrm-test.dts new file mode 100644 index 00000000..25739864 --- /dev/null +++ b/pineapple/pineapple-mmrm-test.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +#include "pineapple-mmrm-test.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Pineapple SoC"; + compatible = "qcom,pineapple"; + qcom,msm-id = <557 0x10000>, <577 0x10000>; + qcom,board-id = <0 0>; /* required by merge_dtbs.py */ +}; diff --git a/pineapple/pineapple-mmrm-test.dtsi b/pineapple/pineapple-mmrm-test.dtsi new file mode 100644 index 00000000..87565d63 --- /dev/null +++ b/pineapple/pineapple-mmrm-test.dtsi @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + msm_mmrm_test: qcom,mmrm-test { + compatible = "qcom,msm-mmrm-test", "qcom,pineapple-mmrm-test"; + status = "disable"; + + /* Clock info */ + clock-names = + "cam_cc_ife_0_clk_src", + "cam_cc_ife_1_clk_src", + "cam_cc_ife_2_clk_src", + "cam_cc_csid_clk_src", + "cam_cc_sfe_0_clk_src", + "cam_cc_sfe_1_clk_src", + "cam_cc_sfe_2_clk_src", + "cam_cc_ipe_nps_clk_src", + "cam_cc_bps_clk_src", + "cam_cc_ife_lite_clk_src", + "cam_cc_jpeg_clk_src", + "cam_cc_camnoc_axi_rt_clk_src", + "cam_cc_ife_lite_csid_clk_src", + "cam_cc_icp_clk_src", + "cam_cc_cphy_rx_clk_src", + "cam_cc_csi0phytimer_clk_src", + "cam_cc_csi1phytimer_clk_src", + "cam_cc_csi2phytimer_clk_src", + "cam_cc_csi3phytimer_clk_src", + "cam_cc_csi4phytimer_clk_src", + "cam_cc_csi5phytimer_clk_src", + "cam_cc_csi6phytimer_clk_src", + "cam_cc_csi7phytimer_clk_src", + "cam_cc_cci_0_clk_src", + "cam_cc_cci_1_clk_src", + "cam_cc_cci_2_clk_src", + "cam_cc_slow_ahb_clk_src", + "cam_cc_fast_ahb_clk_src", + "cam_cc_cre_clk_src", + "video_cc_mvs1_clk_src", + "disp_cc_mdss_mdp_clk_src", + "disp_cc_mdss_dptx0_link_clk_src", + "video_cc_mvs0_clk_src"; + + clocks = + <&camcc CAM_CC_IFE_0_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CLK_SRC>, + <&camcc CAM_CC_IFE_2_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_SFE_0_CLK_SRC>, + <&camcc CAM_CC_SFE_1_CLK_SRC>, + <&camcc CAM_CC_SFE_2_CLK_SRC>, + <&camcc CAM_CC_IPE_NPS_CLK_SRC>, + <&camcc CAM_CC_BPS_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_ICP_CLK_SRC>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI6PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI7PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CCI_0_CLK_SRC>, + <&camcc CAM_CC_CCI_1_CLK_SRC>, + <&camcc CAM_CC_CCI_2_CLK_SRC>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_CRE_CLK_SRC>, + <&videocc VIDEO_CC_MVS1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&videocc VIDEO_CC_MVS0_CLK_SRC>; + + /* + * clock_data : domain, clock-ID, + * rate-LOWSVS, rate-SVS, rate-SVS_L1, rate-NOM, rate-TURBO, + * num_hw_blocks, hw_drv_instances, num_pwr_states + */ + clock_data = + <0x1 CAM_CC_IFE_0_CLK_SRC 466000000 594000000 675000000 785000000 785000000 1 3 2>, + <0x1 CAM_CC_IFE_1_CLK_SRC 466000000 594000000 675000000 785000000 785000000 1 3 2>, + <0x1 CAM_CC_IFE_2_CLK_SRC 466000000 594000000 675000000 785000000 785000000 1 3 2>, + <0x1 CAM_CC_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000 3 3 2>, + <0x1 CAM_CC_SFE_0_CLK_SRC 466000000 594000000 675000000 785000000 785000000 1 3 2>, + <0x1 CAM_CC_SFE_1_CLK_SRC 466000000 594000000 675000000 785000000 785000000 1 3 2>, + <0x1 CAM_CC_SFE_2_CLK_SRC 466000000 594000000 675000000 785000000 785000000 1 3 2>, + <0x1 CAM_CC_IPE_NPS_CLK_SRC 455000000 575000000 675000000 825000000 825000000 1 0 0>, + <0x1 CAM_CC_BPS_CLK_SRC 200000000 400000000 480000000 785000000 785000000 1 0 0>, + <0x1 CAM_CC_IFE_LITE_CLK_SRC 400000000 480000000 480000000 480000000 480000000 2 0 0>, + <0x1 CAM_CC_JPEG_CLK_SRC 200000000 400000000 480000000 600000000 600000000 4 0 0>, + <0x1 CAM_CC_CAMNOC_AXI_RT_CLK_SRC 300000000 400000000 400000000 400000000 400000000 1 3 2>, + <0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000 2 0 0>, + <0x1 CAM_CC_ICP_CLK_SRC 400000000 480000000 600000000 600000000 600000000 1 0 0>, + <0x1 CAM_CC_CPHY_RX_CLK_SRC 400000000 480000000 480000000 480000000 480000000 10 3 2>, + <0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI6PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI7PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CCI_0_CLK_SRC 37500000 37500000 37500000 37500000 37500000 1 0 0>, + <0x1 CAM_CC_CCI_1_CLK_SRC 37500000 37500000 37500000 37500000 37500000 1 0 0>, + <0x1 CAM_CC_CCI_2_CLK_SRC 37500000 37500000 37500000 37500000 37500000 1 0 0>, + <0x1 CAM_CC_SLOW_AHB_CLK_SRC 80000000 80000000 80000000 80000000 80000000 1 0 0>, + <0x1 CAM_CC_FAST_AHB_CLK_SRC 300000000 300000000 300000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CRE_CLK_SRC 200000000 400000000 480000000 600000000 600000000 1 0 0>, + <0x2 VIDEO_CC_MVS1_CLK_SRC 1050000000 1350000000 1500000000 1650000000 1650000000 1 0 0>, + <0x3 DISP_CC_MDSS_MDP_CLK_SRC 200000000 325000000 402000000 514000000 514000000 1 0 0>, + <0x3 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 270000000 270000000 540000000 810000000 810000000 1 0 0>, + <0x4 VIDEO_CC_MVS0_CLK_SRC 840000000 1140000000 1305000000 1440000000 1600000000 1 0 0>; + }; +}; diff --git a/pineapple/pineapple-mmrm.dts b/pineapple/pineapple-mmrm.dts new file mode 100644 index 00000000..f2e1f3ee --- /dev/null +++ b/pineapple/pineapple-mmrm.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include "pineapple-mmrm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Pineapple SoC"; + compatible = "qcom,pineapple"; + qcom,msm-id = <557 0x10000>, <557 0x20000>, + <577 0x10000>, <577 0x20000>; + qcom,board-id = <0 0>; /* required by merge_dtbs.py */ +}; diff --git a/pineapple/pineapple-mmrm.dtsi b/pineapple/pineapple-mmrm.dtsi new file mode 100644 index 00000000..cbe5fab9 --- /dev/null +++ b/pineapple/pineapple-mmrm.dtsi @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + msm_mmrm: qcom,mmrm { + compatible = "qcom,msm-mmrm", "qcom,pineapple-mmrm"; + status = "okay"; + + /* MMRM clock threshold */ + mmrm-peak-threshold = <10000>; + + /* MM Rail info */ + mm-rail-corners = "lowsvs", "svs", "svsl1", "nom", "noml1", "turbo"; + mm-rail-fact-volt = <38929 40633 41944 44237 49349 49349>; + + /* Scaling factors */ + scaling-fact-dyn = <50856 55706 59638 66847 84804 84804>; + scaling-fact-leak = <831718 890766 938410 1025967 1249903 1249903>; + + /* Client info */ + mmrm-client-info = + <0x1 CAM_CC_IFE_0_CLK_SRC 25563894 315884 1>, + <0x1 CAM_CC_IFE_1_CLK_SRC 25563894 315884 1>, + <0x1 CAM_CC_IFE_2_CLK_SRC 25563894 315884 1>, + <0x1 CAM_CC_CSID_CLK_SRC 2121415 56165 3>, + <0x1 CAM_CC_SFE_0_CLK_SRC 23995177 352199 1>, + <0x1 CAM_CC_SFE_1_CLK_SRC 23995177 352199 1>, + <0x1 CAM_CC_SFE_2_CLK_SRC 23995177 352199 1>, + <0x1 CAM_CC_IPE_NPS_CLK_SRC 76475209 874251 1>, + <0x1 CAM_CC_BPS_CLK_SRC 39943309 67337 1>, + <0x1 CAM_CC_IFE_LITE_CLK_SRC 1329704 29190 2>, + <0x1 CAM_CC_JPEG_CLK_SRC 778295 18351 4>, + <0x1 CAM_CC_CAMNOC_AXI_RT_CLK_SRC 8018836 158270 1>, + <0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 238635 15257 2>, + <0x1 CAM_CC_ICP_CLK_SRC 329148 7590 1>, + + <0x1 CAM_CC_CPHY_RX_CLK_SRC 19661 33247 10>, + <0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 6554 5 1>, + <0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 6554 5 1>, + <0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 6554 5 1>, + <0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 6554 5 1>, + <0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 6554 5 1>, + <0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 6554 5 1>, + <0x1 CAM_CC_CSI6PHYTIMER_CLK_SRC 6554 5 1>, + <0x1 CAM_CC_CSI7PHYTIMER_CLK_SRC 6554 5 1>, + <0x1 CAM_CC_CCI_0_CLK_SRC 0 397 1>, + <0x1 CAM_CC_CCI_1_CLK_SRC 0 397 1>, + <0x1 CAM_CC_CCI_2_CLK_SRC 0 397 1>, + <0x1 CAM_CC_SLOW_AHB_CLK_SRC 58983 11666 1>, + <0x1 CAM_CC_FAST_AHB_CLK_SRC 32768 6492 1>, + <0x1 CAM_CC_CRE_CLK_SRC 84182 1927 1>, + + <0x2 VIDEO_CC_MVS1_CLK_SRC 140136940 1283195 1>, + <0x3 DISP_CC_MDSS_MDP_CLK_SRC 14273741 213648 1>, + <0x3 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 707789 3572 1>, + <0x4 VIDEO_CC_MVS0_CLK_SRC 41008497 1926104 1>; + }; +}; diff --git a/sun/sun-mmrm-test.dts b/sun/sun-mmrm-test.dts new file mode 100644 index 00000000..a9f60612 --- /dev/null +++ b/sun/sun-mmrm-test.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include "sun-mmrm-test.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun SoC"; + compatible = "qcom,sun"; + qcom,msm-id = <618 0x10000>, <639 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/sun/sun-mmrm-test.dtsi b/sun/sun-mmrm-test.dtsi new file mode 100644 index 00000000..5223b3a3 --- /dev/null +++ b/sun/sun-mmrm-test.dtsi @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + msm_mmrm_test: qcom,mmrm-test { + compatible = "qcom,msm-mmrm-test", "qcom,sun-mmrm-test"; + status = "disable"; + + /* Clock info */ + clock-names = + "cam_cc_camnoc_rt_axi_clk_src", + "cam_cc_csid_clk_src", + "cam_cc_icp_0_clk_src", + "cam_cc_icp_1_clk_src", + "cam_cc_ife_lite_clk_src", + "cam_cc_ipe_nps_clk_src", + "cam_cc_jpeg_clk_src", + "cam_cc_ofe_clk_src", + "cam_cc_tfe_0_clk_src", + "cam_cc_tfe_1_clk_src", + "cam_cc_tfe_2_clk_src", + "cam_cc_fast_ahb_clk_src", + "cam_cc_slow_ahb_clk_src", + "cam_cc_cci_0_clk_src", + "cam_cc_cci_1_clk_src", + "cam_cc_cci_2_clk_src", + "cam_cc_cre_clk_src", + "cam_cc_csi0phytimer_clk_src", + "cam_cc_csi1phytimer_clk_src", + "cam_cc_csi2phytimer_clk_src", + "cam_cc_csi3phytimer_clk_src", + "cam_cc_csi4phytimer_clk_src", + "cam_cc_csi5phytimer_clk_src", + "cam_cc_cphy_rx_clk_src", + "cam_cc_ife_lite_csid_clk_src", + "eva_cc_mvs0_clk_src", + "disp_cc_mdss_mdp_clk_src", + "video_cc_mvs0_clk_src"; + + clocks = + <&camcc CAM_CC_CAMNOC_RT_AXI_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_ICP_0_CLK_SRC>, + <&camcc CAM_CC_ICP_1_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IPE_NPS_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_OFE_CLK_SRC>, + <&camcc CAM_CC_TFE_0_CLK_SRC>, + <&camcc CAM_CC_TFE_1_CLK_SRC>, + <&camcc CAM_CC_TFE_2_CLK_SRC>, + <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CCI_0_CLK_SRC>, + <&camcc CAM_CC_CCI_1_CLK_SRC>, + <&camcc CAM_CC_CCI_2_CLK_SRC>, + <&camcc CAM_CC_CRE_CLK_SRC>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&evacc EVA_CC_MVS0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, + <&videocc VIDEO_CC_MVS0_CLK_SRC>; + + /* + * clock_data : domain, clock-ID, + * rate-LOWSVS, rate-SVS, rate-SVS_L1, rate-NOM, rate-TURBO, + * num_hw_blocks, hw_drv_instances, num_pwr_states + */ + clock_data = + <0x1 CAM_CC_CAMNOC_RT_AXI_CLK_SRC 300000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000 1 0 0>, + <0x1 CAM_CC_ICP_0_CLK_SRC 400000000 480000000 600000000 600000000 600000000 1 0 0>, + <0x1 CAM_CC_ICP_1_CLK_SRC 400000000 480000000 600000000 600000000 600000000 1 0 0>, + <0x1 CAM_CC_IFE_LITE_CLK_SRC 400000000 480000000 480000000 480000000 480000000 1 0 0>, + <0x1 CAM_CC_IPE_NPS_CLK_SRC 475000000 575000000 675000000 825000000 825000000 1 0 0>, + <0x1 CAM_CC_JPEG_CLK_SRC 200000000 400000000 480000000 600000000 600000000 1 0 0>, + <0x1 CAM_CC_OFE_CLK_SRC 484000000 586000000 688000000 841000000 841000000 1 0 0>, + <0x1 CAM_CC_TFE_0_CLK_SRC 480000000 630000000 716000000 833000000 833000000 1 0 0>, + <0x1 CAM_CC_TFE_1_CLK_SRC 480000000 630000000 716000000 833000000 833000000 1 0 0>, + <0x1 CAM_CC_TFE_2_CLK_SRC 480000000 630000000 716000000 833000000 833000000 1 0 0>, + <0x1 CAM_CC_FAST_AHB_CLK_SRC 300000000 300000000 300000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_SLOW_AHB_CLK_SRC 80000000 80000000 80000000 80000000 80000000 1 0 0>, + <0x1 CAM_CC_CCI_0_CLK_SRC 37500000 37500000 37500000 37500000 37500000 1 0 0>, + <0x1 CAM_CC_CCI_1_CLK_SRC 37500000 37500000 37500000 37500000 37500000 1 0 0>, + <0x1 CAM_CC_CCI_2_CLK_SRC 37500000 37500000 37500000 37500000 37500000 1 0 0>, + <0x1 CAM_CC_CRE_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CPHY_RX_CLK_SRC 400000000 480000000 480000000 480000000 480000000 10 0 0>, + <0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000 2 0 0>, + <0x1 EVA_CC_MVS0_CLK_SRC 1200000000 1350000000 1500000000 1650000000 1650000000 1 0 0>, + <0x1 DISP_CC_MDSS_MDP_CLK_SRC 207000000 337000000 417000000 532000000 575000000 1 0 0>, + <0x1 VIDEO_CC_MVS0_CLK_SRC 1014000000 1260000000 1332000000 1600000000 1890000000 1 0 0>; + }; +}; diff --git a/sun/sun-mmrm.dts b/sun/sun-mmrm.dts new file mode 100644 index 00000000..ee03ab3b --- /dev/null +++ b/sun/sun-mmrm.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include "sun-mmrm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun SoC"; + compatible = "qcom,sun"; + qcom,msm-id = <618 0x10000>, <639 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/sun/sun-mmrm.dtsi b/sun/sun-mmrm.dtsi new file mode 100644 index 00000000..e0e9987a --- /dev/null +++ b/sun/sun-mmrm.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + msm_mmrm: qcom,mmrm { + compatible = "qcom,msm-mmrm", "qcom,sun-mmrm"; + status = "okay"; + + /* MMRM clock threshold */ + mmrm-peak-threshold = <10000>; + + /* MM Rail info */ + mm-rail-corners = "lowsvs", "svs", "svsl1", "nom", "noml1", "turbo"; + mm-rail-fact-volt = <37487 41157 44827 47711 50332 52429>; + + /* Scaling factors */ + scaling-fact-dyn = <39977 48497 57672 66192 74056 81265>; + scaling-fact-leak = <827720 969278 1133118 1283851 1445069 1597768>; + + /* Client info */ + mmrm-client-info = + <0x1 CAM_CC_CAMNOC_RT_AXI_CLK_SRC 3193177 86508 1>, + <0x1 CAM_CC_CSID_CLK_SRC 1285358 55706 3>, + <0x1 CAM_CC_ICP_0_CLK_SRC 253232 17040 1>, + <0x1 CAM_CC_ICP_1_CLK_SRC 253232 17040 1>, + <0x1 CAM_CC_IFE_LITE_CLK_SRC 274531 10028 2>, + <0x1 CAM_CC_IPE_NPS_CLK_SRC 50230789 394986 1>, + <0x1 CAM_CC_JPEG_CLK_SRC 551486 17040 4>, + <0x1 CAM_CC_OFE_CLK_SRC 63019221 400622 1>, + <0x1 CAM_CC_TFE_0_CLK_SRC 17560437 241435 1>, + <0x1 CAM_CC_TFE_1_CLK_SRC 17560437 241435 1>, + <0x1 CAM_CC_TFE_2_CLK_SRC 17604543 248120 1>, + <0x1 CAM_CC_FAST_AHB_CLK_SRC 32768 6554 1>, + <0x1 CAM_CC_SLOW_AHB_CLK_SRC 58983 11797 1>, + <0x1 CAM_CC_CCI_0_CLK_SRC 0 656 1>, + <0x1 CAM_CC_CCI_1_CLK_SRC 0 656 1>, + <0x1 CAM_CC_CCI_2_CLK_SRC 0 656 1>, + <0x1 CAM_CC_CRE_CLK_SRC 65536 1967 1>, + <0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CPHY_RX_CLK_SRC 19661 33424 10>, + <0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 262144 15074 2>, + + <0x2 EVA_CC_MVS0_CLK_SRC 47360246 407372 1>, + <0x3 DISP_CC_MDSS_MDP_CLK_SRC 21561344 319816 1>, + <0x4 VIDEO_CC_MVS0_CLK_SRC 29233906 839582 1>; + }; +}; diff --git a/waipio/waipio-mmrm-test.dts b/waipio/waipio-mmrm-test.dts new file mode 100644 index 00000000..57a45784 --- /dev/null +++ b/waipio/waipio-mmrm-test.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include "waipio-mmrm-test.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. waipio v1 & v2 SoC"; + compatible = "qcom,waipio"; + qcom,msm-id = <457 0x10000>, <482 0x10000>; + qcom,board-id = <0 0>; /* required by merge_dtbs.py */ +}; diff --git a/waipio/waipio-mmrm-test.dtsi b/waipio/waipio-mmrm-test.dtsi new file mode 100644 index 00000000..1339205e --- /dev/null +++ b/waipio/waipio-mmrm-test.dtsi @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + msm_mmrm_test: qcom,mmrm-test { + compatible = "qcom,msm-mmrm-test", "qcom,waipio-mmrm-test"; + status = "disable"; + + /* Clock info */ + clock-names = + "cam_cc_ife_0_clk_src", + "cam_cc_ife_1_clk_src", + "cam_cc_ife_2_clk_src", + "cam_cc_csid_clk_src", + "cam_cc_sfe_0_clk_src", + "cam_cc_sfe_1_clk_src", + "cam_cc_ipe_nps_clk_src", + "cam_cc_bps_clk_src", + "cam_cc_ife_lite_clk_src", + "cam_cc_jpeg_clk_src", + "cam_cc_camnoc_axi_clk_src", + "cam_cc_ife_lite_csid_clk_src", + "cam_cc_icp_clk_src", + "cam_cc_cphy_rx_clk_src", + "cam_cc_csi0phytimer_clk_src", + "cam_cc_csi1phytimer_clk_src", + "cam_cc_csi2phytimer_clk_src", + "cam_cc_csi3phytimer_clk_src", + "cam_cc_csi4phytimer_clk_src", + "cam_cc_csi5phytimer_clk_src", + "cam_cc_cci_0_clk_src", + "cam_cc_cci_1_clk_src", + "cam_cc_slow_ahb_clk_src", + "cam_cc_fast_ahb_clk_src", + "video_cc_mvs1_clk_src", + "disp_cc_mdss_mdp_clk_src", + "disp_cc_mdss_dptx0_link_clk_src", + "video_cc_mvs0_clk_src"; + clocks = + <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_2_CLK_SRC>, + <&clock_camcc CAM_CC_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_SFE_0_CLK_SRC>, + <&clock_camcc CAM_CC_SFE_1_CLK_SRC>, + <&clock_camcc CAM_CC_IPE_NPS_CLK_SRC>, + <&clock_camcc CAM_CC_BPS_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&clock_camcc CAM_CC_JPEG_CLK_SRC>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_ICP_CLK_SRC>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CCI_0_CLK_SRC>, + <&clock_camcc CAM_CC_CCI_1_CLK_SRC>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&clock_videocc VIDEO_CC_MVS1_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_MDP_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&clock_videocc VIDEO_CC_MVS0_CLK_SRC>; + clock_rates = + <0x1 CAM_CC_IFE_0_CLK_SRC 432000000 594000000 675000000 785000000 785000000>, + <0x1 CAM_CC_IFE_1_CLK_SRC 432000000 594000000 675000000 785000000 785000000>, + <0x1 CAM_CC_IFE_2_CLK_SRC 432000000 594000000 675000000 785000000 785000000>, + <0x1 CAM_CC_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000>, + <0x1 CAM_CC_SFE_0_CLK_SRC 432000000 594000000 675000000 785000000 785000000>, + <0x1 CAM_CC_SFE_1_CLK_SRC 364000000 500000000 600000000 700000000 700000000>, + <0x1 CAM_CC_IPE_NPS_CLK_SRC 200000000 400000000 480000000 600000000 600000000>, + <0x1 CAM_CC_BPS_CLK_SRC 200000000 400000000 480000000 600000000 600000000>, + <0x1 CAM_CC_IFE_LITE_CLK_SRC 400000000 480000000 480000000 480000000 480000000>, + <0x1 CAM_CC_JPEG_CLK_SRC 200000000 400000000 480000000 600000000 600000000>, + <0x1 CAM_CC_CAMNOC_AXI_CLK_SRC 300000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000>, + <0x1 CAM_CC_ICP_CLK_SRC 400000000 480000000 600000000 600000000 600000000>, + <0x1 CAM_CC_CPHY_RX_CLK_SRC 400000000 480000000 480000000 480000000 480000000>, + <0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_CCI_0_CLK_SRC 37500000 37500000 37500000 37500000 37500000>, + <0x1 CAM_CC_CCI_1_CLK_SRC 37500000 37500000 37500000 37500000 37500000>, + <0x1 CAM_CC_SLOW_AHB_CLK_SRC 80000000 80000000 80000000 80000000 80000000>, + <0x1 CAM_CC_FAST_AHB_CLK_SRC 100000000 200000000 300000000 400000000 400000000>, + <0x2 VIDEO_CC_MVS1_CLK_SRC 1050000000 1350000000 1500000000 1650000000 1650000000>, + <0x3 DISP_CC_MDSS_MDP_CLK_SRC 200000000 325000000 375000000 500000000 500000000>, + <0x3 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 270000 270000 540000 810000 810000>, + <0x4 VIDEO_CC_MVS0_CLK_SRC 720000000 1014000000 1098000000 1332000000 1332000000>; + }; +}; diff --git a/waipio/waipio-mmrm.dts b/waipio/waipio-mmrm.dts new file mode 100644 index 00000000..fde5e3c3 --- /dev/null +++ b/waipio/waipio-mmrm.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include "waipio-mmrm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. waipio v1 SoC"; + compatible = "qcom,waipio"; + qcom,msm-id = <457 0x10000>, <482 0x10000>; + qcom,board-id = <0 0>; /* required by merge_dtbs.py */ +}; diff --git a/waipio/waipio-mmrm.dtsi b/waipio/waipio-mmrm.dtsi new file mode 100644 index 00000000..04da1496 --- /dev/null +++ b/waipio/waipio-mmrm.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + msm_mmrm: qcom,mmrm { + compatible = "qcom,msm-mmrm", "qcom,waipio-mmrm"; + status = "okay"; + + /* MMRM clock threshold */ + mmrm-peak-threshold = <9000>; + + /* MM Rail info */ + mm-rail-corners = "lowsvs", "svs", "svsl1", "nom", "noml1", "turbo"; + mm-rail-fact-volt = <36439 41157 44827 49152 54526 54526>; + + /* Scaling factors */ + scaling-fact-dyn = <35390 45876 54395 66192 82576 82576>; + scaling-fact-leak = <451544 548537 633078 746456 920126 920126>; + + /* Client info */ + mmrm-client-info = + <0x1 CAM_CC_IFE_0_CLK_SRC 36280730 260834 1>, + <0x1 CAM_CC_IFE_1_CLK_SRC 36280730 260834 1>, + <0x1 CAM_CC_IFE_2_CLK_SRC 36280730 260834 1>, + <0x1 CAM_CC_CSID_CLK_SRC 2160722 0 3>, + <0x1 CAM_CC_SFE_0_CLK_SRC 20833895 135660 1>, + <0x1 CAM_CC_SFE_1_CLK_SRC 20833895 135660 1>, + <0x1 CAM_CC_IPE_NPS_CLK_SRC 67423437 608830 1>, + <0x1 CAM_CC_BPS_CLK_SRC 70584894 212992 1>, + <0x1 CAM_CC_IFE_LITE_CLK_SRC 1698431 20055 5>, + <0x1 CAM_CC_JPEG_CLK_SRC 1011876 0 2>, + <0x1 CAM_CC_CAMNOC_AXI_CLK_SRC 3407872 589824 1>, + <0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 262144 0 5>, + <0x1 CAM_CC_ICP_CLK_SRC 314573 0 1>, + <0x1 CAM_CC_CPHY_RX_CLK_SRC 222823 0 9>, + <0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CCI_0_CLK_SRC 656 0 1>, + <0x1 CAM_CC_CCI_1_CLK_SRC 656 0 1>, + <0x1 CAM_CC_SLOW_AHB_CLK_SRC 70124 0 1>, + <0x1 CAM_CC_FAST_AHB_CLK_SRC 35390 0 1>, + + <0x2 VIDEO_CC_MVS1_CLK_SRC 81149297 488244 1>, + <0x3 DISP_CC_MDSS_MDP_CLK_SRC 21954560 184812 1>, + <0x3 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 1004667 4916 1>, + <0x4 VIDEO_CC_MVS0_CLK_SRC 28970189 582288 1>; + }; +}; diff --git a/waipio/waipio-v2-mmrm-test.dts b/waipio/waipio-v2-mmrm-test.dts new file mode 100644 index 00000000..15feda13 --- /dev/null +++ b/waipio/waipio-v2-mmrm-test.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include "waipio-v2-mmrm-test.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. waipio v1 & v2 SoC"; + compatible = "qcom,waipio"; + qcom,msm-id = <457 0x20000>, <482 0x20000>; + qcom,board-id = <0 0>; /* required by merge_dtbs.py */ +}; diff --git a/waipio/waipio-v2-mmrm-test.dtsi b/waipio/waipio-v2-mmrm-test.dtsi new file mode 100644 index 00000000..381e0750 --- /dev/null +++ b/waipio/waipio-v2-mmrm-test.dtsi @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + msm_mmrm_test: qcom,mmrm-test { + compatible = "qcom,msm-mmrm-test", "qcom,waipio-mmrm-test"; + status = "disable"; + + /* Clock info */ + clock-names = + "cam_cc_ife_0_clk_src", + "cam_cc_ife_1_clk_src", + "cam_cc_ife_2_clk_src", + "cam_cc_csid_clk_src", + "cam_cc_sfe_0_clk_src", + "cam_cc_sfe_1_clk_src", + "cam_cc_ipe_nps_clk_src", + "cam_cc_bps_clk_src", + "cam_cc_ife_lite_clk_src", + "cam_cc_jpeg_clk_src", + "cam_cc_camnoc_axi_clk_src", + "cam_cc_ife_lite_csid_clk_src", + "cam_cc_icp_clk_src", + "cam_cc_cphy_rx_clk_src", + "cam_cc_csi0phytimer_clk_src", + "cam_cc_csi1phytimer_clk_src", + "cam_cc_csi2phytimer_clk_src", + "cam_cc_csi3phytimer_clk_src", + "cam_cc_csi4phytimer_clk_src", + "cam_cc_csi5phytimer_clk_src", + "cam_cc_cci_0_clk_src", + "cam_cc_cci_1_clk_src", + "cam_cc_slow_ahb_clk_src", + "cam_cc_fast_ahb_clk_src", + "video_cc_mvs1_clk_src", + "disp_cc_mdss_mdp_clk_src", + "disp_cc_mdss_dptx0_link_clk_src", + "video_cc_mvs0_clk_src"; + clocks = + <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_2_CLK_SRC>, + <&clock_camcc CAM_CC_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_SFE_0_CLK_SRC>, + <&clock_camcc CAM_CC_SFE_1_CLK_SRC>, + <&clock_camcc CAM_CC_IPE_NPS_CLK_SRC>, + <&clock_camcc CAM_CC_BPS_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&clock_camcc CAM_CC_JPEG_CLK_SRC>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_ICP_CLK_SRC>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CCI_0_CLK_SRC>, + <&clock_camcc CAM_CC_CCI_1_CLK_SRC>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&clock_videocc VIDEO_CC_MVS1_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_MDP_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&clock_videocc VIDEO_CC_MVS0_CLK_SRC>; + clock_rates = + <0x1 CAM_CC_IFE_0_CLK_SRC 432000000 594000000 675000000 727000000 727000000>, + <0x1 CAM_CC_IFE_1_CLK_SRC 432000000 594000000 675000000 727000000 727000000>, + <0x1 CAM_CC_IFE_2_CLK_SRC 432000000 594000000 675000000 727000000 727000000>, + <0x1 CAM_CC_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000>, + <0x1 CAM_CC_SFE_0_CLK_SRC 432000000 594000000 675000000 727000000 727000000>, + <0x1 CAM_CC_SFE_1_CLK_SRC 432000000 594000000 675000000 727000000 727000000>, + <0x1 CAM_CC_IPE_NPS_CLK_SRC 364000000 500000000 600000000 700000000 700000000>, + <0x1 CAM_CC_BPS_CLK_SRC 200000000 400000000 480000000 600000000 600000000>, + <0x1 CAM_CC_IFE_LITE_CLK_SRC 400000000 480000000 480000000 480000000 480000000>, + <0x1 CAM_CC_JPEG_CLK_SRC 200000000 400000000 480000000 600000000 600000000>, + <0x1 CAM_CC_CAMNOC_AXI_CLK_SRC 300000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000>, + <0x1 CAM_CC_ICP_CLK_SRC 400000000 480000000 600000000 600000000 600000000>, + <0x1 CAM_CC_CPHY_RX_CLK_SRC 400000000 480000000 480000000 480000000 480000000>, + <0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>, + <0x1 CAM_CC_CCI_0_CLK_SRC 37500000 37500000 37500000 37500000 37500000>, + <0x1 CAM_CC_CCI_1_CLK_SRC 37500000 37500000 37500000 37500000 37500000>, + <0x1 CAM_CC_SLOW_AHB_CLK_SRC 80000000 80000000 80000000 80000000 80000000>, + <0x1 CAM_CC_FAST_AHB_CLK_SRC 100000000 200000000 300000000 400000000 400000000>, + <0x2 VIDEO_CC_MVS1_CLK_SRC 1050000000 1350000000 1500000000 1650000000 1650000000>, + <0x3 DISP_CC_MDSS_MDP_CLK_SRC 200000000 325000000 375000000 500000000 500000000>, + <0x3 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 270000 270000 540000 810000 810000>, + <0x4 VIDEO_CC_MVS0_CLK_SRC 720000000 1014000000 1098000000 1332000000 1332000000>; + }; +}; diff --git a/waipio/waipio-v2-mmrm.dts b/waipio/waipio-v2-mmrm.dts new file mode 100644 index 00000000..97f0563a --- /dev/null +++ b/waipio/waipio-v2-mmrm.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include "waipio-v2-mmrm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. waipio v2 SoC"; + compatible = "qcom,waipio"; + qcom,msm-id = <457 0x20000>, <482 0x20000>; + qcom,board-id = <0 0>; /* required by merge_dtbs.py */ +}; diff --git a/waipio/waipio-v2-mmrm.dtsi b/waipio/waipio-v2-mmrm.dtsi new file mode 100644 index 00000000..539ce0e9 --- /dev/null +++ b/waipio/waipio-v2-mmrm.dtsi @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + msm_mmrm: qcom,mmrm { + compatible = "qcom,msm-mmrm", "qcom,waipio-mmrm"; + status = "okay"; + + /* MMRM clock threshold */ + mmrm-peak-threshold = <9000>; + + /* MM Rail info */ + mm-rail-corners = "lowsvs", "svs", "svsl1", "nom", "noml1", "turbo"; + mm-rail-fact-volt = <36438 41157 44827 49152 54526 54526>; + + /* Scaling factors */ + scaling-fact-dyn = <35389 45876 54395 66192 82575 82575>; + scaling-fact-leak = <451543 548537 633078 746456 920125 920125>; + + /* Client info */ + mmrm-client-info = + <0x1 CAM_CC_IFE_0_CLK_SRC 33751040 279839 1>, + <0x1 CAM_CC_IFE_1_CLK_SRC 33751040 279839 1>, + <0x1 CAM_CC_IFE_2_CLK_SRC 33751040 279839 1>, + <0x1 CAM_CC_CSID_CLK_SRC 2160722 0 3>, + <0x1 CAM_CC_SFE_0_CLK_SRC 19333120 132383 1>, + <0x1 CAM_CC_SFE_1_CLK_SRC 19333120 132383 1>, + <0x1 CAM_CC_IPE_NPS_CLK_SRC 67436544 587203 1>, + <0x1 CAM_CC_BPS_CLK_SRC 70584893 334234 1>, + <0x1 CAM_CC_IFE_LITE_CLK_SRC 8492155 11796 5>, + <0x1 CAM_CC_JPEG_CLK_SRC 1097073 595067 2>, + <0x1 CAM_CC_CAMNOC_AXI_CLK_SRC 7602176 3533701 1>, + <0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 262144 0 5>, + <0x1 CAM_CC_ICP_CLK_SRC 314573 0 1>, + <0x1 CAM_CC_CPHY_RX_CLK_SRC 222822 0 9>, + <0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CCI_0_CLK_SRC 655 0 1>, + <0x1 CAM_CC_CCI_1_CLK_SRC 655 0 1>, + <0x1 CAM_CC_SLOW_AHB_CLK_SRC 70124 0 1>, + <0x1 CAM_CC_FAST_AHB_CLK_SRC 35389 0 1>, + <0x2 VIDEO_CC_MVS1_CLK_SRC 81149297 488243 1>, + <0x3 DISP_CC_MDSS_MDP_CLK_SRC 21954560 184812 1>, + <0x3 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 1004667 5243 1>, + <0x4 VIDEO_CC_MVS0_CLK_SRC 28970189 582287 1>; + }; +}; From bbac280506f1abead98a2f0d8f012233949317f0 Mon Sep 17 00:00:00 2001 From: Vedang Nagar Date: Thu, 28 Mar 2024 10:52:01 +0530 Subject: [PATCH 3/8] ARM: dts: msm: Add support for sun V2 devices Adding support for sun v2 devices Change-Id: I3bc8fadb31dff0bbb7f43bb0cdc5e298221ec9be Signed-off-by: Vedang Nagar --- sun/sun-mmrm-test.dts | 3 ++- sun/sun-mmrm.dts | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/sun/sun-mmrm-test.dts b/sun/sun-mmrm-test.dts index a9f60612..6b4074c5 100644 --- a/sun/sun-mmrm-test.dts +++ b/sun/sun-mmrm-test.dts @@ -15,6 +15,7 @@ / { model = "Qualcomm Technologies, Inc. Sun SoC"; compatible = "qcom,sun"; - qcom,msm-id = <618 0x10000>, <639 0x10000>; + qcom,msm-id = <618 0x10000>, <639 0x10000>, + <618 0x20000>, <639 0x20000>; qcom,board-id = <0 0>; }; diff --git a/sun/sun-mmrm.dts b/sun/sun-mmrm.dts index ee03ab3b..d40e938e 100644 --- a/sun/sun-mmrm.dts +++ b/sun/sun-mmrm.dts @@ -15,6 +15,7 @@ / { model = "Qualcomm Technologies, Inc. Sun SoC"; compatible = "qcom,sun"; - qcom,msm-id = <618 0x10000>, <639 0x10000>; + qcom,msm-id = <618 0x10000>, <639 0x10000>, + <618 0x20000>, <639 0x20000>; qcom,board-id = <0 0>; }; From 156118b0013c5679074fecd0d2c7fbba87d0a0e1 Mon Sep 17 00:00:00 2001 From: Vedang Nagar Date: Thu, 4 Apr 2024 15:25:51 -0700 Subject: [PATCH 4/8] mmrm dts: msm: new MSM-ID to support for different packagings add new MSM-ID for SUN target Change-Id: Ia83d5b35dd4af6c1cc4a61ccf273c9c0e96a0bc3 Signed-off-by: Vedang Nagar --- sun/sun-mmrm-test.dts | 4 +++- sun/sun-mmrm.dts | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/sun/sun-mmrm-test.dts b/sun/sun-mmrm-test.dts index 6b4074c5..2888aad5 100644 --- a/sun/sun-mmrm-test.dts +++ b/sun/sun-mmrm-test.dts @@ -16,6 +16,8 @@ model = "Qualcomm Technologies, Inc. Sun SoC"; compatible = "qcom,sun"; qcom,msm-id = <618 0x10000>, <639 0x10000>, - <618 0x20000>, <639 0x20000>; + <618 0x20000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100027f 0x10000>, + <0x100026a 0x20000>, <0x100027f 0x20000>; qcom,board-id = <0 0>; }; diff --git a/sun/sun-mmrm.dts b/sun/sun-mmrm.dts index d40e938e..20e6352c 100644 --- a/sun/sun-mmrm.dts +++ b/sun/sun-mmrm.dts @@ -16,6 +16,8 @@ model = "Qualcomm Technologies, Inc. Sun SoC"; compatible = "qcom,sun"; qcom,msm-id = <618 0x10000>, <639 0x10000>, - <618 0x20000>, <639 0x20000>; + <618 0x20000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100027f 0x10000>, + <0x100026a 0x20000>, <0x100027f 0x20000>; qcom,board-id = <0 0>; }; From d0684af03f6fbbb9b26cdc9077fb2a2fe00fdf0d Mon Sep 17 00:00:00 2001 From: Vedang Nagar Date: Thu, 4 Apr 2024 15:25:51 -0700 Subject: [PATCH 5/8] mmrm dts: msm: new MSM-ID to support for different packagings add new MSM-ID for SUN target Change-Id: Ia83d5b35dd4af6c1cc4a61ccf273c9c0e96a0bc3 Signed-off-by: Vedang Nagar Signed-off-by: Bruce Levy --- sun/sun-mmrm-test.dts | 4 +++- sun/sun-mmrm.dts | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/sun/sun-mmrm-test.dts b/sun/sun-mmrm-test.dts index 6b4074c5..2888aad5 100644 --- a/sun/sun-mmrm-test.dts +++ b/sun/sun-mmrm-test.dts @@ -16,6 +16,8 @@ model = "Qualcomm Technologies, Inc. Sun SoC"; compatible = "qcom,sun"; qcom,msm-id = <618 0x10000>, <639 0x10000>, - <618 0x20000>, <639 0x20000>; + <618 0x20000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100027f 0x10000>, + <0x100026a 0x20000>, <0x100027f 0x20000>; qcom,board-id = <0 0>; }; diff --git a/sun/sun-mmrm.dts b/sun/sun-mmrm.dts index d40e938e..20e6352c 100644 --- a/sun/sun-mmrm.dts +++ b/sun/sun-mmrm.dts @@ -16,6 +16,8 @@ model = "Qualcomm Technologies, Inc. Sun SoC"; compatible = "qcom,sun"; qcom,msm-id = <618 0x10000>, <639 0x10000>, - <618 0x20000>, <639 0x20000>; + <618 0x20000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100027f 0x10000>, + <0x100026a 0x20000>, <0x100027f 0x20000>; qcom,board-id = <0 0>; }; From 8457ce5818ef92472214ed1176d849084ee48b38 Mon Sep 17 00:00:00 2001 From: Linux Image Build Automation Date: Tue, 14 May 2024 01:56:33 -0700 Subject: [PATCH 6/8] Revert "mmrm dts: msm: new MSM-ID to support for different packagings" This reverts commit d0684af03f6fbbb9b26cdc9077fb2a2fe00fdf0d. Change-Id: I15a02e511e537f484f5db501a900748c375b694f Signed-off-by: Linux Image Build Automation --- sun/sun-mmrm-test.dts | 4 +--- sun/sun-mmrm.dts | 4 +--- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/sun/sun-mmrm-test.dts b/sun/sun-mmrm-test.dts index 2888aad5..6b4074c5 100644 --- a/sun/sun-mmrm-test.dts +++ b/sun/sun-mmrm-test.dts @@ -16,8 +16,6 @@ model = "Qualcomm Technologies, Inc. Sun SoC"; compatible = "qcom,sun"; qcom,msm-id = <618 0x10000>, <639 0x10000>, - <618 0x20000>, <639 0x20000>, - <0x100026a 0x10000>, <0x100027f 0x10000>, - <0x100026a 0x20000>, <0x100027f 0x20000>; + <618 0x20000>, <639 0x20000>; qcom,board-id = <0 0>; }; diff --git a/sun/sun-mmrm.dts b/sun/sun-mmrm.dts index 20e6352c..d40e938e 100644 --- a/sun/sun-mmrm.dts +++ b/sun/sun-mmrm.dts @@ -16,8 +16,6 @@ model = "Qualcomm Technologies, Inc. Sun SoC"; compatible = "qcom,sun"; qcom,msm-id = <618 0x10000>, <639 0x10000>, - <618 0x20000>, <639 0x20000>, - <0x100026a 0x10000>, <0x100027f 0x10000>, - <0x100026a 0x20000>, <0x100027f 0x20000>; + <618 0x20000>, <639 0x20000>; qcom,board-id = <0 0>; }; From 2c1be65d15618f9bc3cb1a665f1c143ee0819b33 Mon Sep 17 00:00:00 2001 From: Megha Byahatti Date: Tue, 17 Dec 2024 14:13:02 +0530 Subject: [PATCH 7/8] mmrm: drvier: Add mmrm devicetree support for tuna variant Add mmrm devicetree support for tuna variant Change-Id: I18339a06951c6b562a6b4e3b3b9058599d08540b Signed-off-by: Megha Byahatti --- Kbuild | 6 +++ tuna/tuna-mmrm-test.dts | 20 ++++++++ tuna/tuna-mmrm-test.dtsi | 107 +++++++++++++++++++++++++++++++++++++++ tuna/tuna-mmrm.dts | 20 ++++++++ tuna/tuna-mmrm.dtsi | 54 ++++++++++++++++++++ 5 files changed, 207 insertions(+) create mode 100644 tuna/tuna-mmrm-test.dts create mode 100644 tuna/tuna-mmrm-test.dtsi create mode 100644 tuna/tuna-mmrm.dts create mode 100644 tuna/tuna-mmrm.dtsi diff --git a/Kbuild b/Kbuild index d4bed0d9..ae7a2d3f 100644 --- a/Kbuild +++ b/Kbuild @@ -1,3 +1,9 @@ +ifeq ($(CONFIG_ARCH_TUNA), y) +dtbo-y += tuna/tuna-mmrm.dtbo +dtbo-y += tuna/tuna-mmrm-test.dtbo +endif + + ifeq ($(CONFIG_ARCH_SUN), y) dtbo-y += sun/sun-mmrm.dtbo dtbo-y += sun/sun-mmrm-test.dtbo diff --git a/tuna/tuna-mmrm-test.dts b/tuna/tuna-mmrm-test.dts new file mode 100644 index 00000000..de5b9074 --- /dev/null +++ b/tuna/tuna-mmrm-test.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include "tuna-mmrm-test.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun SoC"; + compatible = "qcom,tuna"; + qcom,msm-id = <655 0x10000>, <681 0x10000>, <694 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/tuna/tuna-mmrm-test.dtsi b/tuna/tuna-mmrm-test.dtsi new file mode 100644 index 00000000..3c46dd09 --- /dev/null +++ b/tuna/tuna-mmrm-test.dtsi @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + msm_mmrm_test: qcom,mmrm-test { + compatible = "qcom,msm-mmrm-test", "qcom,tuna-mmrm-test"; + status = "disable"; + + /* Clock info */ + clock-names = + "cam_cc_camnoc_rt_axi_clk_src", + "cam_cc_csid_clk_src", + "cam_cc_icp_0_clk_src", + "cam_cc_icp_1_clk_src", + "cam_cc_ife_lite_clk_src", + "cam_cc_ipe_nps_clk_src", + "cam_cc_jpeg_clk_src", + "cam_cc_ofe_clk_src", + "cam_cc_tfe_0_clk_src", + "cam_cc_tfe_1_clk_src", + "cam_cc_tfe_2_clk_src", + "cam_cc_fast_ahb_clk_src", + "cam_cc_slow_ahb_clk_src", + "cam_cc_cci_0_clk_src", + "cam_cc_cci_1_clk_src", + "cam_cc_cci_2_clk_src", + "cam_cc_cre_clk_src", + "cam_cc_csi0phytimer_clk_src", + "cam_cc_csi1phytimer_clk_src", + "cam_cc_csi2phytimer_clk_src", + "cam_cc_csi3phytimer_clk_src", + "cam_cc_csi4phytimer_clk_src", + "cam_cc_csi5phytimer_clk_src", + "cam_cc_cphy_rx_clk_src", + "cam_cc_ife_lite_csid_clk_src", + "eva_cc_mvs0_clk_src", + "disp_cc_mdss_mdp_clk_src", + "video_cc_mvs0_clk_src"; + + clocks = + <&camcc CAM_CC_CAMNOC_RT_AXI_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_ICP_0_CLK_SRC>, + <&camcc CAM_CC_ICP_1_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IPE_NPS_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_OFE_CLK_SRC>, + <&camcc CAM_CC_TFE_0_CLK_SRC>, + <&camcc CAM_CC_TFE_1_CLK_SRC>, + <&camcc CAM_CC_TFE_2_CLK_SRC>, + <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CCI_0_CLK_SRC>, + <&camcc CAM_CC_CCI_1_CLK_SRC>, + <&camcc CAM_CC_CCI_2_CLK_SRC>, + <&camcc CAM_CC_CRE_CLK_SRC>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&evacc EVA_CC_MVS0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, + <&videocc VIDEO_CC_MVS0_CLK_SRC>; + + /* + * clock_data : domain, clock-ID, + * rate-LOWSVS, rate-SVS, rate-SVS_L1, rate-NOM, rate-TURBO, + * num_hw_blocks, hw_drv_instances, num_pwr_states + */ + clock_data = + <0x1 CAM_CC_CAMNOC_RT_AXI_CLK_SRC 300000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000 1 0 0>, + <0x1 CAM_CC_ICP_0_CLK_SRC 400000000 480000000 600000000 600000000 600000000 1 0 0>, + <0x1 CAM_CC_ICP_1_CLK_SRC 400000000 480000000 600000000 600000000 600000000 1 0 0>, + <0x1 CAM_CC_IFE_LITE_CLK_SRC 400000000 480000000 480000000 480000000 480000000 1 0 0>, + <0x1 CAM_CC_IPE_NPS_CLK_SRC 450000000 575000000 675000000 825000000 825000000 1 0 0>, + <0x1 CAM_CC_JPEG_CLK_SRC 200000000 400000000 480000000 600000000 600000000 1 0 0>, + <0x1 CAM_CC_OFE_CLK_SRC 436000000 570000000 675000000 757000000 757000000 1 0 0>, + <0x1 CAM_CC_TFE_0_CLK_SRC 400000000 525000000 644000000 750000000 750000000 1 0 0>, + <0x1 CAM_CC_TFE_1_CLK_SRC 400000000 525000000 644000000 750000000 750000000 1 0 0>, + <0x1 CAM_CC_TFE_2_CLK_SRC 400000000 525000000 644000000 750000000 750000000 1 0 0>, + <0x1 CAM_CC_FAST_AHB_CLK_SRC 300000000 300000000 300000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_SLOW_AHB_CLK_SRC 80000000 80000000 80000000 80000000 80000000 1 0 0>, + <0x1 CAM_CC_CCI_0_CLK_SRC 37500000 37500000 37500000 37500000 37500000 1 0 0>, + <0x1 CAM_CC_CCI_1_CLK_SRC 37500000 37500000 37500000 37500000 37500000 1 0 0>, + <0x1 CAM_CC_CCI_2_CLK_SRC 37500000 37500000 37500000 37500000 37500000 1 0 0>, + <0x1 CAM_CC_CRE_CLK_SRC 200000000 400000000 480000000 600000000 600000000 1 0 0>, + <0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CPHY_RX_CLK_SRC 400000000 480000000 480000000 480000000 480000000 10 0 0>, + <0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000 2 0 0>, + <0x1 EVA_CC_MVS0_CLK_SRC 350000000 450000000 500000000 550000000 550000000 1 0 0>, + <0x1 DISP_CC_MDSS_MDP_CLK_SRC 207000000 342000000 417000000 535000000 600000000 1 0 0>, + <0x1 VIDEO_CC_MVS0_CLK_SRC 338000000 3360000000 444000000 444000000 533000000 1 0 0>; + }; +}; diff --git a/tuna/tuna-mmrm.dts b/tuna/tuna-mmrm.dts new file mode 100644 index 00000000..0a166cdd --- /dev/null +++ b/tuna/tuna-mmrm.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include "tuna-mmrm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun SoC"; + compatible = "qcom,tuna"; + qcom,msm-id = <655 0x10000>, <681 0x10000>, <694 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/tuna/tuna-mmrm.dtsi b/tuna/tuna-mmrm.dtsi new file mode 100644 index 00000000..098fba51 --- /dev/null +++ b/tuna/tuna-mmrm.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + msm_mmrm: qcom,mmrm { + compatible = "qcom,msm-mmrm", "qcom,tuna-mmrm"; + status = "okay"; + + /* MMRM clock threshold */ + mmrm-peak-threshold = <10000>; + + /* MM Rail info */ + mm-rail-corners = "lowsvs", "svs", "svsl1", "nom", "noml1", "turbo"; + mm-rail-fact-volt = <35652 41157 44827 47711 50332 52429>; + + /* Scaling factors */ + scaling-fact-dyn = <36045 49152 58983 67503 75367 82576>; + scaling-fact-leak = <844760 1055785 1215038 1353974 1492911 1616118>; + + /* Client info */ + mmrm-client-info = + <0x1 CAM_CC_CAMNOC_RT_AXI_CLK_SRC 4459070 263455 1>, + <0x1 CAM_CC_CSID_CLK_SRC 1795032 131072 3>, + <0x1 CAM_CC_ICP_0_CLK_SRC 353895 17040 1>, + <0x1 CAM_CC_ICP_1_CLK_SRC 253232 17040 1>, + <0x1 CAM_CC_IFE_LITE_CLK_SRC 383386 418120 2>, + <0x1 CAM_CC_IPE_NPS_CLK_SRC 35389440 409600 1>, + <0x1 CAM_CC_JPEG_CLK_SRC 770048 26870 4>, + <0x1 CAM_CC_OFE_CLK_SRC 41680896 418120 1>, + <0x1 CAM_CC_TFE_0_CLK_SRC 22514893 312607 1>, + <0x1 CAM_CC_TFE_1_CLK_SRC 22514893 312607 1>, + <0x1 CAM_CC_TFE_2_CLK_SRC 22514893 312607 1>, + <0x1 CAM_CC_FAST_AHB_CLK_SRC 32768 6554 1>, + <0x1 CAM_CC_SLOW_AHB_CLK_SRC 58983 11797 1>, + <0x1 CAM_CC_CCI_0_CLK_SRC 0 656 1>, + <0x1 CAM_CC_CCI_1_CLK_SRC 0 656 1>, + <0x1 CAM_CC_CCI_2_CLK_SRC 0 656 1>, + <0x1 CAM_CC_CRE_CLK_SRC 65536 1967 1>, + <0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CPHY_RX_CLK_SRC 19661 33424 10>, + <0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 492831 24249 2>, + + <0x2 EVA_CC_MVS0_CLK_SRC 3723822 105513 1>, + <0x3 DISP_CC_MDSS_MDP_CLK_SRC 16117269 346686 1>, + <0x4 VIDEO_CC_MVS0_CLK_SRC 727974 8127 1>; + }; +}; From 94d2ad40f065791f2b1665b56e69060b6699e266 Mon Sep 17 00:00:00 2001 From: Megha Byahatti Date: Tue, 17 Dec 2024 14:13:02 +0530 Subject: [PATCH 8/8] mmrm: drvier: Add mmrm devicetree support for tuna variant Add mmrm devicetree support for tuna variant Change-Id: I18339a06951c6b562a6b4e3b3b9058599d08540b Signed-off-by: Megha Byahatti --- Kbuild | 6 +++ tuna/tuna-mmrm-test.dts | 20 ++++++++ tuna/tuna-mmrm-test.dtsi | 107 +++++++++++++++++++++++++++++++++++++++ tuna/tuna-mmrm.dts | 20 ++++++++ tuna/tuna-mmrm.dtsi | 54 ++++++++++++++++++++ 5 files changed, 207 insertions(+) create mode 100644 tuna/tuna-mmrm-test.dts create mode 100644 tuna/tuna-mmrm-test.dtsi create mode 100644 tuna/tuna-mmrm.dts create mode 100644 tuna/tuna-mmrm.dtsi diff --git a/Kbuild b/Kbuild index d4bed0d9..ae7a2d3f 100644 --- a/Kbuild +++ b/Kbuild @@ -1,3 +1,9 @@ +ifeq ($(CONFIG_ARCH_TUNA), y) +dtbo-y += tuna/tuna-mmrm.dtbo +dtbo-y += tuna/tuna-mmrm-test.dtbo +endif + + ifeq ($(CONFIG_ARCH_SUN), y) dtbo-y += sun/sun-mmrm.dtbo dtbo-y += sun/sun-mmrm-test.dtbo diff --git a/tuna/tuna-mmrm-test.dts b/tuna/tuna-mmrm-test.dts new file mode 100644 index 00000000..de5b9074 --- /dev/null +++ b/tuna/tuna-mmrm-test.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include "tuna-mmrm-test.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun SoC"; + compatible = "qcom,tuna"; + qcom,msm-id = <655 0x10000>, <681 0x10000>, <694 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/tuna/tuna-mmrm-test.dtsi b/tuna/tuna-mmrm-test.dtsi new file mode 100644 index 00000000..3c46dd09 --- /dev/null +++ b/tuna/tuna-mmrm-test.dtsi @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + msm_mmrm_test: qcom,mmrm-test { + compatible = "qcom,msm-mmrm-test", "qcom,tuna-mmrm-test"; + status = "disable"; + + /* Clock info */ + clock-names = + "cam_cc_camnoc_rt_axi_clk_src", + "cam_cc_csid_clk_src", + "cam_cc_icp_0_clk_src", + "cam_cc_icp_1_clk_src", + "cam_cc_ife_lite_clk_src", + "cam_cc_ipe_nps_clk_src", + "cam_cc_jpeg_clk_src", + "cam_cc_ofe_clk_src", + "cam_cc_tfe_0_clk_src", + "cam_cc_tfe_1_clk_src", + "cam_cc_tfe_2_clk_src", + "cam_cc_fast_ahb_clk_src", + "cam_cc_slow_ahb_clk_src", + "cam_cc_cci_0_clk_src", + "cam_cc_cci_1_clk_src", + "cam_cc_cci_2_clk_src", + "cam_cc_cre_clk_src", + "cam_cc_csi0phytimer_clk_src", + "cam_cc_csi1phytimer_clk_src", + "cam_cc_csi2phytimer_clk_src", + "cam_cc_csi3phytimer_clk_src", + "cam_cc_csi4phytimer_clk_src", + "cam_cc_csi5phytimer_clk_src", + "cam_cc_cphy_rx_clk_src", + "cam_cc_ife_lite_csid_clk_src", + "eva_cc_mvs0_clk_src", + "disp_cc_mdss_mdp_clk_src", + "video_cc_mvs0_clk_src"; + + clocks = + <&camcc CAM_CC_CAMNOC_RT_AXI_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_ICP_0_CLK_SRC>, + <&camcc CAM_CC_ICP_1_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IPE_NPS_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_OFE_CLK_SRC>, + <&camcc CAM_CC_TFE_0_CLK_SRC>, + <&camcc CAM_CC_TFE_1_CLK_SRC>, + <&camcc CAM_CC_TFE_2_CLK_SRC>, + <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CCI_0_CLK_SRC>, + <&camcc CAM_CC_CCI_1_CLK_SRC>, + <&camcc CAM_CC_CCI_2_CLK_SRC>, + <&camcc CAM_CC_CRE_CLK_SRC>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&evacc EVA_CC_MVS0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, + <&videocc VIDEO_CC_MVS0_CLK_SRC>; + + /* + * clock_data : domain, clock-ID, + * rate-LOWSVS, rate-SVS, rate-SVS_L1, rate-NOM, rate-TURBO, + * num_hw_blocks, hw_drv_instances, num_pwr_states + */ + clock_data = + <0x1 CAM_CC_CAMNOC_RT_AXI_CLK_SRC 300000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000 1 0 0>, + <0x1 CAM_CC_ICP_0_CLK_SRC 400000000 480000000 600000000 600000000 600000000 1 0 0>, + <0x1 CAM_CC_ICP_1_CLK_SRC 400000000 480000000 600000000 600000000 600000000 1 0 0>, + <0x1 CAM_CC_IFE_LITE_CLK_SRC 400000000 480000000 480000000 480000000 480000000 1 0 0>, + <0x1 CAM_CC_IPE_NPS_CLK_SRC 450000000 575000000 675000000 825000000 825000000 1 0 0>, + <0x1 CAM_CC_JPEG_CLK_SRC 200000000 400000000 480000000 600000000 600000000 1 0 0>, + <0x1 CAM_CC_OFE_CLK_SRC 436000000 570000000 675000000 757000000 757000000 1 0 0>, + <0x1 CAM_CC_TFE_0_CLK_SRC 400000000 525000000 644000000 750000000 750000000 1 0 0>, + <0x1 CAM_CC_TFE_1_CLK_SRC 400000000 525000000 644000000 750000000 750000000 1 0 0>, + <0x1 CAM_CC_TFE_2_CLK_SRC 400000000 525000000 644000000 750000000 750000000 1 0 0>, + <0x1 CAM_CC_FAST_AHB_CLK_SRC 300000000 300000000 300000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_SLOW_AHB_CLK_SRC 80000000 80000000 80000000 80000000 80000000 1 0 0>, + <0x1 CAM_CC_CCI_0_CLK_SRC 37500000 37500000 37500000 37500000 37500000 1 0 0>, + <0x1 CAM_CC_CCI_1_CLK_SRC 37500000 37500000 37500000 37500000 37500000 1 0 0>, + <0x1 CAM_CC_CCI_2_CLK_SRC 37500000 37500000 37500000 37500000 37500000 1 0 0>, + <0x1 CAM_CC_CRE_CLK_SRC 200000000 400000000 480000000 600000000 600000000 1 0 0>, + <0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>, + <0x1 CAM_CC_CPHY_RX_CLK_SRC 400000000 480000000 480000000 480000000 480000000 10 0 0>, + <0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000 2 0 0>, + <0x1 EVA_CC_MVS0_CLK_SRC 350000000 450000000 500000000 550000000 550000000 1 0 0>, + <0x1 DISP_CC_MDSS_MDP_CLK_SRC 207000000 342000000 417000000 535000000 600000000 1 0 0>, + <0x1 VIDEO_CC_MVS0_CLK_SRC 338000000 3360000000 444000000 444000000 533000000 1 0 0>; + }; +}; diff --git a/tuna/tuna-mmrm.dts b/tuna/tuna-mmrm.dts new file mode 100644 index 00000000..0a166cdd --- /dev/null +++ b/tuna/tuna-mmrm.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include "tuna-mmrm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun SoC"; + compatible = "qcom,tuna"; + qcom,msm-id = <655 0x10000>, <681 0x10000>, <694 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/tuna/tuna-mmrm.dtsi b/tuna/tuna-mmrm.dtsi new file mode 100644 index 00000000..098fba51 --- /dev/null +++ b/tuna/tuna-mmrm.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + msm_mmrm: qcom,mmrm { + compatible = "qcom,msm-mmrm", "qcom,tuna-mmrm"; + status = "okay"; + + /* MMRM clock threshold */ + mmrm-peak-threshold = <10000>; + + /* MM Rail info */ + mm-rail-corners = "lowsvs", "svs", "svsl1", "nom", "noml1", "turbo"; + mm-rail-fact-volt = <35652 41157 44827 47711 50332 52429>; + + /* Scaling factors */ + scaling-fact-dyn = <36045 49152 58983 67503 75367 82576>; + scaling-fact-leak = <844760 1055785 1215038 1353974 1492911 1616118>; + + /* Client info */ + mmrm-client-info = + <0x1 CAM_CC_CAMNOC_RT_AXI_CLK_SRC 4459070 263455 1>, + <0x1 CAM_CC_CSID_CLK_SRC 1795032 131072 3>, + <0x1 CAM_CC_ICP_0_CLK_SRC 353895 17040 1>, + <0x1 CAM_CC_ICP_1_CLK_SRC 253232 17040 1>, + <0x1 CAM_CC_IFE_LITE_CLK_SRC 383386 418120 2>, + <0x1 CAM_CC_IPE_NPS_CLK_SRC 35389440 409600 1>, + <0x1 CAM_CC_JPEG_CLK_SRC 770048 26870 4>, + <0x1 CAM_CC_OFE_CLK_SRC 41680896 418120 1>, + <0x1 CAM_CC_TFE_0_CLK_SRC 22514893 312607 1>, + <0x1 CAM_CC_TFE_1_CLK_SRC 22514893 312607 1>, + <0x1 CAM_CC_TFE_2_CLK_SRC 22514893 312607 1>, + <0x1 CAM_CC_FAST_AHB_CLK_SRC 32768 6554 1>, + <0x1 CAM_CC_SLOW_AHB_CLK_SRC 58983 11797 1>, + <0x1 CAM_CC_CCI_0_CLK_SRC 0 656 1>, + <0x1 CAM_CC_CCI_1_CLK_SRC 0 656 1>, + <0x1 CAM_CC_CCI_2_CLK_SRC 0 656 1>, + <0x1 CAM_CC_CRE_CLK_SRC 65536 1967 1>, + <0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 6554 0 1>, + <0x1 CAM_CC_CPHY_RX_CLK_SRC 19661 33424 10>, + <0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 492831 24249 2>, + + <0x2 EVA_CC_MVS0_CLK_SRC 3723822 105513 1>, + <0x3 DISP_CC_MDSS_MDP_CLK_SRC 16117269 346686 1>, + <0x4 VIDEO_CC_MVS0_CLK_SRC 727974 8127 1>; + }; +};