From 60fb7e2b874acd52b568c4dc38c4bb523ba63bca Mon Sep 17 00:00:00 2001 From: Paras Sharma Date: Tue, 17 Sep 2024 15:34:05 +0530 Subject: [PATCH] ARM: dts: msm: Add PCIe controller RC node for Tuna Add PCIe controller RC node for Tuna target. Change-Id: I5c81b2f691ded29ea49f35cf8afe2e41afb9930e Signed-off-by: Vivek Pernamitta Signed-off-by: Paras Sharma --- qcom/tuna-pcie.dtsi | 301 +++++++++++++++++++++++++++++++++++++++++ qcom/tuna-pinctrl.dtsi | 56 +++++++- qcom/tuna.dtsi | 13 +- 3 files changed, 368 insertions(+), 2 deletions(-) create mode 100644 qcom/tuna-pcie.dtsi diff --git a/qcom/tuna-pcie.dtsi b/qcom/tuna-pcie.dtsi new file mode 100644 index 00000000..b0972852 --- /dev/null +++ b/qcom/tuna-pcie.dtsi @@ -0,0 +1,301 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&soc { + pcie0: pcie@1c00000 { + compatible = "qcom,pci-msm"; + device_type = "pci"; + + reg = <0x1c00000 0x3000>, + <0x1c06000 0x2000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40100000 0x100000>, + <0x1c03000 0x1000>; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf", "mhi"; + + cell-index = <0>; + linux,pci-domain = <0>; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x40300000 0x0 0x3d00000>; + + interrupts = ; + + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + + msi-map = <0x0 &gic_its 0x1400 0x1>, + <0x100 &gic_its 0x1401 0x1>; /* 32 event IDs */ + + perst-gpio = <&tlmm 33 GPIO_ACTIVE_HIGH>; + wake-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pcie0_perst_default + &pcie0_clkreq_default + &pcie0_wake_default>; + pinctrl-1 = <&pcie0_perst_default + &pcie0_clkreq_sleep + &pcie0_wake_default>; + + gdsc-core-vdd-supply = <&gcc_pcie_0_gdsc>; + gdsc-phy-vdd-supply = <&gcc_pcie_0_phy_gdsc>; + + vreg-1p2-supply = <&L4B>; + vreg-0p9-supply = <&L2B>; + vreg-qref-supply = <&L2B>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + vreg-mx-supply = <&VDD_MXA_LEVEL>; + qcom,vreg-1p2-voltage-level = <1200000 1200000 15010>; + qcom,vreg-0p9-voltage-level = <912000 880000 92070>; + qcom,vreg-qref-voltage-level = <880000 880000 46800>; + qcom,vreg-cx-voltage-level = ; + qcom,vreg-mx-voltage-level = ; + + qcom,bw-scale = /* Gen1 */ + ; + + interconnect-names = "icc_path"; + interconnects = <&pcie_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&tcsrcc TCSR_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>, + <&gcc GCC_PCIE_0_PIPE_DIV2_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, + <&pcie_0_pipe_clk>; + clock-names = "pcie_pipe_clk", "pcie_ref_clk_src", + "pcie_aux_clk", "pcie_cfg_ahb_clk", + "pcie_mstr_axi_clk", "pcie_slv_axi_clk", + "pcie_clkref_en", "pcie_slv_q2a_axi_clk", + "pcie_rate_change_clk", + "gcc_ddrss_pcie_sf_qtb_clk", + "pcie_aggre_noc_axi_clk", + "gcc_cnoc_pcie_sf_axi_clk", "pcie_0_pipe_div2_clk", + "pcie_pipe_clk_mux", + "pcie_pipe_clk_ext_src"; + clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>, + <100000000>, <0>, <0>, <0>, <0>, <0>, <0>; + clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>, + <0>, <0>, <0>, <1>, <0>, <0>, <0>; + + resets = <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "pcie_0_core_reset", + "pcie_0_phy_reset"; + + dma-coherent; + qcom,smmu-sid-base = <0x1400>; + iommu-map = <0x0 &apps_smmu 0x1400 0x1>, + <0x100 &apps_smmu 0x1401 0x1>; + + qcom,boot-option = <0x1>; + qcom,aux-clk-freq = <20>; /* 19.2 MHz */ + qcom,l1-2-th-scale = <2>; + qcom,l1-2-th-value = <150>; + qcom,ep-latency = <10>; + qcom,num-parf-testbus-sel = <0xb9>; + qcom,drv-name = "lpass"; + qcom,drv-l1ss-timeout-us = <5000>; + + qcom,pcie-phy-ver = <112>; + qcom,phy-status-offset = <0x214>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x240>; + + qcom,phy-sequence = <0x0240 0x03 0x0 + 0x00c0 0x01 0x0 + 0x00cc 0x62 0x0 + 0x00d0 0x02 0x0 + 0x0060 0xf8 0x0 + 0x0064 0x01 0x0 + 0x0000 0x93 0x0 + 0x0004 0x01 0x0 + 0x00e0 0x90 0x0 + 0x00e4 0x82 0x0 + 0x00f4 0x07 0x0 + 0x0070 0x02 0x0 + 0x0010 0x02 0x0 + 0x0074 0x16 0x0 + 0x0014 0x16 0x0 + 0x0078 0x36 0x0 + 0x0018 0x36 0x0 + 0x0110 0x08 0x0 + 0x00bc 0x0a 0x0 + 0x0120 0x42 0x0 + 0x0080 0x04 0x0 + 0x0084 0x0d 0x0 + 0x0020 0x0a 0x0 + 0x0024 0x1a 0x0 + 0x0088 0x41 0x0 + 0x0028 0x34 0x0 + 0x0090 0xab 0x0 + 0x0094 0xaa 0x0 + 0x0098 0x01 0x0 + 0x0030 0x55 0x0 + 0x0034 0x55 0x0 + 0x0038 0x01 0x0 + 0x0140 0x14 0x0 + 0x0164 0x34 0x0 + 0x003c 0x01 0x0 + 0x001c 0x04 0x0 + 0x0174 0x16 0x0 + 0x01bc 0x0f 0x0 + 0x0170 0xa0 0x0 + 0x11a4 0x38 0x0 + 0x10dc 0x11 0x0 + 0x1160 0xbf 0x0 + 0x1164 0xbf 0x0 + 0x1168 0xb7 0x0 + 0x116c 0xea 0x0 + 0x115c 0x3f 0x0 + 0x1174 0x5c 0x0 + 0x1178 0x9c 0x0 + 0x117c 0x1a 0x0 + 0x1180 0x89 0x0 + 0x1170 0xdc 0x0 + 0x1188 0x94 0x0 + 0x118c 0x5b 0x0 + 0x1190 0x1a 0x0 + 0x1194 0x89 0x0 + 0x10cc 0x00 0x0 + 0x1008 0x09 0x0 + 0x1014 0x05 0x0 + 0x104c 0x08 0x0 + 0x1050 0x08 0x0 + 0x10d8 0x0f 0x0 + 0x1118 0x1c 0x0 + 0x10f8 0x07 0x0 + 0x11f8 0x08 0x0 + 0x1600 0x00 0x0 + 0x0e84 0x15 0x0 + 0x0e90 0x3f 0x0 + 0x0ee4 0x02 0x0 + 0x0e40 0x06 0x0 + 0x0e3c 0x18 0x0 + 0x19a4 0x38 0x0 + 0x18dc 0x11 0x0 + 0x1960 0xbf 0x0 + 0x1964 0xbf 0x0 + 0x1968 0xb7 0x0 + 0x196c 0xea 0x0 + 0x195c 0x3f 0x0 + 0x1974 0x5c 0x0 + 0x1978 0x9c 0x0 + 0x197c 0x1a 0x0 + 0x1980 0x89 0x0 + 0x1970 0xdc 0x0 + 0x1988 0x94 0x0 + 0x198c 0x5b 0x0 + 0x1990 0x1a 0x0 + 0x1994 0x89 0x0 + 0x18cc 0x00 0x0 + 0x1808 0x09 0x0 + 0x1814 0x05 0x0 + 0x184c 0x08 0x0 + 0x1850 0x08 0x0 + 0x18d8 0x0f 0x0 + 0x1918 0x1c 0x0 + 0x18f8 0x07 0x0 + 0x19f8 0x08 0x0 + 0x1684 0x15 0x0 + 0x1690 0x3f 0x0 + 0x16e4 0x02 0x0 + 0x1640 0x06 0x0 + 0x163c 0x18 0x0 + 0x02dc 0x05 0x0 + 0x0388 0x77 0x0 + 0x0398 0x0b 0x0 + 0x06a4 0x1e 0x0 + 0x06f4 0x27 0x0 + 0x03e0 0x0f 0x0 + 0x060c 0x1d 0x0 + 0x0614 0x07 0x0 + 0x0620 0xc1 0x0 + 0x0694 0x00 0x0 + 0x03d0 0x8c 0x0 + 0x0368 0x17 0x0 + 0x0370 0x2e 0x0 + 0x0200 0x00 0x0 + 0x0244 0x03 0x0>; + + status = "disabled"; + + pcie0_rp: pcie0_rp { + reg = <0 0 0 0 0>; + }; + }; + + pcie0_msi: qcom,pcie0_msi@17110040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x17110040 0x0>; + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + status = "disabled"; + }; +}; diff --git a/qcom/tuna-pinctrl.dtsi b/qcom/tuna-pinctrl.dtsi index 8c3ca7ff..68084ef2 100644 --- a/qcom/tuna-pinctrl.dtsi +++ b/qcom/tuna-pinctrl.dtsi @@ -1638,8 +1638,8 @@ drive-strength = <2>; }; }; - /* touchscreen pins */ + /* touchscreen pins */ pmx_ts_active { ts_active: ts_active { mux { @@ -1700,4 +1700,58 @@ }; }; + pcie0 { + pcie0_perst_default: pcie0_perst_default { + mux { + pins = "gpio33"; + function = "gpio"; + }; + + config { + pins = "gpio33"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie0_clkreq_default: pcie0_clkreq_default { + mux { + pins = "gpio118"; + function = "pcie0_clk_req_n"; + }; + + config { + pins = "gpio118"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_wake_default: pcie0_wake_default { + mux { + pins = "gpio81"; + function = "gpio"; + }; + + config { + pins = "gpio81"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_clkreq_sleep: pcie0_clkreq_sleep { + mux { + pins = "gpio118"; + function = "gpio"; + }; + + config { + pins = "gpio118"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; + }; }; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 7e4aad78..caab965e 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -36,7 +36,7 @@ }; chosen: chosen { - bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 irqaffinity=0-1 printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 ftrace_dump_on_oops"; + bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 pcie_ports=compat irqaffinity=0-1 printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 ftrace_dump_on_oops"; stdout-path = "/soc/qcom,qupv3_1_geni_se@ac0000/qcom,qup_uart@a9c000:115200n8"; }; @@ -406,6 +406,7 @@ #include "msm-arm-smmu-tuna.dtsi" #include "tuna-dma-heaps.dtsi" #include "tuna-vm-dma-heaps.dtsi" +#include "tuna-pcie.dtsi" &reserved_memory { #address-cells = <2>; @@ -525,11 +526,21 @@ compatible = "arm,gic-v3"; #interrupt-cells = <3>; interrupt-controller; + ranges; #redistributor-regions = <1>; redistributor-stride = <0x0 0x40000>; reg = <0x17100000 0x10000>, /* GICD */ <0x17180000 0x200000>; /* GICR * 8 */ interrupts = ; + + #address-cells = <1>; + #size-cells = <1>; + gic_its: msi-controller@0x17140000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x17140000 0x20000>; + }; }; qcom,hdcp {