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Revert "ARM: dts: msm: enable display cesta on sun target"

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This reverts commit 5b87ecc6bd.
Disable display cesta until reboot recovery issue is fixed.

Change-Id: Iedc5fc570f753532e5f936488d8bcc14a6889be7
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
This commit is contained in:
Veera Sundaram Sankaran
2024-04-15 11:41:36 -07:00
committed by Manoj Amara
parent 6f466e30c0
commit 60ea2afaaa
3 changed files with 19 additions and 56 deletions
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64
display/sun-sde.dtsi
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@@ -204,63 +204,26 @@
qcom,iommu-faults = "non-fatal";
qcom,iommu-vmid = <0xa>;
};
sde_cesta: qcom,sde_cesta@0x0af30000 {
cell-index = <0>;
compatible = "qcom,sde-cesta";
reg = <0xaf30000 0x60>,
<0xaf31000 0x30>,
<0xaf32000 0x30>,
<0xaf33000 0x30>,
<0xaf34000 0x30>,
<0xaf35000 0x30>,
<0xaf36000 0x30>;
reg-names = "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5";
clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>;
clock-names = "branch_clk", "core_clk";
clock-rate = <575000000 575000000>;
clock-max-rate = <575000000 575000000>;
clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC>;
interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0
&mc_virt SLAVE_EBI1_DISP_CRM_HW_0>,
<&mmss_noc MASTER_MDP_DISP_CRM_HW_1
&mc_virt SLAVE_EBI1_DISP_CRM_HW_1>,
<&mmss_noc MASTER_MDP_DISP_CRM_HW_2
&mc_virt SLAVE_EBI1_DISP_CRM_HW_2>,
<&mmss_noc MASTER_MDP_DISP_CRM_HW_3
&mc_virt SLAVE_EBI1_DISP_CRM_HW_3>,
<&mmss_noc MASTER_MDP_DISP_CRM_HW_4
&mc_virt SLAVE_EBI1_DISP_CRM_HW_4>,
<&mmss_noc MASTER_MDP_DISP_CRM_HW_5
&mc_virt SLAVE_EBI1_DISP_CRM_HW_5>,
<&mmss_noc MASTER_MDP_DISP_CRM_SW_0
&mc_virt SLAVE_EBI1_DISP_CRM_SW_0>;
interconnect-names = "qcom,sde-data-bus-hw-0", "qcom,sde-data-bus-hw-1",
"qcom,sde-data-bus-hw-2", "qcom,sde-data-bus-hw-3",
"qcom,sde-data-bus-hw-4", "qcom,sde-data-bus-hw-5",
"qcom,sde-data-bus-sw-0";
vdd-supply = <&disp_cc_mdss_core_gdsc>;
};
};
&mdss_mdp {
clocks =
<&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>;
clock-names = "gcc_bus", "iface_clk", "vsync_clk", "lut_clk";
clock-rate = <0 0 19200000 575000000>;
clock-max-rate = <0 0 19200000 575000000>;
clock-names = "gcc_bus",
"iface_clk", "branch_clk", "core_clk", "vsync_clk",
"lut_clk";
clock-rate = <0 0 575000000 575000000 19200000 575000000>;
clock-max-rate = <0 0 575000000 575000000 19200000 575000000>;
clock-mmrm = <0 0 0 DISP_CC_MDSS_MDP_CLK_SRC 0 0>;
qcom,hw-fence-sw-version = <0x1>;
vdd-supply = <&disp_cc_mdss_core_gdsc>;
mmcx-supply = <&VDD_MMCX_LEVEL>;
qti,smmu-proxy-cb-id = <QTI_SMMU_PROXY_DISPLAY_CB>;
@@ -299,6 +262,15 @@
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
qcom,platform-supply-entry@1 {
reg = <1>;
qcom,supply-name = "vdd";
qcom,supply-min-voltage = <0>;
qcom,supply-max-voltage = <0>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
};
};