From 1172faef7262fa4fa47a41124f312315ba481608 Mon Sep 17 00:00:00 2001
From: Sarannya S <quic_sarannya@quicinc.com>
Date: Wed, 29 Nov 2023 12:23:18 +0530
Subject: [PATCH] ARM: dts: msm: Add ipcc_mproc_ns1 for sun TUIVM

Add ipcc_mproc_ns1 device tree node and entries to enable IPCC and
mbox communication between TUIVM and CDSP SecurePD on sun TUIVM.

Change-Id: I1e37ee86b86ba1f6b99669c0a71476c9a9da5e75
Signed-off-by: Kishore Kumar Ravi <quic_kiskum@quicinc.com>
Signed-off-by: Sarannya S <quic_sarannya@quicinc.com>
---
 qcom/sun-vm.dtsi | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/qcom/sun-vm.dtsi b/qcom/sun-vm.dtsi
index 4aabb202..2abdd324 100644
--- a/qcom/sun-vm.dtsi
+++ b/qcom/sun-vm.dtsi
@@ -6,6 +6,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/qcom,gcc-sun.h>
 #include <dt-bindings/arm/msm/qti-smmu-proxy-dt-ids.h>
+#include <dt-bindings/soc/qcom,ipcc.h>
 
 / {
 	#address-cells = <0x2>;
@@ -104,14 +105,16 @@
 		vm-attrs = "crash-fatal", "context-dump";
 
 		iomemory-ranges = <0x0 0xa24000 0x0 0xa24000 0x0 0x4000 0x0
-				0x0 0x824000 0x0 0x824000 0x0 0x4000 0x0>;
+				0x0 0x824000 0x0 0x824000 0x0 0x4000 0x0
+				0x0 0x407000 0x0 0x407000 0x0 0x1000 0x0>;
 
 		/* For LEVM por usecases is QUP1_SE4 and QUP2_SE7.
 		 * QUP1_SE4: GPII5 : IRQ_316
 		 * QUP2_SE7: GPII5 : IRQ_625
 		 */
 		gic-irq-ranges = <316 316
-				  625 625>; /* PVM->SVM IRQ transfer */
+				  625 625 /* PVM->SVM IRQ transfer */
+				  279 279>;
 
 		memory {
 			#address-cells = <0x2>;
@@ -399,6 +402,15 @@
 		      <0x16080000 0x200000>;    /* GICR * 8 */
 	};
 
+	ipcc_mproc_ns1: qcom,ipcc@407000 {
+		compatible = "qcom,ipcc";
+		reg = <0x407000 0x1000>;
+		interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		#mbox-cells = <2>;
+	};
+
 	arch_timer: timer {
 		compatible = "arm,armv8-timer";
 		always-on;