From 4ee5875a30bf0dec1944633417c6b53b63c9a297 Mon Sep 17 00:00:00 2001 From: MingShu Pang Date: Wed, 4 Dec 2024 14:21:11 +0800 Subject: [PATCH 1/4] =?UTF-8?q?ARM:=20dts:=20msm:=20add=20wcn-bt-ext=20for?= =?UTF-8?q?=20enabling=20second=20bt=20backend=E3=80=82?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add wcn-bt-ext for enabling second bt backend. Change-Id: Ifde1e204bad2d3496297ac9184a53c3e282510aa Signed-off-by: MingShu Pang --- sun-audio-overlay.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/sun-audio-overlay.dtsi b/sun-audio-overlay.dtsi index ed513359..e6ba7752 100644 --- a/sun-audio-overlay.dtsi +++ b/sun-audio-overlay.dtsi @@ -439,6 +439,7 @@ qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>, <1>, <1>; qcom,mi2s-tdm-is-hw-vote-needed = <1>, <1>, <1>, <1>, <1>, <1>, <1>; qcom,wcn-bt = <1>; + qcom,wcn-bt-ext = <1>; qcom,ext-disp-audio-rx = <1>; qcom,tdm-max-slots = <8>; qcom,tdm-clk-attribute = <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>; From d2fe78d4a6d17852c12b56bf1cfeb5b82c10d69a Mon Sep 17 00:00:00 2001 From: Ravulapati Vishnu Vardhan Rao Date: Tue, 11 Feb 2025 13:15:19 +0530 Subject: [PATCH 2/4] ARM: dts: msm: Add record audio routes Add record in audio-routes for tuna7 where it is missing for record over AATC. With this can record using AATC. Change-Id: I9a76e16d5dc8168a11411ce715559350e6cc0c1f Signed-off-by: Ravulapati Vishnu Vardhan Rao --- tuna7-audio-mtp.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tuna7-audio-mtp.dtsi b/tuna7-audio-mtp.dtsi index 90adbb5c..6def512f 100644 --- a/tuna7-audio-mtp.dtsi +++ b/tuna7-audio-mtp.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "tuna-audio-mtp.dtsi" @@ -91,6 +91,8 @@ "RX_TX DEC3_INP", "TX DEC3 MUX", "SpkrLeft IN", "WSA_SPK1 OUT", "SpkrRight IN", "WSA_SPK2 OUT", + "TX SWR_INPUT", "WCD_TX_OUTPUT", + "VA SWR_INPUT", "WCD_TX_OUTPUT", "VA SWR_INPUT", "VA_SWR_CLK", "VA_AIF1 CAP", "VA_SWR_CLK", "VA_AIF2 CAP", "VA_SWR_CLK", From 54e16fa76df4b133469483bebbff0692adce98da Mon Sep 17 00:00:00 2001 From: Ravulapati Vishnu Vardhan Rao Date: Thu, 13 Feb 2025 12:56:41 +0530 Subject: [PATCH 3/4] ARM: dts: msm: Add support KERA + RCM + ORNE Add support for RCM KERA device with Orne. Change-Id: I1b1878fee4d5f662dc011fe76bdba3f6950d42f7 Signed-off-by: Ravulapati Vishnu Vardhan Rao --- Kbuild | 3 ++- kera-audio-rcm-orne.dts | 17 +++++++++++++++++ kera-audio-rcm-orne.dtsi | 13 +++++++++++++ 3 files changed, 32 insertions(+), 1 deletion(-) create mode 100644 kera-audio-rcm-orne.dts create mode 100644 kera-audio-rcm-orne.dtsi diff --git a/Kbuild b/Kbuild index 063f5400..2995f6c5 100644 --- a/Kbuild +++ b/Kbuild @@ -53,7 +53,8 @@ dtbo-y += kera-audio.dtbo \ kera-audio-mtp.dtbo \ kera-audio-mtp-qmp1000.dtbo \ kera-audio-qrd.dtbo \ - kera-audio-rcm.dtbo + kera-audio-rcm.dtbo \ + kera-audio-rcm-orne.dtbo endif diff --git a/kera-audio-rcm-orne.dts b/kera-audio-rcm-orne.dts new file mode 100644 index 00000000..5ea555a6 --- /dev/null +++ b/kera-audio-rcm-orne.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-audio-rcm-orne.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Kuna RCM+ORNE"; + compatible = "qcom,kera-rcm", "qcom,kera", "qcom,kerap-rcm", "qcom,kerap", + "qcom,rcm"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x10015 0>, <0x20015 0>, <0x30015 0>, <0x30015 1>, + <0x10015 1>, <0x20015 1>; +}; diff --git a/kera-audio-rcm-orne.dtsi b/kera-audio-rcm-orne.dtsi new file mode 100644 index 00000000..62b7ef32 --- /dev/null +++ b/kera-audio-rcm-orne.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-audio-cdp.dtsi" + +&lpass_bt_swr { + status = "okay"; +}; From 78c03916feb50972214efd6f628e90169e230a58 Mon Sep 17 00:00:00 2001 From: Ravulapati Vishnu Vardhan Rao Date: Tue, 25 Feb 2025 19:50:24 +0530 Subject: [PATCH 4/4] ARM: dts: msm: update clk div factor entry for TX and VA macros Update clk div factor entries for TX and VA macros to reflect proper HW configuration. Change-Id: Ic5456d7e30245a484b6a4888835c7e6f838eb92b Signed-off-by: Ravulapati Vishnu Vardhan Rao --- kera-audio-overlay.dtsi | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/kera-audio-overlay.dtsi b/kera-audio-overlay.dtsi index ceea5f64..a3f4786c 100644 --- a/kera-audio-overlay.dtsi +++ b/kera-audio-overlay.dtsi @@ -32,8 +32,20 @@ compatible = "qcom,lpass-cdc-va-macro"; clock-names = "lpass_audio_hw_vote"; clocks = <&lpass_audio_hw_vote 0>; - qcom,va-dmic-sample-rate = <600000>; qcom,va-clk-mux-select = <1>; + /* + * Clk divding factors for each DMIC pair. + * Valid entries for each DMIC pair: + * 2, 3, 4, 6, 8, 16 + * + * These factors are translated to corresponding config values + * for the following registers, + * -- LPASS_VA_TOP_CSR_DMIC0_CTL, + * -- LPASS_VA_TOP_CSR_DMIC1_CTL, + * -- LPASS_VA_TOP_CSR_DMIC2_CTL, + * -- LPASS_VA_TOP_CSR_DMIC3_CTL, + */ + qcom,va-dmic-clk-div-factor = <16 16 16 16>; qcom,default-clk-id = ; qcom,use-clk-id = ; qcom,is-used-swr-gpio = <1>; @@ -82,7 +94,19 @@ tx_macro: tx-macro@6AE0000 { compatible = "qcom,lpass-cdc-tx-macro"; qcom,default-clk-id = ; - qcom,tx-dmic-sample-rate = <2400000>; + /* + * Clk divding factors for each DMIC pair. + * Valid entries for each DMIC pair: + * 2, 3, 4, 6, 8, 16 + * + * These factors are translated to corresponding config values + * for the following registers, + * -- LPASS_VA_TOP_CSR_DMIC0_CTL, + * -- LPASS_VA_TOP_CSR_DMIC1_CTL, + * -- LPASS_VA_TOP_CSR_DMIC2_CTL, + * -- LPASS_VA_TOP_CSR_DMIC3_CTL, + */ + qcom,tx-dmic-clk-div-factor = <4 4 4 4>; qcom,is-used-swr-gpio = <0>; };