From 5f39e6b14137229a98c74a14b91137c98e939a69 Mon Sep 17 00:00:00 2001 From: Sai Harshini Nimmala Date: Tue, 12 Sep 2023 13:24:05 -0700 Subject: [PATCH] ARM: dts: msm: sun: Add capacity related information The "capacity-dmips-mhz" and "dynamic-power-coefficient" are used to build Energy Model and subsequently capacity values are derived from them which in turn is used by EAS to take placement decisions. Add these to sun devicetree. Change-Id: If96b00b5ba1e211867ba9b44c5af5f2c9e65200f Signed-off-by: Sai Harshini Nimmala --- qcom/sun.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index c3e1026b..b19775ab 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -60,6 +60,8 @@ power-domains = <&CPU_PD0>; power-domain-names = "psci"; #cooling-cells = <2>; + capacity-dmips-mhz = <1792>; + dynamic-power-coefficient = <238>; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "arm,arch-cache"; @@ -76,6 +78,8 @@ power-domains = <&CPU_PD1>; power-domain-names = "psci"; #cooling-cells = <2>; + capacity-dmips-mhz = <1792>; + dynamic-power-coefficient = <238>; next-level-cache = <&L2_0>; }; @@ -88,6 +92,8 @@ power-domains = <&CPU_PD2>; power-domain-names = "psci"; #cooling-cells = <2>; + capacity-dmips-mhz = <1792>; + dynamic-power-coefficient = <238>; next-level-cache = <&L2_0>; }; @@ -100,6 +106,8 @@ power-domains = <&CPU_PD3>; power-domain-names = "psci"; #cooling-cells = <2>; + capacity-dmips-mhz = <1792>; + dynamic-power-coefficient = <238>; next-level-cache = <&L2_0>; }; @@ -112,6 +120,8 @@ power-domains = <&CPU_PD4>; power-domain-names = "psci"; #cooling-cells = <2>; + capacity-dmips-mhz = <1792>; + dynamic-power-coefficient = <238>; next-level-cache = <&L2_0>; }; @@ -124,6 +134,8 @@ power-domains = <&CPU_PD5>; power-domain-names = "psci"; #cooling-cells = <2>; + capacity-dmips-mhz = <1792>; + dynamic-power-coefficient = <238>; next-level-cache = <&L2_0>; }; @@ -136,6 +148,8 @@ power-domains = <&CPU_PD6>; power-domain-names = "psci"; #cooling-cells = <2>; + capacity-dmips-mhz = <1894>; + dynamic-power-coefficient = <588>; next-level-cache = <&L2_6>; L2_6: l2-cache { compatible = "arm,arch-cache"; @@ -152,6 +166,8 @@ power-domains = <&CPU_PD7>; power-domain-names = "psci"; #cooling-cells = <2>; + capacity-dmips-mhz = <1894>; + dynamic-power-coefficient = <588>; next-level-cache = <&L2_6>; };