From e72923880954e59ab4c732a253e334d0fca63b1e Mon Sep 17 00:00:00 2001
From: Prem Sai Grandhi <quic_grandhir@quicinc.com>
Date: Tue, 15 Oct 2024 17:38:32 +0530
Subject: [PATCH] ARM: dts: msm: Add llcc perfmon node for tuna SOC

Add llcc perfmon entry, qdss clock node to
llcc perfmon driver and aoss_qmp headers.

Change-Id: I8f3b823f754bcf505c8441820cddfa03b5782305
Signed-off-by: Prem Sai Grandhi <quic_grandhir@quicinc.com>
---
 qcom/tuna.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi
index 217a3488..9bae067a 100644
--- a/qcom/tuna.dtsi
+++ b/qcom/tuna.dtsi
@@ -20,6 +20,8 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/spmi/spmi.h>
 #include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+#include <dt-bindings/power/qcom-aoss-qmp.h>
+#include <dt-bindings/clock/qcom,aop-qmp.h>
 
 / {
 	model = "Qualcomm Technologies, Inc. Tuna";
@@ -648,6 +650,12 @@
 
 		interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
 		cap-based-alloc-and-pwr-collapse;
+
+		llcc_perfmon {
+			compatible = "qcom,llcc-perfmon";
+			clocks = <&aoss_qmp QDSS_CLK>;
+			clock-names = "qdss_clk";
+		};
 	};
 
 	gic-interrupt-router {