Merge "ARM: dts: qcom: add ufs support for Sun"
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qctecmdr
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Gerrit - the friendly Code Review server
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5d6cb31087
@@ -49,3 +49,53 @@
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maximum-speed = "high-speed";
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};
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};
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&ufsphy_mem {
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compatible = "qcom,ufs-phy-qrbtc-sdm845";
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/* VDDA_UFS_CORE */
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vdda-phy-supply = <&pm_v6j_l1>;
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vdda-phy-max-microamp = <211000>;
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/* VDDA_UFS_0_1P2 */
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vdda-pll-supply = <&pm_v8g_l3>;
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vdda-pll-max-microamp = <18300>;
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/* Phy GDSC for VDD_MX, always on */
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vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>;
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/* Qref power supply, Refer Qref diagram */
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vdda-qref-supply = <&pm_v8i_l3>;
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vdda-qref-max-microamp = <64500>;
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status = "ok";
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};
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&ufshc_mem {
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limit-tx-hs-gear = <1>;
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limit-rx-hs-gear = <1>;
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limit-rate = <2>; /* HS Rate-B */
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rpm-level = <0>;
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spm-level = <0>;
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vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
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vcc-supply = <&pm_humu_l17>;
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vcc-max-microamp = <1300000>;
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vccq-supply = <&pm_v8d_l1>;
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vccq-max-microamp = <750000>;
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qcom,vddp-ref-clk-supply = <&pm_v8i_l2>;
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qcom,vddp-ref-clk-max-microamp = <100>;
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qcom,vccq-parent-supply = <&pm_v8i_s7>;
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qcom,vccq-parent-max-microamp = <210000>;
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vdda-qref-supply = <&pm_v8i_l3>;
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vdda-qref-max-microamp = <30000>;
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qcom,disable-lpm;
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status = "ok";
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};
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174
qcom/sun.dtsi
174
qcom/sun.dtsi
@@ -33,6 +33,7 @@
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aliases {
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serial0 = &qupv3_se7_2uart;
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ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
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};
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firmware: firmware { };
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@@ -734,6 +735,179 @@
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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ufsphy_mem: ufsphy_mem@1d80000 {
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reg = <0x1d80000 0x2000>;
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reg-names = "phy_mem";
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#phy-cells = <0>;
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lanes-per-direction = <2>;
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clock-names = "ref_clk_src",
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"ref_aux_clk", "qref_clk",
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"rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk",
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"rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk";
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clocks = <&rpmhcc RPMH_CXO_PAD_CLK>,
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<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
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<&tcsrcc TCSR_UFS_CLKREF_EN>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>,
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<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
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<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>;
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resets = <&ufshc_mem 0>;
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status = "disabled";
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};
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ice_cfg: shared_ice {
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alg1 {
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alg-name = "alg1";
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rx-alloc-percent = <60>;
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status = "disabled";
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};
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alg2 {
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alg-name = "alg2";
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status = "disabled";
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};
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alg3 {
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alg-name = "alg3";
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num-core = <28 28 15 13>;
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status = "ok";
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};
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};
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ufshc_mem: ufshc@1d84000 {
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compatible = "qcom,ufshc";
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reg = <0x1d84000 0x3000>,
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<0x1d88000 0x8000>,
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<0x1d90000 0x9800>;
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reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm";
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interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&ufsphy_mem>;
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phy-names = "ufsphy";
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#reset-cells = <1>;
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lanes-per-direction = <2>;
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dev-ref-clk-freq = <0>; /* 19.2 MHz */
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clock-names =
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"core_clk",
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"bus_aggr_clk",
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"iface_clk",
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"core_clk_unipro",
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"core_clk_ice",
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"ref_clk",
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"tx_lane0_sync_clk",
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"rx_lane0_sync_clk",
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"rx_lane1_sync_clk";
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clocks =
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<&gcc GCC_UFS_PHY_AXI_CLK>,
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<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
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<&gcc GCC_UFS_PHY_AHB_CLK>,
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<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
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<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
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<&rpmhcc RPMH_LN_BB_CLK3>,
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<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
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freq-table-hz =
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<100000000 403000000>,
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<0 0>,
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<0 0>,
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<100000000 403000000>,
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<100000000 403000000>,
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<0 0>,
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<0 0>,
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<0 0>,
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<0 0>;
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interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
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interconnect-names = "ufs-ddr", "cpu-ufs";
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qcom,ufs-bus-bw,name = "ufshc_mem";
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qcom,ufs-bus-bw,num-cases = <30>;
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qcom,ufs-bus-bw,num-paths = <2>;
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qcom,ufs-bus-bw,vectors-KBps =
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/*
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* During HS G3 UFS runs at nominal voltage corner, vote
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* higher bandwidth to push other buses in the data path
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* to run at nominal to achieve max throughput.
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* 4GBps pushes BIMC to run at nominal.
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* 200MBps pushes CNOC to run at nominal.
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* Vote for half of this bandwidth for HS G3 1-lane.
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* For max bandwidth, vote high enough to push the buses
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* to run in turbo voltage corner.
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*/
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<0 0>, <0 0>, /* No vote */
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<922 0>, <1000 0>, /* PWM G1 */
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<1844 0>, <1000 0>, /* PWM G2 */
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<3688 0>, <1000 0>, /* PWM G3 */
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<7376 0>, <1000 0>, /* PWM G4 */
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<14752 0>, <1000 0>, /* PWM G5 */
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<1844 0>, <1000 0>, /* PWM G1 L2 */
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<3688 0>, <1000 0>, /* PWM G2 L2 */
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<7376 0>, <1000 0>, /* PWM G3 L2 */
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<14752 0>, <1000 0>, /* PWM G4 L2 */
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<29504 0>, <1000 0>, /* PWM G5 L2 */
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<127796 0>, <1000 0>, /* HS G1 RA */
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<255591 0>, <1000 0>, /* HS G2 RA */
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<1492582 0>, <102400 0>, /* HS G3 RA */
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<2915200 0>, <204800 0>, /* HS G4 RA */
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<255591 0>, <1000 0>, /* HS G1 RA L2 */
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<511181 0>, <1000 0>, /* HS G2 RA L2 */
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<1492582 0>, <204800 0>, /* HS G3 RA L2 */
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<2915200 0>, <409600 0>, /* HS G4 RA L2 */
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<149422 0>, <1000 0>, /* HS G1 RB */
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<298189 0>, <1000 0>, /* HS G2 RB */
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<1492582 0>, <102400 0>, /* HS G3 RB */
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<2915200 0>, <204800 0>, /* HS G4 RB */
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<298189 0>, <1000 0>, /* HS G1 RB L2 */
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<596378 0>, <1000 0>, /* HS G2 RB L2 */
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/* As UFS working in HS G3 RB L2 mode, aggregated
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* bandwidth (AB) should take care of providing
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* optimum throughput requested. However, as tested,
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* in order to scale up CNOC clock, instantaneous
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* bindwidth (IB) needs to be given a proper value too.
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*/
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<1492582 0>, <204800 409600>, /* HS G3 RB L2 KBPs */
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<2915200 0>, <409600 409600>, /* HS G4 RB L2 */
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<5836800 0>, <819200 0>, /* HS G5 RA L2*/
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<5836800 0>, <819200 0>, /* HS G5 RB L2 */
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<7643136 0>, <819200 0>; /* Max. bandwidth */
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qcom,bus-vector-names = "MIN",
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"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", "PWM_G5_L1",
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"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", "PWM_G5_L2",
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"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
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"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
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"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
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"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
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"HS_RA_G5_L2", "HS_RB_G5_L2",
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"MAX";
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iommus = <&apps_smmu 0x60 0x0>;
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shared-ice-cfg = <&ice_cfg>;
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qcom,bypass-pbl-rst-wa;
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status = "disabled";
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qos0 {
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mask = <0xfc>;
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vote = <44>;
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perf;
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cpu_freq_vote = <2 5 7>;
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};
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qos1 {
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mask = <0x03>;
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vote = <44>;
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cpu_freq_vote = <0>;
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};
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};
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};
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&reserved_memory {
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