samsung_sm8750/android_kernel_samsung_sm8750-devicetrees
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

ARM: dts: msm: Add upstream compatible iommu-addresses property

Browse Source 
Upstream Linux kernel has added a new devicetree property
"iommu-addresses", to replace "qcom,iommu-dma-addr-pool".
The new property defines the address range the device
cannot use, in contrast to the older property which
defines the address range the device can use.

Change-Id: I8fc13e27593193af7be5ca1bcc03c04a25f36c91
CRs-Fixed: 3724373
This commit is contained in:
Namita Nair
2024-01-17 22:24:23 -08:00
parent ebd9ddee76
commit 5d47bd95de
4 changed files with 28 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
sun-kiwi-cnss-v8.dtsi
View File

@@ -145,20 +145,23 @@
};
&pcie0_rp {
#address-cells = <5>;
#size-cells = <0>;
cnss_pci0: cnss_pci0 {
reg = <0 0 0 0 0>;
qcom,iommu-group = <&cnss_pci_iommu_group0>;
memory-region = <&cnss_wlan_mem>;
memory-region = <&cnss_wlan_mem &cnss_pci0_iommu_region_partition>;
#address-cells = <1>;
#size-cells = <1>;
cnss_pci0_iommu_region_partition: cnss_pci0_iommu_region_partition {
/* address-cells =3 size-cells=2 from sun-pcie.dtsi */
iommu-addresses = <&cnss_pci0 0x0 0x0 0x0 0x0 0xa0000000>,
<&cnss_pci0 0x0 0x0 0xB0000000 0x0 0x50000000>;
};
cnss_pci_iommu_group0: cnss_pci_iommu_group0 {
qcom,iommu-msi-size = <0x1000>;
qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
qcom,iommu-geometry = <0xa0000000 0x10010000>;
qcom,iommu-dma = "fastmap";
qcom,iommu-pagetable = "coherent";

11
sun-kiwi-cnss.dtsi
View File

@@ -147,20 +147,23 @@
};
&pcie0_rp {
#address-cells = <5>;
#size-cells = <0>;
cnss_pci0: cnss_pci0 {
reg = <0 0 0 0 0>;
qcom,iommu-group = <&cnss_pci_iommu_group0>;
memory-region = <&cnss_wlan_mem>;
memory-region = <&cnss_wlan_mem &cnss_pci0_iommu_region_partition>;
#address-cells = <1>;
#size-cells = <1>;
cnss_pci0_iommu_region_partition: cnss_pci0_iommu_region_partition {
/* address-cells =3 size-cells=2 from sun-pcie.dtsi */
iommu-addresses = <&cnss_pci0 0x0 0x0 0x0 0x0 0xa0000000>,
<&cnss_pci0 0x0 0x0 0xB0000000 0x0 0x50000000>;
};
cnss_pci_iommu_group0: cnss_pci_iommu_group0 {
qcom,iommu-msi-size = <0x1000>;
qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
qcom,iommu-geometry = <0xa0000000 0x10010000>;
qcom,iommu-dma = "fastmap";
qcom,iommu-pagetable = "coherent";

11
sun-peach-cnss-v8.dtsi
View File

@@ -146,20 +146,23 @@
};
&pcie0_rp {
#address-cells = <5>;
#size-cells = <0>;
cnss_pci0: cnss_pci0 {
reg = <0 0 0 0 0>;
qcom,iommu-group = <&cnss_pci_iommu_group0>;
memory-region = <&cnss_wlan_mem>;
memory-region = <&cnss_wlan_mem &cnss_pci0_iommu_region_partition>;
#address-cells = <1>;
#size-cells = <1>;
cnss_pci0_iommu_region_partition: cnss_pci0_iommu_region_partition {
/* address-cells =3 size-cells=2 from sun-pcie.dtsi */
iommu-addresses = <&cnss_pci0 0x0 0x0 0x0 0x0 0xa0000000>,
<&cnss_pci0 0x0 0x0 0xB0000000 0x0 0x50000000>;
};
cnss_pci_iommu_group0: cnss_pci_iommu_group0 {
qcom,iommu-msi-size = <0x1000>;
qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
qcom,iommu-geometry = <0xa0000000 0x10010000>;
qcom,iommu-dma = "fastmap";
qcom,iommu-pagetable = "coherent";

11
sun-peach-cnss.dtsi
View File

@@ -139,20 +139,23 @@
};
&pcie0_rp {
#address-cells = <5>;
#size-cells = <0>;
cnss_pci0: cnss_pci0 {
reg = <0 0 0 0 0>;
qcom,iommu-group = <&cnss_pci_iommu_group0>;
memory-region = <&cnss_wlan_mem>;
memory-region = <&cnss_wlan_mem &cnss_pci0_iommu_region_partition>;
#address-cells = <1>;
#size-cells = <1>;
cnss_pci0_iommu_region_partition: cnss_pci0_iommu_region_partition {
/* address-cells =3 size-cells=2 from sun-pcie.dtsi */
iommu-addresses = <&cnss_pci0 0x0 0x0 0x0 0x0 0xa0000000>,
<&cnss_pci0 0x0 0x0 0xB0000000 0x0 0x50000000>;
};
cnss_pci_iommu_group0: cnss_pci_iommu_group0 {
qcom,iommu-msi-size = <0x1000>;
qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
qcom,iommu-geometry = <0xa0000000 0x10010000>;
qcom,iommu-dma = "fastmap";
qcom,iommu-pagetable = "coherent";