diff --git a/Kbuild b/Kbuild index d4bcf0dc..a1ea245a 100644 --- a/Kbuild +++ b/Kbuild @@ -4,6 +4,7 @@ dtbo-y += nxp/sun-nfc.dtbo \ nxp/sun-nfc-mtp.dtbo \ nxp/sun-nfc-qrd.dtbo \ nxp/tuna-nfc.dtbo \ + nxp/kera-nfc.dtbo \ dtbo-y += st/sun-nfc.dtbo \ st/sun-nfc-mtp.dtbo \ @@ -14,7 +15,8 @@ dtbo-y += st/sun-nfc.dtbo \ st/sun-nfc-atp.dtbo \ st/sun-mtp-kiwi-v8.dtbo \ st/sun-nfc-rcm.dtbo \ - st/tuna-nfc.dtbo + st/tuna-nfc.dtbo \ + st/kera-nfc.dtbo endif ifeq ($(CONFIG_ARCH_PARROT),y) diff --git a/nxp/kera-nfc-common.dtsi b/nxp/kera-nfc-common.dtsi new file mode 100644 index 00000000..c15f739d --- /dev/null +++ b/nxp/kera-nfc-common.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-nfc-pinctrl.dtsi" +&qupv3_se9_i2c { + status = "ok"; + qcom,clk-freq-out = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + nq@28 { + compatible = "qcom,sn-nci"; + reg = <0x28>; + qcom,sn-irq = <&tlmm 7 0x00>; + qcom,sn-ven = <&tlmm 57 0x00>; + qcom,sn-clkreq = <&tlmm 6 0x00>; + qcom,sn-szone = "enable"; + interrupt-parent = <&tlmm>; + interrupts = <7 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + }; +}; + diff --git a/nxp/kera-nfc-pinctrl.dtsi b/nxp/kera-nfc-pinctrl.dtsi new file mode 100644 index 00000000..f0ac326d --- /dev/null +++ b/nxp/kera-nfc-pinctrl.dtsi @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&tlmm { + nfc { + nfc_int_active: nfc_int_active { + /* active state */ + mux { + /* NFC Read Interrupt */ + pins = "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio7"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; + }; + }; + + nfc_int_suspend: nfc_int_suspend { + /* sleep state */ + mux { + /* NFC Read Interrupt */ + pins = "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio7"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; + }; + }; + + nfc_enable_active: nfc_enable_active { + mux { + /* Enable, and Clock request gpios */ + pins = "gpio57", "gpio6"; + function = "gpio"; + }; + + config { + pins = "gpio57", "gpio6"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + + nfc_enable_suspend: nfc_enable_suspend { + mux { + pins = "gpio57", "gpio6"; + function = "gpio"; + }; + + config { + pins = "gpio57", "gpio6"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; //nfc +}; //tlmm + diff --git a/nxp/kera-nfc.dts b/nxp/kera-nfc.dts new file mode 100644 index 00000000..d7bc1aa7 --- /dev/null +++ b/nxp/kera-nfc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-nfc-common.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Kera SoC"; + compatible = "qcom,kera"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x10008 0>, <33 0>, <0x10001 0>, <0x1000B 0>, <0x10015 0>; +}; diff --git a/st/kera-nfc-common.dtsi b/st/kera-nfc-common.dtsi new file mode 100644 index 00000000..abca9415 --- /dev/null +++ b/st/kera-nfc-common.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-nfc-pinctrl.dtsi" + +&qupv3_se9_i2c { + status = "ok"; + qcom,clk-freq-out = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + st21nfc: st21nfc@08 { + compatible = "st,st21nfc"; + reg = <0x08>; + irq-gpios = <&tlmm 7 0x00>; + reset-gpios = <&tlmm 57 0x00>; + clkreq-gpios = <&tlmm 6 0x00>; + interrupt-parent = <&tlmm>; + interrupts = <7 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + }; +}; diff --git a/st/kera-nfc-pinctrl.dtsi b/st/kera-nfc-pinctrl.dtsi new file mode 100644 index 00000000..7e4a17ad --- /dev/null +++ b/st/kera-nfc-pinctrl.dtsi @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&tlmm { + nfc { + nfc_int_active: nfc_int_active { + /* active state */ + mux { + /* NFC Read Interrupt */ + pins = "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio7"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; + }; + }; + + nfc_int_suspend: nfc_int_suspend { + /* sleep state */ + mux { + /* NFC Read Interrupt */ + pins = "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio7"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; + }; + }; + + nfc_enable_active: nfc_enable_active { + mux { + /* Enable, and Clock request gpios */ + pins = "gpio57", "gpio6"; + function = "gpio"; + }; + + config { + pins = "gpio57", "gpio6"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + + nfc_enable_suspend: nfc_enable_suspend { + mux { + pins = "gpio57", "gpio6"; + function = "gpio"; + }; + + config { + pins = "gpio57", "gpio6"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; //nfc +}; //tlmm diff --git a/st/kera-nfc.dts b/st/kera-nfc.dts new file mode 100644 index 00000000..4a68a621 --- /dev/null +++ b/st/kera-nfc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-nfc-common.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Kera SoC"; + compatible = "qcom,kera"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x30008 0>, <0x30008 1>; +};