Add 'qcom/data/' from LA.VENDOR.15.4.0.r1-17000-pakala.0 of https://git.codelinaro.org/clo/la/platform/vendor/qcom-opensource/data-devicetree
git-subtree-dir: qcom/data git-subtree-mainline:3c51dd18f2git-subtree-split:cd0a03556c
This commit is contained in:
kmiit
50
qcom/data/Kbuild
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50
qcom/data/Kbuild
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@@ -0,0 +1,50 @@
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ifeq ($(CONFIG_ARCH_SUN),y)
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dtbo-y += sun-ipa.dtbo
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dtbo-y += smem-mailbox.dtbo
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endif
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ifeq ($(CONFIG_ARCH_KALAMA),y)
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dtbo-y += kalama-ipa.dtbo
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endif
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ifeq ($(CONFIG_ARCH_PINEAPPLE),y)
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dtbo-y += pineapple-ipa.dtbo
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endif
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ifeq ($(CONFIG_ARCH_BLAIR),y)
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dtbo-y += blair-ipa.dtbo
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endif
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ifeq ($(CONFIG_ARCH_HOLI),y)
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dtbo-y += holi-ipa.dtbo
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endif
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ifeq ($(CONFIG_ARCH_CLIFFS),y)
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dtbo-y += cliffs-ipa.dtbo
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endif
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ifeq ($(CONFIG_ARCH_PARROT),y)
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dtbo-y += parrot-ipa.dtbo
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endif
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ifeq ($(CONFIG_ARCH_MONACO),y)
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dtbo-y += monaco-ipa.dtbo
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endif
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ifeq ($(CONFIG_ARCH_RAVELIN),y)
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dtbo-y += ravelin-ipa.dtbo
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endif
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ifeq ($(CONFIG_ARCH_TUNA),y)
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dtbo-y += tuna-ipa.dtbo
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dtbo-y += tuna-smem-mailbox.dtbo
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endif
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ifeq ($(CONFIG_ARCH_KERA),y)
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dtbo-y += kera-ipa.dtbo
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dtbo-y += kera-smem-mailbox.dtbo
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endif
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always-y := $(dtb-y) $(dtbo-y)
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subdir-y := $(dts-dirs)
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clean-files := *.dtb *.dtbo
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9
qcom/data/Makefile
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9
qcom/data/Makefile
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@@ -0,0 +1,9 @@
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KBUILD_OPTIONS+=KBUILD_EXTMOD_DTS=.
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all: dtbs
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clean:
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$(MAKE) -C $(KERNEL_SRC) M=$(M) clean
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%:
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$(MAKE) -C $(KERNEL_SRC) M=$(M) $@ $(KBUILD_OPTIONS)
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296
qcom/data/bindings/ipa.txt
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296
qcom/data/bindings/ipa.txt
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@@ -0,0 +1,296 @@
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Qualcomm technologies inc. Internet Packet Accelerator
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Internet Packet Accelerator (IPA) is a programmable protocol
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processor HW block. It is designed to support generic HW processing
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of UL/DL IP packets for various use cases independent of radio technology.
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Required properties:
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IPA node:
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- compatible : "qcom,ipa"
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- reg: Specifies the base physical addresses and the sizes of the IPA
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registers.
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- reg-names: "ipa-base" - string to identify the IPA CORE base registers.
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"bam-base" - string to identify the IPA BAM base registers.
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"a2-bam-base" - string to identify the A2 BAM base registers.
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- pas-ids: specify the image ids of the FW images that needs to be loaded.
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- firmware-names:- String name of the FW images that need to be loaded.
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- memory-regions:- Carved memory regions of the FW images.
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- interrupts: Specifies the interrupt associated with IPA.
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- interrupt-names: "ipa-irq" - string to identify the IPA core interrupt.
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"bam-irq" - string to identify the IPA BAM interrupt.
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"a2-bam-irq" - string to identify the A2 BAM interrupt.
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"msi-irq-rmnet-ctl" - string to identify QMAP MSI interrupt
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"msi-irq-rmnet-ll" - string to identify LL MSI interrupt
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- qcom,ipa-hw-ver: Specifies the IPA hardware version.
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- qcom,ipa-ram-mmap: An array of unsigned integers representing addresses and
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sizes which are used by the driver to access IPA RAM.
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Optional:
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- qcom,tx-poll: Enable performing TX completions in polling mode.
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- qcom,tx-wrapper-cache-max-size: Define the tx warpper cache pool max size,
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if set to zero then the feature is disabled.
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- qcom,tx-napi: Enable usage of NAPI in the TX data path.
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- qcom,lan-rx-napi: Enable NAPI in the LAN RX data path.
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- qcom,ipa-uc-holb-monitor: Enable uC HOLB monitor feature.
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- qcom,ipa-holb-monitor-poll-period: Poll period for HOLB monitor feature.
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- qcom,holb-monitor-max-cnt-wlan: Max stuck count for HOLB on WLAN channel.
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- qcom,holb-monitor-max-cnt-usb: Max stuck count for HOLB on USB channel.
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- qcom,holb-monitor-max-cnt-11ad: Max stuck count for HOLB on 11AD channel.
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- qcom,wan-rx-ring-size: size of WAN rx ring, default is 192
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- qcom,lan-rx-ring-size: size of LAN rx ring, default is 192
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- qcom,arm-smmu: SMMU is present and ARM SMMU driver is used
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- qcom,msm-smmu: SMMU is present and QSMMU driver is used
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- qcom,smmu-fast-map: Boolean context flag to set SMMU to fastpath mode
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- ipa_smmu_ap: AP general purpose SMMU device
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compatible "qcom,ipa-smmu-ap-cb"
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- ipa_smmu_wlan: WDI SMMU device
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compatible "qcom,ipa-smmu-wlan-cb"
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- ipa_smmu_uc: uc SMMU device
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compatible "qcom,ipa-smmu-uc-cb"
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- ipa_smmu_11ad: 11AD SMMU device
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compatible "qcom,ipa-smmu-11ad-cb"
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- qcom,use-a2-service: determine if A2 service will be used
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- qcom,use-ipa-tethering-bridge: determine if tethering bridge will be used
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- qcom,use-ipa-in-mhi-mode: Boolean context flag to indicate whether
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device booting in MHI config or not.
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- qcom,use-ipa-bamdma-a2-bridge: determine if a2/ipa hw bridge will be used
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- qcom,ee: which EE is assigned to (non-secure) APPS from IPA-BAM POV. This
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|
is a number
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- qcom,ipa-hw-mode: IPA hardware mode - Normal, Virtual memory allocation,
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memory allocation over a PCIe bridge
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-qcom,platform-type: MDM platform, MSM platform or APQ platform
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- qcom,msm-bus,name: String representing the client-name
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- qcom,msm-bus,num-cases: Total number of usecases
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- qcom,msm-bus,active-only: Boolean context flag for requests in active or
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dual (active & sleep) contex
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- qcom,msm-bus,num-paths: Total number of master-slave pairs
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- qcom,msm-bus,vectors-KBps: Arrays of unsigned integers representing:
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master-id, slave-id, arbitrated bandwidth
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in KBps, instantaneous bandwidth in KBps
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- qcom,ipa-bam-remote-mode: Boolean context flag to determine if ipa bam
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is in remote mode.
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- qcom,modem-cfg-emb-pipe-flt: Boolean context flag to determine if modem
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configures embedded pipe filtering rules
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- qcom,skip-uc-pipe-reset: Boolean context flag to indicate whether
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a pipe reset via the IPA uC is required
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- qcom,ipa-wdi2: Boolean context flag to indicate whether
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|
using wdi-2.0 or not
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- qcom,ipa-wdi3-over-gsi: Boolean context flag to indicate whether
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using wdi-3.0 or not
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- qcom,bandwidth-vote-for-ipa: Boolean context flag to indicate whether
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ipa clock voting is done by bandwidth
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voting via msm-bus-scale driver or not
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- qcom,use-64-bit-dma-mask: Boolean context flag to indicate whether
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using 64bit dma mask or not
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- qcom,use-dma-zone: Boolean context flag to indicate whether memory
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allocations controlled by IPA driver that do not
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specify a struct device * should use GFP_DMA to
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workaround IPA HW limitations
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- qcom,use-rg10-limitation-mitigation: Boolean context flag to activate
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the mitigation to register group 10
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AP access limitation
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- qcom,do-not-use-ch-gsi-20: Boolean context flag to activate
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software workaround for IPA limitation
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to not use GSI physical channel 20
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- qcom,tethered-flow-control: Boolean context flag to indicate whether
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|
apps based flow control is needed for tethered
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|
call.
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- qcom,rx-polling-sleep-ms: Receive Polling Timeout in millisecond,
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default is 1 millisecond.
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- qcom,ipa-polling-iteration: IPA Polling Iteration Count,default is 40.
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- qcom,mhi-event-ring-id-limits: Two elements property. Start and End limits
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for MHI event rings ids.
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- qcom,ipa-tz-unlock-reg: Register start addresses and ranges which
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|
need to be unlocked by TZ.
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- qcom,ipa-uc-monitor-holb: Boolean context flag to indicate whether
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||||||
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monitoring of holb via IPA uc is required.
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-qcom,ipa-fltrt-not-hashable: Boolean context flag to indicate filter/route rules
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hashing not supported.
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- qcom,wlan-ce-db-over-pcie: Boolean context flag to represent WLAN CE DB
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over pcie bus or not.
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- qcom,ipa-wdi2_over_gsi: Boolean context flag to indicate WDI2 offload over GSI
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supported or not.
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- qcom,register-collection-on-crash: Boolean that controls IPA/GSI register
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collection upon system crash (i.e. SSR).
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- qcom,testbus-collection-on-crash: Boolean that controls testbus register
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collection upon system crash.
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- qcom,non-tn-collection-on-crash: Boolean to control a certain subset of IPA/GSI
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register collection relative to an SSR. Accessing
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|
these registers can cause stalling, hence this
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|
control.
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- qcom,entire-ipa-block-size: Complete size of the ipa block in which all
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registers, collected upon crash, reside.
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- qcom,ipa-endp-delay-wa: Boolean context flag to indicate end point delay work around
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|
supported or not.
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- qcom,secure-debug-check-action: Drives secure memory debug check. Three values allowed:
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0 (use scm call),
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1 (override scm call as though it returned true), and
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2 (override scm call as though it returned false)
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- qcom,ipa-gpi-event-rp-ddr: Boolean context flag to control whether GPI and GCI event
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rings read pointer should be read from the ddr.
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- qcom,rmnet-ll-enable: Flag to indicate low latency data channels should be supported
|
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|
for the target
|
||||||
|
- qcom,gsi-msi-addr: APSS_GICA_SETSPI_NSR register address for IPA firmware to write
|
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the MSI IRQ number to get the ISR triggered
|
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- qcom,gsi-msi-clear-addr: APSS_GICA_CLRSPI_NSR register address for IPA driver to write
|
||||||
|
the MSI IRQ number to clear the respective interrupt
|
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- qcom,gsi-rmnet-ctl-evt-ring-intvec: Integer vector value for the QMAP flow control pipe
|
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|
- qcom,gsi-rmnet-ll-evt-ring-intvec: Integer vector value for the low lat data pipe
|
||||||
|
|
||||||
|
IPA pipe sub nodes (A2 static pipes configurations):
|
||||||
|
|
||||||
|
-label: two labels are supported, a2-to-ipa and ipa-to-a2 which
|
||||||
|
supply static configuration for A2-IPA connection.
|
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|
-qcom,src-bam-physical-address: The physical address of the source BAM
|
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|
-qcom,ipa-bam-mem-type:The memory type:
|
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|
0(Pipe memory), 1(Private memory), 2(System memory)
|
||||||
|
-qcom,src-bam-pipe-index: Source pipe index
|
||||||
|
-qcom,dst-bam-physical-address: The physical address of the
|
||||||
|
destination BAM
|
||||||
|
-qcom,dst-bam-pipe-index: Destination pipe index
|
||||||
|
-qcom,data-fifo-offset: Data fifo base offset
|
||||||
|
-qcom,data-fifo-size: Data fifo size (bytes)
|
||||||
|
-qcom,descriptor-fifo-offset: Descriptor fifo base offset
|
||||||
|
-qcom,descriptor-fifo-size: Descriptor fifo size (bytes)
|
||||||
|
|
||||||
|
Optional properties:
|
||||||
|
-qcom,ipa-pipe-mem: Specifies the base physical address and the
|
||||||
|
size of the IPA pipe memory region.
|
||||||
|
Pipe memory is a feature which may be supported by the
|
||||||
|
target (HW platform). The Driver support using pipe
|
||||||
|
memory instead of system memory. In case this property
|
||||||
|
will not appear in the IPA DTS entry, the driver will
|
||||||
|
use system memory.
|
||||||
|
- clocks: This property shall provide a list of entries each of which
|
||||||
|
contains a phandle to clock controller device and a macro that is
|
||||||
|
the clock's name in hardware.This should be "clock_rpm" as clock
|
||||||
|
controller phandle and "clk_ipa_clk" as macro for "iface_clk"
|
||||||
|
- clock-names: This property shall contain the clock input names used
|
||||||
|
by driver in same order as the clocks property.This should be "iface_clk"
|
||||||
|
- emulator-bar0-offset: Specifies the offset, within PCIe BAR0, where
|
||||||
|
IPA/GSI programmable registers reside. This property is used only
|
||||||
|
with the IPA/GSI emulation system, which is connected to and
|
||||||
|
communicated with via PCIe.
|
||||||
|
|
||||||
|
IPA SMMU sub nodes
|
||||||
|
|
||||||
|
-compatible: "qcom,ipa-smmu-ap-cb" - represents the AP context bank.
|
||||||
|
|
||||||
|
-compatible: "qcom,ipa-smmu-wlan-cb" - represents IPA WLAN context bank.
|
||||||
|
|
||||||
|
-compatible: "qcom,ipa-smmu-uc-cb" - represents IPA uC context bank (for uC
|
||||||
|
offload scenarios).
|
||||||
|
|
||||||
|
- qcom,smmu-s1-bypass: Boolean context flag to set SMMU to S1 bypass.
|
||||||
|
|
||||||
|
- dma-coherent: Indicate using dma-coherent or not in SMMU block
|
||||||
|
|
||||||
|
- iommus : the phandle and stream IDs for the SMMU used by this root
|
||||||
|
|
||||||
|
- qcom,iova-mapping: specifies the start address and size of iova space.
|
||||||
|
|
||||||
|
- qcom,additional-mapping: specifies any addtional mapping needed for this
|
||||||
|
context bank. The format is <iova pa size>
|
||||||
|
|
||||||
|
IPA SMP2P sub nodes
|
||||||
|
|
||||||
|
-compatible: "qcom,smp2p-map-ipa-1-out" - represents the out smp2p from
|
||||||
|
ipa driver to modem.
|
||||||
|
|
||||||
|
-compatible: "qcom,smp2p-map-ipa-1-in" - represents the in smp2p to
|
||||||
|
ipa driver from modem.
|
||||||
|
|
||||||
|
|
||||||
|
Example:
|
||||||
|
|
||||||
|
qcom,ipa@fd4c0000 {
|
||||||
|
compatible = "qcom,ipa";
|
||||||
|
reg = <0xfd4c0000 0x26000>,
|
||||||
|
<0xfd4c4000 0x14818>;
|
||||||
|
<0xfc834000 0x7000>;
|
||||||
|
reg-names = "ipa-base", "bam-base"; "a2-bam-base";
|
||||||
|
interrupts = <0 252 0>,
|
||||||
|
<0 253 0>;
|
||||||
|
<0 29 1>;
|
||||||
|
interrupt-names = "ipa-irq", "bam-irq"; "a2-bam-irq";
|
||||||
|
qcom,ipa-hw-ver = <1>;
|
||||||
|
clocks = <&clock_rpm clk_ipa_clk>;
|
||||||
|
clock-names = "iface_clk";
|
||||||
|
|
||||||
|
qcom,msm-bus,name = "ipa";
|
||||||
|
qcom,msm-bus,num-cases = <3>;
|
||||||
|
qcom,msm-bus,num-paths = <2>;
|
||||||
|
qcom,msm-bus,vectors-KBps =
|
||||||
|
<90 512 0 0>, <90 585 0 0>, /* No vote */
|
||||||
|
<90 512 100000 800000>, <90 585 100000 800000>, /* SVS */
|
||||||
|
<90 512 100000 1200000>, <90 585 100000 1200000>; /* PERF */
|
||||||
|
qcom,bus-vector-names = "MIN", "SVS", "PERF";
|
||||||
|
|
||||||
|
qcom,pipe1 {
|
||||||
|
label = "a2-to-ipa";
|
||||||
|
qcom,src-bam-physical-address = <0xfc834000>;
|
||||||
|
qcom,ipa-bam-mem-type = <0>;
|
||||||
|
qcom,src-bam-pipe-index = <1>;
|
||||||
|
qcom,dst-bam-physical-address = <0xfd4c0000>;
|
||||||
|
qcom,dst-bam-pipe-index = <6>;
|
||||||
|
qcom,data-fifo-offset = <0x1000>;
|
||||||
|
qcom,data-fifo-size = <0xd00>;
|
||||||
|
qcom,descriptor-fifo-offset = <0x1d00>;
|
||||||
|
qcom,descriptor-fifo-size = <0x300>;
|
||||||
|
};
|
||||||
|
|
||||||
|
qcom,pipe2 {
|
||||||
|
label = "ipa-to-a2";
|
||||||
|
qcom,src-bam-physical-address = <0xfd4c0000>;
|
||||||
|
qcom,ipa-bam-mem-type = <0>;
|
||||||
|
qcom,src-bam-pipe-index = <7>;
|
||||||
|
qcom,dst-bam-physical-address = <0xfc834000>;
|
||||||
|
qcom,dst-bam-pipe-index = <0>;
|
||||||
|
qcom,data-fifo-offset = <0x00>;
|
||||||
|
qcom,data-fifo-size = <0xd00>;
|
||||||
|
qcom,descriptor-fifo-offset = <0xd00>;
|
||||||
|
qcom,descriptor-fifo-size = <0x300>;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* smp2p information */
|
||||||
|
qcom,smp2p_map_ipa_1_out {
|
||||||
|
compatible = "qcom,smp2p-map-ipa-1-out";
|
||||||
|
};
|
||||||
|
|
||||||
|
qcom,smp2p_map_ipa_1_in {
|
||||||
|
compatible = "qcom,smp2p-map-ipa-1-in";
|
||||||
|
};
|
||||||
|
|
||||||
|
ipa_smmu_ap: ipa_smmu_ap {
|
||||||
|
compatible = "qcom,ipa-smmu-ap-cb";
|
||||||
|
iommus = <&apps_smmu 0x720>;
|
||||||
|
qcom,iova-mapping = <0x20000000 0x40000000>;
|
||||||
|
qcom,additional-mapping =
|
||||||
|
/* modem tables in IMEM */
|
||||||
|
<0x146bd000 0x146bd000 0x2000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
ipa_smmu_wlan: ipa_smmu_wlan {
|
||||||
|
compatible = "qcom,ipa-smmu-wlan-cb";
|
||||||
|
iommus = <&apps_smmu 0x721>;
|
||||||
|
qcom,additional-mapping =
|
||||||
|
/* ipa-uc ram */
|
||||||
|
<0x1e60000 0x1e60000 0x80000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
ipa_smmu_uc: ipa_smmu_uc {
|
||||||
|
compatible = "qcom,ipa-smmu-uc-cb";
|
||||||
|
iommus = <&apps_smmu 0x722>;
|
||||||
|
qcom,iova-mapping = <0x40000000 0x20000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
ipa_smmu_11ad: ipa_smmu_11ad {
|
||||||
|
compatible = "qcom,ipa-smmu-11ad-cb";
|
||||||
|
iommus = <&apps_smmu 0x5C3 0x0>;
|
||||||
|
dma-coherent;
|
||||||
|
qcom,shared-cb;
|
||||||
|
qcom,iommu-group = <&wil6210_pci_iommu_group>;
|
||||||
|
};
|
||||||
|
};
|
||||||
301
qcom/data/bindings/ipa.yaml
Normal file
301
qcom/data/bindings/ipa.yaml
Normal file
@@ -0,0 +1,301 @@
|
|||||||
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||||
|
%YAML 1.2
|
||||||
|
---
|
||||||
|
|
||||||
|
title: Qualcomm technologies inc. Internet Packet Accelerator
|
||||||
|
|
||||||
|
description:
|
||||||
|
Internet Packet Accelerator (IPA) is a programmable protocol
|
||||||
|
processor HW block. It is designed to support generic HW processing
|
||||||
|
of UL/DL IP packets for various use cases independent of radio technology.
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
|
||||||
|
IPA node:
|
||||||
|
|
||||||
|
- compatible : "qcom,ipa"
|
||||||
|
- reg: Specifies the base physical addresses and the sizes of the IPA
|
||||||
|
registers.
|
||||||
|
- reg-names: "ipa-base" - string to identify the IPA CORE base registers.
|
||||||
|
"bam-base" - string to identify the IPA BAM base registers.
|
||||||
|
"a2-bam-base" - string to identify the A2 BAM base registers.
|
||||||
|
- pas-ids: specify the image ids of the FW images that needs to be loaded.
|
||||||
|
- firmware-names: - String name of the FW images that need to be loaded.
|
||||||
|
- memory-regions: - Carved memory regions of the FW images.
|
||||||
|
- interrupts: Specifies the interrupt associated with IPA.
|
||||||
|
- interrupt-names: "ipa-irq" - string to identify the IPA core interrupt.
|
||||||
|
"bam-irq" - string to identify the IPA BAM interrupt.
|
||||||
|
"a2-bam-irq" - string to identify the A2 BAM interrupt.
|
||||||
|
"msi-irq-rmnet-ctl" - string to identify QMAP MSI interrupt
|
||||||
|
"msi-irq-rmnet-ll" - string to identify LL MSI interrupt
|
||||||
|
- qcom,ipa-hw-ver: Specifies the IPA hardware version.
|
||||||
|
- qcom,ipa-ram-mmap: An array of unsigned integers representing addresses and
|
||||||
|
sizes which are used by the driver to access IPA RAM.
|
||||||
|
|
||||||
|
Optional:
|
||||||
|
- qcom,tx-poll: Enable performing TX completions in polling mode.
|
||||||
|
- qcom,tx-wrapper-cache-max-size: Define the tx warpper cache pool max size,
|
||||||
|
if set to zero then the feature is disabled.
|
||||||
|
- qcom,tx-napi: Enable usage of NAPI in the TX data path.
|
||||||
|
- qcom,lan-rx-napi: Enable NAPI in the LAN RX data path.
|
||||||
|
- qcom,ipa-uc-holb-monitor: Enable uC HOLB monitor feature.
|
||||||
|
- qcom,ipa-holb-monitor-poll-period: Poll period for HOLB monitor feature.
|
||||||
|
- qcom,holb-monitor-max-cnt-wlan: Max stuck count for HOLB on WLAN channel.
|
||||||
|
- qcom,holb-monitor-max-cnt-usb: Max stuck count for HOLB on USB channel.
|
||||||
|
- qcom,holb-monitor-max-cnt-11ad: Max stuck count for HOLB on 11AD channel.
|
||||||
|
- qcom,wan-rx-ring-size: size of WAN rx ring, default is 192
|
||||||
|
- qcom,lan-rx-ring-size: size of LAN rx ring, default is 192
|
||||||
|
- qcom,arm-smmu: SMMU is present and ARM SMMU driver is used
|
||||||
|
- qcom,msm-smmu: SMMU is present and QSMMU driver is used
|
||||||
|
- qcom,smmu-fast-map: Boolean context flag to set SMMU to fastpath mode
|
||||||
|
- ipa_smmu_ap: AP general purpose SMMU device
|
||||||
|
compatible "qcom,ipa-smmu-ap-cb"
|
||||||
|
- ipa_smmu_wlan: WDI SMMU device
|
||||||
|
compatible "qcom,ipa-smmu-wlan-cb"
|
||||||
|
- ipa_smmu_uc: uc SMMU device
|
||||||
|
compatible "qcom,ipa-smmu-uc-cb"
|
||||||
|
- ipa_smmu_11ad: 11AD SMMU device
|
||||||
|
compatible "qcom,ipa-smmu-11ad-cb"
|
||||||
|
- qcom,use-a2-service: determine if A2 service will be used
|
||||||
|
- qcom,use-ipa-tethering-bridge: determine if tethering bridge will be used
|
||||||
|
- qcom,use-ipa-in-mhi-mode: Boolean context flag to indicate whether
|
||||||
|
device booting in MHI config or not.
|
||||||
|
- qcom,use-ipa-bamdma-a2-bridge: determine if a2/ipa hw bridge will be used
|
||||||
|
- qcom,ee: which EE is assigned to (non-secure) APPS from IPA-BAM POV. This
|
||||||
|
is a number
|
||||||
|
- qcom,ipa-hw-mode: IPA hardware mode - Normal, Virtual memory allocation,
|
||||||
|
memory allocation over a PCIe bridge
|
||||||
|
-qcom,platform-type: MDM platform, MSM platform or APQ platform
|
||||||
|
- qcom,msm-bus,name: String representing the client-name
|
||||||
|
- qcom,msm-bus,num-cases: Total number of usecases
|
||||||
|
- qcom,msm-bus,active-only: Boolean context flag for requests in active or
|
||||||
|
dual (active & sleep) contex
|
||||||
|
- qcom,msm-bus,num-paths: Total number of master-slave pairs
|
||||||
|
- qcom,msm-bus,vectors-KBps: Arrays of unsigned integers representing:
|
||||||
|
master-id, slave-id, arbitrated bandwidth
|
||||||
|
in KBps, instantaneous bandwidth in KBps
|
||||||
|
- qcom,ipa-bam-remote-mode: Boolean context flag to determine if ipa bam
|
||||||
|
is in remote mode.
|
||||||
|
- qcom,modem-cfg-emb-pipe-flt: Boolean context flag to determine if modem
|
||||||
|
configures embedded pipe filtering rules
|
||||||
|
- qcom,skip-uc-pipe-reset: Boolean context flag to indicate whether
|
||||||
|
a pipe reset via the IPA uC is required
|
||||||
|
- qcom,ipa-wdi2: Boolean context flag to indicate whether
|
||||||
|
using wdi-2.0 or not
|
||||||
|
- qcom,ipa-wdi3-over-gsi: Boolean context flag to indicate whether
|
||||||
|
using wdi-3.0 or not
|
||||||
|
- qcom,bandwidth-vote-for-ipa: Boolean context flag to indicate whether
|
||||||
|
ipa clock voting is done by bandwidth
|
||||||
|
voting via msm-bus-scale driver or not
|
||||||
|
- qcom,use-64-bit-dma-mask: Boolean context flag to indicate whether
|
||||||
|
using 64bit dma mask or not
|
||||||
|
- qcom,use-dma-zone: Boolean context flag to indicate whether memory
|
||||||
|
allocations controlled by IPA driver that do not
|
||||||
|
specify a struct device * should use GFP_DMA to
|
||||||
|
workaround IPA HW limitations
|
||||||
|
- qcom,use-rg10-limitation-mitigation: Boolean context flag to activate
|
||||||
|
the mitigation to register group 10
|
||||||
|
AP access limitation
|
||||||
|
- qcom,do-not-use-ch-gsi-20: Boolean context flag to activate
|
||||||
|
software workaround for IPA limitation
|
||||||
|
to not use GSI physical channel 20
|
||||||
|
- qcom,tethered-flow-control: Boolean context flag to indicate whether
|
||||||
|
apps based flow control is needed for tethered
|
||||||
|
call.
|
||||||
|
- qcom,rx-polling-sleep-ms: Receive Polling Timeout in millisecond,
|
||||||
|
default is 1 millisecond.
|
||||||
|
- qcom,ipa-polling-iteration: IPA Polling Iteration Count,default is 40.
|
||||||
|
- qcom,mhi-event-ring-id-limits: Two elements property. Start and End limits
|
||||||
|
for MHI event rings ids.
|
||||||
|
- qcom,ipa-tz-unlock-reg: Register start addresses and ranges which
|
||||||
|
need to be unlocked by TZ.
|
||||||
|
- qcom,ipa-uc-monitor-holb: Boolean context flag to indicate whether
|
||||||
|
monitoring of holb via IPA uc is required.
|
||||||
|
-qcom,ipa-fltrt-not-hashable: Boolean context flag to indicate filter/route rules
|
||||||
|
hashing not supported.
|
||||||
|
- qcom,wlan-ce-db-over-pcie: Boolean context flag to represent WLAN CE DB
|
||||||
|
over pcie bus or not.
|
||||||
|
- qcom,ipa-wdi2_over_gsi: Boolean context flag to indicate WDI2 offload over GSI
|
||||||
|
supported or not.
|
||||||
|
- qcom,register-collection-on-crash: Boolean that controls IPA/GSI register
|
||||||
|
collection upon system crash (i.e. SSR).
|
||||||
|
- qcom,testbus-collection-on-crash: Boolean that controls testbus register
|
||||||
|
collection upon system crash.
|
||||||
|
- qcom,non-tn-collection-on-crash: Boolean to control a certain subset of IPA/GSI
|
||||||
|
register collection relative to an SSR. Accessing
|
||||||
|
these registers can cause stalling, hence this
|
||||||
|
control.
|
||||||
|
- qcom,entire-ipa-block-size: Complete size of the ipa block in which all
|
||||||
|
registers, collected upon crash, reside.
|
||||||
|
- qcom,ipa-endp-delay-wa: Boolean context flag to indicate end point delay work around
|
||||||
|
supported or not.
|
||||||
|
- qcom,secure-debug-check-action: Drives secure memory debug check. Three values allowed:
|
||||||
|
0 (use scm call),
|
||||||
|
1 (override scm call as though it returned true), and
|
||||||
|
2 (override scm call as though it returned false)
|
||||||
|
- qcom,ipa-gpi-event-rp-ddr: Boolean context flag to control whether GPI and GCI event
|
||||||
|
rings read pointer should be read from the ddr.
|
||||||
|
- qcom,rmnet-ll-enable: Flag to indicate low latency data channels should be supported
|
||||||
|
for the target
|
||||||
|
- qcom,gsi-msi-addr: APSS_GICA_SETSPI_NSR register address for IPA firmware to write
|
||||||
|
the MSI IRQ number to get the ISR triggered
|
||||||
|
- qcom,gsi-msi-clear-addr: APSS_GICA_CLRSPI_NSR register address for IPA driver to write
|
||||||
|
the MSI IRQ number to clear the respective interrupt
|
||||||
|
- qcom,gsi-rmnet-ctl-evt-ring-intvec: Integer vector value for the QMAP flow control pipe
|
||||||
|
- qcom,gsi-rmnet-ll-evt-ring-intvec: Integer vector value for the low lat data pipe
|
||||||
|
|
||||||
|
IPA pipe sub nodes (A2 static pipes configurations):
|
||||||
|
|
||||||
|
-label: two labels are supported, a2-to-ipa and ipa-to-a2 which
|
||||||
|
supply static configuration for A2-IPA connection.
|
||||||
|
-qcom,src-bam-physical-address: The physical address of the source BAM
|
||||||
|
-qcom,ipa-bam-mem-type:The memory type:
|
||||||
|
0(Pipe memory), 1(Private memory), 2(System memory)
|
||||||
|
-qcom,src-bam-pipe-index: Source pipe index
|
||||||
|
-qcom,dst-bam-physical-address: The physical address of the
|
||||||
|
destination BAM
|
||||||
|
-qcom,dst-bam-pipe-index: Destination pipe index
|
||||||
|
-qcom,data-fifo-offset: Data fifo base offset
|
||||||
|
-qcom,data-fifo-size: Data fifo size (bytes)
|
||||||
|
-qcom,descriptor-fifo-offset: Descriptor fifo base offset
|
||||||
|
-qcom,descriptor-fifo-size: Descriptor fifo size (bytes)
|
||||||
|
|
||||||
|
Optional properties:
|
||||||
|
-qcom,ipa-pipe-mem: Specifies the base physical address and the
|
||||||
|
size of the IPA pipe memory region.
|
||||||
|
Pipe memory is a feature which may be supported by the
|
||||||
|
target (HW platform). The Driver support using pipe
|
||||||
|
memory instead of system memory. In case this property
|
||||||
|
will not appear in the IPA DTS entry, the driver will
|
||||||
|
use system memory.
|
||||||
|
- clocks: This property shall provide a list of entries each of which
|
||||||
|
contains a phandle to clock controller device and a macro that is
|
||||||
|
the clock's name in hardware.This should be "clock_rpm" as clock
|
||||||
|
controller phandle and "clk_ipa_clk" as macro for "iface_clk"
|
||||||
|
- clock-names: This property shall contain the clock input names used
|
||||||
|
by driver in same order as the clocks property.This should be "iface_clk"
|
||||||
|
- emulator-bar0-offset: Specifies the offset, within PCIe BAR0, where
|
||||||
|
IPA/GSI programmable registers reside. This property is used only
|
||||||
|
with the IPA/GSI emulation system, which is connected to and
|
||||||
|
communicated with via PCIe.
|
||||||
|
|
||||||
|
IPA SMMU sub nodes
|
||||||
|
|
||||||
|
-compatible: "qcom,ipa-smmu-ap-cb" - represents the AP context bank.
|
||||||
|
|
||||||
|
-compatible: "qcom,ipa-smmu-wlan-cb" - represents IPA WLAN context bank.
|
||||||
|
|
||||||
|
-compatible: "qcom,ipa-smmu-uc-cb" - represents IPA uC context bank (for uC
|
||||||
|
offload scenarios).
|
||||||
|
|
||||||
|
- qcom,smmu-s1-bypass: Boolean context flag to set SMMU to S1 bypass.
|
||||||
|
|
||||||
|
- dma-coherent: Indicate using dma-coherent or not in SMMU block
|
||||||
|
|
||||||
|
- iommus : the phandle and stream IDs for the SMMU used by this root
|
||||||
|
|
||||||
|
- qcom,iova-mapping: specifies the start address and size of iova space.
|
||||||
|
|
||||||
|
- qcom,additional-mapping: specifies any addtional mapping needed for this
|
||||||
|
context bank. The format is <iova pa size>
|
||||||
|
|
||||||
|
IPA SMP2P sub nodes
|
||||||
|
|
||||||
|
-compatible: "qcom,smp2p-map-ipa-1-out" - represents the out smp2p from
|
||||||
|
ipa driver to modem.
|
||||||
|
|
||||||
|
-compatible: "qcom,smp2p-map-ipa-1-in" - represents the in smp2p to
|
||||||
|
ipa driver from modem.
|
||||||
|
|
||||||
|
|
||||||
|
Example:
|
||||||
|
|
||||||
|
qcom,ipa@fd4c0000 {
|
||||||
|
compatible = "qcom,ipa";
|
||||||
|
reg = <0xfd4c0000 0x26000>,
|
||||||
|
<0xfd4c4000 0x14818>;
|
||||||
|
<0xfc834000 0x7000>;
|
||||||
|
reg-names = "ipa-base", "bam-base"; "a2-bam-base";
|
||||||
|
interrupts = <0 252 0>,
|
||||||
|
<0 253 0>;
|
||||||
|
<0 29 1>;
|
||||||
|
interrupt-names = "ipa-irq", "bam-irq"; "a2-bam-irq";
|
||||||
|
qcom,ipa-hw-ver = <1>;
|
||||||
|
clocks = <&clock_rpm clk_ipa_clk>;
|
||||||
|
clock-names = "iface_clk";
|
||||||
|
|
||||||
|
qcom,msm-bus,name = "ipa";
|
||||||
|
qcom,msm-bus,num-cases = <3>;
|
||||||
|
qcom,msm-bus,num-paths = <2>;
|
||||||
|
qcom,msm-bus,vectors-KBps =
|
||||||
|
<90 512 0 0>, <90 585 0 0>, /* No vote */
|
||||||
|
<90 512 100000 800000>, <90 585 100000 800000>, /* SVS */
|
||||||
|
<90 512 100000 1200000>, <90 585 100000 1200000>; /* PERF */
|
||||||
|
qcom,bus-vector-names = "MIN", "SVS", "PERF";
|
||||||
|
|
||||||
|
qcom,pipe1 {
|
||||||
|
label = "a2-to-ipa";
|
||||||
|
qcom,src-bam-physical-address = <0xfc834000>;
|
||||||
|
qcom,ipa-bam-mem-type = <0>;
|
||||||
|
qcom,src-bam-pipe-index = <1>;
|
||||||
|
qcom,dst-bam-physical-address = <0xfd4c0000>;
|
||||||
|
qcom,dst-bam-pipe-index = <6>;
|
||||||
|
qcom,data-fifo-offset = <0x1000>;
|
||||||
|
qcom,data-fifo-size = <0xd00>;
|
||||||
|
qcom,descriptor-fifo-offset = <0x1d00>;
|
||||||
|
qcom,descriptor-fifo-size = <0x300>;
|
||||||
|
};
|
||||||
|
|
||||||
|
qcom,pipe2 {
|
||||||
|
label = "ipa-to-a2";
|
||||||
|
qcom,src-bam-physical-address = <0xfd4c0000>;
|
||||||
|
qcom,ipa-bam-mem-type = <0>;
|
||||||
|
qcom,src-bam-pipe-index = <7>;
|
||||||
|
qcom,dst-bam-physical-address = <0xfc834000>;
|
||||||
|
qcom,dst-bam-pipe-index = <0>;
|
||||||
|
qcom,data-fifo-offset = <0x00>;
|
||||||
|
qcom,data-fifo-size = <0xd00>;
|
||||||
|
qcom,descriptor-fifo-offset = <0xd00>;
|
||||||
|
qcom,descriptor-fifo-size = <0x300>;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* smp2p information */
|
||||||
|
qcom,smp2p_map_ipa_1_out {
|
||||||
|
compatible = "qcom,smp2p-map-ipa-1-out";
|
||||||
|
};
|
||||||
|
|
||||||
|
qcom,smp2p_map_ipa_1_in {
|
||||||
|
compatible = "qcom,smp2p-map-ipa-1-in";
|
||||||
|
};
|
||||||
|
|
||||||
|
ipa_smmu_ap: ipa_smmu_ap {
|
||||||
|
compatible = "qcom,ipa-smmu-ap-cb";
|
||||||
|
iommus = <&apps_smmu 0x720>;
|
||||||
|
qcom,iova-mapping = <0x20000000 0x40000000>;
|
||||||
|
qcom,additional-mapping =
|
||||||
|
/* modem tables in IMEM */
|
||||||
|
<0x146bd000 0x146bd000 0x2000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
ipa_smmu_wlan: ipa_smmu_wlan {
|
||||||
|
compatible = "qcom,ipa-smmu-wlan-cb";
|
||||||
|
iommus = <&apps_smmu 0x721>;
|
||||||
|
qcom,additional-mapping =
|
||||||
|
/* ipa-uc ram */
|
||||||
|
<0x1e60000 0x1e60000 0x80000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
ipa_smmu_uc: ipa_smmu_uc {
|
||||||
|
compatible = "qcom,ipa-smmu-uc-cb";
|
||||||
|
iommus = <&apps_smmu 0x722>;
|
||||||
|
qcom,iova-mapping = <0x40000000 0x20000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
ipa_smmu_11ad: ipa_smmu_11ad {
|
||||||
|
compatible = "qcom,ipa-smmu-11ad-cb";
|
||||||
|
iommus = <&apps_smmu 0x5C3 0x0>;
|
||||||
|
dma-coherent;
|
||||||
|
qcom,shared-cb;
|
||||||
|
qcom,iommu-group = <&wil6210_pci_iommu_group>;
|
||||||
|
};
|
||||||
|
};
|
||||||
23
qcom/data/bindings/ipa_mpm.txt
Normal file
23
qcom/data/bindings/ipa_mpm.txt
Normal file
@@ -0,0 +1,23 @@
|
|||||||
|
* Qualcomm Technologies, Inc. IPA MHI Prime Manager driver module
|
||||||
|
|
||||||
|
This module enables IPA Modem to IPA APQ communication using
|
||||||
|
MHI Prime.
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
- compatible: Must be "qcom,ipa-mpm"
|
||||||
|
- qcom,mhi-chdb-base: MHI channel doorbell base address in MMIO space.
|
||||||
|
- qcom,mhi-erdb-base: MHI event doorbell base address in MMIO space.
|
||||||
|
|
||||||
|
Optional:
|
||||||
|
- qcom,iova-mapping: Start address and size of the carved IOVA space
|
||||||
|
dedicated for MHI control structures
|
||||||
|
(such as transfer rings, event rings, doorbells).
|
||||||
|
If not present, SMMU S1 is considered to be in bypass mode.
|
||||||
|
|
||||||
|
Example:
|
||||||
|
ipa_mpm: qcom,ipa-mpm {
|
||||||
|
compatible = "qcom,ipa-mpm";
|
||||||
|
qcom,mhi-chdb-base = <0x40300300>;
|
||||||
|
qcom,mhi-erdb-base = <0x40300700>;
|
||||||
|
qcom,iova-mapping = <0x10000000 0x1FFFFFFF>;
|
||||||
|
}
|
||||||
28
qcom/data/bindings/ipa_mpm.yaml
Normal file
28
qcom/data/bindings/ipa_mpm.yaml
Normal file
@@ -0,0 +1,28 @@
|
|||||||
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||||
|
%YAML 1.2
|
||||||
|
---
|
||||||
|
|
||||||
|
title: Qualcomm Technologies, Inc. IPA MHI Prime Manager driver module
|
||||||
|
|
||||||
|
description:
|
||||||
|
This module enables IPA Modem to IPA APQ communication using
|
||||||
|
MHI Prime.
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
- compatible: Must be "qcom,ipa-mpm"
|
||||||
|
- qcom,mhi-chdb-base: MHI channel doorbell base address in MMIO space.
|
||||||
|
- qcom,mhi-erdb-base: MHI event doorbell base address in MMIO space.
|
||||||
|
|
||||||
|
Optional:
|
||||||
|
- qcom,iova-mapping: Start address and size of the carved IOVA space
|
||||||
|
dedicated for MHI control structures
|
||||||
|
(such as transfer rings, event rings, doorbells).
|
||||||
|
If not present, SMMU S1 is considered to be in bypass mode.
|
||||||
|
|
||||||
|
Example:
|
||||||
|
ipa_mpm: qcom,ipa-mpm {
|
||||||
|
compatible = "qcom,ipa-mpm";
|
||||||
|
qcom,mhi-chdb-base = <0x40300300>;
|
||||||
|
qcom,mhi-erdb-base = <0x40300700>;
|
||||||
|
qcom,iova-mapping = <0x10000000 0x1FFFFFFF>;
|
||||||
|
}
|
||||||
15
qcom/data/bindings/msm_gsi.txt
Normal file
15
qcom/data/bindings/msm_gsi.txt
Normal file
@@ -0,0 +1,15 @@
|
|||||||
|
* Qualcomm Technologies, Inc. GSI driver module
|
||||||
|
|
||||||
|
GSI is a HW accelerator that supports Generic SW Interfaces (GSI) which are
|
||||||
|
peripheral specific (IPA in this case).
|
||||||
|
GSI translates SW transfer elements (TRE) into TLV transactions which are
|
||||||
|
then processed by the peripheral.
|
||||||
|
This Driver configures and communicates with GSI HW.
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
- compatible: Must be "qcom,msm_gsi"
|
||||||
|
|
||||||
|
Example:
|
||||||
|
qcom,msm-gsi {
|
||||||
|
compatible = "qcom,msm_gsi";
|
||||||
|
}
|
||||||
20
qcom/data/bindings/msm_gsi.yaml
Normal file
20
qcom/data/bindings/msm_gsi.yaml
Normal file
@@ -0,0 +1,20 @@
|
|||||||
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||||
|
%YAML 1.2
|
||||||
|
---
|
||||||
|
|
||||||
|
title: Qualcomm Technologies, Inc. GSI driver module
|
||||||
|
|
||||||
|
description:
|
||||||
|
GSI is a HW accelerator that supports Generic SW Interfaces (GSI) which are
|
||||||
|
peripheral specific (IPA in this case).
|
||||||
|
GSI translates SW transfer elements (TRE) into TLV transactions which are
|
||||||
|
then processed by the peripheral.
|
||||||
|
This Driver configures and communicates with GSI HW.
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
- compatible: Must be "qcom,msm_gsi"
|
||||||
|
|
||||||
|
Example:
|
||||||
|
qcom,msm-gsi {
|
||||||
|
compatible = "qcom,msm_gsi";
|
||||||
|
}
|
||||||
22
qcom/data/bindings/rmnet_ipa3.txt
Normal file
22
qcom/data/bindings/rmnet_ipa3.txt
Normal file
@@ -0,0 +1,22 @@
|
|||||||
|
* Qualcomm Technologies, Inc. RmNet IPA driver module
|
||||||
|
|
||||||
|
This module enables embedded data calls using IPA v3 HW.
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
- compatible: Must be "qcom,rmnet-ipa3"
|
||||||
|
|
||||||
|
Optional:
|
||||||
|
- qcom,rmnet-ipa-ssr: determine if modem SSR is supported
|
||||||
|
- qcom,ipa-platform-type-msm: indicates the platform type is msm or not
|
||||||
|
- qcom,ipa-advertise-sg-support: determine how to respond to a query
|
||||||
|
regarding scatter-gather capability
|
||||||
|
- qcom,ipa-napi-enable: Boolean context flag to indicate whether
|
||||||
|
to enable napi framework or not
|
||||||
|
- qcom,wan-rx-desc-size: size of WAN rx desc fifo ring, default is 256
|
||||||
|
|
||||||
|
Example:
|
||||||
|
qcom,rmnet-ipa3 {
|
||||||
|
compatible = "qcom,rmnet-ipa3";
|
||||||
|
qcom,wan-rx-desc-size = <256>;
|
||||||
|
}
|
||||||
|
|
||||||
27
qcom/data/bindings/rmnet_ipa3.yaml
Normal file
27
qcom/data/bindings/rmnet_ipa3.yaml
Normal file
@@ -0,0 +1,27 @@
|
|||||||
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||||
|
%YAML 1.2
|
||||||
|
---
|
||||||
|
|
||||||
|
title: Qualcomm Technologies, Inc. RmNet IPA driver module
|
||||||
|
|
||||||
|
description:
|
||||||
|
This module enables embedded data calls using IPA v3 HW.
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
- compatible: Must be "qcom,rmnet-ipa3"
|
||||||
|
|
||||||
|
Optional:
|
||||||
|
- qcom,rmnet-ipa-ssr: determine if modem SSR is supported
|
||||||
|
- qcom,ipa-platform-type-msm: indicates the platform type is msm or not
|
||||||
|
- qcom,ipa-advertise-sg-support: determine how to respond to a query
|
||||||
|
regarding scatter-gather capability
|
||||||
|
- qcom,ipa-napi-enable: Boolean context flag to indicate whether
|
||||||
|
to enable napi framework or not
|
||||||
|
- qcom,wan-rx-desc-size: size of WAN rx desc fifo ring, default is 256
|
||||||
|
|
||||||
|
Example:
|
||||||
|
qcom,rmnet-ipa3 {
|
||||||
|
compatible = "qcom,rmnet-ipa3";
|
||||||
|
qcom,wan-rx-desc-size = <256>;
|
||||||
|
}
|
||||||
|
|
||||||
21
qcom/data/blair-ipa.dts
Normal file
21
qcom/data/blair-ipa.dts
Normal file
@@ -0,0 +1,21 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
|
#include <dt-bindings/soc/qcom,ipcc.h>
|
||||||
|
#include <dt-bindings/interconnect/qcom,blair.h>
|
||||||
|
#include <dt-bindings/clock/qcom,gcc-blair.h>
|
||||||
|
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||||
|
#include "ipa_v4.dtsi"
|
||||||
|
|
||||||
|
/{
|
||||||
|
model = "Qualcomm Technologies, Inc. Blair";
|
||||||
|
compatible = "qcom,blair";
|
||||||
|
qcom,msm-id = <507 0x10000>, <578 0x10000>;
|
||||||
|
qcom,board-id = <0 0>;
|
||||||
|
};
|
||||||
21
qcom/data/cliffs-ipa.dts
Normal file
21
qcom/data/cliffs-ipa.dts
Normal file
@@ -0,0 +1,21 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
|
#include <dt-bindings/soc/qcom,ipcc.h>
|
||||||
|
#include <dt-bindings/interconnect/qcom,cliffs.h>
|
||||||
|
#include <dt-bindings/clock/qcom,gcc-cliffs.h>
|
||||||
|
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||||
|
#include "cliffs-ipa.dtsi"
|
||||||
|
|
||||||
|
/{
|
||||||
|
model = "Qualcomm Technologies, Inc. Cliffs";
|
||||||
|
compatible = "qcom,cliffs";
|
||||||
|
qcom,msm-id = <614 0x10000>, <632 0x10000>;
|
||||||
|
qcom,board-id = <0 0>;
|
||||||
|
};
|
||||||
45
qcom/data/cliffs-ipa.dtsi
Normal file
45
qcom/data/cliffs-ipa.dtsi
Normal file
@@ -0,0 +1,45 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "ipa.dtsi"
|
||||||
|
&ipa_hw {
|
||||||
|
qcom,interconnect,num-cases = <5>;
|
||||||
|
qcom,interconnect,num-paths = <3>;
|
||||||
|
interconnects = <&aggre2_noc MASTER_IPA &gem_noc SLAVE_LLCC>,
|
||||||
|
<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
|
||||||
|
<&gem_noc MASTER_APPSS_PROC &cnoc_main SLAVE_IPA_CFG>;
|
||||||
|
interconnect-names = "ipa_to_llcc", "llcc_to_ebi1", "appss_to_ipa";
|
||||||
|
/* No vote */
|
||||||
|
qcom,no-vote =
|
||||||
|
<0 0 0 0 0 0>;
|
||||||
|
|
||||||
|
/* SVS2 */
|
||||||
|
qcom,svs2 =
|
||||||
|
<0 0 0 1300000 0 76800>;
|
||||||
|
|
||||||
|
/* SVS */
|
||||||
|
qcom,svs =
|
||||||
|
<1200000 0 1200000 2800000 0 150000>;
|
||||||
|
|
||||||
|
/* NOMINAL */
|
||||||
|
qcom,nominal =
|
||||||
|
<2400000 0 2400000 5500000 0 400000>;
|
||||||
|
|
||||||
|
/* TURBO */
|
||||||
|
qcom,turbo =
|
||||||
|
<3600000 0 3600000 5500000 0 400000>;
|
||||||
|
|
||||||
|
qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL",
|
||||||
|
"TURBO";
|
||||||
|
|
||||||
|
/* Low Latency pipe alloc factor */
|
||||||
|
qcom,ipa-gen-rx-ll-pool-sz-factor = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&ipa_smmu_ap {
|
||||||
|
qcom,additional-mapping =
|
||||||
|
/* modem tables in IMEM */
|
||||||
|
<0x14683000 0x14683000 0x2000>;
|
||||||
|
};
|
||||||
21
qcom/data/holi-ipa.dts
Normal file
21
qcom/data/holi-ipa.dts
Normal file
@@ -0,0 +1,21 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
|
#include <dt-bindings/soc/qcom,ipcc.h>
|
||||||
|
#include <dt-bindings/interconnect/qcom,holi.h>
|
||||||
|
#include <dt-bindings/clock/qcom,gcc-holi.h>
|
||||||
|
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||||
|
#include "ipa_v4.dtsi"
|
||||||
|
|
||||||
|
/{
|
||||||
|
model = "Qualcomm Technologies, Inc. Holi";
|
||||||
|
compatible = "qcom,holi";
|
||||||
|
qcom,msm-id = <454 0x10000>, <472 0x10000>;
|
||||||
|
qcom,board-id = <0 0>;
|
||||||
|
};
|
||||||
126
qcom/data/ipa.dtsi
Normal file
126
qcom/data/ipa.dtsi
Normal file
@@ -0,0 +1,126 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
&soc {
|
||||||
|
qcom,msm_gsi {
|
||||||
|
compatible = "qcom,msm_gsi";
|
||||||
|
};
|
||||||
|
|
||||||
|
qcom,rmnet-ipa {
|
||||||
|
compatible = "qcom,rmnet-ipa3";
|
||||||
|
qcom,rmnet-ipa-ssr;
|
||||||
|
qcom,ipa-platform-type-msm;
|
||||||
|
qcom,ipa-advertise-sg-support;
|
||||||
|
qcom,ipa-napi-enable;
|
||||||
|
};
|
||||||
|
|
||||||
|
qcom,ipa_fws {
|
||||||
|
compatible = "qcom,pil-tz-generic";
|
||||||
|
qcom,pas-id = <0xf>;
|
||||||
|
qcom,firmware-name = "ipa_fws";
|
||||||
|
qcom,pil-force-shutdown;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
ipa_hw: qcom,ipa@3e00000 {
|
||||||
|
compatible = "qcom,ipa";
|
||||||
|
reg =
|
||||||
|
<0x3e00000 0x84000>,
|
||||||
|
<0x3e04000 0xfc000>;
|
||||||
|
reg-names = "ipa-base", "gsi-base";
|
||||||
|
pas-ids = <0xf>;
|
||||||
|
firmware-names = "ipa_fws";
|
||||||
|
memory-regions = <&ipa_gsi_mem>;
|
||||||
|
qcom,ipa-cfg-offset = <0x0140000>;
|
||||||
|
interrupt-names = "ipa-irq", "gsi-irq";
|
||||||
|
qcom,ipa-hw-ver = <24>; /* IPA core version = IPAv5.5 */
|
||||||
|
qcom,ipa-hw-mode = <0>;
|
||||||
|
qcom,platform-type = <1>; /* MSM platform */
|
||||||
|
qcom,ee = <0>;
|
||||||
|
qcom,entire-ipa-block-size = <0x200000>;
|
||||||
|
qcom,use-ipa-tethering-bridge;
|
||||||
|
qcom,mhi-event-ring-id-limits = <9 11>; /* start and end */
|
||||||
|
qcom,modem-cfg-emb-pipe-flt;
|
||||||
|
qcom,ipa-wdi3-over-gsi;
|
||||||
|
qcom,arm-smmu;
|
||||||
|
qcom,smmu-fast-map;
|
||||||
|
qcom,use-64-bit-dma-mask;
|
||||||
|
qcom,ipa-endp-delay-wa-v2;
|
||||||
|
qcom,lan-rx-napi;
|
||||||
|
qcom,tx-napi;
|
||||||
|
qcom,tx-poll;
|
||||||
|
qcom,register-collection-on-crash;
|
||||||
|
qcom,testbus-collection-on-crash;
|
||||||
|
qcom,non-tn-collection-on-crash;
|
||||||
|
qcom,wan-use-skb-page;
|
||||||
|
qcom,rmnet-ctl-enable;
|
||||||
|
qcom,rmnet-ll-enable;
|
||||||
|
qcom,ipa-uc-holb-monitor;
|
||||||
|
qcom,ipa-holb-monitor-poll-period = <5>;
|
||||||
|
qcom,ipa-holb-monitor-max-cnt-wlan = <10>;
|
||||||
|
qcom,ipa-holb-monitor-max-cnt-usb = <10>;
|
||||||
|
qcom,ipa-holb-monitor-max-cnt-11ad = <10>;
|
||||||
|
qcom,tx-wrapper-cache-max-size = <400>;
|
||||||
|
qcom,ipa-gpi-event-rp-ddr;
|
||||||
|
qcom,ulso-supported;
|
||||||
|
qcom,ulso-ip-id-min-linux-val = <0>;
|
||||||
|
qcom,ulso-ip-id-max-linux-val = <0xffff>;
|
||||||
|
qcom,ulso-ip-id-min-windows-val = <0>;
|
||||||
|
qcom,ulso-ip-id-max-windows-val = <0x7fff>;
|
||||||
|
qcom,max_num_smmu_cb = <4>;
|
||||||
|
clock-names = "core_clk";
|
||||||
|
clocks = <&rpmhcc RPMH_IPA_CLK>;
|
||||||
|
qcom,throughput-threshold = <2000 4000 8000>;
|
||||||
|
qcom,scaling-exceptions = <>;
|
||||||
|
|
||||||
|
/* smp2p information */
|
||||||
|
qcom,smp2p_map_ipa_1_out {
|
||||||
|
compatible = "qcom,smp2p-map-ipa-1-out";
|
||||||
|
qcom,smem-states = <&smp2p_ipa_1_out 0>;
|
||||||
|
qcom,smem-state-names = "ipa-smp2p-out";
|
||||||
|
};
|
||||||
|
|
||||||
|
qcom,smp2p_map_ipa_1_in {
|
||||||
|
compatible = "qcom,smp2p-map-ipa-1-in";
|
||||||
|
interrupts-extended = <&smp2p_ipa_1_in 0 0>;
|
||||||
|
interrupt-names = "ipa-smp2p-in";
|
||||||
|
};
|
||||||
|
|
||||||
|
ipa_smmu_ap: ipa_smmu_ap {
|
||||||
|
compatible = "qcom,ipa-smmu-ap-cb";
|
||||||
|
iommus = <&apps_smmu 0x4A0 0x0>;
|
||||||
|
qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>;
|
||||||
|
qcom,additional-mapping =
|
||||||
|
/* modem tables in IMEM */
|
||||||
|
<0x146A8000 0x146A8000 0x2000>;
|
||||||
|
qcom,iommu-dma = "atomic";
|
||||||
|
dma-coherent;
|
||||||
|
qcom,ipa-q6-smem-size = <45056>;
|
||||||
|
};
|
||||||
|
|
||||||
|
ipa_smmu_wlan: ipa_smmu_wlan {
|
||||||
|
compatible = "qcom,ipa-smmu-wlan-cb";
|
||||||
|
iommus = <&apps_smmu 0x4A1 0x0>;
|
||||||
|
qcom,iommu-dma = "atomic";
|
||||||
|
dma-coherent;
|
||||||
|
};
|
||||||
|
|
||||||
|
ipa_smmu_uc: ipa_smmu_uc {
|
||||||
|
compatible = "qcom,ipa-smmu-uc-cb";
|
||||||
|
iommus = <&apps_smmu 0x4A2 0x0>;
|
||||||
|
qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>;
|
||||||
|
qcom,iommu-dma = "atomic";
|
||||||
|
dma-coherent;
|
||||||
|
};
|
||||||
|
|
||||||
|
ipa_smmu_11ad: ipa_smmu_11ad {
|
||||||
|
compatible = "qcom,ipa-smmu-11ad-cb";
|
||||||
|
iommus = <&apps_smmu 0x4A4 0x0>;
|
||||||
|
dma-coherent;
|
||||||
|
qcom,shared-cb;
|
||||||
|
qcom,iommu-group = <>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
128
qcom/data/ipa_v4.dtsi
Normal file
128
qcom/data/ipa_v4.dtsi
Normal file
@@ -0,0 +1,128 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
&soc {
|
||||||
|
|
||||||
|
qcom,msm_gsi {
|
||||||
|
compatible = "qcom,msm_gsi";
|
||||||
|
};
|
||||||
|
|
||||||
|
qcom,rmnet-ipa {
|
||||||
|
compatible = "qcom,rmnet-ipa3";
|
||||||
|
qcom,rmnet-ipa-ssr;
|
||||||
|
qcom,ipa-platform-type-msm;
|
||||||
|
qcom,ipa-advertise-sg-support;
|
||||||
|
qcom,ipa-napi-enable;
|
||||||
|
};
|
||||||
|
|
||||||
|
qcom,ipa_fws {
|
||||||
|
compatible = "qcom,pil-tz-generic";
|
||||||
|
qcom,pas-id = <0xf>;
|
||||||
|
qcom,firmware-name = "ipa_fws";
|
||||||
|
qcom,pil-force-shutdown;
|
||||||
|
memory-region = <&pil_ipa_fw_mem>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
ipa_hw: qcom,ipa@0x5800000 {
|
||||||
|
compatible = "qcom,ipa";
|
||||||
|
reg = <0x5800000 0x84000>,
|
||||||
|
<0x5804000 0x23000>;
|
||||||
|
reg-names = "ipa-base", "gsi-base";
|
||||||
|
pas-ids = <0xf>;
|
||||||
|
firmware-names = "ipa_fws";
|
||||||
|
memory-regions = <&pil_ipa_fw_mem>;
|
||||||
|
interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
interrupt-names = "ipa-irq", "gsi-irq";
|
||||||
|
qcom,ipa-hw-ver = <20>; /* IPA core version = IPAv4.11 */
|
||||||
|
qcom,ipa-hw-mode = <0>;
|
||||||
|
qcom,platform-type = <1>; /* MSM platform */
|
||||||
|
qcom,ee = <0>;
|
||||||
|
qcom,use-ipa-tethering-bridge;
|
||||||
|
qcom,modem-cfg-emb-pipe-flt;
|
||||||
|
qcom,ipa-wdi2;
|
||||||
|
qcom,ipa-wdi2_over_gsi;
|
||||||
|
qcom,arm-smmu;
|
||||||
|
qcom,use-64-bit-dma-mask;
|
||||||
|
qcom,lan-rx-napi;
|
||||||
|
qcom,wan-use-skb-page;
|
||||||
|
qcom,rmnet-ctl-enable;
|
||||||
|
qcom,ipa-endp-delay-wa;
|
||||||
|
qcom,tx-wrapper-cache-max-size = <400>;
|
||||||
|
clock-names = "core_clk";
|
||||||
|
clocks = <&rpmcc RPM_SMD_IPA_CLK>;
|
||||||
|
qcom,max_num_smmu_cb = <4>;
|
||||||
|
/* No vote */
|
||||||
|
qcom,no-vote =
|
||||||
|
<0 0 0 0 0 0>;
|
||||||
|
|
||||||
|
/* SVS2 */
|
||||||
|
qcom,svs2 =
|
||||||
|
<80000 465000 80000 68570 80000 30>;
|
||||||
|
|
||||||
|
/* SVS */
|
||||||
|
qcom,svs =
|
||||||
|
<80000 2000000 80000 267461 80000 109890>;
|
||||||
|
|
||||||
|
/* NOMINAL */
|
||||||
|
qcom,nominal =
|
||||||
|
<206000 4000000 206000 712961 206000 491520>;
|
||||||
|
|
||||||
|
/* TURBO */
|
||||||
|
qcom,turbo =
|
||||||
|
<206000 5598900 206000 1436481 206000 491520>;
|
||||||
|
|
||||||
|
qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL",
|
||||||
|
"TURBO";
|
||||||
|
|
||||||
|
qcom,throughput-threshold = <600 2500 5000>;
|
||||||
|
qcom,scaling-exceptions = <>;
|
||||||
|
|
||||||
|
/* smp2p information */
|
||||||
|
qcom,smp2p_map_ipa_1_out {
|
||||||
|
compatible = "qcom,smp2p-map-ipa-1-out";
|
||||||
|
qcom,smem-states = <&smp2p_ipa_1_out 0>;
|
||||||
|
qcom,smem-state-names = "ipa-smp2p-out";
|
||||||
|
};
|
||||||
|
|
||||||
|
qcom,smp2p_map_ipa_1_in {
|
||||||
|
compatible = "qcom,smp2p-map-ipa-1-in";
|
||||||
|
interrupts-extended = <&smp2p_ipa_1_in 0 0>;
|
||||||
|
interrupt-names = "ipa-smp2p-in";
|
||||||
|
};
|
||||||
|
|
||||||
|
ipa_smmu_ap: ipa_smmu_ap {
|
||||||
|
compatible = "qcom,ipa-smmu-ap-cb";
|
||||||
|
iommus = <&apps_smmu 0x04A0 0x0>;
|
||||||
|
qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>;
|
||||||
|
qcom,additional-mapping =
|
||||||
|
/* modem tables in IMEM */
|
||||||
|
<0x0C123000 0x0C123000 0x2000>;
|
||||||
|
qcom,iommu-dma = "fastmap";
|
||||||
|
qcom,ipa-q6-smem-size = <36864>;
|
||||||
|
};
|
||||||
|
|
||||||
|
ipa_smmu_wlan: ipa_smmu_wlan {
|
||||||
|
compatible = "qcom,ipa-smmu-wlan-cb";
|
||||||
|
iommus = <&apps_smmu 0x04A1 0x0>;
|
||||||
|
qcom,iommu-dma = "atomic";
|
||||||
|
};
|
||||||
|
|
||||||
|
ipa_smmu_uc: ipa_smmu_uc {
|
||||||
|
compatible = "qcom,ipa-smmu-uc-cb";
|
||||||
|
iommus = <&apps_smmu 0x04A2 0x0>;
|
||||||
|
qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>;
|
||||||
|
qcom,iommu-dma = "atomic";
|
||||||
|
};
|
||||||
|
|
||||||
|
ipa_smmu_11ad: ipa_smmu_11ad {
|
||||||
|
compatible = "qcom,ipa-smmu-11ad-cb";
|
||||||
|
iommus = <&apps_smmu 0x04A3 0x0>;
|
||||||
|
qcom,shared-cb;
|
||||||
|
qcom,iommu-group = <>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
21
qcom/data/kalama-ipa.dts
Normal file
21
qcom/data/kalama-ipa.dts
Normal file
@@ -0,0 +1,21 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
|
#include <dt-bindings/soc/qcom,ipcc.h>
|
||||||
|
#include <dt-bindings/interconnect/qcom,kalama.h>
|
||||||
|
#include <dt-bindings/clock/qcom,gcc-kalama.h>
|
||||||
|
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||||
|
#include "kalama-ipa.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Qualcomm Technologies, Inc. Kalama SOCs";
|
||||||
|
compatible = "qcom,kalama";
|
||||||
|
qcom,msm-id = <519 0x10000>, <519 0x20000>, <600 0x20000>;
|
||||||
|
qcom,board-id = <0 0>;
|
||||||
|
};
|
||||||
42
qcom/data/kalama-ipa.dtsi
Normal file
42
qcom/data/kalama-ipa.dtsi
Normal file
@@ -0,0 +1,42 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "ipa.dtsi"
|
||||||
|
|
||||||
|
&ipa_hw {
|
||||||
|
qcom,interconnect,num-cases = <5>;
|
||||||
|
qcom,interconnect,num-paths = <3>;
|
||||||
|
interconnects = <&aggre2_noc MASTER_IPA &gem_noc SLAVE_LLCC>,
|
||||||
|
<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
|
||||||
|
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>;
|
||||||
|
interconnect-names = "ipa_to_llcc", "llcc_to_ebi1", "appss_to_ipa";
|
||||||
|
|
||||||
|
/* ipa and gsi interrupts */
|
||||||
|
interrupts =
|
||||||
|
<0 654 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<0 432 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
|
||||||
|
/* No vote */
|
||||||
|
qcom,no-vote =
|
||||||
|
<0 0 0 0 0 0>;
|
||||||
|
|
||||||
|
/* SVS2 */
|
||||||
|
qcom,svs2 =
|
||||||
|
<0 0 0 1300000 0 76800>;
|
||||||
|
|
||||||
|
/* SVS */
|
||||||
|
qcom,svs =
|
||||||
|
<1200000 0 1200000 2800000 0 150000>;
|
||||||
|
|
||||||
|
/* NOMINAL */
|
||||||
|
qcom,nominal =
|
||||||
|
<2400000 0 2400000 5500000 0 400000>;
|
||||||
|
|
||||||
|
/* TURBO */
|
||||||
|
qcom,turbo =
|
||||||
|
<3600000 0 3600000 5500000 0 400000>;
|
||||||
|
qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL",
|
||||||
|
"TURBO";
|
||||||
|
};
|
||||||
21
qcom/data/kera-ipa.dts
Normal file
21
qcom/data/kera-ipa.dts
Normal file
@@ -0,0 +1,21 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
|
#include <dt-bindings/soc/qcom,ipcc.h>
|
||||||
|
#include <dt-bindings/interconnect/qcom,kera.h>
|
||||||
|
#include <dt-bindings/clock/qcom,gcc-kera.h>
|
||||||
|
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||||
|
#include "kera-ipa.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Qualcomm Technologies, Inc. Kera SoC";
|
||||||
|
compatible = "qcom,kera";
|
||||||
|
qcom,board-id = <0 0>;
|
||||||
|
qcom,msm-id = <659 0x10000>, <686 0x10000>;
|
||||||
|
};
|
||||||
51
qcom/data/kera-ipa.dtsi
Normal file
51
qcom/data/kera-ipa.dtsi
Normal file
@@ -0,0 +1,51 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "ipa.dtsi"
|
||||||
|
|
||||||
|
&ipa_hw {
|
||||||
|
qcom,interconnect,num-cases = <5>;
|
||||||
|
qcom,interconnect,num-paths = <3>;
|
||||||
|
|
||||||
|
interrupts =
|
||||||
|
<0 654 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<0 432 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
|
||||||
|
/* Low Latency pipe alloc factor */
|
||||||
|
qcom,ipa-gen-rx-ll-pool-sz-factor = <1>;
|
||||||
|
|
||||||
|
qcom,wan-rx-ring-size = <128>;
|
||||||
|
qcom,ipa-gen-rx-cmn-page-pool-sz-factor = <8>;
|
||||||
|
qcom,ipa-gen-rx-cmn-temp-pool-sz-factor = <3>;
|
||||||
|
|
||||||
|
interconnects = <&aggre2_noc MASTER_IPA &gem_noc SLAVE_LLCC>,
|
||||||
|
<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
|
||||||
|
<&gem_noc MASTER_APPSS_PROC &cnoc_main SLAVE_IPA_CFG>;
|
||||||
|
interconnect-names = "ipa_to_llcc", "llcc_to_ebi1", "appss_to_ipa";
|
||||||
|
|
||||||
|
qcom,no-vote =
|
||||||
|
<0 0 0 0 0 0>;
|
||||||
|
|
||||||
|
qcom,svs2 =
|
||||||
|
<0 0 0 1300000 0 76800>;
|
||||||
|
|
||||||
|
qcom,svs =
|
||||||
|
<1200000 0 1200000 2800000 0 150000>;
|
||||||
|
|
||||||
|
qcom,nominal =
|
||||||
|
<2400000 0 2400000 5500000 0 400000>;
|
||||||
|
|
||||||
|
qcom,turbo =
|
||||||
|
<3600000 0 3600000 5500000 0 400000>;
|
||||||
|
|
||||||
|
qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL",
|
||||||
|
"TURBO";
|
||||||
|
};
|
||||||
|
|
||||||
|
&ipa_smmu_ap {
|
||||||
|
qcom,additional-mapping =
|
||||||
|
/* modem tables in IMEM */
|
||||||
|
<0x14683000 0x14683000 0x2000>;
|
||||||
|
};
|
||||||
19
qcom/data/kera-smem-mailbox.dts
Normal file
19
qcom/data/kera-smem-mailbox.dts
Normal file
@@ -0,0 +1,19 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
|
#include <dt-bindings/soc/qcom,ipcc.h>
|
||||||
|
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||||
|
#include "smem-mailbox.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Qualcomm Technologies, Inc. Kera SoC";
|
||||||
|
compatible = "qcom,kera";
|
||||||
|
qcom,msm-id = <659 0x10000>;
|
||||||
|
qcom,board-id = <0 0>;
|
||||||
|
};
|
||||||
21
qcom/data/monaco-ipa.dts
Normal file
21
qcom/data/monaco-ipa.dts
Normal file
@@ -0,0 +1,21 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
|
#include <dt-bindings/soc/qcom,ipcc.h>
|
||||||
|
#include <dt-bindings/interconnect/qcom,monaco.h>
|
||||||
|
#include <dt-bindings/clock/qcom,gcc-monaco.h>
|
||||||
|
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||||
|
#include "monaco-ipa.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Qualcomm Technologies, Inc. Monaco";
|
||||||
|
compatible = "qcom,monaco";
|
||||||
|
qcom,msm-id = <486 0x10000>;
|
||||||
|
qcom,board-id = <0 0>;
|
||||||
|
};
|
||||||
72
qcom/data/monaco-ipa.dtsi
Normal file
72
qcom/data/monaco-ipa.dtsi
Normal file
@@ -0,0 +1,72 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "ipa_v4.dtsi"
|
||||||
|
|
||||||
|
&ipa_hw {
|
||||||
|
reg = <0x5800000 0x34000>,
|
||||||
|
<0x5804000 0x28000>;
|
||||||
|
qcom,ipa-hw-ver = <16>; /* IPA core version = IPAv4.2 */
|
||||||
|
qcom,use-ipa-pm;
|
||||||
|
qcom,max_num_smmu_cb = <3>;
|
||||||
|
qcom,ipa-fltrt-not-hashable;
|
||||||
|
qcom,skip-ieob-mask-wa;
|
||||||
|
/delete-property/ qcom,use-64-bit-dma-mask;
|
||||||
|
/delete-property/ qcom,lan-rx-napi;
|
||||||
|
/delete-property/ qcom,wan-use-skb-page;
|
||||||
|
/delete-property/ qcom,rmnet-ctl-enable;
|
||||||
|
/delete-property/ qcom,tx-wrapper-cache-max-size;
|
||||||
|
|
||||||
|
qcom,interconnect,num-cases = <5>;
|
||||||
|
qcom,interconnect,num-paths = <4>;
|
||||||
|
interconnects = <&system_noc MASTER_IPA &system_noc SNOC_BIMC_SLV>,
|
||||||
|
<&bimc SNOC_BIMC_MAS &bimc SLAVE_EBI_CH0>,
|
||||||
|
<&system_noc MASTER_IPA &system_noc SLAVE_OCIMEM>,
|
||||||
|
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_IPA_CFG>;
|
||||||
|
interconnect-names = "ipa_to_llcc", "llcc_to_ebi1", "ipa_to_imem", "appss_to_ipa";
|
||||||
|
|
||||||
|
/* No vote */
|
||||||
|
qcom,no-vote =
|
||||||
|
<0 0 0 0 0 0 0 0>;
|
||||||
|
/* SVS2 */
|
||||||
|
qcom,svs2 =
|
||||||
|
<80000 590000 80000 2160000 80000 560000 80000 120000>;
|
||||||
|
|
||||||
|
/* SVS */
|
||||||
|
qcom,svs =
|
||||||
|
<80000 800000 80000 5414000 80000 920000 80000 180000>;
|
||||||
|
|
||||||
|
/* NOMINAL */
|
||||||
|
qcom,nominal =
|
||||||
|
<206000 1500000 206000 7200000 206000 1560000 206000 380000>;
|
||||||
|
|
||||||
|
/* TURBO */
|
||||||
|
qcom,turbo =
|
||||||
|
<206000 1800000 206000 8500000 206000 1880000 206000 520000>;
|
||||||
|
|
||||||
|
qcom,bus-vector-names =
|
||||||
|
"MIN", "SVS2", "SVS", "NOMINAL", "TURBO";
|
||||||
|
qcom,throughput-threshold = <310 600 1000>;
|
||||||
|
qcom,scaling-exceptions = <>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&ipa_smmu_ap {
|
||||||
|
iommus = <&apps_smmu 0x0140 0x0>;
|
||||||
|
qcom,iommu-dma-addr-pool = <0x10000000 0x30000000>;
|
||||||
|
qcom,additional-mapping = <0x0c123000 0x0c123000 0x2000>;
|
||||||
|
qcom,iommu-geometry = <0 0xB0000000>;
|
||||||
|
/delete-property/ qcom,ipa-q6-smem-size;
|
||||||
|
};
|
||||||
|
|
||||||
|
&ipa_smmu_wlan {
|
||||||
|
iommus = <&apps_smmu 0x141 0x0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&ipa_smmu_uc {
|
||||||
|
iommus = <&apps_smmu 0x0142 0x0>;
|
||||||
|
qcom,iommu-dma-addr-pool = <0x40400000 0x1fc00000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
/delete-node/ &ipa_smmu_11ad;
|
||||||
21
qcom/data/parrot-ipa.dts
Normal file
21
qcom/data/parrot-ipa.dts
Normal file
@@ -0,0 +1,21 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
|
#include <dt-bindings/soc/qcom,ipcc.h>
|
||||||
|
#include <dt-bindings/interconnect/qcom,parrot.h>
|
||||||
|
#include <dt-bindings/clock/qcom,gcc-parrot.h>
|
||||||
|
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||||
|
#include "parrot-ipa.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Qualcomm Technologies, Inc. Parrot SoC";
|
||||||
|
compatible = "qcom,parrot";
|
||||||
|
qcom,msm-id = <537 0x10000>, <613 0x10000>, <633 0x10000>, <663 0x10000>;
|
||||||
|
qcom,board-id = <0 0>;
|
||||||
|
};
|
||||||
61
qcom/data/parrot-ipa.dtsi
Normal file
61
qcom/data/parrot-ipa.dtsi
Normal file
@@ -0,0 +1,61 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "ipa.dtsi"
|
||||||
|
|
||||||
|
&ipa_hw {
|
||||||
|
interrupts =
|
||||||
|
<0 654 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<0 432 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
qcom,ipa-hw-ver = <23>; /* IPA core version = IPAv5.2 */
|
||||||
|
qcom,ipa-ulso-wa;
|
||||||
|
qcom,gfp-no-retry;
|
||||||
|
/delete-property/ qcom,rmnet-ll-enable;
|
||||||
|
/delete-property/ qcom,ipa-uc-holb-monitor;
|
||||||
|
qcom,ipa-gen-rx-cmn-page-pool-sz-factor = <2>;
|
||||||
|
qcom,ipa-gen-rx-cmn-temp-pool-sz-factor = <1>;
|
||||||
|
qcom,interconnect,num-cases = <5>;
|
||||||
|
qcom,interconnect,num-paths = <3>;
|
||||||
|
interconnects = <&aggre2_noc MASTER_IPA &gem_noc SLAVE_LLCC>,
|
||||||
|
<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
|
||||||
|
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_IPA_CFG>;
|
||||||
|
interconnect-names = "ipa_to_llcc", "llcc_to_ebi1", "appss_to_ipa";
|
||||||
|
|
||||||
|
/* No vote */
|
||||||
|
qcom,no-vote =
|
||||||
|
<0 0 0 0 0 0>;
|
||||||
|
|
||||||
|
/* SVS2 */
|
||||||
|
qcom,svs2 =
|
||||||
|
<0 0 0 1900000 0 76800>;
|
||||||
|
/* SVS */
|
||||||
|
qcom,svs =
|
||||||
|
<1200000 0 1200000 2800000 0 150000>;
|
||||||
|
|
||||||
|
/* NOMINAL */
|
||||||
|
qcom,nominal =
|
||||||
|
<2400000 0 2400000 5500000 0 400000>;
|
||||||
|
|
||||||
|
/* TURBO */
|
||||||
|
qcom,turbo =
|
||||||
|
<3600000 0 3600000 5500000 0 400000>;
|
||||||
|
|
||||||
|
qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL",
|
||||||
|
"TURBO";
|
||||||
|
qcom,throughput-threshold = <600 2500 5000>;
|
||||||
|
qcom,scaling-exceptions = <>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&ipa_smmu_wlan {
|
||||||
|
/delete-property/ dma-coherent;
|
||||||
|
};
|
||||||
|
|
||||||
|
&ipa_smmu_uc {
|
||||||
|
/delete-property/ dma-coherent;
|
||||||
|
};
|
||||||
|
|
||||||
|
&ipa_smmu_11ad {
|
||||||
|
iommus = <&apps_smmu 0x4A3 0x0>;
|
||||||
|
};
|
||||||
21
qcom/data/pineapple-ipa.dts
Normal file
21
qcom/data/pineapple-ipa.dts
Normal file
@@ -0,0 +1,21 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
|
#include <dt-bindings/soc/qcom,ipcc.h>
|
||||||
|
#include <dt-bindings/interconnect/qcom,pineapple.h>
|
||||||
|
#include <dt-bindings/clock/qcom,gcc-pineapple.h>
|
||||||
|
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||||
|
#include "pineapple-ipa.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Qualcomm Technologies, Inc. Pineapple SOC";
|
||||||
|
compatible = "qcom,pineapple";
|
||||||
|
qcom,msm-id = <557 0x10000>, <557 0x20000>;
|
||||||
|
qcom,board-id = <0 0>;
|
||||||
|
};
|
||||||
53
qcom/data/pineapple-ipa.dtsi
Normal file
53
qcom/data/pineapple-ipa.dtsi
Normal file
@@ -0,0 +1,53 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "ipa.dtsi"
|
||||||
|
|
||||||
|
&ipa_hw {
|
||||||
|
qcom,interconnect,num-cases = <5>;
|
||||||
|
qcom,interconnect,num-paths = <3>;
|
||||||
|
qcom,ipa-wdi-opt-dpath;
|
||||||
|
interconnects = <&aggre2_noc MASTER_IPA &gem_noc SLAVE_LLCC>,
|
||||||
|
<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
|
||||||
|
<&gem_noc MASTER_APPSS_PROC &cnoc_main SLAVE_IPA_CFG>;
|
||||||
|
interconnect-names = "ipa_to_llcc", "llcc_to_ebi1", "appss_to_ipa";
|
||||||
|
|
||||||
|
/* ipa and gsi interrupts */
|
||||||
|
interrupts =
|
||||||
|
<0 654 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<0 432 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
|
||||||
|
/* No vote */
|
||||||
|
qcom,no-vote =
|
||||||
|
<0 0 0 0 0 0>;
|
||||||
|
|
||||||
|
/* SVS2 */
|
||||||
|
qcom,svs2 =
|
||||||
|
<0 0 0 1300000 0 76800>;
|
||||||
|
|
||||||
|
/* SVS */
|
||||||
|
qcom,svs =
|
||||||
|
<1200000 0 1200000 2800000 0 150000>;
|
||||||
|
|
||||||
|
/* NOMINAL */
|
||||||
|
qcom,nominal =
|
||||||
|
<2400000 0 2400000 5500000 0 400000>;
|
||||||
|
|
||||||
|
/* TURBO */
|
||||||
|
qcom,turbo =
|
||||||
|
<3600000 0 3600000 5500000 0 400000>;
|
||||||
|
|
||||||
|
qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL",
|
||||||
|
"TURBO";
|
||||||
|
|
||||||
|
/* Low Latency pipe alloc factor */
|
||||||
|
qcom,ipa-gen-rx-ll-pool-sz-factor = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&ipa_smmu_ap {
|
||||||
|
qcom,additional-mapping =
|
||||||
|
/* modem tables in IMEM */
|
||||||
|
<0x14683000 0x14683000 0x2000>;
|
||||||
|
};
|
||||||
20
qcom/data/ravelin-ipa.dts
Normal file
20
qcom/data/ravelin-ipa.dts
Normal file
@@ -0,0 +1,20 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
|
#include <dt-bindings/soc/qcom,ipcc.h>
|
||||||
|
#include <dt-bindings/interconnect/qcom,ravelin.h>
|
||||||
|
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||||
|
#include "ravelin-ipa.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Qualcomm Technologies, Inc. Ravelin";
|
||||||
|
compatible = "qcom,ravelin";
|
||||||
|
qcom,msm-id = <568 0x10000>, <581 0x10000>, <653 0x10000>;
|
||||||
|
qcom,board-id = <0 0>, <34 0x601>, <0x1000B 0x600>;
|
||||||
|
};
|
||||||
61
qcom/data/ravelin-ipa.dtsi
Normal file
61
qcom/data/ravelin-ipa.dtsi
Normal file
@@ -0,0 +1,61 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "ipa.dtsi"
|
||||||
|
|
||||||
|
&ipa_hw {
|
||||||
|
interrupts =
|
||||||
|
<0 654 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<0 432 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
qcom,ipa-hw-ver = <23>; /* IPA core version = IPAv5.2 */
|
||||||
|
qcom,ipa-ulso-wa;
|
||||||
|
qcom,gfp-no-retry;
|
||||||
|
/delete-property/ qcom,rmnet-ll-enable;
|
||||||
|
/delete-property/ qcom,ipa-uc-holb-monitor;
|
||||||
|
qcom,ipa-gen-rx-cmn-page-pool-sz-factor = <2>;
|
||||||
|
qcom,ipa-gen-rx-cmn-temp-pool-sz-factor = <1>;
|
||||||
|
qcom,interconnect,num-cases = <5>;
|
||||||
|
qcom,interconnect,num-paths = <3>;
|
||||||
|
interconnects = <&aggre2_noc MASTER_IPA &gem_noc SLAVE_LLCC>,
|
||||||
|
<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
|
||||||
|
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_IPA_CFG>;
|
||||||
|
interconnect-names = "ipa_to_llcc", "llcc_to_ebi1", "appss_to_ipa";
|
||||||
|
|
||||||
|
/* No vote */
|
||||||
|
qcom,no-vote =
|
||||||
|
<0 0 0 0 0 0>;
|
||||||
|
|
||||||
|
/* SVS2 */
|
||||||
|
qcom,svs2 =
|
||||||
|
<0 0 0 1900000 0 76800>;
|
||||||
|
/* SVS */
|
||||||
|
qcom,svs =
|
||||||
|
<1200000 0 1200000 2800000 0 150000>;
|
||||||
|
|
||||||
|
/* NOMINAL */
|
||||||
|
qcom,nominal =
|
||||||
|
<2400000 0 2400000 5500000 0 400000>;
|
||||||
|
|
||||||
|
/* TURBO */
|
||||||
|
qcom,turbo =
|
||||||
|
<3600000 0 3600000 5500000 0 400000>;
|
||||||
|
|
||||||
|
qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL",
|
||||||
|
"TURBO";
|
||||||
|
qcom,throughput-threshold = <600 2500 5000>;
|
||||||
|
qcom,scaling-exceptions = <>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&ipa_smmu_wlan {
|
||||||
|
/delete-property/ dma-coherent;
|
||||||
|
};
|
||||||
|
|
||||||
|
&ipa_smmu_uc {
|
||||||
|
/delete-property/ dma-coherent;
|
||||||
|
};
|
||||||
|
|
||||||
|
&ipa_smmu_11ad {
|
||||||
|
iommus = <&apps_smmu 0x4A3 0x0>;
|
||||||
|
};
|
||||||
20
qcom/data/smem-mailbox.dts
Normal file
20
qcom/data/smem-mailbox.dts
Normal file
@@ -0,0 +1,20 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
|
#include <dt-bindings/soc/qcom,ipcc.h>
|
||||||
|
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||||
|
#include "smem-mailbox.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Qualcomm Technologies, Inc. Sun SOC";
|
||||||
|
compatible = "qcom,sun";
|
||||||
|
qcom,msm-id = <618 0x10000>, <618 0x20000>,
|
||||||
|
<0x100026a 0x10000>, <0x100026a 0x20000>;
|
||||||
|
qcom,board-id = <0 0>;
|
||||||
|
};
|
||||||
22
qcom/data/smem-mailbox.dtsi
Normal file
22
qcom/data/smem-mailbox.dtsi
Normal file
@@ -0,0 +1,22 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
&soc {
|
||||||
|
smem_mailbox {
|
||||||
|
compatible = "qcom,smem_mailbox";
|
||||||
|
|
||||||
|
qcom,smem-states = <&smp2p_smem_mailbox_1_out 0>;
|
||||||
|
qcom,smem-state-names = "smem-mailbox-smp2p-out";
|
||||||
|
|
||||||
|
interrupts-extended = <&smp2p_smem_mailbox_1_in 0 0>,
|
||||||
|
<&smp2p_smem_mailbox_1_in 1 0>,
|
||||||
|
<&smp2p_smem_mailbox_1_in 2 0>,
|
||||||
|
<&smp2p_smem_mailbox_1_in 3 0>;
|
||||||
|
interrupt-names = "smem-mailbox-smp2p-1-in",
|
||||||
|
"smem-mailbox-smp2p-2-in",
|
||||||
|
"smem-mailbox-smp2p-3-in",
|
||||||
|
"smem-mailbox-smp2p-4-in";
|
||||||
|
};
|
||||||
|
};
|
||||||
22
qcom/data/sun-ipa.dts
Normal file
22
qcom/data/sun-ipa.dts
Normal file
@@ -0,0 +1,22 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
|
#include <dt-bindings/soc/qcom,ipcc.h>
|
||||||
|
#include <dt-bindings/interconnect/qcom,sun.h>
|
||||||
|
#include <dt-bindings/clock/qcom,gcc-sun.h>
|
||||||
|
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||||
|
#include "sun-ipa.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Qualcomm Technologies, Inc. Sun SOC";
|
||||||
|
compatible = "qcom,sun";
|
||||||
|
qcom,msm-id = <618 0x10000>, <618 0x20000>,
|
||||||
|
<0x100026a 0x10000>, <0x100026a 0x20000>;
|
||||||
|
qcom,board-id = <0 0>;
|
||||||
|
};
|
||||||
54
qcom/data/sun-ipa.dtsi
Normal file
54
qcom/data/sun-ipa.dtsi
Normal file
@@ -0,0 +1,54 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "ipa.dtsi"
|
||||||
|
|
||||||
|
&ipa_hw {
|
||||||
|
qcom,interconnect,num-cases = <5>;
|
||||||
|
qcom,interconnect,num-paths = <3>;
|
||||||
|
qcom,ipa-wdi-opt-dpath;
|
||||||
|
interconnects = <&aggre2_noc MASTER_IPA &gem_noc SLAVE_LLCC>,
|
||||||
|
<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
|
||||||
|
<&gem_noc MASTER_APPSS_PROC &cnoc_main SLAVE_IPA_CFG>;
|
||||||
|
interconnect-names = "ipa_to_llcc", "llcc_to_ebi1", "appss_to_ipa";
|
||||||
|
|
||||||
|
/* ipa and gsi interrupts */
|
||||||
|
interrupts =
|
||||||
|
<0 655 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<0 432 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
|
||||||
|
/* No vote */
|
||||||
|
qcom,no-vote =
|
||||||
|
<0 0 0 0 0 0>;
|
||||||
|
|
||||||
|
/* SVS2 */
|
||||||
|
qcom,svs2 =
|
||||||
|
<0 0 0 1300000 0 76800>;
|
||||||
|
|
||||||
|
/* SVS */
|
||||||
|
qcom,svs =
|
||||||
|
<1200000 0 1200000 2800000 0 150000>;
|
||||||
|
|
||||||
|
/* NOMINAL */
|
||||||
|
qcom,nominal =
|
||||||
|
<2400000 0 2400000 5500000 0 400000>;
|
||||||
|
|
||||||
|
/* TURBO */
|
||||||
|
qcom,turbo =
|
||||||
|
<3600000 0 3600000 5500000 0 400000>;
|
||||||
|
|
||||||
|
qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL",
|
||||||
|
"TURBO";
|
||||||
|
|
||||||
|
/* Low Latency pipe alloc factor */
|
||||||
|
qcom,ipa-gen-rx-ll-pool-sz-factor = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&ipa_smmu_ap {
|
||||||
|
qcom,additional-mapping =
|
||||||
|
/* modem tables in IMEM */
|
||||||
|
<0x14683000 0x14683000 0x2000>;
|
||||||
|
qcom,ipa-q6-smem-size = <55296>;
|
||||||
|
};
|
||||||
22
qcom/data/tuna-ipa.dts
Normal file
22
qcom/data/tuna-ipa.dts
Normal file
@@ -0,0 +1,22 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
|
#include <dt-bindings/soc/qcom,ipcc.h>
|
||||||
|
#include <dt-bindings/interconnect/qcom,tuna.h>
|
||||||
|
#include <dt-bindings/clock/qcom,gcc-tuna.h>
|
||||||
|
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||||
|
#include "tuna-ipa.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Qualcomm Technologies, Inc. Tuna SOC";
|
||||||
|
compatible = "qcom,tuna";
|
||||||
|
qcom,msm-id = <655 0x10000>, <681 0x10000>;
|
||||||
|
qcom,board-id = <0 0>;
|
||||||
|
};
|
||||||
|
|
||||||
48
qcom/data/tuna-ipa.dtsi
Normal file
48
qcom/data/tuna-ipa.dtsi
Normal file
@@ -0,0 +1,48 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "ipa.dtsi"
|
||||||
|
|
||||||
|
&ipa_hw {
|
||||||
|
qcom,interconnect,num-cases = <5>;
|
||||||
|
qcom,interconnect,num-paths = <3>;
|
||||||
|
|
||||||
|
interrupts =
|
||||||
|
<0 654 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<0 432 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
|
||||||
|
/* Low Latency pipe alloc factor */
|
||||||
|
qcom,ipa-gen-rx-ll-pool-sz-factor = <1>;
|
||||||
|
|
||||||
|
interconnects = <&aggre2_noc MASTER_IPA &gem_noc SLAVE_LLCC>,
|
||||||
|
<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
|
||||||
|
<&gem_noc MASTER_APPSS_PROC &cnoc_main SLAVE_IPA_CFG>;
|
||||||
|
interconnect-names = "ipa_to_llcc", "llcc_to_ebi1", "appss_to_ipa";
|
||||||
|
|
||||||
|
qcom,no-vote =
|
||||||
|
<0 0 0 0 0 0>;
|
||||||
|
|
||||||
|
qcom,svs2 =
|
||||||
|
<0 0 0 1300000 0 76800>;
|
||||||
|
|
||||||
|
qcom,svs =
|
||||||
|
<1200000 0 1200000 2800000 0 150000>;
|
||||||
|
|
||||||
|
qcom,nominal =
|
||||||
|
<2400000 0 2400000 5500000 0 400000>;
|
||||||
|
|
||||||
|
qcom,turbo =
|
||||||
|
<3600000 0 3600000 5500000 0 400000>;
|
||||||
|
|
||||||
|
qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL",
|
||||||
|
"TURBO";
|
||||||
|
};
|
||||||
|
|
||||||
|
&ipa_smmu_ap {
|
||||||
|
qcom,additional-mapping =
|
||||||
|
/* modem tables in IMEM */
|
||||||
|
<0x14683000 0x14683000 0x2000>;
|
||||||
|
};
|
||||||
|
|
||||||
19
qcom/data/tuna-smem-mailbox.dts
Normal file
19
qcom/data/tuna-smem-mailbox.dts
Normal file
@@ -0,0 +1,19 @@
|
|||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
|
#include <dt-bindings/soc/qcom,ipcc.h>
|
||||||
|
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||||
|
#include "smem-mailbox.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Qualcomm Technologies, Inc. Tuna SoC";
|
||||||
|
compatible = "qcom,tuna";
|
||||||
|
qcom,msm-id = <655 0x10000>;
|
||||||
|
qcom,board-id = <0 0>;
|
||||||
|
};
|
||||||
Reference in New Issue
Block a user