From 5a99ac82db7ebe6caf0a5de942f1ab2d9c99b081 Mon Sep 17 00:00:00 2001 From: Khageswararao Rao B Date: Wed, 21 Feb 2024 20:21:10 +0530 Subject: [PATCH] nfc: dts: Add device tree entries for sun target Add initial device tree entries for sun target Change-Id: Ieeb7eb1f6e300b1453cda59f75f50b9de2b58c6c --- Kbuild | 18 +++++++++++ Makefile | 12 +++++++ nxp/sun-nfc-cdp.dts | 17 ++++++++++ nxp/sun-nfc-common.dtsi | 26 +++++++++++++++ nxp/sun-nfc-mtp.dts | 17 ++++++++++ nxp/sun-nfc-pinctrl.dtsi | 66 ++++++++++++++++++++++++++++++++++++++ nxp/sun-nfc.dts | 15 +++++++++ st/sun-nfc-atp.dts | 17 ++++++++++ st/sun-nfc-cdp.dts | 16 +++++++++ st/sun-nfc-common.dtsi | 29 +++++++++++++++++ st/sun-nfc-mtp.dts | 16 +++++++++ st/sun-nfc-pinctrl.dtsi | 66 ++++++++++++++++++++++++++++++++++++++ st/sun-nfc-qrd-sku1-v8.dts | 16 +++++++++ st/sun-nfc-qrd-sku1.dts | 16 +++++++++ st/sun-nfc-qrd-sku2-v8.dts | 16 +++++++++ st/sun-nfc-rcm.dts | 16 +++++++++ st/sun-nfc.dts | 16 +++++++++ 17 files changed, 395 insertions(+) create mode 100644 Kbuild create mode 100644 Makefile create mode 100644 nxp/sun-nfc-cdp.dts create mode 100644 nxp/sun-nfc-common.dtsi create mode 100644 nxp/sun-nfc-mtp.dts create mode 100644 nxp/sun-nfc-pinctrl.dtsi create mode 100644 nxp/sun-nfc.dts create mode 100644 st/sun-nfc-atp.dts create mode 100644 st/sun-nfc-cdp.dts create mode 100644 st/sun-nfc-common.dtsi create mode 100644 st/sun-nfc-mtp.dts create mode 100644 st/sun-nfc-pinctrl.dtsi create mode 100644 st/sun-nfc-qrd-sku1-v8.dts create mode 100644 st/sun-nfc-qrd-sku1.dts create mode 100644 st/sun-nfc-qrd-sku2-v8.dts create mode 100644 st/sun-nfc-rcm.dts create mode 100644 st/sun-nfc.dts diff --git a/Kbuild b/Kbuild new file mode 100644 index 00000000..30c9ad8e --- /dev/null +++ b/Kbuild @@ -0,0 +1,18 @@ +ifeq ($(CONFIG_ARCH_SUN),y) +dtbo-y += nxp/sun-nfc.dtbo \ + nxp/sun-nfc-cdp.dtbo \ + nxp/sun-nfc-mtp.dtbo \ + +dtbo-y += st/sun-nfc.dtbo \ + st/sun-nfc-mtp.dtbo \ + st/sun-nfc-cdp.dtbo \ + st/sun-nfc-qrd-sku1.dtbo \ + st/sun-nfc-qrd-sku1-v8.dtbo \ + st/sun-nfc-qrd-sku2-v8.dtbo \ + st/sun-nfc-atp.dtbo \ + st/sun-nfc-rcm.dtbo +endif + +always-y := $(dtb-y) $(dtbo-y) +subdir-y := $(dts-dirs) +clean-files := *.dtb *.dtbo diff --git a/Makefile b/Makefile new file mode 100644 index 00000000..f2d100f2 --- /dev/null +++ b/Makefile @@ -0,0 +1,12 @@ +KBUILD_OPTIONS += KBUILD_EXTMOD_DTS=. + +all: dtbs + +%: + $(MAKE) -C $(KERNEL_SRC) M=$(M) $@ $(KBUILD_OPTIONS) + +modules_install: + $(MAKE) M=$(M) -C $(KERNEL_SRC) modules_install + +clean: + $(MAKE) -C $(KERNEL_SRC) M=$(M) clean \ No newline at end of file diff --git a/nxp/sun-nfc-cdp.dts b/nxp/sun-nfc-cdp.dts new file mode 100644 index 00000000..3a93ef7f --- /dev/null +++ b/nxp/sun-nfc-cdp.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-nfc-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun CDP"; + compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp", "qcom,cdp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x40001 0>; +}; diff --git a/nxp/sun-nfc-common.dtsi b/nxp/sun-nfc-common.dtsi new file mode 100644 index 00000000..2ba69808 --- /dev/null +++ b/nxp/sun-nfc-common.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&qupv3_se0_i2c { + status = "ok"; + qcom,clk-freq-out = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + nq@28 { + compatible = "qcom,sn-nci"; + reg = <0x28>; + qcom,sn-irq = <&tlmm 75 0x00>; + qcom,sn-ven = <&tlmm 34 0x00>; + qcom,sn-clkreq = <&tlmm 35 0x00>; + qcom,sn-szone = "enable"; + interrupt-parent = <&tlmm>; + interrupts = <75 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + }; +}; diff --git a/nxp/sun-nfc-mtp.dts b/nxp/sun-nfc-mtp.dts new file mode 100644 index 00000000..2af0da47 --- /dev/null +++ b/nxp/sun-nfc-mtp.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-nfc-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun MTP"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x30008 0>; +}; diff --git a/nxp/sun-nfc-pinctrl.dtsi b/nxp/sun-nfc-pinctrl.dtsi new file mode 100644 index 00000000..9f17d1c3 --- /dev/null +++ b/nxp/sun-nfc-pinctrl.dtsi @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&tlmm { + nfc { + nfc_int_active: nfc_int_active { + /* active state */ + mux { + /* NFC Read Interrupt */ + pins = "gpio75"; + function = "gpio"; + }; + + config { + pins = "gpio75"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; + }; + }; + + nfc_int_suspend: nfc_int_suspend { + /* sleep state */ + mux { + /* NFC Read Interrupt */ + pins = "gpio75"; + function = "gpio"; + }; + + config { + pins = "gpio75"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; + }; + }; + + nfc_enable_active: nfc_enable_active { + mux { + /* Enable, and Clock request gpios */ + pins = "gpio34", "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio34", "gpio35"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + + nfc_enable_suspend: nfc_enable_suspend { + mux { + pins = "gpio34", "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio34", "gpio35"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; //nfc +}; //tlmm diff --git a/nxp/sun-nfc.dts b/nxp/sun-nfc.dts new file mode 100644 index 00000000..5daec909 --- /dev/null +++ b/nxp/sun-nfc.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-nfc-pinctrl.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Sun SoC"; + compatible = "qcom,sun"; + qcom,board-id = <0 0>; +}; diff --git a/st/sun-nfc-atp.dts b/st/sun-nfc-atp.dts new file mode 100644 index 00000000..3226e9ca --- /dev/null +++ b/st/sun-nfc-atp.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-nfc-common.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Sun ATP"; + compatible = "qcom,sun-atp", "qcom,sun", "qcom,sunp-atp", "qcom,sunp", + "qcom,atp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,board-id = <0x10021 0>; +}; diff --git a/st/sun-nfc-cdp.dts b/st/sun-nfc-cdp.dts new file mode 100644 index 00000000..e138c38b --- /dev/null +++ b/st/sun-nfc-cdp.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-nfc-common.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Sun CDP"; + compatible = "qcom, sun-cdp", "qcom,sun", "qcom,cdp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x1 0>, <0x20001 0>, <0x50001 0>; +}; diff --git a/st/sun-nfc-common.dtsi b/st/sun-nfc-common.dtsi new file mode 100644 index 00000000..096c930b --- /dev/null +++ b/st/sun-nfc-common.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + + +#include +&qupv3_se0_i2c { + status = "ok"; + qcom,clk-freq-out = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + st21nfc: st21nfc@08 { + compatible = "st,st21nfc"; + reg = <0x08>; + irq-gpios = <&tlmm 75 0x00>; + reset-gpios = <&tlmm 34 0x00>; + clkreq-gpios = <&tlmm 35 0x00>; + interrupt-parent = <&tlmm>; + interrupts = <75 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + clocks = <&rpmhcc RPMH_RF_CLK3>; + clock-names = "nfc_ref_clk"; + }; +}; diff --git a/st/sun-nfc-mtp.dts b/st/sun-nfc-mtp.dts new file mode 100644 index 00000000..f8196483 --- /dev/null +++ b/st/sun-nfc-mtp.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-nfc-common.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Sun MTP"; + compatible = "qcom, sun-mtp", "qcom,sun", "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x8 0>, <0x20008 0>, <0x40008 0>; +}; diff --git a/st/sun-nfc-pinctrl.dtsi b/st/sun-nfc-pinctrl.dtsi new file mode 100644 index 00000000..1c69223f --- /dev/null +++ b/st/sun-nfc-pinctrl.dtsi @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&tlmm { + nfc { + nfc_int_active: nfc_int_active { + /* active state */ + mux { + /* NFC Read Interrupt */ + pins = "gpio75"; + function = "gpio"; + }; + + config { + pins = "gpio75"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; + }; + }; + + nfc_int_suspend: nfc_int_suspend { + /* sleep state */ + mux { + /* NFC Read Interrupt */ + pins = "gpio75"; + function = "gpio"; + }; + + config { + pins = "gpio75"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; + }; + }; + + nfc_enable_active: nfc_enable_active { + mux { + /* Enable and Clock request gpios */ + pins = "gpio34", "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio34", "gpio35"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + + nfc_enable_suspend: nfc_enable_suspend { + mux { + pins = "gpio34", "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio34", "gpio35"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; //nfc +}; //tlmm diff --git a/st/sun-nfc-qrd-sku1-v8.dts b/st/sun-nfc-qrd-sku1-v8.dts new file mode 100644 index 00000000..b0bc48df --- /dev/null +++ b/st/sun-nfc-qrd-sku1-v8.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-nfc-common.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Sun QRD SKU1 V8 Power Grid"; + compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp","qcom,qrd"; + qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,board-id = <0x3000B 0>; +}; diff --git a/st/sun-nfc-qrd-sku1.dts b/st/sun-nfc-qrd-sku1.dts new file mode 100644 index 00000000..f19198e3 --- /dev/null +++ b/st/sun-nfc-qrd-sku1.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-nfc-common.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Sun QRD SKU1"; + compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp", "qcom,qrd"; + qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,board-id = <0x1000B 0>; +}; diff --git a/st/sun-nfc-qrd-sku2-v8.dts b/st/sun-nfc-qrd-sku2-v8.dts new file mode 100644 index 00000000..1b14a5ec --- /dev/null +++ b/st/sun-nfc-qrd-sku2-v8.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-nfc-common.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Sun QRD SKU2 V8 Power Grid"; + compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp","qcom,qrd"; + qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,board-id = <0x2000B 0>; +}; diff --git a/st/sun-nfc-rcm.dts b/st/sun-nfc-rcm.dts new file mode 100644 index 00000000..5bc5d3ec --- /dev/null +++ b/st/sun-nfc-rcm.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-nfc-common.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Sun RCM"; + compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp", "qcom,rcm"; + qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,board-id = <0x15 0>; +}; diff --git a/st/sun-nfc.dts b/st/sun-nfc.dts new file mode 100644 index 00000000..246b0014 --- /dev/null +++ b/st/sun-nfc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-nfc-pinctrl.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Sun"; + compatible = "qcom,sun"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0 0>; +};