From 2f39297be8515ef36ead23864dadc6bf84495a41 Mon Sep 17 00:00:00 2001 From: Prerna Singh Date: Fri, 26 Apr 2024 16:05:25 +0530 Subject: [PATCH] ARM: dts: msm: Add compatible string for cc nodes monaco Add the compatible strings for clk controller nodes in monaco. Change-Id: I2acb4c9520bb217711a75eb8e79fc75ba98e587f Signed-off-by: Prerna Singh --- qcom/monaco.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 6f631075..01a9a5b2 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1065,13 +1065,13 @@ }; rpmcc: qcom,rpmcc { - /* compatible = "qcom,rpmcc-monaco"; */ + compatible = "qcom,rpmcc-monaco"; #clock-cells = <1>; #reset-cells = <1>; }; gcc: clock-controller@1410000 { - /* compatible = "qcom,monaco-gcc", "syscon"; */ + compatible = "qcom,monaco-gcc", "syscon"; reg = <0x1400000 0x1e0000>; reg-names = "cc_base"; vdd_cx-supply = <&VDD_CX_LEVEL>; @@ -1085,7 +1085,7 @@ }; dispcc: clock-controller@5f00000 { - /* compatible = "qcom,monaco-dispcc", "syscon"; */ + compatible = "qcom,monaco-dispcc", "syscon"; reg = <0x05f00000 0x20000>; reg-names = "cc_base"; clock-names = "bi_tcxo", "bi_tcxo_ao", "gpll0_out_main", @@ -1098,7 +1098,7 @@ }; gpucc: clock-controller@5990000 { - /* compatible = "qcom,monaco-gpucc", "syscon"; */ + compatible = "qcom,monaco-gpucc", "syscon"; reg = <0x5990000 0x9000>; reg-names = "cc_base"; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, @@ -1122,7 +1122,7 @@ }; debugcc: clock-controller@0 { - /* compatible = "qcom,monaco-debugcc"; */ + compatible = "qcom,monaco-debugcc"; qcom,gcc = <&gcc>; qcom,dispcc = <&dispcc>; qcom,gpucc = <&gpucc>;