From 58d15eeee5339dd8ce070275d411e7a440f8df0f Mon Sep 17 00:00:00 2001
From: Pranav Mahesh Phansalkar <quic_pphansal@quicinc.com>
Date: Sun, 1 Dec 2024 22:11:38 +0530
Subject: [PATCH] ARM: dts: msm: Add ipcc_mproc_ns1 for kera TUIVM

Add ipcc_mproc_n1 device tree node and entries to enable IPCC and mbox
communication between TUIVM and CDSP SecurePD on kera TUIVM.

Change-Id: Ib06f11a0a8e218af0cd94288531f9789de9630d9
Signed-off-by: Pranav Mahesh Phansalkar <quic_pphansal@quicinc.com>
---
 qcom/kera-vm.dtsi | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/qcom/kera-vm.dtsi b/qcom/kera-vm.dtsi
index d15de5f6..452ce2e8 100644
--- a/qcom/kera-vm.dtsi
+++ b/qcom/kera-vm.dtsi
@@ -96,7 +96,8 @@
 		vm-attrs = "context-dump", "crash-restart";
 
 		iomemory-ranges = <0x0 0xa24000 0x0 0xa24000 0x0 0x4000 0x0
-				0x0 0x824000 0x0 0x824000 0x0 0x4000 0x0>;
+				0x0 0x824000 0x0 0x824000 0x0 0x4000 0x0
+				0x0 0x407000 0x0 0x407000 0x0 0x1000 0x0>;
 
 		/* For LEVM por usecases is QUP1_SE4 and QUP2_SE7.
 		 * QUP1_SE4: GPII5 : IRQ_316
@@ -405,6 +406,15 @@
 		method = "smc";
 	};
 
+	ipcc_mproc_ns1: qcom,ipcc@407000 {
+		compatible = "qcom,ipcc";
+		reg = <0x407000 0x1000>;
+		interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		#mbox-cells = <2>;
+	};
+
 	vgic: interrupt-controller@17100000 {
 		compatible = "arm,gic-v3";
 		interrupt-controller;