From 1429d7994ef0bf3a113f0c37e7859014dd5d327c Mon Sep 17 00:00:00 2001
From: Anaadi Mishra <quic_anaadim@quicinc.com>
Date: Wed, 27 Mar 2024 12:43:47 +0530
Subject: [PATCH] ARM: dts: msm: Add support for dummy clocks/GDSCs for tuna

Add the dummy clock & gdsc handles for clients to be able to request
on them for tuna platform.

Change-Id: I6afb889a443b6e34ba94cbaff26bec43a85f6b88
Signed-off-by: Anaadi Mishra <quic_anaadim@quicinc.com>
---
 qcom/tuna-gdsc.dtsi | 235 ++++++++++++++++++++++++++++++++++++++++++++
 qcom/tuna.dtsi      | 226 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 461 insertions(+)
 create mode 100644 qcom/tuna-gdsc.dtsi

diff --git a/qcom/tuna-gdsc.dtsi b/qcom/tuna-gdsc.dtsi
new file mode 100644
index 00000000..8524ab0f
--- /dev/null
+++ b/qcom/tuna-gdsc.dtsi
@@ -0,0 +1,235 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&soc {
+	/* CAM_CC GDSCs */
+	cam_cc_ipe_0_gdsc: qcom,gdsc@adf017c {
+		compatible = "qcom,gdsc";
+		reg = <0xadf017c 0x4>;
+		regulator-name = "cam_cc_ipe_0_gdsc";
+		parent-supply = <&cam_cc_titan_top_gdsc>;
+		qcom,retain-regs;
+		qcom,support-hw-trigger;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	cam_cc_ofe_gdsc: qcom,gdsc@adf00c8 {
+		compatible = "qcom,gdsc";
+		reg = <0xadf00c8 0x4>;
+		regulator-name = "cam_cc_ofe_gdsc";
+		parent-supply = <&cam_cc_titan_top_gdsc>;
+		qcom,retain-regs;
+		qcom,support-hw-trigger;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	cam_cc_tfe_0_gdsc: qcom,gdsc@adf1004 {
+		compatible = "qcom,gdsc";
+		reg = <0xadf1004 0x4>;
+		regulator-name = "cam_cc_tfe_0_gdsc";
+		parent-supply = <&cam_cc_titan_top_gdsc>;
+		qcom,retain-regs;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	cam_cc_tfe_1_gdsc: qcom,gdsc@adf1084 {
+		compatible = "qcom,gdsc";
+		reg = <0xadf1084 0x4>;
+		regulator-name = "cam_cc_tfe_1_gdsc";
+		parent-supply = <&cam_cc_titan_top_gdsc>;
+		qcom,retain-regs;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	cam_cc_tfe_2_gdsc: qcom,gdsc@adf10ec {
+		compatible = "qcom,gdsc";
+		reg = <0xadf10ec 0x4>;
+		regulator-name = "cam_cc_tfe_2_gdsc";
+		parent-supply = <&cam_cc_titan_top_gdsc>;
+		qcom,retain-regs;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	cam_cc_titan_top_gdsc: qcom,gdsc@adf134c {
+		compatible = "qcom,gdsc";
+		reg = <0xadf134c 0x4>;
+		regulator-name = "cam_cc_titan_top_gdsc";
+		qcom,retain-regs;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	/* DISP_CC GDSCs */
+	disp_cc_mdss_core_gdsc: qcom,gdsc@af09000 {
+		compatible = "qcom,gdsc";
+		reg = <0xaf09000 0x4>;
+		regulator-name = "disp_cc_mdss_core_gdsc";
+		proxy-supply = <&disp_cc_mdss_core_gdsc>;
+		qcom,proxy-consumer-enable;
+		qcom,retain-regs;
+		qcom,support-hw-trigger;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	disp_cc_mdss_core_int2_gdsc: qcom,gdsc@af0b000 {
+		compatible = "qcom,gdsc";
+		reg = <0xaf0b000 0x4>;
+		regulator-name = "disp_cc_mdss_core_int2_gdsc";
+		qcom,retain-regs;
+		qcom,support-hw-trigger;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	/* EVA_CC GDSCs */
+	eva_cc_mvs0_gdsc: qcom,gdsc@abf8068 {
+		compatible = "qcom,gdsc";
+		reg = <0xabf8068 0x4>;
+		regulator-name = "eva_cc_mvs0_gdsc";
+		parent-supply = <&eva_cc_mvs0c_gdsc>;
+		qcom,retain-regs;
+		qcom,support-hw-trigger;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	eva_cc_mvs0c_gdsc: qcom,gdsc@abf8034 {
+		compatible = "qcom,gdsc";
+		reg = <0xabf8034 0x4>;
+		regulator-name = "eva_cc_mvs0c_gdsc";
+		qcom,retain-regs;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	gcc_apcs_gdsc_vote_ctrl: syscon@15214c {
+		compatible = "syscon";
+		reg = <0x15214c 0x4>;
+	};
+
+	/* GCC GDSCs */
+	gcc_pcie_0_gdsc: qcom,gdsc@16b004 {
+		compatible = "qcom,gdsc";
+		reg = <0x16b004 0x4>;
+		regulator-name = "gcc_pcie_0_gdsc";
+		qcom,retain-regs;
+		qcom,no-status-check-on-disable;
+		qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 0>;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	gcc_pcie_0_phy_gdsc: qcom,gdsc@16c000 {
+		compatible = "qcom,gdsc";
+		reg = <0x16c000 0x4>;
+		regulator-name = "gcc_pcie_0_phy_gdsc";
+		qcom,retain-regs;
+		qcom,no-status-check-on-disable;
+		qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 2>;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	gcc_ufs_mem_phy_gdsc: qcom,gdsc@19e000 {
+		compatible = "qcom,gdsc";
+		reg = <0x19e000 0x4>;
+		regulator-name = "gcc_ufs_mem_phy_gdsc";
+		proxy-supply = <&gcc_ufs_mem_phy_gdsc>;
+		qcom,proxy-consumer-enable;
+		qcom,retain-regs;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	gcc_ufs_phy_gdsc: qcom,gdsc@177004 {
+		compatible = "qcom,gdsc";
+		reg = <0x177004 0x4>;
+		regulator-name = "gcc_ufs_phy_gdsc";
+		proxy-supply = <&gcc_ufs_phy_gdsc>;
+		qcom,proxy-consumer-enable;
+		qcom,retain-regs;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	gcc_usb30_prim_gdsc: qcom,gdsc@139004 {
+		compatible = "qcom,gdsc";
+		reg = <0x139004 0x4>;
+		regulator-name = "gcc_usb30_prim_gdsc";
+		proxy-supply = <&gcc_usb30_prim_gdsc>;
+		qcom,proxy-consumer-enable;
+		qcom,retain-regs;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	gcc_usb3_phy_gdsc: qcom,gdsc@150018 {
+		compatible = "qcom,gdsc";
+		reg = <0x150018 0x4>;
+		regulator-name = "gcc_usb3_phy_gdsc";
+		proxy-supply = <&gcc_usb3_phy_gdsc>;
+		qcom,proxy-consumer-enable;
+		qcom,retain-regs;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	/* GPU_CC GDSCs */
+	gpu_cc_cx_gdsc_hw_ctrl: syscon@3d99094 {
+		compatible = "syscon";
+		reg = <0x3d99094 0x4>;
+	};
+
+	gpu_cc_cx_gdsc: qcom,gdsc@3d99080 {
+		compatible = "qcom,gdsc";
+		reg = <0x3d99080 0x4>;
+		regulator-name = "gpu_cc_cx_gdsc";
+		hw-ctrl-addr = <&gpu_cc_cx_gdsc_hw_ctrl>;
+		proxy-supply = <&gpu_cc_cx_gdsc>;
+		qcom,proxy-consumer-enable;
+		qcom,retain-regs;
+		qcom,support-cfg-gdscr;
+		qcom,no-status-check-on-disable;
+		status = "disabled";
+	};
+
+	/* GX_CLKCTL GDSCs */
+	gx_clkctl_gx_gdsc: qcom,gdsc@3d68024 {
+		compatible = "qcom,gdsc";
+		reg = <0x3d68024 0x4>;
+		regulator-name = "gx_clkctl_gx_gdsc";
+		reg-supply = <&gpu_cc_cx_gdsc>;
+		qcom,retain-regs;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	/* VIDEO_CC GDSCs */
+	video_cc_mvs0_gdsc: qcom,gdsc@aaf808c {
+		compatible = "qcom,gdsc";
+		reg = <0xaaf808c 0x4>;
+		regulator-name = "video_cc_mvs0_gdsc";
+		parent-supply = <&video_cc_mvs0c_gdsc>;
+		qcom,retain-regs;
+		qcom,support-hw-trigger;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	video_cc_mvs0c_gdsc: qcom,gdsc@aaf8034 {
+		compatible = "qcom,gdsc";
+		reg = <0xaaf8034 0x4>;
+		regulator-name = "video_cc_mvs0c_gdsc";
+		qcom,retain-regs;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+};
diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi
index b064f121..0cc30f4e 100644
--- a/qcom/tuna.dtsi
+++ b/qcom/tuna.dtsi
@@ -3,6 +3,15 @@
  * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
+#include <dt-bindings/clock/qcom,cambistmclkcc-sun.h>
+#include <dt-bindings/clock/qcom,camcc-sun.h>
+#include <dt-bindings/clock/qcom,dispcc-tuna.h>
+#include <dt-bindings/clock/qcom,evacc-tuna.h>
+#include <dt-bindings/clock/qcom,gcc-tuna.h>
+#include <dt-bindings/clock/qcom,gpucc-tuna.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,tcsrcc-sun.h>
+#include <dt-bindings/clock/qcom,videocc-tuna.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/soc/qcom,ipcc.h>
 
@@ -301,6 +310,223 @@
 		#interrupt-cells = <3>;
 		#mbox-cells = <2>;
 	};
+
+	clocks {
+		xo_board: xo_board {
+			compatible = "fixed-clock";
+			clock-frequency = <76800000>;
+			clock-output-names = "xo_board";
+			#clock-cells = <0>;
+		};
+
+		sleep_clk: sleep_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <32000>;
+			clock-output-names = "sleep_clk";
+			#clock-cells = <0>;
+		};
+
+		pcie_0_pipe_clk: pcie_0_pipe_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <1000>;
+			clock-output-names = "pcie_0_pipe_clk";
+			#clock-cells = <0>;
+		};
+
+		ufs_phy_rx_symbol_0_clk: ufs_phy_rx_symbol_0_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <1000>;
+			clock-output-names = "ufs_phy_rx_symbol_0_clk";
+			#clock-cells = <0>;
+		};
+
+		ufs_phy_rx_symbol_1_clk: ufs_phy_rx_symbol_1_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <1000>;
+			clock-output-names = "ufs_phy_rx_symbol_1_clk";
+			#clock-cells = <0>;
+		};
+
+		ufs_phy_tx_symbol_0_clk: ufs_phy_tx_symbol_0_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <1000>;
+			clock-output-names = "ufs_phy_tx_symbol_0_clk";
+			#clock-cells = <0>;
+		};
+
+		usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <1000>;
+			clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
+			#clock-cells = <0>;
+		};
+	};
+
+	rpmhcc: clock-controller {
+		compatible = "fixed-clock";
+		clock-output-names = "rpmh_clocks";
+		clock-frequency = <19200000>;
+		#clock-cells = <1>;
+	};
+
+	cambistmclkcc: clock-controller@1760000 {
+		compatible = "qcom,dummycc";
+		clock-output-names = "cambistmclkcc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	camcc: clock-controller@ade0000 {
+		compatible = "qcom,dummycc";
+		clock-output-names = "camcc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	dispcc: clock-controller@af00000 {
+		compatible = "qcom,dummycc";
+		clock-output-names = "dispcc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	evacc: clock-controller@abf0000 {
+		compatible = "qcom,dummycc";
+		clock-output-names = "evacc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	gcc: clock-controller@100000 {
+		compatible = "qcom,dummycc";
+		clock-output-names = "gcc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	gpucc: clock-controller@3d90000 {
+		compatible = "qcom,dummycc";
+		clock-output-names = "gpucc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	tcsrcc: clock-controller@f100000 {
+		compatible = "qcom,dummycc";
+		clock-output-names = "tcsrcc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	videocc: clock-controller@aaf0000 {
+		compatible = "qcom,dummycc";
+		clock-output-names = "videocc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+};
+
+#include "tuna-gdsc.dtsi"
+
+&cam_cc_ipe_0_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok";
+};
+
+&cam_cc_ofe_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok";
+};
+
+&cam_cc_tfe_0_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok";
+};
+
+&cam_cc_tfe_1_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok";
+};
+
+&cam_cc_tfe_2_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok";
+};
+
+&cam_cc_titan_top_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok";
+};
+
+&disp_cc_mdss_core_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok";
+};
+
+&disp_cc_mdss_core_int2_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok";
+};
+
+&eva_cc_mvs0_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok";
+};
+
+&eva_cc_mvs0c_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok";
+};
+
+&gcc_pcie_0_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok";
+};
+
+&gcc_pcie_0_phy_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok";
+};
+
+&gcc_ufs_mem_phy_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok";
+};
+
+&gcc_ufs_phy_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok";
+};
+
+&gcc_usb30_prim_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok";
+};
+
+&gcc_usb3_phy_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok";
+};
+
+&gpu_cc_cx_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok";
+};
+
+&gx_clkctl_gx_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok";
+};
+
+&video_cc_mvs0_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok";
+};
+
+&video_cc_mvs0c_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok";
 };
 
 #include "tuna-pinctrl.dtsi"