diff --git a/qcom/msm-arm-smmu-sun.dtsi b/qcom/msm-arm-smmu-sun.dtsi
index aefc2677..4e647841 100644
--- a/qcom/msm-arm-smmu-sun.dtsi
+++ b/qcom/msm-arm-smmu-sun.dtsi
@@ -6,6 +6,66 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 &soc {
+	kgsl_smmu: kgsl-smmu@3da0000 {
+		compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu";
+		reg = <0x3da0000 0x40000>;
+		#iommu-cells = <2>;
+		qcom,use-3-lvl-tables;
+		#global-interrupts = <1>;
+		#size-cells = <1>;
+		#address-cells = <1>;
+		ranges;
+		dma-coherent;
+
+		qcom,regulator-names = "vdd";
+		vdd-supply = <&gpu_cc_cx_gdsc>;
+
+		clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
+		clock-names =
+			"gpu_cc_hlos1_vote_gpu_smmu";
+
+
+                interrupts =    <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;
+
+                qcom,actlr =
+                        /* All CBs of GFX: +15 deep PF */
+                        <0x000 0x3ff 0x32B>;
+
+		gpu_qtb: gpu_qtb@3de8000 {
+			compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
+			reg = <0x3de8000 0x1000>;
+			qcom,stream-id-range = <0x0 0x400>;
+			qcom,iova-width = <49>;
+			interconnects = <&gem_noc MASTER_GPU_TCU &mc_virt SLAVE_EBI1>;
+			qcom,num-qtb-ports = <2>;
+		};
+	};
+
 	apps_smmu: apps-smmu@15000000 {
 		compatible = "qcom,qsmmu-v500";
 		reg = <0x15000000 0x100000>;
@@ -130,12 +190,66 @@
 				<GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,actlr =
+			/* CAM_HF:Camera */
+			<0x1c00 0x0000 0x00000001>,
+
+			/* Mnoc_HF_23:Display */
+			<0x0800 0x0002 0x00000001>,
+			<0x0801 0x0000 0x00000001>,
+
+			/* NSP:Compute */
+			<0x0c01 0x0040 0x00000303>,
+			<0x0c02 0x0020 0x00000303>,
+			<0x0c03 0x0040 0x00000303>,
+			<0x0c04 0x0040 0x00000303>,
+			<0x0c05 0x0040 0x00000303>,
+			<0x0c06 0x0020 0x00000303>,
+			<0x0c07 0x0040 0x00000303>,
+			<0x0c08 0x0020 0x00000303>,
+			<0x0c09 0x0040 0x00000303>,
+			<0x0c0c 0x0040 0x00000303>,
+			<0x0c0d 0x0020 0x00000303>,
+			<0x0c0e 0x0040 0x00000303>,
+			<0x0c21 0x0000 0x00000303>,
+			<0x0c23 0x0000 0x00000303>,
+			<0x0c24 0x0000 0x00000303>,
+			<0x0c25 0x0000 0x00000303>,
+			<0x0c27 0x0000 0x00000303>,
+			<0x0c29 0x0000 0x00000303>,
+			<0x0c2c 0x0000 0x00000303>,
+			<0x0c2e 0x0000 0x00000303>,
+			<0x0c42 0x0000 0x00000303>,
+			<0x0c46 0x0000 0x00000303>,
+			<0x0c48 0x0000 0x00000303>,
+			<0x0c4d 0x0000 0x00000303>,
+
+			/* SF:Camera */
+			<0x1800 0x00c0 0x00000001>,
+			<0x1820 0x0000 0x00000001>,
+			<0x1860 0x0000 0x00000103>,
+			<0x18a0 0x0000 0x00000103>,
+			<0x18e0 0x0000 0x00000103>,
+			<0x1980 0x0000 0x00000001>,
+
+			/* SF:EVA */
+			<0x1900 0x0020 0x00000103>,
+			<0x1904 0x0020 0x00000103>,
+			<0x1923 0x0000 0x00000103>,
+
+			/* SF:Video */
+			<0x1940 0x0000 0x00000103>,
+			<0x1941 0x0004 0x00000103>,
+			<0x1943 0x0000 0x00000103>,
+			<0x1944 0x0000 0x00000103>,
+			<0x1947 0x0000 0x00000103>;
 
 		anoc_1_qtb: anoc_1_qtb@16f2000 {
 			compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
 			reg = <0x16f2000 0x1000>;
 			qcom,stream-id-range = <0x0 0x400>;
 			qcom,iova-width = <36>;
+			interconnects = <&system_noc MASTER_A1NOC_SNOC &mc_virt SLAVE_EBI1>;
 			qcom,num-qtb-ports = <1>;
 		};
 
@@ -144,6 +258,7 @@
 			reg = <0x171b000 0x1000>;
 			qcom,stream-id-range = <0x400 0x400>;
 			qcom,iova-width = <36>;
+			interconnects = <&system_noc MASTER_A2NOC_SNOC &mc_virt SLAVE_EBI1>;
 			qcom,num-qtb-ports = <1>;
 		};
 
@@ -152,6 +267,7 @@
 			reg = <0x17d2000 0x1000>;
 			qcom,stream-id-range = <0x800 0x400>;
 			qcom,iova-width = <36>;
+			interconnects = <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI1>;
 			qcom,num-qtb-ports = <2>;
 		};
 
@@ -160,6 +276,7 @@
 			reg = <0x7d3000 0x1000>;
 			qcom,stream-id-range = <0xc00 0x400>;
 			qcom,iova-width = <34>;
+			interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>;
 			qcom,num-qtb-ports = <2>;
 		};
 
@@ -168,6 +285,7 @@
 			reg = <0x7b3000 0x1000>;
 			qcom,stream-id-range = <0x1000 0x400>;
 			qcom,iova-width = <32>;
+			interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC &mc_virt SLAVE_EBI1>;
 			qcom,num-qtb-ports = <1>;
 		};
 
@@ -176,6 +294,7 @@
 			reg = <0x16cd000 0x1000>;
 			qcom,stream-id-range = <0x1400 0x400>;
 			qcom,iova-width = <36>;
+			interconnects = <&pcie_noc MASTER_PCIE_3 &mc_virt SLAVE_EBI1>;
 			qcom,num-qtb-ports = <1>;
 			qcom,opt-out-tbu-halting;
 		};
@@ -185,6 +304,7 @@
 			reg = <0x17d1000 0x1000>;
 			qcom,stream-id-range = <0x1800 0x400>;
 			qcom,iova-width = <36>;
+			interconnects = <&mmss_noc MASTER_VIDEO_EVA &mc_virt SLAVE_EBI1>;
 			qcom,num-qtb-ports = <2>;
 		};
 
@@ -193,6 +313,7 @@
 			reg = <0x17d0000 0x1000>;
 			qcom,stream-id-range = <0x1c00 0x400>;
 			qcom,iova-width = <32>;
+			interconnects = <&mmss_noc MASTER_MDP &mc_virt SLAVE_EBI1>;
 			qcom,num-qtb-ports = <2>;
 		};
 
@@ -201,6 +322,7 @@
 			reg = <0x24423000 0x1000>;
 			qcom,stream-id-range = <0x2000 0x400>;
 			qcom,iova-width = <36>;
+			interconnects = <&gem_noc MASTER_UBWC &mc_virt SLAVE_EBI1>;
 			qcom,num-qtb-ports = <1>;
 		};
 	};
@@ -241,5 +363,16 @@
 			iommus = <&apps_smmu 0x400 0x0>;
 			qcom,iommu-vmid = <0xa>; /* VMID_CP_PIXEL */
 		};
+
+		usecase5_kgsl {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&kgsl_smmu 0x7 0x0>;
+		};
+
+		usecase6_kgsl_dma {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&kgsl_smmu 0x7 0x0>;
+			dma-coherent;
+		};
 	};
 };