samsung_sm8750/android_kernel_samsung_sm8750-devicetrees
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

ARM: dts: msm: Add support for GCC and TCSRCC on Kera

Browse Source 
Add support for GCC and TCSRCC on Kera platform. While at it,
move the corresponding GDSC's to real.

Change-Id: I1ecf7e1ec14afc71a9fc228c636668d9052ba14b
Signed-off-by: Anaadi Mishra <quic_anaadim@quicinc.com>
This commit is contained in:
Anaadi Mishra
2024-06-17 16:03:10 +05:30
parent 6f7280c96d
commit 57d974a176
1 changed files with 32 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

44
qcom/kera.dtsi
View File

@@ -1132,8 +1132,27 @@
}; };
gcc: clock-controller@100000 { gcc: clock-controller@100000 {
compatible = "qcom,dummycc"; compatible = "qcom,kera-gcc", "syscon";
clock-output-names = "gcc_clocks"; reg = <0x100000 0x1f4200>;
reg-name = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_mx-supply = <&VDD_MX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&pcie_0_pipe_clk>,
<&pcie_1_pipe_clk>,
<&sleep_clk>,
<&ufs_phy_rx_symbol_0_clk>,
<&ufs_phy_rx_symbol_1_clk>,
<&ufs_phy_tx_symbol_0_clk>,
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
clock-names = "bi_tcxo",
"pcie_0_pipe_clk",
"pcie_1_pipe_clk",
"sleep_clk",
"ufs_phy_rx_symbol_0_clk",
"ufs_phy_rx_symbol_1_clk",
"ufs_phy_tx_symbol_0_clk",
"usb3_phy_wrapper_gcc_usb30_pipe_clk";
#clock-cells = <1>; #clock-cells = <1>;
#reset-cells = <1>; #reset-cells = <1>;
}; };
@@ -1146,8 +1165,9 @@
}; };
tcsrcc: clock-controller@1f40000 { tcsrcc: clock-controller@1f40000 {
compatible = "qcom,dummycc"; compatible = "qcom,kera-tcsrcc", "syscon";
clock-output-names = "tcsrcc_clocks"; reg = <0x1fbf000 0x20>;
reg-name = "cc_base";
#clock-cells = <1>; #clock-cells = <1>;
#reset-cells = <1>; #reset-cells = <1>;
}; };
@@ -1366,42 +1386,42 @@
}; };
&gcc_pcie_0_gdsc { &gcc_pcie_0_gdsc {
compatible = "regulator-fixed"; parent-supply = <&VDD_CX_LEVEL>;
status = "ok"; status = "ok";
}; };
&gcc_pcie_0_phy_gdsc { &gcc_pcie_0_phy_gdsc {
compatible = "regulator-fixed"; parent-supply = <&VDD_MX_LEVEL>;
status = "ok"; status = "ok";
}; };
&gcc_pcie_1_gdsc { &gcc_pcie_1_gdsc {
compatible = "regulator-fixed"; parent-supply = <&VDD_CX_LEVEL>;
status = "ok"; status = "ok";
}; };
&gcc_pcie_1_phy_gdsc { &gcc_pcie_1_phy_gdsc {
compatible = "regulator-fixed"; parent-supply = <&VDD_MX_LEVEL>;
status = "ok"; status = "ok";
}; };
&gcc_ufs_mem_phy_gdsc { &gcc_ufs_mem_phy_gdsc {
compatible = "regulator-fixed"; parent-supply = <&VDD_MX_LEVEL>;
status = "ok"; status = "ok";
}; };
&gcc_ufs_phy_gdsc { &gcc_ufs_phy_gdsc {
compatible = "regulator-fixed"; parent-supply = <&VDD_CX_LEVEL>;
status = "ok"; status = "ok";
}; };
&gcc_usb30_prim_gdsc { &gcc_usb30_prim_gdsc {
compatible = "regulator-fixed"; parent-supply = <&VDD_CX_LEVEL>;
status = "ok"; status = "ok";
}; };
&gcc_usb3_phy_gdsc { &gcc_usb3_phy_gdsc {
compatible = "regulator-fixed"; parent-supply = <&VDD_MX_LEVEL>;
status = "ok"; status = "ok";
}; };