dt-bindings: cpufreq: Add qcom,cpufreq-thermal docs

Add documentation for the qcom,cpufreq-thermal device, which is used to
handle CPU thermal limit mailboxes notifications.

Change-Id: I6e2c33d2a9d55ab4bb2c8361091ebb0110739d43
Signed-off-by: Mike Tipton <quic_mdtipton@quicinc.com>

bindings/cpufreq/cpufreq-qcom-thermal.yaml

@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-thermal.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. CPUFREQ Thermal
+
+maintainers:
+  - Mike Tipton <quic_mdtipton@quicinc.com>
+
+description: |
+
+  This device listens for CPU thermal frequency limit mailbox notifications and
+  informs the scheduler of them via thermal pressure.
+
+properties:
+  compatible:
+    const: qcom,cpufreq-thermal
+
+  mboxes:
+    description: Mailboxes used for each cpufreq policy
+
+  qcom,policy-cpus:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    description: Base CPU indices for each cpufreq policy
+
+required:
+  - compatible
+  - mboxes
+  - qcom,policy-cpus
+
+additionalProperties: false
+
+examples:
+  - |
+    // Two clusters. The first cluster starts with CPU0, and the second cluster
+    // starts with CPU6. The mailboxes for each cluster are indexes 5 and 6 of
+    // the cpucp device.
+    soc {
+      cpufreq_thermal: qcom,cpufreq-thermal {
+        compatible = "qcom,cpufreq-thermal";
+        mboxes = <&cpucp 5>, <&cpucp 6>;
+        qcom,policy-cpus = <0 6>;
+      };
+    };
+...