From 05133adf46835eb2f1e066d1037233f207afa818 Mon Sep 17 00:00:00 2001 From: Grace An Date: Mon, 23 Oct 2023 11:55:09 -0700 Subject: [PATCH 1/2] ARM: dts: msm: mm-drivers: add support for hw-fence feature on sun This change adds support for device tree configuration and settings for the hw-fence driver that initialize, expose and manage the interfaces for hw-fences on sun target. Change-Id: I99fd3678728af8b9000db8867a1c776d46b7cc16 Signed-off-by: Grace An --- Kbuild | 21 +++++++++ Makefile | 9 ++++ bindings/hw-fence.txt | 80 ++++++++++++++++++++++++++++++++++ hw_fence/sun-hw-fence.dts | 15 +++++++ hw_fence/sun-hw-fence.dtsi | 37 ++++++++++++++++ sun-mm-cdp-kiwi-overlay.dts | 17 ++++++++ sun-mm-cdp-kiwi-v8-overlay.dts | 17 ++++++++ sun-mm-cdp-nfc-overlay.dts | 16 +++++++ sun-mm-cdp-overlay.dts | 17 ++++++++ sun-mm-cdp-v8-overlay.dts | 17 ++++++++ sun-mm-mtp-kiwi-overlay.dts | 17 ++++++++ sun-mm-mtp-kiwi-v8-overlay.dts | 17 ++++++++ sun-mm-mtp-nfc-overlay.dts | 16 +++++++ sun-mm-mtp-overlay.dts | 17 ++++++++ sun-mm-mtp-v8-overlay.dts | 17 ++++++++ sun-mm-qrd-sku1-overlay.dts | 17 ++++++++ sun-mm-qrd-sku1-v8-overlay.dts | 17 ++++++++ sun-mm-qrd-sku2-v8-overlay.dts | 17 ++++++++ sun-mm-rumi-overlay.dts | 16 +++++++ 19 files changed, 397 insertions(+) create mode 100644 Kbuild create mode 100644 Makefile create mode 100644 bindings/hw-fence.txt create mode 100644 hw_fence/sun-hw-fence.dts create mode 100644 hw_fence/sun-hw-fence.dtsi create mode 100644 sun-mm-cdp-kiwi-overlay.dts create mode 100644 sun-mm-cdp-kiwi-v8-overlay.dts create mode 100644 sun-mm-cdp-nfc-overlay.dts create mode 100644 sun-mm-cdp-overlay.dts create mode 100644 sun-mm-cdp-v8-overlay.dts create mode 100644 sun-mm-mtp-kiwi-overlay.dts create mode 100644 sun-mm-mtp-kiwi-v8-overlay.dts create mode 100644 sun-mm-mtp-nfc-overlay.dts create mode 100644 sun-mm-mtp-overlay.dts create mode 100644 sun-mm-mtp-v8-overlay.dts create mode 100644 sun-mm-qrd-sku1-overlay.dts create mode 100644 sun-mm-qrd-sku1-v8-overlay.dts create mode 100644 sun-mm-qrd-sku2-v8-overlay.dts create mode 100644 sun-mm-rumi-overlay.dts diff --git a/Kbuild b/Kbuild new file mode 100644 index 00000000..57bd5f08 --- /dev/null +++ b/Kbuild @@ -0,0 +1,21 @@ +ifeq ($(CONFIG_ARCH_SUN), y) + dtbo-y += hw_fence/sun-hw-fence.dtbo \ + sun-mm-cdp-kiwi-overlay.dtbo \ + sun-mm-cdp-kiwi-v8-overlay.dtbo \ + sun-mm-cdp-nfc-overlay.dtbo \ + sun-mm-cdp-overlay.dtbo \ + sun-mm-cdp-v8-overlay.dtbo \ + sun-mm-mtp-kiwi-overlay.dtbo \ + sun-mm-mtp-kiwi-v8-overlay.dtbo \ + sun-mm-mtp-nfc-overlay.dtbo \ + sun-mm-mtp-overlay.dtbo \ + sun-mm-mtp-v8-overlay.dtbo \ + sun-mm-qrd-sku1-overlay.dtbo \ + sun-mm-qrd-sku1-v8-overlay.dtbo \ + sun-mm-qrd-sku2-v8-overlay.dtbo \ + sun-mm-rumi-overlay.dtbo +endif + +always-y := $(dtb-y) $(dtbo-y) +subdir-y := $(dts-dirs) +clean-files := *.dtb *.dtbo diff --git a/Makefile b/Makefile new file mode 100644 index 00000000..b1e0dfe9 --- /dev/null +++ b/Makefile @@ -0,0 +1,9 @@ +KBUILD_OPTIONS+=KBUILD_EXTMOD_DTS=. + +all: dtbs + +clean: + $(MAKE) -C $(KERNEL_SRC) M=$(M) clean + +%: + $(MAKE) -C $(KERNEL_SRC) M=$(M) $@ $(KBUILD_OPTIONS) diff --git a/bindings/hw-fence.txt b/bindings/hw-fence.txt new file mode 100644 index 00000000..fd36a30e --- /dev/null +++ b/bindings/hw-fence.txt @@ -0,0 +1,80 @@ +Qualcomm Technologies, Inc. HW FENCE + +HW Fence implements Linux APIs to initialize, deinitialize, register-for-signal, and +overall manage the hw-fences, for hw-to-hw communcation between hw cores. + +Required properties +- compatible: Must be "qcom,msm-hw-fence". +- qcom,ipcc-reg: Registers ranges for ipcc registers. +- qcom,hw-fence-table-entries: A u32 indicating number of entries for the hw-fence table +- qcom,hw-fence-queue-entries: A u32 indicating default number of entries for the Queues +- hw_fence@0: Doorbell configuration to communicate with secondary vm through hypervisor. +- hw_fence@1: Carved-out emory-mapping region, to be used for mapping of global tables and queues + used by the hw-fence driver and fence controller running in secondary vm. + +Optional properties: +- qcom,hw-fence-ipc-ver: A u32 indicating ipc version. If not provided in device-tree, this is read + from the registers. +- qcom,hw-fence-client-type-[name]: A list of four u32 indicating , where [name] specifies the client + type these properties apply to. If provided, all four u32 values + must be provided, and these override default values specified by + the driver for some clients (e.g. dpu, gpu). + -- clients_num: number of clients for given client type + -- queues_num: 1 queue (TxQ) or 2 queues (RxQ and TxQ) + -- queue_entries: number of entries per client queue + -- skip_txq_wr_idx: bool indicating whether tx queue wr_idx update + is skipped within hw fence driver and + hfi_header->tx_wm is used instead +- qcom,hw-fence-client-type-[name]-extra: A list of four u32 indicating extra client queue + properties: . Later u32 values do not need to be + provided to provide values for earlier u32 values. + -- start_padding: size of padding between queue table header + and first queue header in bytes + -- end_padding: size of padding between queue header(s) and + first queue payload in bytes + -- txq_idx_start: start_index for TxQ rd_wr_index + -- txq_idx_by_payload: bool indicating whether TxQ rd_wr_idx + indexes by payloads instead of default + dwords + +Example: + msm_hw_fence: qcom,hw-fence { + compatible = "qcom,msm-hw-fence"; + status = "ok"; + + qcom,ipcc-reg = <0x400000 0x100000>; + qcom,hw-fence-table-entries = <8192>; + qcom,hw-fence-queue-entries = <800>; + + /* time register */ + qcom,qtime-reg = <0xC221000 0x1000>; + + /* ipc version */ + qcom,hw-fence-ipc-ver = <0x20003>; + + /* client queues: clients_num, queues_num, queue_entries, skip_txq_wr_idx */ + qcom,hw-fence-client-type-dpu = <4 2 128 0>; + qcom,hw-fence-client-type-ife2 = <3 1 64 1>; + + /* extra client queue properties */ + qcom,hw-fence-client-type-ife2-extra = <20 28 1 1>; + + /* haven doorbell specific */ + hw_fence@0 { + compatible = "qcom,msm-hw-fence-db"; + qcom,master; + gunyah-label = <6>; + peer-name = <3>; + }; + + /* haven io-mem specific */ + hw_fence@1 { + compatible = "qcom,msm-hw-fence-mem"; + qcom,master; + gunyah-label = <5>; + peer-name = <3>; + shared-buffer = <&hwfence_shbuf>; + }; + }; diff --git a/hw_fence/sun-hw-fence.dts b/hw_fence/sun-hw-fence.dts new file mode 100644 index 00000000..d4bb31aa --- /dev/null +++ b/hw_fence/sun-hw-fence.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-hw-fence.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun SoC"; + compatible = "qcom,sun"; + qcom,board-id = <0 0>; +}; diff --git a/hw_fence/sun-hw-fence.dtsi b/hw_fence/sun-hw-fence.dtsi new file mode 100644 index 00000000..117980c8 --- /dev/null +++ b/hw_fence/sun-hw-fence.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + msm_hw_fence: qcom,hw-fence { + compatible = "qcom,msm-hw-fence"; + status = "ok"; + + qcom,hw-fence-table-entries = <8192>; + qcom,hw-fence-queue-entries = <800>; + qcom,ipcc-reg = <0x400000 0x140000>; + + /* time register */ + qcom,qtime-reg = <0xC221000 0x1000>; + + /* ipc version */ + qcom,hw-fence-ipc-ver = <0x20A02>; + + /* base client queue properties */ + qcom,hw-fence-client-type-dpu = <6 2 128 1>; + qcom,hw-fence-client-type-ipe = <1 2 800 0>; + qcom,hw-fence-client-type-vpu = <1 2 800 0>; + qcom,hw-fence-client-type-ife0 = <1 1 128 1>; + + /* extra client queue properties */ + qcom,hw-fence-client-type-ife0-extra = <20 28 1 1>; + + /* haven io-mem specific */ + hw_fence@1 { + compatible = "qcom,msm-hw-fence-mem"; + qcom,master; + shared-buffer = <&hwfence_shbuf>; + }; + }; +}; diff --git a/sun-mm-cdp-kiwi-overlay.dts b/sun-mm-cdp-kiwi-overlay.dts new file mode 100644 index 00000000..fb9ed903 --- /dev/null +++ b/sun-mm-cdp-kiwi-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "hw_fence/sun-hw-fence.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun CDP Kiwi WLAN"; + compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp", + "qcom,cdp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x20001 0>; +}; diff --git a/sun-mm-cdp-kiwi-v8-overlay.dts b/sun-mm-cdp-kiwi-v8-overlay.dts new file mode 100644 index 00000000..06651d95 --- /dev/null +++ b/sun-mm-cdp-kiwi-v8-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "hw_fence/sun-hw-fence.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun CDP Kiwi WLAN V8 Power Grid"; + compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp", + "qcom,cdp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x60001 0>; +}; diff --git a/sun-mm-cdp-nfc-overlay.dts b/sun-mm-cdp-nfc-overlay.dts new file mode 100644 index 00000000..64fa90b3 --- /dev/null +++ b/sun-mm-cdp-nfc-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "hw_fence/sun-hw-fence.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun CDP SN300 NFC"; + compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp", "qcom,cdp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x40001 0>; +}; diff --git a/sun-mm-cdp-overlay.dts b/sun-mm-cdp-overlay.dts new file mode 100644 index 00000000..370d3a12 --- /dev/null +++ b/sun-mm-cdp-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "hw_fence/sun-hw-fence.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun CDP"; + compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp", + "qcom,cdp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <1 0>; +}; diff --git a/sun-mm-cdp-v8-overlay.dts b/sun-mm-cdp-v8-overlay.dts new file mode 100644 index 00000000..aaa799a1 --- /dev/null +++ b/sun-mm-cdp-v8-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "hw_fence/sun-hw-fence.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun CDP V8 Power Grid"; + compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp", + "qcom,cdp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x50001 0>; +}; diff --git a/sun-mm-mtp-kiwi-overlay.dts b/sun-mm-mtp-kiwi-overlay.dts new file mode 100644 index 00000000..171fb3a1 --- /dev/null +++ b/sun-mm-mtp-kiwi-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "hw_fence/sun-hw-fence.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun MTP Kiwi WLAN"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", + "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x20008 0>; +}; diff --git a/sun-mm-mtp-kiwi-v8-overlay.dts b/sun-mm-mtp-kiwi-v8-overlay.dts new file mode 100644 index 00000000..5bcab679 --- /dev/null +++ b/sun-mm-mtp-kiwi-v8-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "hw_fence/sun-hw-fence.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun MTP Kiwi WLAN V8 Power Grid"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", + "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x50008 0>; +}; diff --git a/sun-mm-mtp-nfc-overlay.dts b/sun-mm-mtp-nfc-overlay.dts new file mode 100644 index 00000000..9106f485 --- /dev/null +++ b/sun-mm-mtp-nfc-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "hw_fence/sun-hw-fence.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun MTP SN300 NFC"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x30008 0>; +}; diff --git a/sun-mm-mtp-overlay.dts b/sun-mm-mtp-overlay.dts new file mode 100644 index 00000000..3c5a1ea0 --- /dev/null +++ b/sun-mm-mtp-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "hw_fence/sun-hw-fence.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun MTP"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", + "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <8 0>; +}; diff --git a/sun-mm-mtp-v8-overlay.dts b/sun-mm-mtp-v8-overlay.dts new file mode 100644 index 00000000..0313a032 --- /dev/null +++ b/sun-mm-mtp-v8-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "hw_fence/sun-hw-fence.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun MTP V8 Power Grid"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", + "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x40008 0>; +}; diff --git a/sun-mm-qrd-sku1-overlay.dts b/sun-mm-qrd-sku1-overlay.dts new file mode 100644 index 00000000..0cd2ea34 --- /dev/null +++ b/sun-mm-qrd-sku1-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "hw_fence/sun-hw-fence.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun QRD SKU1"; + compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp", + "qcom,qrd"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x1000B 0>; +}; diff --git a/sun-mm-qrd-sku1-v8-overlay.dts b/sun-mm-qrd-sku1-v8-overlay.dts new file mode 100644 index 00000000..93678c21 --- /dev/null +++ b/sun-mm-qrd-sku1-v8-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "hw_fence/sun-hw-fence.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun QRD SKU1 V8 Power Grid"; + compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp", + "qcom,qrd"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x3000B 0>; +}; diff --git a/sun-mm-qrd-sku2-v8-overlay.dts b/sun-mm-qrd-sku2-v8-overlay.dts new file mode 100644 index 00000000..83be5632 --- /dev/null +++ b/sun-mm-qrd-sku2-v8-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "hw_fence/sun-hw-fence.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun QRD SKU2 V8 Power Grid"; + compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp", + "qcom,qrd"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x2000B 0>; +}; diff --git a/sun-mm-rumi-overlay.dts b/sun-mm-rumi-overlay.dts new file mode 100644 index 00000000..32c0f7c7 --- /dev/null +++ b/sun-mm-rumi-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "hw_fence/sun-hw-fence.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun RUMI"; + compatible = "qcom,sun-rumi", "qcom,sun", "qcom,rumi"; + qcom,msm-id = <618 0x10000>; + qcom,board-id = <15 0>; +}; From 3bb27e105099c0ed90954c46f356306703a0c53f Mon Sep 17 00:00:00 2001 From: Grace An Date: Mon, 23 Oct 2023 13:33:24 -0700 Subject: [PATCH 2/2] ARM: dts: msm: mm-drivers: add soccp dtsi properties to sun target Add dtsi properties for HW Fence Driver to access the phandle of the SOCCP driver, receive IPCC interrupts from SOCCP on the sun target, and map memory for SOCCP access. Change-Id: Iaa5e381fcb38dbb33771e6b15f12d0425e2d1b4b Signed-off-by: Grace An --- bindings/hw-fence.txt | 53 +++++++++++++++++++++++++++++++++++--- hw_fence/sun-hw-fence.dtsi | 9 +++++++ 2 files changed, 58 insertions(+), 4 deletions(-) diff --git a/bindings/hw-fence.txt b/bindings/hw-fence.txt index fd36a30e..3e4159ff 100644 --- a/bindings/hw-fence.txt +++ b/bindings/hw-fence.txt @@ -8,9 +8,17 @@ Required properties - qcom,ipcc-reg: Registers ranges for ipcc registers. - qcom,hw-fence-table-entries: A u32 indicating number of entries for the hw-fence table - qcom,hw-fence-queue-entries: A u32 indicating default number of entries for the Queues +- hw_fence@1: Carved-out memory-mapping region, to be used for mapping of global tables and queues + used by the hw-fence driver and fence controller running either in secondary vm or + on SOCCP. +Required properties on targets without SOCCP: - hw_fence@0: Doorbell configuration to communicate with secondary vm through hypervisor. -- hw_fence@1: Carved-out emory-mapping region, to be used for mapping of global tables and queues - used by the hw-fence driver and fence controller running in secondary vm. +Required properties on targets with SOCCP: +- soccp_controller: Phandle for the soccp controller. +- interrupts: Interrupt associated with APSS NS0 (to receive interrupts from SOCCP). +- interrupt-controller: Mark the device node as an interrupt controller. +- #interrupt-cells: Should be one. The first cell is interrupt number. +- iommus: Specifies the SID's used by this context bank. Optional properties: - qcom,hw-fence-ipc-ver: A u32 indicating ipc version. If not provided in device-tree, this is read @@ -39,7 +47,44 @@ Optional properties: indexes by payloads instead of default dwords -Example: +Example for target with SOCCP: + msm_hw_fence: qcom,hw-fence { + compatible = "qcom,msm-hw-fence"; + status = "ok"; + + /* SOCCP properties */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + iommus = <&apps_smmu 0x562 0x1>; + soccp_controller = <&soccp_pas>; + + qcom,ipcc-reg = <0x400000 0x100000>; + qcom,hw-fence-table-entries = <8192>; + qcom,hw-fence-queue-entries = <800>; + + /* time register */ + qcom,qtime-reg = <0xC221000 0x1000>; + + /* ipc version */ + qcom,hw-fence-ipc-ver = <0x20003>; + + /* base client queue properties */ + qcom,hw-fence-client-type-dpu = <4 2 128 0>; + qcom,hw-fence-client-type-ife2 = <3 1 64 1>; + + /* extra client queue properties */ + qcom,hw-fence-client-type-ife2-extra = <20 28 1 1>; + + /* haven io-mem specific */ + hw_fence@1 { + compatible = "qcom,msm-hw-fence-mem"; + qcom,master; + shared-buffer = <&hwfence_shbuf>; + }; + }; + +Example for target without SOCCP: msm_hw_fence: qcom,hw-fence { compatible = "qcom,msm-hw-fence"; status = "ok"; @@ -54,7 +99,7 @@ Example: /* ipc version */ qcom,hw-fence-ipc-ver = <0x20003>; - /* client queues: clients_num, queues_num, queue_entries, skip_txq_wr_idx */ + /* base client queue properties */ qcom,hw-fence-client-type-dpu = <4 2 128 0>; qcom,hw-fence-client-type-ife2 = <3 1 64 1>; diff --git a/hw_fence/sun-hw-fence.dtsi b/hw_fence/sun-hw-fence.dtsi index 117980c8..38832617 100644 --- a/hw_fence/sun-hw-fence.dtsi +++ b/hw_fence/sun-hw-fence.dtsi @@ -3,11 +3,20 @@ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include + &soc { msm_hw_fence: qcom,hw-fence { compatible = "qcom,msm-hw-fence"; status = "ok"; + /* SOCCP properties */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + iommus = <&apps_smmu 0x562 0x1>; + soccp_controller = <&soccp_pas>; + qcom,hw-fence-table-entries = <8192>; qcom,hw-fence-queue-entries = <800>; qcom,ipcc-reg = <0x400000 0x140000>;