Merge "dt-bindings: Update cpucp bindings to add support for pdp"

bindings/soc/qcom/qcom,cpucp-log.yaml

@@ -6,32 +6,48 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: Qualcomm Technologies, Inc. CPUCP Logging
 
-description: |
+maintainers:
-    CPUCP logging is a device that uses mailbox to collect the logs
+  - Amir Vajid <quic_avajid@quicinc.com>
-    generated from cpucp, and dump them into a dedicated log buffer
+  - Shivnandan Kumar <quic_kshivnan@quicinc.com>
-    through ipc_logging framework.
+
-    An instance of cpucp-log should have the mailbox controller phandle and
+description:
-    addresses of log buffer set aside for this purpose.
+  CPUCP logging is a device that uses mailbox to collect the logs
+  generated from cpucp, and dump them into a dedicated log buffer
+  through ipc_logging framework.
+  An instance of cpucp-log should have the mailbox controller phandle and
+  addresses of log buffer set aside for this purpose.
 
 properties:
   compatible:
-    const: qcom,cpucp-log
+    enum:
+      - qcom,cpucp-log
+      - qcom,pdp-log
+  reg:
+    maxItems: 2
 
   mboxes:
     description:
       reference to "cpucp" mailbox, as described in mailbox/mailbox.txt.
 
+  qcom,log-type:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      CPUCP log type as described in enum cpucp_log_type in cpucp_log.c.
+
 required:
   - compatible
   - mboxes
   - reg
+  - qcom,log-type
+
+additionalProperties: false
 
 examples:
   - |
     cpucp_log: qcom,cpucp_log@fd04780 {
-      #address-cells = <2>;
-      #size-cells = <2>;
       compatible = "qcom,cpucp-log";
-      reg = <0x0fd04580 0x200>, <0x0fd04780 0x200>;
+      reg = <0x0fd04580 0x200>,
+            <0x0fd04780 0x200>;
       mboxes = <&cpucp 1>;
+      qcom,log-type = <0>;
     };

bindings/soc/qcom/qcom,cpucp.yaml

@@ -6,7 +6,11 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: Qualcomm Technologies, Inc. CPUCP Mailbox controller driver
 
-description: |
+maintainers:
+  - Amir Vajid <quic_avajid@quicinc.com>
+  - Shivnandan Kumar <quic_kshivnan@quicinc.com>
+
+description:
   This mailbox controller act as interface to do doorbell between
   HLOS and CPUCP subsystem.
 
@@ -17,25 +21,37 @@ properties:
       - qcom,cpucp-v2
 
   reg:
-      items:
+    items:
-          - description: tx base address
+      - description: tx base address
-          - description: rx base address
+      - description: rx base address
+
+  reg-names:
+    items:
+      - const: rx
+      - const: tx
 
   "#mbox-cells":
-      const: 1
+    const: 1
+
+  qcom,rx-chans:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: Bitmask of RX channels to monitor (optional)
 
 required:
   - compatible
   - reg
+  - reg-names
   - "#mbox-cells"
 
+additionalProperties: false
+
 examples:
   - |
-    qcom,cpucp@0f400000 {
+    qcom,cpucp@f400000 {
-      #address-cells = <2>;
-      #size-cells = <2>;
       compatible = "qcom,cpucp";
-      reg =   <0x0f400000 0x10>, <0x0fd90000 0x2000>;
+      reg = <0x0f400000 0x10>,
+            <0x0fd90000 0x2000>;
+      reg-names = "tx",
+                  "rx";
       #mbox-cells = <1>;
-      status = "ok";
     };